JP2013080763A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device that allows reduction in variation of a threshold voltage.SOLUTION: A silicon carbide semiconductor device 10 includes a substrate 11, and a silicon carbide layer 4 that is provided on the substrate 11 and has a primary surface 13A and a thickness direction crossing to the primary surface 13A. The silicon carbide layer 4 includes a channel layer 7, a source region 15, a drain region 17, and a gate region 16R between the source region 15 and the drain region 17. The gate region 16R is epitaxially grown with respect to the channel layer 7 so as to have a second conductivity type different from a first conductivity type.

Description

  The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more specifically to a silicon carbide semiconductor device which is a lateral junction field effect transistor and a manufacturing method thereof.

  A RESURF-JFET (Reduced SURface Field-Junction Field Effect Transistor) is known as a SiC (silicon carbide) transistor that can be expected to be switched at high speed (for example, see Non-Patent Document 1). .

Hideto Tamaso, 10 others, “Development of SiC high-speed transistor”, No. 172, SEI Technical Review, January 2008, p. 40-46

  In the RESURF-JFET, the gate region is formed by ion implantation. In this case, since it is difficult to control the depth of ion implantation, the variation in the thickness of the channel layer immediately below the gate region and the variation in the impurity concentration in the boundary region between the gate region and the channel layer become large. Therefore, the threshold voltage varies greatly.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a silicon carbide semiconductor device capable of reducing variations in threshold voltage and a method for manufacturing the same.

  A silicon carbide semiconductor device according to the present invention includes a substrate, a silicon carbide layer provided on the substrate, and having a main surface and a thickness direction intersecting the main surface. The silicon carbide layer includes a channel layer having the first conductivity type, a source region having the first conductivity type and extending from the main surface into the channel layer along the thickness direction, and the first conductivity type A drain region that extends from the main surface along the thickness direction into the channel layer and sandwiches the channel layer between the source region in the opposite direction intersecting the thickness direction, and the source region and the drain And a gate region extending from the main surface into the channel layer along the thickness direction. The gate region is epitaxially grown with respect to the channel layer so as to have a second conductivity type different from the first conductivity type.

  Here, “provided on the substrate” may be either directly provided on the substrate or provided on the substrate via another layer.

  If the gate region is formed by ion implantation, it is difficult to control the depth of ion implantation. Therefore, variations in the thickness of the channel layer immediately below the gate region and variations in the impurity concentration in the boundary region between the gate region and the channel layer occur. growing. Therefore, the threshold voltage of the semiconductor device varies. On the other hand, according to the silicon carbide semiconductor device of the present invention, the gate region is formed not by ion implantation but by an epitaxial film. Therefore, since variations due to ion implantation do not occur, variations in threshold voltage can be reduced.

In the silicon carbide semiconductor device described above, the first conductivity type is preferably n-type.
As a result, the conductivity type of the channel layer becomes n-type. Therefore, electrons having a higher mobility than holes can be used as main carriers flowing in the channel layer. Therefore, the on-resistance is reduced.

  Preferably, the silicon carbide semiconductor device further includes an epitaxial layer that connects the source region and the drain region along the opposing direction on the channel layer provided with the gate region, and that has the second conductivity type.

  Thereby, since the RESURF structure is provided on the channel layer by the epitaxial layer, the breakdown voltage is higher than that in the case where there is no RESURF structure. Therefore, the impurity concentration of the channel layer can be made relatively high. Thereby, the on-resistance can be further reduced.

  Preferably, in the above silicon carbide semiconductor device, the channel layer is provided on the first layer with the first impurity concentration, penetrated by the gate region, and has the second impurity concentration. And a second layer. The second impurity concentration is higher than the first impurity concentration.

  Since the threshold voltage is mainly determined by the first impurity concentration of the first layer, the first impurity concentration is determined by the required threshold voltage. On the other hand, the second impurity concentration of the second layer has a smaller influence on the threshold voltage than the first impurity concentration of the first layer. Therefore, by making the second impurity concentration higher than the first impurity concentration, the on-resistance can be lowered without significantly affecting the threshold voltage.

  Preferably, in the silicon carbide semiconductor device described above, in a cross-sectional view including the thickness direction and the facing direction, the dimension along the facing direction of the gate region decreases as the distance from the main surface increases.

  As a result, the resistance of the channel portion in the vicinity of the gate region is reduced, so that the on-resistance can be lowered.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention includes the following steps. A first layer having the first conductivity type is epitaxially formed on the substrate. A gate layer having a second conductivity type different from the first conductivity type is epitaxially formed on the first layer. By patterning the gate layer, a gate region is formed on a portion of the first layer. A second layer having the first conductivity type is epitaxially formed on the first layer provided with the gate region. By removing a portion of the second layer located on the gate region, a channel layer having the first and second layers and a gate region penetrating the second layer are formed on the substrate. A silicon carbide layer having a surface and a thickness direction intersecting with the main surface is formed. A source region and a drain region are provided in the silicon carbide layer. The step of providing the source region and the drain region is performed such that each of the source region and the drain region has the first conductivity type and extends from the main surface along the thickness direction into the channel layer, and the source region The drain region is formed so as to sandwich a gate region extending so as to protrude into the channel layer between the source region and the drain region in the opposite direction intersecting the thickness direction.

  Here, “on the substrate” may be either directly on the substrate or via another layer on the substrate.

  If the gate region is formed by ion implantation, it is difficult to control the depth of ion implantation. Therefore, variations in the thickness of the channel layer immediately below the gate region and variations in the impurity concentration in the boundary region between the gate region and the channel layer occur. growing. Therefore, the threshold voltage of the semiconductor device varies. On the other hand, according to the silicon carbide semiconductor device of the present invention, the gate region is formed not by ion implantation but by an epitaxial film. Therefore, since variations due to ion implantation do not occur, variations in threshold voltage can be reduced.

  In the above method for manufacturing a silicon carbide semiconductor device, preferably, the first conductivity type is n-type.

  As a result, the conductivity type of the channel layer becomes n-type. Therefore, electrons having a higher mobility than holes can be used as main carriers flowing in the channel layer. Therefore, the on-resistance is reduced.

  In the above method for manufacturing a silicon carbide semiconductor device, an epitaxial layer having the second conductivity type is preferably formed on the silicon carbide layer. The step of providing the source region and the drain region is performed so that each of the source region and the drain region penetrates the epitaxial layer.

  Thereby, since the RESURF structure is provided on the channel layer by the epitaxial layer, the breakdown voltage is higher than that in the case where there is no RESURF structure. Therefore, the impurity concentration of the channel layer can be made relatively high. Thereby, the on-resistance can be further reduced.

  Preferably, in the above method for manufacturing a silicon carbide semiconductor device, each of the first and second layers has first and second impurity concentrations. The second impurity concentration is higher than the first impurity concentration.

  Since the threshold voltage is mainly determined by the first impurity concentration of the first layer, the first impurity concentration is determined by the required threshold voltage. On the other hand, the second impurity concentration of the second layer has a smaller influence on the threshold voltage than the first impurity concentration of the first layer. Therefore, by making the second impurity concentration higher than the first impurity concentration, the on-resistance can be lowered without significantly affecting the threshold voltage.

  Preferably, in the method for manufacturing the silicon carbide semiconductor device described above, the step of forming the gate region is such that the dimension along the facing direction of the gate region decreases as the distance from the main surface increases in a cross-sectional view including the thickness direction and the facing direction. To be done.

  As a result, the resistance of the channel portion in the vicinity of the gate region is reduced, so that the on-resistance can be lowered.

  As described above, according to the present invention, variations in threshold voltage can be reduced by forming the gate region from an epitaxial film.

It is a cross-sectional schematic diagram which shows Embodiment 1 of the silicon carbide semiconductor device according to this invention. 2 is a flowchart for illustrating a method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. It is a cross-sectional schematic diagram which shows Embodiment 2 of the silicon carbide semiconductor device according to this invention. FIG. 16 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 15.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
As shown in FIG. 1, the silicon carbide semiconductor device in the present embodiment is an n-type JFET (Junction Field Effect Transistor) 10. JFET 10 mainly includes substrate 11, p-type layers 2 and 12, and silicon carbide layer 4. The substrate 11 has an upper surface 11A, is made of silicon carbide, and has an n-type (first conductivity type). Silicon carbide layer 4 is provided on upper surface 11A of substrate 11 through p-type layers 2 and 12, and has a main surface 13A and a thickness direction (vertical direction in the figure) intersecting main surface 13A. doing. The p-type layer 2 is an electric field relaxation layer. The p-type layer 12 is a breakdown voltage holding layer formed on the p-type layer 2. The p-type layers 2 and 12 are made of p-type SiC. The thicknesses of the p-type layer 2 and the p-type layer 12 are, for example, 0.5 μm and 10 μm, respectively. The impurity concentrations of the p-type layer 2 and the p-type layer 12 are, for example, 5 × 10 ¹⁶ and 1 × 10 ¹⁶ atoms / cm ³ , respectively.

  Although the p-type layer 2 and the p-type layer 12 are formed in FIG. 1, the p-type layer 12 may be formed directly on the upper surface 11 </ b> A of the n-type substrate 11.

  Silicon carbide layer 4 has channel layer 7, gate region 16 </ b> R, source region 15, and drain region 17.

The channel layer 7 includes a first layer 6 that is an n-type layer and a second layer 13 that is an n-type layer. The impurity concentration (second impurity concentration) of the second layer 13 is higher than the impurity concentration (first impurity concentration) of the first layer 6. For example, the impurity concentrations of the first layer 6 and the second layer 13 are 1 × 10 ¹⁷ atoms / cm ³ and 2 × 10 ¹⁷ atoms / cm ³ , respectively. The film thicknesses of the first layer 6 and the second layer 13 are, for example, 0.1 μm and 0.2 μm.

  Each of source region 15 and drain region 17 extends from main surface 13A into channel layer 7 along the thickness direction. A part of the channel layer 7 is sandwiched between the source region 15 and the drain region 17 in the opposing direction (lateral direction in the figure) intersecting the thickness direction.

Gate region 16R extends between source region 15 and drain region 17 so as to protrude from main surface 13A into channel layer 7 along the thickness direction. In the present embodiment, the gate region 16R extends through the second layer 13 and onto the first layer 6. Gate region 16R is epitaxially grown with respect to channel layer 7 so as to have a p-type (second conductivity type). The thickness of the gate region 16R is, for example, 0.4 μm. The impurity concentration of the gate region 16R is, for example, 1 × 10 ¹⁸ atoms / cm ³ .

An epitaxial layer 14 having p type (second conductivity type) is formed on silicon carbide layer 4. The epitaxial layer 14 is connected between the source region 15 and the drain region 17 along the horizontal direction in the drawing on the channel layer 7. The thickness of the epitaxial layer 14 is, for example, 0.2 μm. The impurity concentration of the epitaxial layer 14 is, for example, 1 × 10 ¹⁷ atoms / cm ³ .

  In the epitaxial layer 14 and the channel layer 7, a source region 15 and a drain region 17 containing impurities having an n conductivity type (n-type impurity) at a higher concentration than the channel layer 7 are formed. A gate region 16 </ b> R containing impurities having a p-type conductivity (p-type impurity) at a higher concentration than the p-type layer 12 and the epitaxial layer 14 is formed so as to be sandwiched between the drain regions 17. That is, the source region 15, the gate region 16R, and the drain region 17 are formed so as to penetrate the epitaxial layer 14 and reach the channel layer 7, respectively. Further, the bottoms of the source region 15, the gate region 16 </ b> R, and the drain region 17 are spaced from the upper surface of the p-type layer 12 (the boundary between the p-type layer 12 and the channel layer 7) inside the channel layer 7. Has been placed.

  Further, on the side opposite to the gate region 16 </ b> R when viewed from the source region 15, the epitaxial layer 14 penetrates the epitaxial layer 14 from the upper surface of the epitaxial layer 14 (the main surface opposite to the channel layer 7 side) to the channel layer 7. The groove part 31 is formed so that it may reach. That is, the bottom wall of the groove 31 is located inside the channel layer 7 with a gap from the interface between the p-type layer 12 and the channel layer 7. Further, a potential holding region 23 containing a p-type impurity having a higher concentration than the p-type layer 12 and the epitaxial layer 14 is formed so as to penetrate the channel layer 7 from the bottom wall of the trench 31 and reach the p-type layer 12. Yes. The bottom of the potential holding region 23 is spaced apart from the upper surface of the n-type substrate 11 (the boundary between the n-type substrate 11 and the p-type layer 2) (more specifically, the p-type layer 2 and the p-type layer). The p-type layer 12 is disposed at a distance from the boundary with the layer 12.

  Further, a contact electrode 19 is formed so as to be in contact with the upper surfaces of the source region 15, the gate region 16 </ b> R, the drain region 17, and the potential holding region 23. The contact electrode 19 is made of a material that can make ohmic contact with the source region 15, the gate region 16R, the drain region 17, and the potential holding region 23, for example, NiSi (nickel silicide).

  An oxide film 18 is formed between adjacent contact electrodes 19. More specifically, an oxide film 18 as an insulating layer is formed on the upper surface of the epitaxial layer 14 and the bottom wall and side wall of the groove 31 so as to cover the entire region other than the region where the contact electrode 19 is formed. ing. As a result, the adjacent contact electrodes 19 are insulated from each other.

  Furthermore, a source electrode 25, a gate electrode 26, and a drain electrode 27 are formed so as to be in contact with the upper surfaces of the contact electrodes 19 on the source region 15, the gate region 16R, and the drain region 17, respectively. Thereby, the source electrode 25, the gate electrode 26, and the drain electrode 27 are electrically connected to the source region 15, the gate region 16R, and the drain region 17 through the contact electrode 19, respectively. The source electrode 25 is also in contact with the upper surface of the contact electrode 19 on the potential holding region 23 and is also electrically connected to the potential holding region 23 through the contact electrode 19. That is, the source electrode 25 is formed to extend from the upper surface of the contact electrode 19 on the source region 15 to the upper surface of the contact electrode 19 on the potential holding region 23. As a result, the contact electrode 19 on the potential holding region 23 is held at the same potential as the contact electrode 19 on the source region 15. The source electrode 25, the gate electrode 26, and the drain electrode 27 are made of a conductor such as aluminum (Al).

  In the JFET 10 shown in FIG. 1, an insulating protective film 28 made of an insulator is formed so as to cover the oxide film 18 and the gate electrode 26 and to fill a region between the source electrode 25 and the drain electrode 27. ing. In the insulating protective film 28, openings 33 and 34 are formed in a region on the source region 15 and the potential holding region 23 and a region on the drain region 17, respectively. The source electrode 25 and the drain electrode 27 are disposed inside the openings 33 and 34. The upper surfaces of the source electrode 25 and the drain electrode 27 are located above the upper surface of the insulating protective film 28 (that is, the upper portions of the source electrode 25 and the drain electrode 27 protrude from the upper surface of the insulating protective film 28, respectively. ing).

  Next, the operation of the case where the JFET 10 is a normally-on type, for example, will be described. Referring to FIG. 1, when the potential of gate electrode 26 is 0V, channel layer 7 is sandwiched between drain region 17 and gate region 16 </ b> R, and sandwiched between the sandwiched region and p-type layer 12. The region sandwiched between the gate region 16R and the p-type layer 12 is not depleted, and the source region 15 and the drain region 17 are electrically connected via the channel layer 7. It has become. Therefore, when an electric field is applied between the source electrode 25 and the drain electrode 27, electrons move between the source region 15 and the drain region 17, thereby causing a current between the source electrode 25 and the drain electrode 27. Flows (ON state).

  On the other hand, when a negative voltage is applied to the gate electrode 26, the depletion of the drift region (the channel layer 7 located between the gate region 16R and the drain region 17) to which the electrons should move proceeds. As a result, the source region 15 and the drain region 17 are electrically cut off. For this reason, electrons cannot move between the source region 15 and the drain region 17 and no current flows (OFF state). Here, the JFET 10 in the present embodiment is a RESURF type JFET in which an epitaxial layer 14 (resurf layer) is formed so as to be in contact with the channel layer 7. Therefore, in the off state, the depletion layer extends in the vertical direction (thickness direction) from the interface between the channel layer 7 and the epitaxial layer 14. As a result, the electric field distribution in the drift region becomes uniform, the electric field concentration near the gate region 16R is relaxed, and the breakdown voltage is improved.

  Next, with reference to FIGS. 2-14, the manufacturing method of JFET10 which is the silicon carbide semiconductor device in Embodiment 1 is demonstrated.

  Referring to FIG. 2, in the method of manufacturing JFET 10 in the first embodiment, first, a substrate preparation step is performed as a step (S10). In the present embodiment, an n-type substrate 11 is used.

Next, with reference to FIG. 2 and FIG. 3, a 1st layer formation process is implemented as process (S20). Specifically, the p-type layer 2 and the p-type layer 12 made of SiC, for example, are formed sequentially on the upper surface 11A of the n-type substrate 11 by vapor phase epitaxial growth. In vapor phase epitaxial growth, for example, silane (SiH ₄ ) gas and propane (C ₃ H ₈ ) gas can be used as a material gas, and hydrogen (H ₂ ) gas can be used as a carrier gas. As a p-type impurity source for forming the p-type layer, for example, diborane (B ₂ H ₆ ) or trimethylaluminum (TMA) can be employed.

An n-type (first conductivity type) first layer 6 made of SiC, for example, is formed on the p-type layer 12 by vapor phase epitaxial growth. As the n-type impurity for forming the first layer 6, for example, nitrogen (N ₂ ) can be employed.

Next, with reference to FIG. 2, a gate layer formation process is implemented as process (S30). In this step, referring to FIG. 3, gate layer 16 made of SiC is formed on first layer 6 by vapor phase epitaxial growth, for example. In vapor phase epitaxial growth, for example, silane (SiH ₄ ) gas and propane (C ₃ H ₈ ) gas can be used as a material gas, and hydrogen (H ₂ ) gas can be used as a carrier gas. As a p-type impurity source for forming the p-type layer, for example, diborane (B ₂ H ₆ ) or trimethylaluminum (TMA) can be employed.

Next, referring to FIG. 2, a gate region forming step is performed as a step (S35).
First, referring to FIG. 4, mask 5 is formed at a position where gate region 16R (FIG. 1) on gate layer 16 is to be formed. The mask 5 is made of a resist, for example. Next, the gate region 16R is formed on a part of the first layer 6 by patterning the gate layer 16. Specifically, referring to FIG. 5, gate region 16 </ b> R is formed by dry etching using mask 5. Dry etching can be performed using, for example, SF ₆ . At this time, over-etching may be performed as shown by a broken line in FIG. That is, a part of the surface of the first layer 6 may be removed.

  Next, with reference to FIG. 2, a 2nd layer formation process is implemented as process (S40). In this step, the second layer 13 having n-type (first conductivity type) is epitaxially formed on the first layer 6 provided with the gate region 16R. Specifically, referring to FIG. 6, an n-type layer (second layer 13) made of SiC, for example, is formed by vapor phase epitaxial growth so as to cover gate region 16R. The second layer 13 is formed so as to cover the upper surface and side surfaces of the gate region 16R. The second layer 13 is also formed on the upper surface of the first layer 6.

  Next, with reference to FIG. 2, a silicon carbide layer formation process is implemented as process (S45). Specifically, as shown in FIG. 7, the second layer 13 located on the gate region 16R is removed, and the upper portion of the gate region 16R is exposed. At this time, a part of the second layer 13 other than the upper part of the gate region 16R may be removed at the same time. The removal of the second layer 13 can be performed by, for example, etch back. As described above, silicon carbide layer 4 having gate region 16R penetrating second layer 13 between main surface 13A and first layer 6 is formed.

  Next, as shown in FIG. 8, epitaxial layer 14 having p type (second conductivity type) is formed on silicon carbide layer 4. Specifically, the epitaxial layer 14 is formed on the gate region 16R and the second layer 13.

Next, with reference to FIG. 2, a groove part formation process is implemented as process (S50). Specifically, as shown in FIG. 9, the groove 31 is formed so as to penetrate from the upper surface 14 </ b> A of the epitaxial layer 14 to the channel layer 7 through the epitaxial layer 14. The formation of the groove 31 can be performed by, for example, dry etching using SF ₆ gas, for example, after forming a mask layer having an opening at a position where the desired groove 31 is formed on the upper surface of the epitaxial layer 14.

  Next, a first ion implantation step is performed as a step (S60). In this step, a potential holding region (base contact region) that is a region containing a high concentration p-type impurity is formed. Specifically, referring to FIG. 9, first, a resist is applied on the upper surface of epitaxial layer 14 and the inner wall of groove portion 31, and then exposure and development are performed to obtain desired gate region 16R and potential holding region. A resist film (not shown) having an opening in a region corresponding to the planar shape of 23 is formed. Then, using this resist film as a mask, p-type impurities such as Al (aluminum) and B (boron) are introduced into the channel layer 7 and the p-type layer 12 by ion implantation. Thereby, the potential holding region 23 is formed.

  Next, a second ion implantation step is performed as a step (S70). In this step, a source region 15 and a drain region 17 that are regions containing high-concentration n-type impurities are formed. Specifically, referring to FIG. 10, first, a resist film (not shown) having openings in regions corresponding to the planar shape of desired source region 15 and drain region 17 in the same procedure as in step (S60). ) Is formed. Then, using this resist film as a mask, n-type impurities such as P (phosphorus) and N (nitrogen) are introduced into the epitaxial layer 14 and the channel layer 7 by ion implantation. Thereby, the source region 15 and the drain region 17 are formed. In the present embodiment, the source region 15 and the drain region 17 are formed in contact with the epitaxial layer 14. In other words, the epitaxial layer 14 is formed on the channel layer 7 so as to connect between the source region 15 and the drain region 17 along the horizontal direction in the drawing.

  Next, referring to FIG. 2, an activation annealing step is performed as a step (S80). In this step, after the resist film formed in the step (S70) is removed, the epitaxial layer 14, the channel layer 7 and the p-type layer 12 in which the ion implantation is performed in the step (S60) and the step (S70) are heated. As a result, activation annealing, which is a heat treatment for activating the impurities introduced by the ion implantation, is performed. The activation annealing can be performed, for example, by performing a heat treatment that is held at a temperature of about 1700 ° C. for about 30 minutes in an argon gas atmosphere.

Next, as a step (S90), an oxide film forming step is performed. In this step (S90), referring to FIG. 11, steps (S10) to (S80) are performed, and epitaxial layer 14, channel layer 7, p-type layer 12, and p-type including a desired ion implantation layer are performed. The n-type substrate 11 on which the layer 2 is formed is thermally oxidized. Thereby, an oxide film 18 made of silicon dioxide (SiO ₂ ) is formed so as to cover the upper surface 14 A of the epitaxial layer 14 and the inner wall of the groove 31.

  Next, with reference to FIG. 2, a contact electrode formation process is implemented as process (S100). In this step, referring to FIG. 12, contact electrode 19 made of, for example, NiSi is formed so as to be in contact with the upper surfaces of source region 15, gate region 16R, drain region 17, and potential holding region 23, respectively. Specifically, first, a resist film (not shown) having an opening in a region corresponding to the planar shape of the desired contact electrode 19 is formed by the same procedure as in the step (S60). Then, using the resist film as a mask, oxide film 18 on source region 15, gate region 16R, drain region 17, and potential holding region 23 is removed by, for example, RIE (Reactive Ion Etching). .

  Thereafter, for example, Ni (nickel) is deposited, thereby forming a nickel layer on the source region 15, the gate region 16R, the drain region 17, the potential holding region 23, and the resist film exposed from the oxide film 18. Further, by removing the resist film, the nickel layer on the resist film is removed (lifted off), and the nickel is formed on the source region 15, the gate region 16 R, the drain region 17, and the potential holding region 23 exposed from the oxide film 18. The layer remains. Then, the nickel layer is silicided by performing a heat treatment to be heated to a predetermined temperature (for example, 950 ° C.) in a temperature range of, for example, 900 ° to 1000 ° C. As a result, as shown in FIG. 12, a contact electrode 19 which is an ohmic electrode made of NiSi capable of making ohmic contact with the source region 15, the gate region 16R, the drain region 17 and the potential holding region 23 is formed.

  Next, with reference to FIG. 2, an electrode formation process is implemented as process (S110). In this step, first, referring to FIG. 13, a gate electrode 26 is formed in contact with the upper surface of contact electrode 19 on gate region 16R. For example, after forming a resist film (not shown) having an opening in a desired region where the gate electrode 26 is to be formed and depositing Al, Al on the resist film is removed together with the resist film (lift-off).

Next, referring to FIG. 14, an insulating protective film 28 made of an insulator such as SiO ₂ is formed so as to cover gate electrode 26, contact electrode 19 and oxide film 18. Specifically, for example, by CVD (Chemical Vapor Deposition), contact electrode 19 disposed on gate electrode 26, source region 15, drain region 17, and potential holding region 23, and oxide film, respectively. An insulating protective film 28 (see FIG. 14) made of a SiO ₂ film covering 18 is formed.

  Next, referring again to FIG. 1, source electrode 25 that contacts the upper surface of contact electrode 19 on source region 15 and potential holding region 23, and drain that contacts the upper surface of contact electrode 19 on drain region 17. Electrode 27 is formed.

  Specifically, first, openings 33 and 34 are formed in the insulating protective film 28 in regions located on the source region 15, the drain region 17, and the potential holding region 23 by using a photolithography method. As a method of forming the openings 33 and 34, for example, a resist film (not shown) having an opening similar to the planar shape of the openings 33 and 34 is formed on the main surface of the insulating protective film 28, and this resist film As a mask, a part of the insulating protective film 28 is removed by etching or the like. In this way, the openings 33 and 34 are formed in the insulating protective film 28 as shown in FIG. Next, the resist film (not shown) is removed by any conventionally known method.

  Then, the source electrode 25 and the drain electrode 27 are formed. For example, after forming a resist film (not shown) having openings in desired regions (regions where the openings 33 and 34 are formed) where the source electrode 25 and the drain electrode 27 are to be formed, and depositing Al, Al on the resist film is removed together with the resist film (lift-off).

  Note that as the resist film used for forming the source electrode 25 and the drain electrode 27, the resist film used for forming the openings 33 and 34 may be used. That is, after forming the openings 33 and 34 by etching using the resist film as a mask as described above, the conductor film constituting the electrode such as Al is formed as described above without removing the resist film. Then, the source electrode 25 and the drain electrode 27 may be formed inside the openings 33 and 34 by lift-off.

The JFET 10 in the present embodiment is completed through the above steps.
Next, the effect of this Embodiment is demonstrated.

  If the gate region 16R is formed by ion implantation, it is difficult to control the depth of ion implantation. Therefore, variations in the thickness of the channel layer 7 immediately below the gate region 16R, and the boundary region between the gate region 16R and the channel layer 7 are obtained. The variation in impurity concentration becomes large. Therefore, the threshold voltage varies greatly. On the other hand, according to the present embodiment, the gate region 16R is formed not by ion implantation but by an epitaxial film. Therefore, the above variation due to ion implantation does not occur. Therefore, variation in threshold voltage can be reduced. As a result, it is possible to manufacture a transistor that does not flow current when the gate voltage is 0, that is, a so-called normally-off transistor.

  If the gate region 16R is fabricated by ion implantation, the impurity concentration in the boundary region between the gate region 16R and the channel layer 7 changes gradually. On the other hand, according to the present embodiment, since the gate region 16R is formed of an epitaxial film, the change in the impurity concentration in the boundary region between the gate region 16R and the channel layer 7 can be made steep.

  The channel layer 7 is n-type. Therefore, electrons having a higher mobility than holes can be used as main carriers flowing in the channel layer. Therefore, the on-resistance is reduced.

  Further, on the channel layer 7 provided with the gate region 16R, the source region 15 and the drain region 17 are connected by the epitaxial layer 14 along the facing direction (lateral direction in the figure). Thereby, since the RESURF structure is provided on the channel layer 7 by the epitaxial layer 14, the breakdown voltage is increased as compared with the case where there is no RESURF structure. Therefore, the impurity concentration of the channel layer can be made relatively high. Thereby, the on-resistance can be further reduced.

  In addition, the impurity concentration (second impurity concentration) of the second layer 13 is higher than the impurity concentration (first impurity concentration) of the first layer 6. Since the threshold voltage is mainly determined by the impurity concentration of the first layer 6 (first impurity concentration), the first impurity concentration is determined by the required threshold voltage. On the other hand, the impurity concentration of the second layer 13 has a smaller influence on the threshold voltage than the first impurity concentration. Therefore, by making the second impurity concentration higher than the first impurity concentration, the on-resistance can be lowered without significantly affecting the threshold voltage.

(Embodiment 2)
Referring to FIG. 15, the JFET 20 according to the second embodiment of the present invention has substantially the same structure as that of JFET 10 (FIG. 1), but an inverted trapezoidal gate is used instead of the rectangular gate region 16R (FIG. 1). It has area | region 16S (FIG. 15). In the inverted trapezoid, the width of the gate region 16S decreases from the main surface 13A of the channel layer 7 toward the substrate 11, and the gate region 16S has a finite width on the side closest to the substrate 11 of the gate region 16S. It is that.

  The shape of the gate region 16S is such that the dimension along the opposing direction (lateral direction in the drawing) of the gate region 16S in the cross-sectional view including the thickness direction and the opposing direction (field of view in FIG. 15) is from the main surface 13A. What is necessary is just to be formed so that it may become small as it leaves | separates, and it is not restricted to an inverted trapezoid. For example, the shape of the gate region 16S on the substrate 11 side may be rounded.

  The manufacturing method of JFET 20 is substantially the same as the manufacturing method shown in FIGS. 2 to 14 (Embodiment 1). The difference from the manufacturing method of the first embodiment is that an inverted trapezoidal gate region 16S is formed as shown in FIG. 16 instead of the step of FIG. Such a shape can be formed by, for example, ion milling.

  According to the present embodiment, the dimension along the facing direction (lateral direction in the figure) of gate region 16S decreases as the distance from main surface 13A increases. Thereby, the resistance of the channel portion in the vicinity of the gate region 16S is reduced, so that the on-resistance can be lowered.

  Note that a form in which the n-type and the p-type in each of the above embodiments are interchanged may be used. In this case, a p-type JFET is configured instead of the n-type JFET.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the embodiments and examples described above but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.

  2, 12 p-type layer, 4 silicon carbide layer, 5 mask, 6 first layer, 7 channel layer, 10 JFET, 11 n-type substrate (substrate), 11A upper surface, 13 second layer, 13A main surface, 14 epitaxial layer, 14A upper surface, 15 source region, 16R, 16S gate region, 17 drain region, 18 oxide film, 19 contact electrode, 23 potential holding region, 25 source electrode, 26 gate electrode, 27 drain electrode, 28 insulation protection Membrane, 31 groove, 33, 34 opening.

Claims (10)

A substrate,
A silicon carbide layer provided on the substrate and having a main surface and a thickness direction intersecting the main surface;
The silicon carbide layer is
A channel layer having a first conductivity type;
A source region having the first conductivity type and extending from the main surface along the thickness direction into the channel layer;
The channel layer having the first conductivity type, extending from the main surface along the thickness direction into the channel layer, and between the source region in an opposing direction intersecting the thickness direction A drain region sandwiching
A gate region extending between the source region and the drain region so as to protrude from the main surface into the channel layer along the thickness direction;
The silicon carbide semiconductor device, wherein the gate region is epitaxially grown with respect to the channel layer so as to have a second conductivity type different from the first conductivity type.   The silicon carbide semiconductor device according to claim 1, wherein the first conductivity type is an n-type.   The epitaxial layer having the second conductivity type and further connecting the source region and the drain region along the facing direction on the channel layer provided with the gate region. The silicon carbide semiconductor device described in 1.   The channel layer includes a first layer having a first impurity concentration, and a second layer provided on the first layer and penetrating through the gate region and having a second impurity concentration. The silicon carbide semiconductor device according to claim 1, wherein the second impurity concentration is higher than the first impurity concentration.   The cross-sectional view including the thickness direction and the facing direction has a dimension along the facing direction of the gate region that decreases as the distance from the main surface increases. Silicon carbide semiconductor device. Epitaxially forming a first layer having a first conductivity type on a substrate;
Epitaxially forming a gate layer having a second conductivity type different from the first conductivity type on the first layer;
Forming a gate region on a portion of the first layer by patterning the gate layer;
Epitaxially forming a second layer having the first conductivity type on the first layer provided with the gate region;
A channel layer having the first and second layers on the substrate by removing a portion of the second layer located on the gate region, and the gate region penetrating the second layer And forming a silicon carbide layer having a main surface and a thickness direction intersecting the main surface;
Providing a source region and a drain region in the silicon carbide layer,
The step of providing the source region and the drain region is such that each of the source region and the drain region has the first conductivity type and extends from the main surface into the channel layer along the thickness direction. And the source region and the drain region extend between the source region and the drain region so as to protrude into the channel layer in a facing direction intersecting the thickness direction. A method for manufacturing a silicon carbide semiconductor device, wherein the silicon carbide semiconductor device is sandwiched.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the first conductivity type is an n-type.   The method further includes forming an epitaxial layer having the second conductivity type on the silicon carbide layer, and the step of providing the source region and the drain region includes the source region and the drain region penetrating the epitaxial layer. The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the method is performed as described above.   Each of the first and second layers has first and second impurity concentrations, and the second impurity concentration is higher than the first impurity concentration. 2. A method for manufacturing a silicon carbide semiconductor device according to item 1.   The step of forming the gate region is performed so that a dimension along the facing direction of the gate region decreases as the distance from the main surface increases in a cross-sectional view including the thickness direction and the facing direction. Item 10. A method for manufacturing a silicon carbide semiconductor device according to any one of Items 6 to 9.

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