JP2013077966A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit in which accurate frequency control of an output clock signal can be performed easily.SOLUTION: A PLL circuit comprises a charge pump which is configured to output an outflow or inflow output current and in which ON/OFF of the output current is switched according to a pulse signal, and a pulse signal generator which generates the pulse signal according to a multi-value reference signal having cyclicity. The PLL circuit is configured to generate an output clock signal according to the output current. The PLL circuit further comprises a current amount adjusting section which adjusts the amount of the output current according to the reference signal.

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit that generates a clock signal.

  Conventionally, PLL circuits are used in various electrical devices. Here, with respect to the configuration of the conventional PLL circuit, a PLL circuit in a format that mainly processes analog signals (analog format) and a PLL circuit in a format that mainly processes digital signals (digital format) are given as examples. Briefly explain.

  FIG. 11 is a block diagram of the analog PLL circuit 100. As shown in FIG. As shown in the figure, the PLL circuit 100 includes a comparator (phase frequency comparator) 101, a charge pump 102, a low-pass filter 103, a voltage controlled oscillation circuit 104, and a frequency divider 105.

  The comparator 101 receives the reference frequency signal and the output signal of the frequency divider 105, and outputs a pulse signal UP or a pulse signal DN according to the result of the phase comparison. The charge pump 102 outputs an outflow or inflow output current, and the on / off of the outflow output current is switched according to the pulse signal UP, and the inflow output current is turned on according to the pulse signal DN. / Off is configured to be switched.

  The low-pass filter 103 is provided on the output side of the charge pump 102, performs low-pass filter processing on the input voltage, and outputs it to the voltage controlled oscillation circuit 104. The voltage controlled oscillation circuit 104 generates a clock signal having a frequency corresponding to the output voltage of the low-pass filter 103 as the output clock signal Sout.

  The generated output clock signal Sout is output to the outside of the PLL circuit 100 and input to the frequency divider 105. The output clock signal Sout input to the frequency divider 105 is output to the comparator 101 after being subjected to frequency division processing. According to the PLL circuit 100, for example, when the reference frequency signal is 1 MHz and the frequency divider 105 performs frequency division by 2, the output clock signal Sout of 2 MHz can be obtained.

  However, according to the PLL circuit 100, when a digital signal (for example, a signal after AD conversion) is input as a reference frequency signal, it is difficult to appropriately perform the phase comparison described above. On the other hand, FIG. 12 shows a configuration diagram of a digital-type PLL circuit 200. As shown in the figure, the PLL circuit 200 includes a counter A, a counter B, and a comparator 201 configured as digital circuits instead of the comparator 101 and the frequency divider 105.

  The counter A counts the clock of the reference frequency signal, and the counter B counts the clock of the output clock signal Sout. The comparator 201 outputs a pulse signal UP or a pulse signal DN according to the magnitude relationship between the count results of the counters.

  FIG. 13 schematically illustrates the operation of each counter when a 2 MHz output clock signal Sout is obtained from a 1 MHz reference frequency signal. As shown in the figure, the counter A repeats counting up to 100, and the counter B operates to repeat counting up to 200. The comparator 201 outputs the pulse signal UP or the pulse signal DN so as to eliminate the deviation when the deviation occurs at the timing of repeating the counting up of each counter.

JP 2008-72469 A Japanese Patent No. 3022870

  According to the above-described digital PLL circuit, the frequency of the output clock signal can be freely changed by controlling the digital circuit with an FPGA or the like, or changing the count number of the counter.

  However, according to such a digital format, the frequency of the pulse signal UP and the pulse signal DN decreases (in the example shown in FIG. 13, it is about 1/100 of the reference frequency signal), and the output clock signal It may be difficult to accurately perform the frequency control.

  In view of the above-described problems, an object of the present invention is to provide a PLL circuit that makes it easy to accurately control the frequency of an output clock signal.

  In order to achieve the above object, a PLL circuit according to the present invention outputs an outflow or inflow output current, and has a charge pump capable of switching on / off of the output current in accordance with a pulse signal, and a periodicity. A pulse signal generation unit that generates the pulse signal according to a multi-level reference signal, and generates an output clock signal according to the output current, the PLL circuit according to the reference signal A current amount adjusting unit that adjusts the amount of output current is used.

  According to this configuration, since the amount of the output current of the charge pump is adjusted according to the reference signal, it is easy to accurately control the frequency of the output clock signal.

  More specifically, the reference signal may be a digital signal representing a sine wave. More specifically, as the above configuration, the pulse signal generation circuit generates, as the pulse signal, an UP signal for switching on / off of the outflow and a DN signal for switching on / off of the inflow. Also good.

  More specifically, as the above configuration, a low-pass filter provided on the output side of the charge pump, and a voltage-controlled oscillation circuit that generates a clock signal having a frequency corresponding to the output voltage of the low-pass filter as the output clock signal It is good also as a structure provided with these.

  Further, in the PLL circuit configured as described above, which generates a target waveform signal representing a target waveform of the reference signal, the current amount adjustment unit calculates the current amount according to a difference value between the reference signal and the target waveform signal. It is good also as a structure to adjust.

  More specifically, the current amount adjustment unit may perform the adjustment so that the current amount increases as the absolute value of the difference value increases. More specifically, the pulse signal generation circuit may be configured to determine which of the UP signal and the DN signal is generated according to the sign of the difference between the reference signal and the target waveform signal. Good.

  More specifically, the current amount adjustment unit may adjust the current amount according to an integral value of the reference signal. More specifically, the pulse signal generation circuit may determine whether to generate an UP signal or a DN signal according to the sign of the integral value of the reference signal.

  Further, in the PLL circuit having the above-described configuration that specifies the zero-cross timing, which is the timing at which the reference signal should be zero-crossed, the current amount adjusting unit, according to the difference value between the reference signal and zero at the zero-cross timing, The current amount may be adjusted. More specifically, in the above configuration, the pulse signal generation circuit determines which of the UP signal and the DN signal is generated according to the sign of the difference between the reference signal and zero at the zero cross timing. It is good.

  More specifically, the above configuration may include a moving average calculation circuit that performs a moving average calculation process on the reference signal. More specifically, the above configuration may include a band pass filter that performs a filtering process on the reference signal.

  As described above, according to the PLL circuit of the present invention, the amount of output current of the charge pump is adjusted according to the reference signal, so that it is easy to accurately control the frequency of the output clock signal.

1 is a configuration diagram of a PLL circuit according to an embodiment of the present invention. It is a lineblock diagram of a charge pump concerning an embodiment of the present invention. 1 is a configuration diagram of a CP control circuit according to a first embodiment. FIG. It is explanatory drawing in connection with operation | movement of CP control circuit which concerns on 1st Embodiment. It is explanatory drawing in connection with operation | movement of CP control circuit which concerns on 2nd Embodiment. It is a block diagram of the CP control circuit which concerns on 3rd Embodiment. It is explanatory drawing in connection with operation | movement of CP control circuit which concerns on 3rd Embodiment. It is a block diagram of CP control circuit which concerns on 4th Embodiment. It is explanatory drawing in connection with operation | movement of CP control circuit which concerns on 4th Embodiment. It is a block diagram of CP control circuit which concerns on 5th Embodiment. It is a block diagram of a conventional analog PLL circuit. It is a block diagram of the conventional digital form PLL circuit. It is explanatory drawing regarding operation | movement of a counter.

  Embodiments of the present invention will be described below by taking each of the first to fifth embodiments as an example.

1. First Embodiment [Overall Configuration of PLL Circuit]
First, the first embodiment will be described. FIG. 1 is a configuration diagram of a PLL circuit 9 according to the present embodiment. As shown in the figure, the PLL circuit 9 includes a sine wave generator 1, an AD converter 2, a charge pump control circuit (hereinafter referred to as "CP control circuit") 3, a charge pump 4, a low-pass filter 5, and a voltage controlled oscillation circuit. 6 and a zero-cross signal generation circuit 7.

  The sine wave generation unit 1 generates an analog signal of a sine wave (sine wave) with a predetermined period and outputs the analog signal to the AD converter 2 on the rear stage side. The AD converter 2 performs AD [Analog to Digital] conversion on the analog signal received from the preceding stage, and sends the converted digital signal (digital signal representing a sine wave) to the CP control circuit 3 as a reference signal Sref. .

  In the PLL circuit 9, instead of providing the sine wave generator 1 and the AD converter 2, a signal corresponding to the reference signal Sref may be input from the outside. The reference signal Sref is a multi-value signal having periodicity, and may be in a form different from a sine wave. Here, the “multilevel signal” in the present application is a signal having at least three or more values, and is a concept that does not include a binary pulse signal. Since the reference signal Sref has periodicity, it can be regarded as a kind of clock signal (reference clock signal).

  The CP control circuit 3 is a digital circuit that generates the pulse signal UP, the pulse signal DN, and the adjustment signal SEL based on the reference signal Sref. The CP control circuit 3 controls the operation of the charge pump 4 by sending these signals to the charge pump 4. The pulse signal UP and the pulse signal DN are binary (H level and L level) pulse signals, and each value represents either on or off. The more detailed configuration of the CP control circuit 3 will be described again.

  The charge pump 4 outputs an outflow or inflow output current, and the outflow is switched on / off according to the pulse signal UP, and the inflow is switched on / off according to the pulse signal DN. It is formed as follows.

  That is, when the pulse signal UP is on, the charge pump 4 causes the current to flow out from itself (ie, output an “outflow” output current), and when the pulse signal DN is on. In addition, the operation is performed so that a current flows from the output side to itself (that is, an “inflow” output current is output). The voltage input to the low-pass filter 5 is determined by the output current of the charge pump 4.

  Further, the charge pump 4 is formed such that the amount of current when the output current is on changes according to the adjustment signal SEL. Here, a configuration example of the charge pump 4 will be described below with reference to FIG. In this example, the adjustment signal SEL includes a plurality of signals (SEL-1 to SEL-6).

  As shown in FIG. 2, the charge pump 4 includes an UP-side PMOS transistor T1 and a DOWN-side NMOS transistor T2. In the PMOS transistor T1, the pulse signal UP is inputted to the gate, and the drains of the current variable PMOS transistors T3 to T5 are commonly connected to the source. Each of the PMOS transistors T3 to T5 has a source connected to a power supply and gates supplied with signals SEL-1 to SEL-3.

  The NMOS transistor T2 has a gate to which the pulse signal DN is input, and the drains of the current varying NMOS transistors T6 to T8 are commonly connected to the source. The sources of the NMOS transistors T6 to T8 are grounded, and the signals SEL-4 to SEL-6 are supplied to the gates.

  According to the configuration shown in FIG. 2, current flows from the charge pump 4 to the low-pass filter 5 when the pulse signal UP is on. The amount of current relating to the outflow changes mainly according to the signals SEL-1 to SEL-3 (that is, depending on which of the PMOS transistors T3 to T5 is turned on).

  Further, when the pulse signal DN is on, a current flows from the low-pass filter 5 to the charge pump 4. The amount of current related to this inflow changes mainly according to the signals SEL-4 to SEL-6 (that is, depending on which of the NMOS transistors T6 to T8 is turned on). The configuration shown in FIG. 2 is an example, and the charge pump 4 may have other configurations.

  Returning to FIG. 1, the low-pass filter 5 is provided on the output side of the charge pump 4, performs low-pass filtering on the input voltage, and outputs it to the voltage-controlled oscillation circuit 6. Further, the voltage controlled oscillation circuit 6 generates a clock signal (square wave) having a frequency corresponding to the output voltage of the low pass filter 5 as the output clock signal Sout. The generated output clock signal Sout is output to the outside of the PLL circuit 9 and used for various purposes.

  Note that the PLL circuit 9 uses a predetermined mechanism (a mechanism that counts and compares the clocks of the reference signal Sref and the output clock signal Sout, a mechanism that uses a frequency divider, or the like) as a reference signal Sref. An output clock signal Sout is generated so as to have a corresponding frequency. In this embodiment, as an example, it is assumed that a 2 MHz output clock signal Sout obtained by multiplying the 125 kHz reference signal Sref by 16 is generated.

  A signal of the reference clock CL is input to the AD converter 2, the CP control circuit 3, and the zero cross signal generation circuit 7. The AD converter 2 performs AD conversion at the cycle of the reference clock CL, and the CP control circuit 3 performs a predetermined operation (details will be described later) according to the reference clock CL.

  Note that the output clock signal Sout may be used as the reference clock CL signal, or a separately generated clock signal may be used. In the following description, the frequency of the reference clock CL is assumed to be 16 times the reference signal Sref.

  The zero cross signal generation circuit 7 detects a zero cross timing (a timing at which the reference signal Sref should become a zero cross), and outputs a signal representing the zero cross timing to the CP control circuit 3. For example, the zero-cross signal generation circuit 7 first detects the sign inversion of the reference signal Sref to detect the timing of the first zero-cross, and then uses the reference clock CL to cycle the reference signal Sref (16 times in this embodiment). It is possible to detect the zero-cross timing permanently by counting the reference clock CL). Note that the zero-cross signal generation circuit 7 may not be provided when the zero-cross timing information is unnecessary in the processing performed by the CP control circuit 3.

[Configuration of CP control circuit]
Next, the configuration and the like of the CP control circuit 3 will be described in detail. FIG. 3 is a configuration diagram of the CP control circuit 3. As shown in the figure, the CP control circuit 3 includes a current amount adjustment circuit 31, a pulse signal generation circuit 32, a target waveform generation circuit 33, and a comparator 34.

  The current amount adjustment circuit 31 generates an adjustment signal SEL based on an input signal (a differential signal described later in the present embodiment) and outputs the adjustment signal SEL to the charge pump 4. The pulse generation circuit 32 generates a pulse signal UP and a pulse signal DN based on an input signal (a differential signal described later in the present embodiment), and outputs it to the charge pump 4.

  The target waveform generation circuit 33 is a circuit that generates a signal having a target waveform (125 kHz sine wave in this embodiment) of the reference signal Sref. For example, the target waveform generation circuit 33 is provided with an LUT [Look up Table] that represents the value of the target waveform at the interval of the reference clock CL. By using the reference clock CL and the LUT, a target waveform signal is generated. Generate.

  The comparator 34 calculates a difference value (referred to as “difference value D1” for convenience) between the value of the reference signal Sref and the signal of the target waveform, and sends the calculated signal to the subsequent stage side as a difference signal. . The calculation in the comparator 34 is executed, for example, by using information of zero cross timing and synchronizing the reference signal Sref and the target waveform.

[Operation of CP control circuit]
Next, the operation of the CP control circuit 3 will be described in more detail. The current amount adjustment circuit 31 generates the adjustment signal SEL according to the difference value D1 represented by the difference signal. More specifically, the adjustment signal SEL is generated so that the amount of current in the charge pump 4 increases as the absolute value of the difference value D1 increases. As an example, the adjustment signal SEL is generated so that the absolute value of the difference value D1 (or a value obtained by multiplying this by a predetermined coefficient) becomes the amount of current in the charge pump 4. The adjustment signal SEL is desirably generated appropriately so that the absolute value of the difference value D1 becomes as small as possible.

  The pulse generation circuit 32 generates the pulse signal UP and the pulse signal DN according to the sign of the difference value D1 represented by the difference signal. More specifically, the pulse signal DN is turned on if the difference value D1 is positive, and is turned off otherwise. The pulse signal UP is turned on if the difference value D1 is negative, and turned off otherwise.

  In the present embodiment, the calculation of the difference value D1 by the comparator 34 is executed every period of the reference clock CL (that is, every time at the timing of the reference clock CL). Then, the content of the difference signal is updated according to the calculation result. Further, the signal generation operation (update of signal contents) by the current amount adjustment circuit 31 and the pulse generation circuit 32 is also performed in synchronization with the calculation timing.

  Here, FIG. 4 illustrates a timing chart related to the operation of the CP control circuit 3. 4 schematically shows the state of the reference signal Sref (solid line) and the target waveform (broken line) (an example in which the phase of the reference signal Sref is delayed). The lower part of FIG. The states of the pulse signal UP, the pulse signal DN, and the adjustment signal SEL are shown. Also, the alternate long and short dash line in FIG. 4 represents each timing of the reference clock CL.

  As shown in FIG. 4, in the present embodiment, the difference value D1 is calculated at the timing for each cycle of the reference clock CL (t1 to t18 are illustrated in FIG. 4), and the respective calculation results are represented by the respective signals (UP, (DN, SEL).

  As described above, the current amount adjustment circuit 31 outputs the output of the charge pump 4 according to the reference signal Sref (more specifically, according to the difference value D1 between the value of the reference signal Sref and the signal value of the target waveform). The amount of current is adjusted. For this reason, the PLL circuit 9 can reduce the absolute value of the difference value D1 more quickly than that in which such adjustment is not performed, and can accurately control the frequency of the output clock signal. Easy. As a result, even if the frequency of the pulse signal UP or the pulse signal DN is small, it is easy to reduce the deterioration of the jitter related to the output clock signal Sout.

2. Second Embodiment Next, a second embodiment will be described. The second embodiment is basically the same as the first embodiment except for the point related to the timing for calculating the difference value. In the following description, emphasis is placed on the description of parts different from the first embodiment, and description of common parts may be omitted.

  In the second embodiment, the calculation of the difference value D1 by the comparator 34 is executed only at the zero cross timing and the timings before and after the timing (in the following description, as an example, the timing before and after one cycle of the reference clock CL). . Then, the content of the difference signal is updated according to the calculation result. Further, the signal generation operation (update of signal contents) by the current amount adjustment circuit 31 and the pulse generation circuit 32 is also performed in synchronization with the calculation timing.

  Note that the zero-cross signal generation unit 7 of the second embodiment detects not only the zero-cross timing but also the timing before and after the zero-cross timing, and outputs a signal representing these timings to the CP control circuit 3. Thereby, the calculation timing of the difference value D1 can be set to only the zero cross timing and the timing before and after the zero cross timing.

  Here, FIG. 5 illustrates a timing chart related to the operation of the CP control circuit 3. The upper part of FIG. 5 schematically shows the state of the reference signal Sref (solid line) and the target waveform (dashed line) (an example in which the phase of the reference signal Sref is delayed), and the lower part of FIG. The states of the pulse signal UP, the pulse signal DN, and the adjustment signal SEL are shown. In addition, a one-dot chain line in FIG. 5 represents each timing of the reference clock CL.

  As shown in FIG. 5, in the second embodiment, the difference value D1 is calculated only at the zero crossing timing and the timings before and after that (t1 to t8 are illustrated in FIG. 5), and the respective calculation results are represented by the respective signals (UP , DN, SEL).

  As described above, according to the second embodiment, the calculation of the difference value D1 is omitted except for the zero cross timing and the timing before and after the zero cross timing. Therefore, even if there is an amplitude difference between the reference signal Sref and the target waveform, it is possible to suppress the influence of the amplitude difference on the calculation of the difference value D1 as much as possible. This makes it easy to reduce the deterioration of jitter in the PLL circuit 9.

3. Third Embodiment Next, a third embodiment will be described. The third embodiment is basically the same as the first embodiment except for the points related to the configuration and operation of the PC control circuit 3. In the following description, emphasis is placed on the description of parts different from the first embodiment, and description of common parts may be omitted.

  FIG. 6 is a configuration diagram of the CP control circuit 3. As shown in the figure, the CP control circuit 3 includes a current amount adjustment circuit 31, a pulse signal generation circuit 32, and an integration circuit 36.

  The current amount adjustment circuit 31 generates an adjustment signal SEL based on an input signal (in this embodiment, an integration signal described later) and outputs the adjustment signal SEL to the charge pump 4. The pulse generation circuit 32 generates a pulse signal UP and a pulse signal DN based on an input signal (in the present embodiment, an integration signal described later), and outputs the pulse signal UP and the pulse signal DN to the charge pump 4. Further, the integration circuit 36 calculates an integral value of the value of the reference signal Sref, and sends the calculated signal to the subsequent stage side as an integration signal.

  Next, the operation of the CP control circuit 3 will be described in more detail. The current amount adjustment circuit 31 generates an adjustment signal SEL according to a difference value (for convenience, “difference value D2”) between the absolute value of the integration value represented by the integration signal and the target integration amount. More specifically, the adjustment signal SEL is generated so that the amount of current in the charge pump 4 increases as the absolute value of the difference value D2 increases.

  As an example, the adjustment signal SEL is generated so that the absolute value of the difference value D2 (or a value obtained by multiplying this by a predetermined coefficient) becomes the amount of current in the charge pump 4. The target integration amount corresponds to the absolute value of the integrated value (that is, the absolute value of the expected integrated value) when the reference signal Sref is assumed to be an ideal waveform. When the reference signal Sref is an ideal waveform, the difference value D2 is zero. The adjustment signal SEL is desirably generated appropriately so that the absolute value of the difference value D2 becomes as small as possible.

  The pulse generation circuit 32 generates the pulse signal UP and the pulse signal DN according to the sign of the difference value D2. More specifically, the pulse signal DN is turned on if the difference value D2 is positive, and is turned off otherwise. The pulse signal UP is turned on if the difference value D2 is negative, and turned off otherwise.

  In the present embodiment, the integration value is calculated by the integration circuit 36 every time the zero cross timing arrives. The content of the integration signal is updated according to the calculation result. Further, the signal generation operation (update of signal contents) by the current amount adjustment circuit 31 and the pulse generation circuit 32 is also performed in synchronization with the calculation timing.

  Here, FIG. 7 illustrates a timing chart related to the operation of the CP control circuit 3. The upper part of FIG. 7 schematically shows the state of the reference signal Sref, and the lower part of FIG. 7 shows the states of the pulse signal UP, the pulse signal DN, and the adjustment signal SEL at this time. In addition, an alternate long and short dash line in FIG. 7 represents each timing of the reference clock CL.

  As shown in FIG. 7, in this embodiment, an integral value is calculated at each zero cross timing (t1 to t3 are illustrated in FIG. 7), and each calculation result is reflected in each signal (UP, DN, SEL). Has been.

  In the present embodiment, the integral value is calculated every zero cross timing, that is, every half cycle of the ideal reference signal Sref. Instead, the integral value may be calculated every cycle. In this way, the target integration amount becomes zero, so that the calculated integration value can be handled as it is as the difference value D2, and the circuit configuration of the CP control circuit 3 can be further simplified.

4). Fourth Embodiment Next, a fourth embodiment will be described. The fourth embodiment is basically the same as the first embodiment except for the points related to the configuration and operation of the PC control circuit 3. In the following description, emphasis is placed on the description of parts different from the first embodiment, and description of common parts may be omitted.

  FIG. 8 is a configuration diagram of the CP control circuit 3. As shown in the figure, the CP control circuit 3 includes a current amount adjustment circuit 31 and a pulse signal generation circuit 32. The current amount adjustment circuit 31 generates an adjustment signal SEL based on an input signal (in this embodiment, a reference signal Sref) and outputs the adjustment signal SEL to the charge pump 4. The pulse generation circuit 32 generates a pulse signal UP and a pulse signal DN based on an input signal (in this embodiment, a reference signal Sref), and outputs it to the charge pump 4.

  Next, the operation of the CP control circuit 3 will be described in more detail. The current amount adjustment circuit 31 generates the adjustment signal SEL according to the difference value between the value of the reference signal Sref and zero (for convenience, “difference value D3”). More specifically, the adjustment signal SEL is generated so that the amount of current in the charge pump 4 increases as the absolute value of the difference value D3 increases. As an example, the adjustment signal SEL is generated so that the absolute value of the difference value D3 (or a value obtained by multiplying this by a predetermined coefficient) becomes the amount of current in the charge pump 4. It is desirable that the adjustment signal is appropriately generated so that the absolute value of the difference value D3 becomes small as quickly as possible.

  The pulse generation circuit 32 generates the pulse signal UP and the pulse signal DN according to the sign of the difference value D3. More specifically, the pulse signal DN is turned on if the difference value D3 is positive, and is turned off otherwise. The pulse signal UP is turned on if the difference value D3 is negative, and turned off otherwise.

  In the present embodiment, signal generation by the current amount adjustment circuit 31 and the pulse generation circuit 32 is performed every time the zero cross timing arrives.

  Here, FIG. 9 illustrates a timing chart related to the operation of the CP control circuit 3. The upper part of FIG. 9 schematically shows the state of the reference signal Sref, and the lower part of FIG. 9 shows the states of the pulse signal UP, the pulse signal DN, and the adjustment signal SEL at this time. In addition, an alternate long and short dash line in FIG. 9 represents each timing of the reference clock CL.

  As shown in FIG. 9, in the present embodiment, integration is performed at each zero cross timing (timing at which the ideal waveform (the waveform indicated by the broken line in the drawing) becomes zero cross as illustrated in t1 to t3 in FIG. 9). A value is calculated, and each calculation result is reflected in each signal (UP, DN, SEL).

  As described above, the current amount adjustment circuit 31 determines the current amount of the output current of the charge pump 4 according to the reference signal Sref (more specifically, according to the difference value D3 between the value of the reference signal Sref and zero). It comes to adjust. For this reason, the PLL circuit 9 can reduce the absolute value of the difference value D3 more quickly than that without such adjustment, and can accurately control the frequency of the output clock signal. Easy. As a result, even if the frequency of the pulse signal UP or the pulse signal DN is small, it is easy to reduce the deterioration of the jitter related to the output clock signal Sout.

5. Fifth Embodiment Next, a fifth embodiment will be described. The fifth embodiment is basically the same as the fourth embodiment except that the moving average of the reference signal Sref is used. In the following description, emphasis is placed on the description of parts different from the fourth embodiment, and description of common parts may be omitted.

  FIG. 10 is a configuration diagram of the CP control circuit 3. As shown in the figure, the CP control circuit 3 includes a current amount adjustment circuit 31, a pulse signal generation circuit 32, and a moving average calculation circuit 37. The moving average calculation circuit 37 calculates a moving average of the values of the input reference signal Sref and sends the calculation result to the current determination circuit 31 and the pulse generation circuit 32. Note that the moving average is calculated using, for example, the value for the latest 1/8 cycle.

  The current amount adjustment circuit 31 generates an adjustment signal SEL based on an input signal (in this embodiment, a moving average of the values of the reference signal Sref), and outputs the adjustment signal SEL to the charge pump 4. The procedure for generating the adjustment signal SEL is the same as that of the fourth embodiment except that the moving average value is used instead of the value of the reference signal Sref.

  The pulse generation circuit 32 generates the pulse signal UP and the pulse signal DN based on the input signal (in this embodiment, the moving average of the value of the reference signal Sref), and outputs it to the charge pump 4. The procedure for generating the pulse signal UP and the pulse signal DN is the same as that of the fourth embodiment except that the moving average value is used instead of the value of the reference signal Sref.

  In the fifth embodiment, a moving average is calculated for the reference signal Sref, and each signal (SEL, UP, DN) is generated using this calculation result. Therefore, even when noise is included in the sine wave output from the sine wave generation unit 1, it is possible to suppress as much as possible the adverse influence of the noise on the generation of each signal (SEL, UP, DN). Is possible.

  In the fifth embodiment, the moving average calculation circuit 37 is provided in the PLL circuit 9 of the fourth embodiment. However, any of the PLL circuits 9 of the first to third embodiments is moved. A device corresponding to the average calculation circuit 37 can be provided. Also in this case, a moving average is calculated for the reference signal Sref, and each signal (SEL, UP, DN) is generated using the calculation result. Therefore, even when noise is included in the sine wave output from the sine wave generation unit 1, it is possible to suppress as much as possible the adverse influence of the noise on the generation of each signal (SEL, UP, DN). Is possible.

6). Others As described above, the PLL circuit 9 according to each embodiment outputs an outflow or inflow output current, and outputs a pulse signal (a pulse signal UP for switching on / off of the outflow and an on / off of inflow). The charge pump 4 whose output current is switched on / off according to the pulse signal DN to be switched, and the pulse signal according to the multi-valued reference signal Sref having a periodicity (a signal obtained by AD-converting a sine wave analog signal) A pulse generation circuit 32 that generates UP and a pulse signal DN, and generates an output clock signal Sout corresponding to the output current of the charge pump 4. Furthermore, the PLL circuit 9 also includes a current amount adjustment circuit 31 that adjusts the amount of current at which the output current is on according to the reference signal Sref.

  Thus, according to the PLL circuit 9, since the amount of output current of the charge pump is adjusted according to the reference signal, it is easy to accurately control the frequency of the output clock signal.

  In each of the above-described embodiments (including the case where the moving average calculation circuit 37 is included), when the frequency of the reference signal Sref is specified, the band pass with respect to the reference signal Sref is provided on the rear stage side of the AD converter 2. A band-pass filter (BPF) that performs the above filtering process may be provided. In this way, the noise included in the reference signal Sref is further reduced, and the jitter in the PLL circuit 9 is improved. The band pass filter may be provided between the sine wave generation unit 1 and the AD converter 2.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be used for various devices having a PLL circuit.

DESCRIPTION OF SYMBOLS 1 Sine wave generation part 2 AD converter 3 Charge pump control circuit 31 Current amount adjustment circuit 32 Pulse generation circuit 33 Target waveform generation circuit 34 Comparator 36 Integration circuit 37 Moving average calculation circuit 4 Charge pump 5 Low pass filter 6 Voltage control oscillation circuit 7 Zero cross Signal generation circuit T1-T8 transistor

Claims (12)

A charge pump that outputs an outflow or inflow output current, the on / off of the output current being switched according to a pulse signal;
A pulse signal generation unit that generates the pulse signal according to a multi-valued reference signal having periodicity;
With
A PLL circuit for generating an output clock signal corresponding to the output current,
A PLL circuit comprising: a current amount adjusting unit that adjusts a current amount when the output current is on according to the reference signal. The reference signal is
The PLL circuit according to claim 1, wherein the PLL circuit is a digital signal representing a sine wave. The pulse signal generation circuit includes:
3. The PLL circuit according to claim 2, wherein an UP signal for switching on / off of the outflow and a DN signal for switching on / off of the inflow are generated as the pulse signals. A low-pass filter provided on the output side of the charge pump;
A voltage-controlled oscillation circuit that generates a clock signal having a frequency corresponding to the output voltage of the low-pass filter as the output clock signal;
The PLL circuit according to claim 3, further comprising: The PLL circuit according to claim 4, wherein the PLL circuit generates a target waveform signal that represents a target waveform of the reference signal.
The current amount adjustment unit includes:
A PLL circuit that adjusts the amount of current according to a difference value between a value of the reference signal and a value of the target waveform signal. The current amount adjustment unit includes:
The PLL circuit according to claim 5, wherein the adjustment is performed so that the current amount increases as the absolute value of the difference value increases. The pulse signal generation circuit includes:
The PLL circuit according to claim 5, wherein an UP signal and a DN signal are generated according to a sign of the difference value. The current amount adjustment unit includes:
The PLL circuit according to claim 4, wherein the amount of current is adjusted according to an integral value of the reference signal. The PLL circuit according to claim 4, wherein the PLL circuit specifies a zero-cross timing, which is a timing at which the reference signal should become a zero-cross.
The current amount adjustment unit includes:
A PLL circuit that adjusts the amount of current according to a difference value between the value of the reference signal and zero at the zero cross timing. The pulse signal generation circuit includes:
The PLL circuit according to claim 9, wherein an UP signal and a DN signal are generated according to a sign of the difference value.   The PLL circuit according to claim 1, further comprising a moving average calculation circuit that performs a moving average calculation process on the reference signal.   12. The PLL circuit according to claim 1, further comprising a band pass filter that performs a band pass filter process on the reference signal.

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