JP2013077747A - Pin grid array package substrate, and method of manufacturing pin grid array package substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pin grid array package substrate that prevents solder for pin joining from creeping up to a shaft part of a pin as the solder is refused and also stably holds the shaft part of the pin upright, and a method of manufacturing the pin grid array package substrate.SOLUTION: A plurality of solder bumps 30 are formed on one surface of a substrate body 20. A pin 40 has a collar part 42 which is wider than a shaft part 41 at a base end of the shaft part 41. A plurality of pins 40 have the collar parts 42 joined to the substrate body 20 with solder 50 for pin joining while having shaft parts 41 stood on the other surface of the substrate body 20. The solder 50 for pin joining is interposed between the collar parts 42 of the pins 40 and the other surface of the substrate body 20. Each pin 40 is provided with a coating material 60, and a top surface of the solder 50 for pin joining is covered with the coating material 60 made of thermosetting resin.

Description

  The present invention relates to a pin grid array package substrate and a method for manufacturing the pin grid array package substrate.

  As a pin grid array package substrate, solder bumps are arranged on one surface of the substrate body, and a large number of pins are arranged upright on the other surface of the substrate body. (Patent document 1 etc.).

  The pins are joined to the substrate body by reflow soldering using a solder paste. Electronic components are bonded to the pin grid array package substrate.

JP 2003-264255 A

  By the way, it is necessary to reflow solder the pin to the board body and prevent the solder from creeping up to the shaft portion of the pin due to remelting of the solder when mounting the electronic component thereafter. In particular, with a solder having a low melting point, the solder tends to creep up to the shaft portion of the pin due to remelting. In addition, it is necessary to prevent the shaft portion of the pin from falling or tilting due to remelting of the solder. Furthermore, it is necessary to prevent the pin joining strength from being remelted.

  SUMMARY OF THE INVENTION An object of the present invention is to prevent pinning of solder onto a shaft portion of a pin that accompanies remelting of pin joining solder, and to stably hold the pin shaft portion in a state where the shaft portion of the pin is erected. It is to provide a manufacturing method of a package substrate and a pin grid array package substrate.

  In invention of Claim 1, it has a board body, a plurality of solder bumps formed on one surface of the board body, and a flange part wider than the shaft part at the base end of the shaft part, A plurality of pins joined to the substrate body by pin joining solder in a state in which the shaft portion is erected from the other surface of the substrate body, and provided for each of the pins. And a coating material made of a thermosetting resin that covers the surface of the solder for pin bonding interposed between the other surface of the substrate body.

  According to the first aspect of the present invention, the plurality of pins has a flange portion wider than the shaft portion at the base end of the shaft portion, and the shaft portion is erected from the other surface of the substrate body. In this state, the collar portion is joined to the substrate body by pin joining solder. The surface of the pin joining solder interposed between the flange of the pin and the other surface of the substrate body is covered with a coating material made of a thermosetting resin provided for each pin.

  Therefore, when it becomes easy to remelt the solder for pin joining, the coating material can prevent the solder for pin joining from creeping up to the shaft part of the pin, and the shaft part of the pin can be erected. The state can be maintained, and furthermore, a decrease in the bonding strength of the pins can be suppressed.

In this way, it is possible to prevent the solder from creeping up onto the shaft portion of the pin accompanying remelting of the solder for pin joining, and to stably hold the pin shaft portion in an upright state.
According to the second aspect of the present invention, a solder bump forming step of forming a plurality of solder bumps on one surface of the substrate main body, and an arrangement of the plurality of pins on the other surface of the substrate main body after the bump forming step. An application step of applying a solder paste containing a thermosetting resin to the region, and a pin having a flange wider than the shaft portion at the base end of the shaft portion using the solder paste after the application step And a reflow step of reflow soldering the flange portion of the pin in a state where the shaft portion is erected from the other surface of the substrate body.

  According to the invention described in claim 2, in the solder bump forming step, a plurality of solder bumps are formed on one surface of the substrate body. After the bump formation process, a solder paste containing a thermosetting resin is applied to the arrangement area of the plurality of pins on the other surface of the substrate body in the application process. After the coating process, in the reflow process, using the solder paste, the pin portion of the pin having the flange portion wider than the shaft portion at the base end of the shaft portion is erected from the other surface of the substrate body. The buttocks are reflow soldered.

  In the reflow process, the surface of the solder for pin bonding is covered with a coating material made of a thermosetting resin for each pin. This coating material can prevent the pin bonding solder from creeping into the pin shaft when the pin bonding solder is likely to remelt, and the pin shaft can be erected. Further, it is possible to suppress a decrease in the bonding strength of the pins.

  In this way, it is possible to prevent the solder from creeping up onto the shaft portion of the pin accompanying remelting of the solder for pin joining, and to stably hold the pin shaft portion in an upright state.

  ADVANTAGE OF THE INVENTION According to this invention, it can hold | maintain stably in the state which stood up the axial part of the pin while preventing the solder creeping to the axial part of a pin accompanying remelting of the solder for pin joining.

(A) is a top view which shows schematic structure of the pin grid array package board | substrate in this embodiment, (b) is a front view which shows schematic structure of the pin grid array package board | substrate. The lower surface which shows schematic structure of the pin grid array package board | substrate in this embodiment. The principal part sectional view showing the schematic structure of a pin grid array package substrate. The principal part bottom view which shows schematic structure of a pin grid array package board | substrate. (A), (b) is a schematic front view for demonstrating the manufacturing process of a pin grid array package board | substrate. (A), (b) is a schematic front view for demonstrating the manufacturing process of a pin grid array package board | substrate. (A), (b) is a schematic front view for demonstrating the component mounting of a pin grid array package board | substrate. The principal part bottom view which shows schematic structure of the pin grid array package board | substrate of another example.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings.
As shown in FIGS. 1 and 2, the pin grid array package substrate 10 includes a substrate body 20, a plurality of solder bumps 30, a plurality of pins 40, and a coating material 60. As a form at the time of use, as shown in FIGS. 7A and 7B, a chip 70 as an electronic component is mounted on the pin grid array package substrate 10 via a solder bump 30.

  As shown in FIG. 3, the substrate body 20 includes an insulating substrate 21, and the insulating substrate 21 has a plate shape. Copper patterns (conductor patterns) are formed on both sides and inside of the insulating substrate 21. 3 is a longitudinal sectional view taken along line AA in the bottom view of FIG.

  As shown in FIG. 3, many copper pads 22 are formed on the lower surface of the insulating substrate 21. In addition, a solder resist 23 is formed on the lower surface of the insulating substrate 21, and the solder resist 23 is open in the region where the pad 22 is formed. A plating layer 24 is formed in the opening of the solder resist 23 in the pad 22. The plating layer 24 is a Ni (nickel) -Au (gold) plating layer or a Ni (nickel) -Pd (palladium) -Au (gold) plating layer.

  As shown in FIG. 3, a large number of copper pads 25 are formed on the upper surface, which is one surface of the substrate body 20. In addition, a solder resist 26 is formed on the upper surface of the insulating substrate 21, and the solder resist 26 is open in the formation region of the pad 25. Solder bumps 30 are formed in the openings of the solder resist 26 in the pads 25. A large number of solder bumps 30 are formed at the center of the upper surface of the substrate body 20. The solder bumps 30 are Sn (tin) -Ag (silver) -Cu (copper) based solder, and specifically 96.5Sn-3.0Ag-0.5Cu solder. The melting point of 96.5Sn-3.0Ag-0.5Cu solder is 220 ° C. A flat surface 31 is formed on the upper surface of the solder bump 30. That is, it has the flat surface 31 by the solder bump flattening process. Connection terminals (bumps) 71 in the chip 70 (see FIG. 7) are joined to the solder bumps 30.

  As shown in FIGS. 1 and 2, a plurality of pins 40 are formed on the lower surface which is the other surface of the substrate body 20. As shown in FIGS. 3 and 4, the pin 40 has a flange portion 42 at the base end of the shaft portion 41. The collar portion 42 has a disk shape and is wider than the shaft portion 41. A cylindrical shaft portion 41 extends vertically from the central portion of one surface of the disc-shaped collar portion 42. In the pin 40, the flange portion 42 is joined to the substrate body 20 by the pin joining solder 50 in a state in which the shaft portion 41 is erected from the lower surface which is the other surface of the substrate body 20. Specifically, the pin bonding solder 50 is interposed between the flange portion 42 of each pin 40 and the plating layer 24 of the substrate body 20, and the pin 40 is bonded to the substrate body 20 by the pin bonding solder 50. The pin joining solder 50 is Sn (tin) -Bi (bismuth) solder, and more specifically, 42Sn-58Bi solder. The melting point of 42Sn-58Bi solder is 138 ° C. The pin joining solder 50 is formed by reflow of solder paste.

  In this way, the melting point of the pin bonding solder 50 (42Sn-58Bi solder) is 138 ° C., and the melting point of the solder bump 30 (96.5Sn-3.0Ag-0.5Cu solder) is 220 ° C. The pin bonding solder 50 has a melting point lower than that of the solder bump 30.

  As shown in FIGS. 3 and 4, a coating material 60 is provided for each pin 40, and the pin joining solder 50 is covered with the coating material 60. Specifically, the coating material 60 covers the surface of the pin bonding solder 50 interposed between the flange portion 42 of the pin 40 and the lower surface of the substrate body 20. The coating material 60 is made of a thermosetting resin. An epoxy resin can be mentioned as a thermosetting resin. The coating material 60 is obtained by coating the pin bonding solder 50 with a thermosetting resin contained in the solder paste through a solder reflow process. Therefore, the flux component remains in the coating material 60 (in the thermosetting resin).

  In FIG. 4, each pin 40 is arranged vertically and horizontally, and a coating material 60 is arranged for each pin 40. At this time, the coating material 60 arranged vertically and horizontally is not in contact with each other, and there is a region A1 where the coating material 60 is not present.

  Thus, the pin bonding solder 50 is covered with the coating material 60 which is a thermoset resin. Therefore, when a solder having a low melting point is used as the pin bonding solder 50, it is possible to prevent the pin bonding solder 50 from creeping at the pin shaft portion 41 due to remelting. Further, it is possible to prevent the pin 40 from falling or tilting due to remelting. Furthermore, it is possible to prevent a decrease in the bonding strength of the pin 40 due to remelting.

  In this manner, lead-free solder having a low melting point can be used as the pin bonding solder 50, whereby the warpage of the substrate body 20 can be prevented by lowering the reflow peak temperature.

As shown in FIG. 7, the connection terminal 71 of the chip 70 is bonded to the solder bump 30 on the upper surface of the substrate body 20, and the chip 70 is mounted on the upper surface of the substrate body 20.
Next, the operation of the pin grid array package substrate 10 will be described.

  The surface of the pin bonding solder 50 interposed between the flange portion 42 of the pin 40 and the lower surface of the substrate body 20 is covered with a coating material 60 made of a thermosetting resin provided for each pin 40. . Therefore, when the pin bonding solder 50 is easily remelted when the chip 70 is mounted (at the time of heat treatment), the pin bonding solder 50 is covered with the coating material 60. Crawling can be prevented. Further, since the pin 40 is restrained by the coating material 60, when the pin joining solder 50 is in a state where it is likely to be remelted, the pin 40 can be prevented from being tilted or tilted. The standing state of the shaft portion 41 can be maintained. Furthermore, when the pin joining solder 50 is in a state of being easily remelted, it is possible to suppress a reduction in the joining strength of the pins 40.

Next, a method for manufacturing the pin grid array package substrate 10 will be described.
As shown in FIG. 5A, a plurality of solder bumps 30 are formed on one surface of the substrate body 20.

  After the formation of the solder bumps 30, as shown in FIG. 5B, a solder paste 80 containing a thermosetting resin is applied to the arrangement area of the plurality of pins on the other surface of the substrate body 20. The solder paste 80 is a mixture of 42Sn-58Bi solder powder and flux, and the flux contains a thermosetting resin. That is, the solder paste 80 contains a flux in the lead-free solder powder, and the flux contains a thermosetting resin.

  After the solder paste 80 is applied, the flange portion 42 wider than the shaft portion 41 is formed at the base end of the shaft portion 41 using the solder paste 80 containing a thermosetting resin, as shown in FIG. The flange portion 42 of the pin 40 is reflow soldered in a state in which the shaft portion 41 of the pin 40 having the pin 40 is erected from the other surface of the substrate body 20.

  As a result, the pins 40 are mounted on the surface of the substrate body 20 opposite to the solder bumps 30. At the time of pin mounting, the pin joining solder 50 is covered with a coating material 60 made of a thermosetting resin. Further, the warpage of the substrate body 20 can be suppressed by reducing the reflow peak temperature.

  After the pins 40 are mounted, the solder bumps 30 are flattened using the solder bump flattening device 110 as shown in FIG. Thereby, a flat surface 31 is formed on the upper surface of the solder bump 30.

  6B, in the solder bump flattening device 110, a lower jig 111 as a pedestal and an upper jig 112 as a pressing jig are arranged vertically. The pin grid array package substrate 10 is placed on the lower jig 111 of the solder bump flattening device. At this time, the pin grid array package substrate 10 is placed on the lower jig 111 with the plurality of solder bumps 30 facing upward, and the substrate body 20 is supported by the lower jig 111. The upper surface of the lower jig 111 is flat, and the upper surface of the lower jig 111 is a mounting surface of the pin grid array package substrate 10. On the upper surface of the lower jig 111, pin contact avoiding recesses 111a are formed so that the pins 40 of the pin grid array package substrate 10 do not come into contact with each other. The upper jig 112 is disposed above the lower jig 111, and the upper jig 112 is movable in the vertical direction. The lower surface of the upper jig 112 is opposed to the upper surface of the lower jig 111. The lower surface of the upper jig 112 is flat, and the lower surface of the upper jig 112 serves as a pressing surface of the solder bump 30 of the pin grid array package substrate 10. The upper jig 112 flattens the plurality of solder bumps 30 by applying pressure F to the plurality of solder bumps 30 against the pin grid array package substrate 10 on the lower jig 111.

  Then, with the pin grid array package substrate 10 placed on the lower jig 111 with the solder bumps 30 facing upward, the upper jig 112 as a pressing jig is moved downward with respect to the substrate body 20. The pressing surface of the upper jig 112 is pressed against the plurality of solder bumps 30 (the plurality of solder bumps 30 are pressed by the upper jig 112). Thereby, the upper surfaces of the plurality of solder bumps 30 are made flat, and the solder bumps 30 are flattened.

  In this solder bump flattening step, the upper surface of the lower jig 111 and the substrate body 20 are in contact with each other in the region A1 where the coating material 60 is not present in FIG. That is, the upper surface of the lower jig 111 and the lower surface of the substrate body 20 come into contact with each other in the region A1 where the coating material 60 is not present on the lower surface of the substrate body 20, and the substrate body 20 is moved by the lower jig 111 without being disturbed by the coating material 60. Can be supported.

In this way, the pin grid array package substrate 10 is manufactured.
Thereafter, the chip 70 is mounted on the pin grid array package substrate 10 with the upper surface of the solder bump 30 flattened, as shown in FIGS. Specifically, as shown in FIG. 7A, the connection terminals (bumps) 71 of the chip 70 and the solder bumps 30 of the pin grid array package substrate 10 are heated in contact with each other as shown in FIG. 7B. The connection terminals (bumps) 71 and the solder bumps 30 are combined and integrated, and the chip 70 is mounted on the pin grid array package substrate 10. At this time, since each solder bump 30 of the pin grid array package substrate 10 is flattened, each connection terminal (bump) 71 of the chip 70 can be uniformly bonded. Component mounting is performed at a temperature higher than the melting point of the solder bump.

Here, reference is made to pin mounting.
In the pin mounting process, pins are joined with a solder paste. In general, the solder paste uses lead-containing solder or lead-free solder. For example, as the lead-containing solder, 82Pb-10Sn-8Sb solder can be cited, and in this case, the melting point is 260 ° C. Moreover, as a lead free solder, 90Sn-10Sb solder can be mentioned, In this case, melting | fusing point is 249 degreeC.

  Furthermore, considering the influence on the human body, it is necessary to select an Sb-free material for Sb (antimony). In this case, as a material, it is necessary to prevent the solder from creeping up to the shaft portion of the pin due to remelting of the solder during flip chip mounting. Moreover, it is necessary to prevent the pin from falling or tilting due to remelting of the solder. Furthermore, it is necessary to avoid insufficient pin joint strength.

  In the present embodiment, the coating material 60 made of a thermosetting resin covers the pin bonding solder 50 at the time of mounting. Therefore, the solder that has been cured by the thermosetting resin can be prevented. In addition, the thermosetting resin can prevent the pin from falling or tilting. Furthermore, since the thermosetting resin can prevent a decrease in the bonding strength of the pins, a solder material having a melting point lower than the melting point of the solder bump can be selected as the Sb-free solder material.

  On the other hand, by using an Sb-free solder material that can lower the peak temperature during reflowing than that of lead-free solder, the amount of warping of the substrate can be suppressed by lowering the reflow peak temperature. In other words, the amount of warpage increases when a high temperature is applied to the substrate while the substrate becomes thinner. If a material with a lower melting point can be used as the solder material for pin bonding, the amount of warpage of the substrate due to heat treatment can be reduced. In the present embodiment, the solder paste contains a thermosetting resin and the pin bonding solder 50 is covered with a coating material 60 made of a thermosetting resin, so that a countermeasure against a high temperature when the chip 70 is bonded is taken. Has been taken. Thereby, Sn-Bi solder with a low melting point can be used as the solder 50 for pin bonding. That is, the peak temperature during reflow can be lowered. As a result, substrate warpage can be suppressed.

As described above, according to the present embodiment, the following effects can be obtained.
(1) As the structure of the pin grid array package substrate, a coating material 60 is provided for each pin 40, and the surface of the pin bonding solder 50 interposed between the flange portion 42 of the pin 40 and the other surface of the substrate body 20 Was covered with a coating material 60 made of a thermosetting resin. As a result, when the pin bonding solder 50 is in a state of being easily remelted, the coating material 60 can prevent the pin bonding solder 50 from creeping up to the shaft portion 41 of the pin 40, and the pin For example, the standing state of the 40 shaft portions 41 can be maintained, and further, a reduction in the bonding strength of the pins 40 can be suppressed. As a result, it is possible to prevent the solder from creeping up to the shaft portion 41 of the pin 40 due to the remelting of the pin bonding solder 50 and to stably hold the shaft portion 41 of the pin 40 in an erected state ( It is possible to suppress the creeping of the solder 50 accompanying the remelting, the fall / inclination of the shaft portion 41 of the pin 40, and the decrease in the bonding strength of the pin 40).

  (2) Furthermore, it becomes possible to select the pin bonding solder 50 having a low melting point, and it is possible to suppress the warpage of the substrate due to the reflow temperature reduction. Specifically, since the solder 50 for pin bonding has a melting point equal to or lower than that of the solder bump 30, it is possible to reduce the peak temperature during reflow soldering, and thereby warp the substrate body 20 due to heat treatment. Can be suppressed.

  (3) In particular, since the pin bonding solder 50 is an Sn—Bi solder, the peak temperature during reflow soldering can be lowered to suppress warping of the substrate body 20 due to heat treatment.

  (4) As a manufacturing method of the pin grid array package substrate, a bump forming process, a coating process, and a reflow process are included. In the bump forming process, a plurality of solder bumps 30 are formed on one surface of the substrate body 20. In the applying process, after the bump forming process, a solder paste 80 containing a thermosetting resin is applied to the arrangement region of the plurality of pins on the other surface of the substrate body 20. In the reflow process, the shaft portion 41 of the pin 40 having the flange portion 42 wider than the shaft portion 41 at the base end of the shaft portion 41 is removed from the other surface of the substrate body 20 by using the solder paste 80 after the coating step. The flange portion 42 of the pin 40 is reflow soldered in a standing state.

  With such a manufacturing method, in the reflow process, the surface of the pin bonding solder 50 is covered with the coating material 60 made of a thermosetting resin for each pin 40. When the connecting material 71 of the chip 70 is joined to the solder bump 30 by the coating material 60, the pin joining solder 50 is easily remelted. 50 scooping can be prevented. Further, the standing state of the shaft portion 41 of the pin 40 can be maintained. Furthermore, a decrease in the bonding strength of the pins 40 can be suppressed.

  Thus, it is possible to prevent the solder from creeping up to the shaft portion 41 of the pin 40 due to remelting of the pin bonding solder 50 and to stably hold the shaft portion 41 of the pin 40 in a standing state. (Suppressing the rise of the solder 50 due to remelting, the fall / inclination of the shaft portion 41 of the pin 40, and the reduction in the bonding strength of the pin 40 can be suppressed).

  (5) After the reflow process, the pressing surface of the upper jig 112 as a pressing jig is pressed against the solder bump 30 against the substrate body 20 on which the plurality of solder bumps 30 are formed, and the plurality of solder bumps 30 are flattened. A bump planarization step is further included. Therefore, the substrate body 20 on which the pins 40 are mounted downward can be easily placed on the lower jig 111 as a pedestal without contacting the coating material 60.

The embodiment is not limited to the above, and may be embodied as follows, for example.
The solder bump 30 is Sn-Ag-Cu solder (specifically 96.5Sn-3.0Ag-0.5Cu), and the pin bonding solder 50 is Sn-Bi solder (specifically 42Sn- 58Bi), but is not limited to this. For example, Sn—Ag—Cu solder may be used as the pin bonding solder 50. Specifically, for example, 96.5Sn-3.0Ag-0.5Cu may be used.

  As described above, the melting point of the solder for pin bonding is lower than the melting point of the solder bump 30, but the melting point of the solder for pin bonding may be the same as the melting point of the solder bump 30. In short, it is preferable that the solder for pin bonding has a melting point lower than that of the solder bump.

  As shown in FIG. 4, the coating material 60 for each pin 40 is not in contact with the coating materials 60 provided on the pins 40 adjacent vertically and horizontally, but the present invention is not limited to this, as shown in FIG. 8. The coating materials 60 provided on the pins 40 adjacent in the vertical and horizontal directions may be in contact with each other. At this time, the coating materials 60 provided on the pins 40 adjacent in the vertical and horizontal directions are in contact with each other, but the coating materials 60 provided on the diagonal pins 40 have a region A1 where the coating material 60 is not present.

  -Although the chip (flip chip) 70 was used as an electronic component, it is not limited to this.

  DESCRIPTION OF SYMBOLS 10 ... Pin grid array package board | substrate, 20 ... Board | substrate main body, 30 ... Solder bump, 40 ... Pin, 41 ... Shaft part, 42 ... Saddle part, 50 ... Solder for pin joining, 60 ... Coating material, 80 ... Solder paste.

Claims (2)

A substrate body;
A plurality of solder bumps formed on one surface of the substrate body;
The base portion of the shaft portion has a flange portion wider than the shaft portion, and the flange portion is joined to the substrate body by the solder for pin connection in a state where the shaft portion is erected from the other surface of the substrate body. A plurality of pins,
A coating material made of a thermosetting resin that is provided for each pin and covers the surface of the solder for pin bonding interposed between the flange of the pin and the other surface of the substrate body;
A pin grid array package substrate comprising: A solder bump forming step of forming a plurality of solder bumps on one surface of the substrate body;
After the bump forming step, an application step of applying a solder paste containing a thermosetting resin to the arrangement area of the plurality of pins on the other surface of the substrate body;
After the coating step, using the solder paste, the shaft portion of the pin having a flange portion wider than the shaft portion at the base end of the shaft portion is erected from the other surface of the substrate body. A reflow process for reflow soldering the pin collar;
A method of manufacturing a pin grid array package substrate, comprising:

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