JP2013077672A - Semiconductor device, parameter optimization method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a parameter optimization method, and a program capable of optimizing a parameter by separating components of capacitance of a transistor and wiring capacitance.SOLUTION: A semiconductor device includes a wiring load pattern which contains first wiring that is to be a load part 12 electrically connected to an output part of each primitive gate circuit 11a of a first ring oscillator part 11 in which primitive gate circuits comprising an MOS transistor are connected in ring at an odd number stage, a plurality of gate load patterns electrically connected to a gate of the MOS transistor in which an output part of each primitive gate circuit of a second ring oscillator part comes to a load part through second wiring, and a plurality of diffusion layer load patterns electrically connected to a diffusion layer in which an output part of each primitive gate circuit of a third ring oscillator part comes to be a load part through third wiring. The plurality of gate load patterns vary in capacitance load for each pattern, and the plurality of diffusion layer load patterns vary in capacitance load for each pattern.

Description

  The present invention relates to a semiconductor device, a parameter optimization method, and a program used to optimize parameters of a MOS transistor model in a circuit simulation program.

  In designing a semiconductor integrated circuit using MOS transistors, a transmission delay time (Tpd) measured by a ring oscillator (ROSC) pattern formed on a silicon wafer and SPICE (Simulation Program with Integrated Circuit Emphasis) are used. Matching verification with the simulated Tpd is performed. In the process of performing the matching verification, in order to analyze the cause of the Tpd error, it is indispensable to separate into a DC (direct current) factor and an AC (capacitance) factor.

  AC factors include gate capacitance, gate overlap capacitance, the capacitance component of the transistor portion of the junction capacitance, and the wiring capacitance forming the ROSC. In order to optimize the AC-like error, it is necessary to analyze the capacitance components and to optimize the capacitance parameter causing the error. In order to measure the capacitance parameter, in general, an LCR meter (coil (L) / capacitor (C) / impedance (Z, R) measuring device) etc. is used to directly gate using the capacitance extraction pattern. Capacitance, gate overlap capacitance, and wiring capacitance are measured, and parameters are extracted from the measured values (see Non-Patent Documents 1 and 2).

JP 2005-251976 A JP 2002-261272 A JP 2000-298683 A JP 2010-10515 A

Aoki Hitoshi, 2 others, “CMOS Modeling Technology-Theory and Practice of Compact Modeling for SPICE”, first edition, Maruzen, January 2006, p. 185-193. Michiko Miura, two others, “Circuit Simulation Technology and MOSFET Modeling”, Realize Science Center, March 2003, p. 385-390.

  However, in order to directly measure with an LCR meter, in order to increase the sensitivity of the capacitance value, parameter extraction is performed with a large layout structure different from the actual circuit (primitive gate circuit such as an inverter, NAND circuit, NOR circuit). In order to determine whether TEG (Test Element Group) area efficiency is poor or whether it is correctly extracted as the delay value during actual circuit operation, the delay value during actual circuit operation is obtained, and the measured value is used as the delay amount. There is a problem of not knowing until you compare.

  In addition, since the value observed as the delay is observed as the total value of the respective capacitance parameters, when the value observed as the frequency (or Tpd) of the actual circuit and the simulation value deviate, There is also a problem that it is difficult to determine which capacitive component is shifted.

  Furthermore, there is a problem that it is difficult to separate the factors of each capacitance component in order to convert the capacity from the Tpd observed from the ROSC.

  By the way, in the Tpd error factor analysis process between the silicon characteristics and the simulation characteristics of Tpd verification, the Tpd error cannot be optimized accurately unless it is divided into DC factor errors and AC factor errors. . Among them, the AC factor error has to be optimized by dividing it into a transistor-caused gate capacitance, gate overlap capacitance, junction capacitance error, and wiring-caused error.

  In the prior art, as a method for optimizing individual parameters in verifying Tpd, a DC factor analysis method using a ROSC pattern (see Patent Document 1) and an AC factor analysis method (Patent Documents 2, 3). Reference). In particular, there are many AC factor analysis methods specialized in wiring capacity. Patent Document 2 discusses only the gate overlap capacitance of a transistor.

  However, the method described in Patent Documents 1-3 does not discuss the breakdown of the capacitance component of the transistor, and cannot analyze the error by separating each component of the capacitance of the transistor and the wiring capacitance.

  Further, Patent Document 4 proposes a pattern for extracting the Tpd impact depending on the number of contacts in the load portion, but no specific optimization and extraction method for the capacitance parameter of the contact portion is discussed.

  A main object of the present invention is to provide a semiconductor device, a parameter optimization method, and a program capable of optimizing parameters by separating each component of the capacitance of a transistor and wiring capacitance.

  According to a first aspect of the present invention, in a semiconductor device, the primitive gate circuit composed of MOS transistors is electrically connected to an output portion of each primitive gate circuit of a first ring oscillator portion in which odd-numbered stages are coupled in a ring shape. A wiring load pattern having a connected first wiring, and a second wiring in which the output part of each primitive gate circuit of the second ring oscillator unit having the same configuration as the first ring oscillator unit has the same configuration as the first wiring And a plurality of gate load patterns electrically connected to the gates of the MOS transistors serving as the load sections via the first ring oscillator section, and an output section of each primitive gate circuit of the third ring oscillator section having the same configuration as the first ring oscillator section. A plurality of diffusion layer negative electrodes electrically connected to a diffusion layer serving as a load portion via a third wiring having a configuration similar to that of the first wiring. Comprising a pattern, wherein the plurality of gate load pattern have different capacitive load for each pattern, the plurality of diffusion layers load pattern, characterized by capacitive loading different for each pattern.

  In a second aspect of the present invention, the semiconductor device, a measuring device electrically connected to the semiconductor device, and a computer that is electrically connected to the measuring device and executes a circuit simulation program, A parameter optimization method for optimizing a parameter of a MOS transistor model in the circuit simulation program, the step of actually measuring and simulating the propagation delay time of the gate load pattern or the diffusion layer load pattern; and the propagation delay When the slope of the measured value and the simulation value of the load dependency of time and the slope of the measured value and the simulation value do not match, the slope of the simulation value is adjusted to the slope of the measured value. A process for optimizing predetermined parameters; Characterized in that it comprises a.

  In a third aspect of the present invention, the semiconductor device, a measurement device electrically connected to the semiconductor device, and a computer that is electrically connected to the measurement device and executes a circuit simulation program, A program for optimizing the parameters of the MOS transistor model in the circuit simulation program, the step of actually measuring and simulating the propagation delay time of the gate load pattern or the diffusion layer load pattern (step A2 in FIG. 12); The step of calculating the slope of the actual measurement value and the simulation value of the load dependence of the propagation delay time (steps A3, A5, A7, A9 in FIG. 12) and the slope of the actual measurement value and the simulation value do not match. , The measured slope of the simulation value With aligning the slope, the step (step A4, A6, A8, A10 in FIG. 12) to optimize certain parameters, characterized in that for the execution.

  According to the present invention, parameters can be indirectly optimized using the sensitivity of propagation delay time without performing capacity extraction directly from a measuring device such as an LCR meter. Further, since parameters can be optimized with a pattern close to an actual circuit, such as a ring oscillator pattern, errors during actual circuit operation can be minimized.

FIG. 2A is a circuit diagram schematically showing a configuration of a ROSC pattern having no load portion as a basic configuration in a semiconductor device used in a parameter optimization method according to Embodiment 1 of the present invention, and FIG. is there. FIG. 2A is a circuit diagram schematically illustrating a configuration of a ROSC pattern having a load portion as a basic configuration in a semiconductor device used in the parameter optimization method according to the first embodiment of the present invention, and FIG. is there. It is the fragmentary top view which showed typically the structure of the wiring load pattern in the ROSC pattern of the semiconductor device used with the parameter optimization method which concerns on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the gate load pattern (1 load number) in the ROSC pattern of the semiconductor device used with the parameter optimization method which concerns on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the gate load pattern (3 loads) in the ROSC pattern of the semiconductor device used with the parameter optimization method which concerns on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the diffused layer load pattern (STI structure; pattern 1) in the ROSC pattern of the semiconductor device used with the parameter optimization method which concerns on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the diffused layer load pattern (STI structure; pattern 2) in the ROSC pattern of the semiconductor device used with the parameter optimization method which concerns on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the diffused layer load pattern (STI structure; pattern 3) in the ROSC pattern of the semiconductor device used with the parameter optimization method which concerns on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the diffused layer load pattern (gate structure; pattern 1) in the ROSC pattern of the semiconductor device used with the parameter optimization method based on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the diffused layer load pattern (gate structure; pattern 2) in the ROSC pattern of the semiconductor device used with the parameter optimization method based on Example 1 of this invention. It is the fragmentary top view which showed typically the structure of the diffused layer load pattern (gate structure; pattern 3) in the ROSC pattern of the semiconductor device used with the parameter optimization method which concerns on Example 1 of this invention. It is the flowchart which showed typically the parameter optimization method which concerns on Example 1 of this invention. FIG. 6 schematically shows measured values and simulation values of Tpd when there is no load portion in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention and when there is a wiring load pattern. It is a graph. Number of gate loads of measured and simulated values (before and after optimization) of Tpd under condition 1 when the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention has a gate load pattern It is the graph which showed the dependence typically. Number of gate loads of measured and simulated values (before and after optimization) of Tpd under condition 2 when the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention has a gate load pattern It is the graph which showed the dependence typically. STI surroundings of measured values and simulation values (before and after optimization) of Tpd when the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention has a diffusion layer load pattern (STI configuration) It is the graph which showed long dependence typically. It is the graph which showed typically the relationship between the diffusion layer load pattern (STI structure) and Tpd of a wiring load pattern in the ROSC pattern of the semiconductor device used with the parameter optimization method concerning Example 1 of the present invention. Gate circumference of measured value and simulation value (before and after optimization) of Tpd when ROSC pattern of semiconductor device used in parameter optimization method according to embodiment 1 of the present invention has a diffusion layer load pattern (gate configuration) It is the graph which showed long dependence typically. It is the graph which showed typically the relationship between the diffusion layer load pattern (gate structure) and Tpd of a wiring load pattern in the ROSC pattern of the semiconductor device used with the parameter optimization method concerning Example 1 of the present invention.

  In the semiconductor device according to the first embodiment of the present invention, each of the first ring oscillator units (11 in FIG. 2) in which a primitive gate circuit (11a in FIG. 2) composed of MOS transistors is coupled in an odd-numbered stage in a ring shape. A wiring load pattern (see FIG. 3) having a first wiring (35 to 38 in FIG. 3) electrically connected to the output section of the primitive gate circuit, and a second ring having the same configuration as the first ring oscillator section The output section of each primitive gate circuit (11a in FIG. 2) of the oscillator section (11 in FIG. 2) is loaded via a second wiring (35 to 38 in FIGS. 4 and 5) having the same configuration as the first wiring. A plurality of gate load patterns (see FIGS. 4 and 5) electrically connected to the gate (40 in FIGS. 4 and 5) of the MOS transistor to be a portion (12 in FIGS. 4 and 5), and the first Ring oscillator section The third ring oscillator (11 in FIG. 2) of the same configuration has a third wiring (35 in FIGS. 6 to 11) in which the output section of each primitive gate circuit (11a in FIG. 2) has the same configuration as the first wiring. A plurality of diffusion layer load patterns (see FIGS. 6 to 11) electrically connected to the diffusion layer (50 or 52 or 53 in FIGS. The plurality of gate load patterns have different capacitive loads for each pattern, and the plurality of diffusion layer load patterns have different capacitive loads for each pattern.

  In the semiconductor device according to the aspect of the invention, it is preferable that the plurality of gate load patterns have different numbers of gates electrically connected to the second wiring for each pattern.

  In the semiconductor device of the present invention, the gate load pattern is configured such that an arbitrary potential can be applied to the source, drain, and substrate terminals of the MOS transistor serving as the load section. Is preferred.

  In the semiconductor device of the present invention, it is preferable that the plurality of diffusion layer load patterns have different numbers of diffusion layers electrically connected to the third wiring.

  In the semiconductor device of the present invention, the plurality of diffusion layer load patterns include an STI configuration in which an STI is arranged in a region around the diffusion layer serving as the load portion, and the diffusion layer serving as the load portion. And a gate structure in which a gate is arranged in a surrounding region.

In the semiconductor device of the present invention, the substrate potential of the load portion in the plurality of diffusion layer load patterns is the same potential as the substrate potential of the third ring oscillator portion,
It is preferable that the gate of the gate configuration in the plurality of diffusion layer load patterns is configured to be able to apply an arbitrary potential.

  In the parameter optimization method according to the second embodiment of the present invention, the semiconductor device, the measurement device electrically connected to the semiconductor device, and the circuit simulation program that is electrically connected to the measurement device are executed. A parameter optimization method for optimizing a parameter of a MOS transistor model in the circuit simulation program using a computer, and measuring and simulating a propagation delay time of the gate load pattern or the diffusion layer load pattern ( Step A2) in FIG. 12, a step of calculating an inclination of an actual measurement value and a simulation value of the load dependency of the propagation delay time (Steps A3, A5, A7, A9 in FIG. 12), the actual measurement value and the simulation value. When the slopes of the Including the inclination of the emission values with aligning the inclination of the measured value, the step of optimizing the predetermined parameter (step A4, A6, A8, A10 in FIG. 12), the.

  In the parameter optimization method of the present invention, in the step of measuring and simulating the propagation delay time, the propagation delay time due to the gate capacitance or gate overlap capacitance of the load portion of the gate load pattern may be measured and simulated. preferable.

  In the parameter optimization method of the present invention, in the step of calculating the inclination, it is preferable to calculate an inclination of an actual measurement value and a simulation value of gate number dependency of the propagation delay time related to the gate load pattern.

  In the parameter optimization method of the present invention, in the step of calculating the slope, the STI perimeter of the diffusion delay time related to the diffusion layer load pattern where the diffusion layer is in contact with the STI, or the diffusion layer is the gate. It is preferable to calculate the measured value and the slope of the simulation value of the dependency of the gate perimeter length adjacent to.

  In the parameter optimization method of the present invention, the difference between the measured value and the simulation value of the propagation delay time when the STI peripheral length or the gate peripheral length is 0 and the propagation delay time of the wiring load pattern does not match. Sometimes, it is preferable to include a step of optimizing other predetermined parameters such that the difference between the simulation values matches the difference between the actual measurement values.

  In the program according to the third embodiment of the present invention, the semiconductor device, a measurement device electrically connected to the semiconductor device, a computer electrically connected to the measurement device and executing a circuit simulation program, A circuit simulation program for optimizing the parameters of the MOS transistor model, the step of actually measuring and simulating the propagation delay time of the gate load pattern or the diffusion layer load pattern, and the propagation delay time The step of calculating the slope of the actual measurement value and the simulation value of the load dependency and the slope of the simulation value are matched with the slope of the actual measurement value when the slope of the actual measurement value and the simulation value does not match. Optimize parameters of And step, to the execution.

  Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments.

  A semiconductor device used in the parameter optimization method according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a circuit diagram schematically illustrating a configuration of a ROSC pattern having no load portion as a basic configuration in a semiconductor device used in a parameter optimization method according to a first embodiment of the present invention, and FIG. FIG. 2A is a circuit diagram schematically showing a configuration of a ROSC pattern having a load portion as a basic configuration in the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention, and FIG. FIG. FIG. 3 is a partial plan view schematically showing the configuration of the wiring load pattern in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. FIG. 4 is a partial plan view schematically showing the configuration of the gate load pattern (the number of loads) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. FIG. 5 is a partial plan view schematically showing the configuration of the gate load pattern (number of loads 3) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to Embodiment 1 of the present invention. FIG. 6 is a partial plan view schematically showing the configuration of the diffusion layer load pattern (STI configuration; pattern 1) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. FIG. 7 is a partial plan view schematically showing the configuration of the diffusion layer load pattern (STI configuration; pattern 2) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. FIG. 8 is a partial plan view schematically showing the configuration of the diffusion layer load pattern (STI configuration; pattern 3) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. FIG. 9 is a partial plan view schematically showing the configuration of the diffusion layer load pattern (gate configuration; pattern 1) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. FIG. 10 is a partial plan view schematically showing the configuration of the diffusion layer load pattern (gate configuration; pattern 2) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. FIG. 11 is a partial plan view schematically showing the configuration of the diffusion layer load pattern (gate configuration; pattern 3) in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention.

  The parameter optimization method is a method for optimizing the parameters of the MOS transistor model in the circuit simulation program. In the parameter optimization method, a transmission delay time (Tpd) is measured using a measurement device (for example, an LCR meter) electrically connected to the semiconductor device, and a circuit simulation program is performed for the same model as the MOS transistor portion in the semiconductor device. By simulating Tpd using a computer that executes (for example, SPICE), Tpd matching verification is performed on the computer, and if it does not match, the parameters of the MOS transistor model in the circuit simulation software are optimized. To do. In order to carry out such a parameter optimization method, the following semiconductor device (model) is used.

  The semiconductor device has a ROSC pattern 10A including only a ring oscillator unit 11 (ROSC unit) without a load unit as a test circuit for evaluating the operation speed of the semiconductor integrated circuit (see FIG. 1A). The ROSC pattern 10A has a multi-stage (odd stage; usually 47 stages) inverter 11a composed of MOS transistors (Nch type transistors, Pch type transistors) (or other primitive gate circuits such as NAND circuits and NOR circuits). It is configured to be connected in a ring shape. In the inverter 11a, a Vin wiring 28 to which a voltage is input is electrically connected to a common gate 21 of an Nch transistor and a Pch transistor via a contact 34. In the Nch transistor, a source / drain region is formed on both sides of the gate 21. Diffusion layers 22 and 23 to be formed are formed. In the Pch transistor, diffusion layers 24 and 25 to be source / drain regions are formed on both sides of the gate 21, and the diffusion layer 22 is electrically connected to the GND wiring 26 through the contact 30. The diffusion layer 24 is electrically connected to the Vdd wiring 27 through the contact 32, and the diffusion layers 23 and 25 are electrically connected to the common Vout wiring 29 through the contacts 31 and 33, respectively. (See FIG. 1B).

  In addition to the ROSC pattern 10A, the semiconductor device has a ROSC pattern 10B in which the load unit 12 is connected to the ring oscillator unit 11 as a model for adjusting DC characteristics in the ROSC pattern 10A (FIG. 2A). )reference). The ROSC pattern 10B includes the ROSC unit 11 having the same configuration as the ROSC unit 11 of the ROSC pattern 10A of FIG. 1A. The Vout wiring 29 of each inverter 11a in the ROSC unit 11 is connected to the wiring 35 via the contact 36. (See FIG. 2B), the wiring 35 is electrically connected to one end of the load capacitor 12a in the load section 12, and the other end of the load capacitor 12a is electrically connected to GND. There are a plurality of models for the load capacitance 12a, and there are a wiring load pattern (see FIG. 3), a gate load pattern (see FIGS. 4 and 5), and a diffusion layer load pattern (see FIGS. 6 to 11). is there.

  The wiring load pattern in FIG. 3 is for eliminating errors due to wiring capacitance in the gate load pattern (see FIGS. 4 and 5) and the diffusion layer load pattern (see FIGS. 6 to 11). In addition, it has the same configuration as the wiring portion (wiring 35, contact 38, wiring 37) of the diffusion layer load pattern. In the wiring load pattern, the wiring 35 drawn from the Vout wiring 29 of each inverter 11a to the load portion (12 in FIG. 2A) is electrically connected to the wiring 37 via the contact 38. . The wiring load pattern is a framework of the capacitive load pattern of the gate load pattern and the diffusion layer load pattern. The gate load pattern and the diffusion layer load pattern are simply connected to the gate or the diffusion layer through the contact to the wiring 37. There is a feature that can be. In general, the wiring capacity can be extracted by using LPE (Layout Parameter Extraction). However, in the wiring load pattern of FIG. 3, the thickness and thinning amount for each wafer can be measured as Tpd.

  4 and 5 is a pattern in which the number of loads in which the wiring 37 of the load section 12 and the gate 40 of the MOS transistor are connected via a contact 41 is changed (one in FIG. 4 and three in FIG. 5). Book). In the gate load pattern, MOS transistors having diffusion layers 42 arranged on both sides of the gate 40 are arranged side by side in the gate length direction, and the predetermined gate 40 is electrically connected to the wiring 37 through the contact 41. Each diffusion layer 42 is electrically connected to the wiring 43 through a contact 44. The MOS transistor is either NMOS or PMOS. The wiring 43 that is electrically connected to the diffusion layer 42 related to the source among the wiring 43 is electrically connected to the source terminal 46. Of the wiring 43, the wiring 43 that is electrically connected to the diffusion layer 42 relating to the drain is electrically connected to the drain terminal 47. The substrate of the MOS transistor is electrically connected to the substrate terminal 48 (body terminal). The source terminal 46, the drain terminal 47, and the substrate terminal 48 are independent terminals in the circuit so that arbitrary potentials can be applied thereto.

  The diffusion layer load patterns (junction capacitance load patterns) in FIGS. 6 to 11 are of two types, the STI (Shallow Trench Isolation) configuration in FIGS. 6 to 8 and the gate configuration in FIGS. There is a configuration.

  The diffusion layer load pattern of the STI configuration of FIGS. 6 to 8 includes a configuration in which a plurality of diffusion layers 50, 52, 53 are arranged, and each diffusion layer 50, 52, 53 is surrounded by STI (not shown). Each diffusion layer 50, 52, 53 is electrically connected to the wiring 37 via the contact 51. Each diffusion layer 50 in FIG. 6 is connected to one contact 51 and is shorter than the diffusion layer 52. Each diffusion layer 52 in FIG. 7 is connected to two contacts 51 and is longer than the diffusion layer 50 and shorter than the diffusion layer 53. Each diffusion layer 53 in FIG. 8 is connected to three contacts 51 and is longer than the diffusion layer 52. The total diffusion layer area of the diffusion layer 50 in FIG. 6 is set to coincide with the total diffusion layer area of the diffusion layer 52 in FIG. 7 and the total diffusion layer area of the diffusion layer 53 in FIG. . The diffusion layer load patterns of the STI configuration in FIGS. 6 to 8 are patterns in which the STI peripheral length that is the peripheral length of the diffusion layer in contact with the STI is changed. The substrate potential in the STI-structured diffusion layer load pattern is the same as the substrate potential of the ROSC section (11 in FIG. 2A). When the substrate is formed of an N + diffusion layer, the substrate potential is GND. When the substrate is formed of a P + diffusion layer, the substrate potential is Vdd.

  The diffusion layer load pattern of the gate configuration in FIGS. 9 to 11 has a configuration in which a plurality of diffusion layers 50, 52, 53 are arranged, and each diffusion layer 50, 52, 53 is surrounded by a gate 55, Each diffusion layer 50, 52, 53 is electrically connected to the wiring 37 via the contact 51. The diffusion layers 50, 52, and 53 in FIGS. 9 to 11 are the same as the configurations of the diffusion layers 50, 52, and 53 in FIGS. Each diffusion layer 50 in FIG. 9 is connected to one contact 51 and is shorter than the diffusion layer 52. Each diffusion layer 52 in FIG. 10 is connected to two contacts 51 and is longer than the diffusion layer 50 and shorter than the diffusion layer 53. Each diffusion layer 53 in FIG. 11 is connected to three contacts 51 and is longer than the diffusion layer 52. The total diffusion layer area of the diffusion layer 50 in FIG. 9 is set to coincide with the total diffusion layer area of the diffusion layer 52 in FIG. 10 and the total diffusion layer area of the diffusion layer 53 in FIG. . 9 to 11 is a pattern in which the gate peripheral length, which is the peripheral length of the diffusion layer adjacent to the gate 55, is changed. The substrate potential in the gated diffusion layer load pattern is the same as the substrate potential of the ROSC section (11 in FIG. 2A). When the substrate is formed of an N + diffusion layer, the substrate potential is GND. When the substrate is formed of a P + diffusion layer, the substrate potential is Vdd. A gate terminal (not shown) electrically connected to the diffusion layers 50, 52, 53 of the load portion (12 in FIG. 2A) is an independent terminal so that an arbitrary potential can be applied. .

  Next, a parameter optimization method according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a flowchart schematically showing the parameter optimization method according to the first embodiment of the present invention. FIG. 13 shows measured values and simulations of Tpd when there is no load portion in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the invention and when there is a wiring load pattern. It is the graph which showed the value typically. FIG. 14 shows measured values and simulation values of Tpd under condition 1 when the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention has a gate load pattern (before and after optimization). It is the graph which showed typically the gate load number dependence. FIG. 15 shows measured values and simulation values of Tpd under condition 2 when the gate load pattern is included in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention (before and after optimization). It is the graph which showed typically the gate load number dependence. FIG. 16 shows measured values and simulation values (before and after optimization) of the Tpd when the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention has a diffusion layer load pattern (STI configuration). Is a graph schematically showing the dependency of STI on the STI circumference. FIG. 17 is a graph schematically showing the relationship between the diffusion layer load pattern (STI configuration) and the wiring load pattern Tpd in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. It is. FIG. 18 shows measured values and simulation values (before and after optimization) of the Tpd when the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention has a diffusion layer load pattern (gate configuration). ) Is a graph schematically showing the dependency on the gate circumference. FIG. 19 is a graph schematically showing the relationship between the diffusion layer load pattern (gate configuration) and the wiring load pattern Tpd in the ROSC pattern of the semiconductor device used in the parameter optimization method according to the first embodiment of the present invention. It is.

  First, as a DC characteristic optimization flow, a model that reproduces the DC characteristic of the ROSC pattern (see FIG. 1A) is prepared (step A1 in FIG. 12). Here, DC characteristics are measured from a pattern obtained by extracting each terminal of one NMOS and PMOS in the ROSC pattern (10A in FIG. 1A), and the DC parameters are optimized. Specifically, basic characteristics such as an IdVg characteristic between the drain current Id and the gate voltage Vg and an IdVd characteristic between the drain current Id and the drain voltage Vd are measured and reflected in the model parameters.

  Next, the propagation delay time (Tpd) of the ROSC pattern (see FIGS. 1A, 2A, and 3 to 11) under each bias condition is measured (actual measurement, simulation) (step of FIG. 12). A2). In the simulation, a model in which parameters are adjusted so as to reproduce the DC measurement result is used.

  Here, in the ROSC pattern without load portion (see FIG. 1A), the wiring load pattern (see FIG. 3), and the STI configuration pattern of the diffusion layer load pattern (see FIGS. 6 to 8), the substrate is N +. When the substrate is formed of a diffusion layer, the substrate potential is fixed to GND. When the substrate is formed of a P + diffusion layer, the substrate potential is fixed to Vdd and Tpd is measured.

  Further, since the gate load pattern (see FIGS. 4 and 5) is a pattern in which each terminal of the transistor of the load unit 12 can be arbitrarily changed, the load unit 12 is used in the evaluation for capturing the gate capacitance. The source terminal 46, the drain terminal 47, and the substrate terminal 48 of the transistor are fixed at −Vdd (or a bias condition in a state where a channel is formed), and Tpd is measured (condition 1). On the other hand, for the purpose of evaluating the gate overlap capacitance, the source terminal 46 and the drain terminal 47 are fixed to Vdd, and the substrate terminal 48 is fixed to GND (or a bias condition in which a channel is not formed), and Tpd is measured. Perform (Condition 2).

  In the diffusion layer load pattern (gate configuration) (see FIGS. 9 to 11), the gate potential related to the gate 55 of the load portion is fixed to GND (or a bias condition in which a channel is not formed), and Tpd is measured. Do.

  Next, the error between the measured value of Tpd obtained in each ROSC pattern (see FIGS. 1A, 2A, and 3 to 11) and the simulation value is calculated. The parameters of the MOS transistor model in the simulation program are optimized (Step A3 to Step A10 in FIG. 12). The error (Tpd error) between the measured value of Tpd and the simulation value of each pattern has a relationship of [Equation 1] to [Equation 5].

  The Tpd error (ΔTpd_ring) of the ROSC pattern without load (see FIG. 1A) has the relationship of [Equation 1].

[Formula 1]
ΔTpd_ring = Tpd_ring_meas−Tpd_ring_sim = ΔCGate + ΔCjtotal + ΔWire_ring
* Tpd_ring_meas: Tpd measurement value of ROSC pattern without load
Tpd_ring_sim: Simulation value of Tpd of ROSC pattern without load ΔCGate = ΔCg + ΔCov
ΔCGate: Error due to gate load capacitance of ROSC pattern without load ΔCg: Error due to gate capacitance component ΔCov: Error due to gate overlap capacitance component ΔCjtotal = ΔCj + ΔCjsw + ΔCjswg
ΔCjtotal: Error due to diffusion layer load capacitance of ROSC pattern without load ΔCj: Error due to capacitance component at the bottom of diffusion layer ΔCjsw: Error due to diffusion layer STI peripheral long capacitance component ΔCjswg: Error due to diffusion layer gate peripheral length capacitance component ΔWire_ring: No load Error due to wiring load of ROSC pattern

  The Tpd error (ΔTpd_wire_load) of the wiring load pattern (see FIG. 3) has the relationship of [Formula 2].

[Formula 2]
ΔTpd_wire_load = Tpd_wire_load_meas−Tpd_wire_load_sim = ΔTpd_ring−ΔWire_load
* Tpd_wire_load_meas: measured value of Tpd of wiring load pattern
Tpd_wire_load_sim: Tpd simulation value of wiring load pattern ΔTpd_ring: Tpd error of ROSC pattern without load ΔWire_load: Error of wiring load due to load

  The Tpd error (ΔTpd_CGate_load) of the gate load pattern (see FIGS. 4 and 5) has the relationship of [Formula 3].

[Formula 3]
ΔTpd_CGate_load = Tpd_CGate_load_meas−Tpd_CGate_load_sim
= ΔTpd_wire_load + ΔCGate_load
* Tpd_CGate_load_meas: Tpd measurement value of gate load pattern
Tpd_CGate_load_sim: Tpd simulation value of the gate load pattern ΔTpd_wire_load: Tpd error of the wiring load pattern ΔCGate_load: Gate load capacitance-induced error of the gate load pattern

  If the gate load capacitance-induced error (ΔCGate_load) of the gate load pattern is optimized, the error of the gate load capacitance-induced error (ΔCGate) of the ROSC pattern without load is eliminated at the same time.

  The Tpd error (ΔTpd_CjSTI_load) of the diffusion layer load pattern (STI configuration) (see FIGS. 6 to 8) has the relationship of [Equation 4].

[Formula 4]
ΔTpd_CjSTI_load = Tpd_Cj_load_meas−Tpd_Cj_load_sim
= ΔTpd_wire_load + ΔCjsw_load + ΔCj_load
* Tpd_Cj_load_meas: Tpd measurement of diffusion layer load pattern (STI configuration)
Tpd_Cj_load_sim: Simulation value of Tpd of diffusion layer load pattern (STI configuration) ΔTpd_wire_load: Tpd error of wiring load pattern ΔCjsw_load: Error due to diffusion layer STI peripheral length capacitance component of diffusion layer load pattern (STI configuration) ΔCj_load: Diffusion layer load pattern ( STI structure) Diffusion layer bottom surface capacitance component error

  If the error of the diffusion layer STI peripheral length component-derived error (ΔCjsw_load) and the diffusion layer bottom surface capacitance component-derived error (ΔCj_load) of the diffusion layer load pattern (STI configuration) is optimized, the diffusion layer of the ROSC pattern without load The STI peripheral long capacitance component error (ΔCjsw) and the diffusion layer bottom capacitance component error (ΔCj) are also eliminated.

  The Tpd error (ΔTpd_Cjate_load) of the diffusion layer load pattern (gate configuration) (see FIGS. 9 to 11) has the relationship of [Equation 5].

[Formula 5]
ΔTpd_Cjate_load = Tpd_Cj_load_meas−Tpd_Cj_load_sim
= ΔTpd_wire_load + ΔCjswg_load + ΔCj_load + ΔCov_load
* Tpd_Cj_load_meas: Tpd measurement of diffusion layer load pattern (gate configuration)
Tpd_Cj_load_sim: Simulation value of Tpd of diffusion layer load pattern (gate configuration) ΔTpd_wire_load: Tpd error of wiring load pattern ΔCjswg_load: Diffusion layer gate peripheral length capacitance component error of diffusion layer load pattern (gate configuration) ΔCj_load: Diffusion layer load pattern ( Diffusion layer bottom surface component error due to gate configuration) ΔCov_load: Diffusion layer load pattern (gate configuration) gate overlap capacitance component error

  In addition, the diffusion layer bottom pattern component error (ΔCj_load) of the diffusion layer load pattern (gate configuration) is optimized, and the gate overlap capacitance component error (ΔCov_load) of the diffusion layer load pattern (gate configuration) is optimized. If this is the case, the diffusion layer load pattern (gate configuration) diffusion is the only error inherent in the diffusion layer load pattern (gate configuration) because the diffusion layer load pattern (gate configuration) causes only the diffusion layer gate peripheral length capacitance component error (ΔCjswg_load). If the layer gate peripheral length capacitance component-derived error (ΔCjswg_load) is optimized, the error of the diffusion layer gate peripheral length capacitance component-derived error (ΔCjswg) of the ROSC pattern without load is eliminated.

  The transistors formed in the ROSC portion (11 in FIGS. 1A and 2A) of each ROSC pattern (see FIGS. 1A, 2A, and 3 to 11) and The conditions for forming the transistors, diffusion layers, and gates of the load portion (12 in FIG. 2A) are based on the same process conditions.

  FIG. 13 shows the measured value and simulation value of Tpd of the ROSC pattern without load (see FIG. 1A), and the measured value and simulation value of Tpd of the wiring load pattern (see FIGS. 2A and 3). Show. The ultimate goal is to set the error (ΔTpd_ring in FIG. 13) between the measured value (Tpd_ring_meas) of the Tpd and the simulation value (Tpd_ring_sim) of the ROSC pattern without load (see FIG. 1A) to “zero”. . The relationship between the errors of each pattern is as shown in [Formula 1] and [Formula 2]. These ΔTpd_rings can be easily adjusted by adjusting parameters so that the slopes of the Tpd-load dependency (asymptotic line) of each load pattern coincide with each other, so that the ROSC unit (11 in FIG. 1A and FIG. ) Error can be eliminated.

  Details of the parameter optimization method (step A3 to step A10 in FIG. 12) for each specific load pattern (see FIGS. 2A and 3 to 11) will be described below.

  After step A2, the slopes of the gate load pattern (see FIGS. 4 and 5), the measured value of the dependency of the Tpd on the number of gates and the slope of the simulation value are calculated under Condition 1, and it is determined whether or not the slopes match. (Step A3 in FIG. 12). Condition 1 is a bias condition in which the channel of the load transistor is formed. When the load transistor is NMOS, the source terminal 46, the drain terminal 47, and the substrate terminal 48 are fixed to the potential −Vdd, and the load transistor is PMOS. In this case, the source terminal 46, the drain terminal 47, and the substrate terminal 48 are fixed at the Vdd potential. FIG. 14 shows measured values and simulation values of Tpd-gate number dependency under condition 1. The deviation of the slope indicates an error (ΔCg) between the actually measured value and the simulation value of the gate capacitance parameter (Cg). If the actual measurement of the dependency of Tpd on the number of gates and the slopes of the simulation match (YES in step A3), the process proceeds to step A5.

  If the measured value of the dependency on the number of gates of Tpd does not match the slope of the simulation value (NO in step A3), the gate capacitance parameter (Cg) is set so that the slope of the simulation value matches the slope of the measured value. By adjusting, the gate capacitance component-induced error (ΔCg) is optimized (step A4 in FIG. 12).

  In the case of YES in step A3 or after step A4, the slopes of the measured value and the simulation value of the gate load pattern dependency (see FIGS. 4 and 5) of the Tpd on the number of gates are calculated according to condition 2, and each slope is calculated. Are matched (step A5 in FIG. 12). Condition 2 is a bias condition in which the channel of the load transistor is not formed. When the load transistor is NMOS, the source terminal 46 and the drain terminal 47 are fixed to the Vdd potential, and the substrate terminal 48 is fixed to the GND potential. When the load transistor is a PMOS, the source terminal 46 and the drain terminal 47 are fixed to the −Vdd potential, and the substrate terminal 48 is fixed to the GND potential. FIG. 15 shows measured values and simulation values of Tpd-gate number dependency under condition 2. This deviation in inclination indicates an error (ΔCov) of the gate overlap capacitance parameter (Cov). When the measured value of the dependency of Tpd on the number of gates and the slope of the simulation value match (YES in step A5), the process proceeds to step A7.

  When the measured value of the dependency of Tpd on the number of gates does not match the slope of the simulation value (NO in step A5), the gate overlap capacitance parameter (Cov) is set so that the slope of the simulation value matches the slope of the measured value. Is adjusted to optimize the gate overlap capacitance component-derived error (ΔCov) (step A6 in FIG. 12).

  In the case of YES in Step A5 or after Step A6, the slopes of the measured values and the simulation values of the dependency of the Tpd on the STI circumference length of the diffusion layer load pattern (STI configuration; see FIGS. 6 to 8) are calculated, It is determined whether or not the difference between each slope and Tpd when the STI perimeter is 0 and the Tpd of the wiring load pattern (see FIGS. 3 and 4) match (step A7 in FIG. 12). Here, the STI perimeter is the perimeter of the diffusion layer in contact with the STI. 16 and 17 show measured values and simulation values of Tpd-STI perimeter length dependence. The measured value of the dependency of Tpd on the STI perimeter and the slope of the simulation value, and the difference between the Tpd when the STI perimeter is 0 and the Tpd of the wiring load pattern (see FIGS. 3 and 4) match ( YES at step A7), the process proceeds to step A9.

  The measured value of the dependency of Tpd on the STI perimeter and the slope of the simulation value, and the difference between the Tpd when the STI perimeter is 0 and the Tpd of the wiring load pattern (see FIGS. 3 and 4) do not match ( In step A7, the parameters are optimized as follows (step A8 in FIG. 12).

  Regarding the deviation of the inclination, the diffusion layer STI peripheral long capacity parameter (Cjsw) is adjusted so that the inclination of the simulation value matches the inclination of the actual measurement value, as in the case of Tpd-gate number dependency (see FIGS. 14 and 15). By doing so, the diffusion layer STI peripheral long capacitance component-induced error (ΔCjsw) is optimized (see FIG. 16). If only the differences do not match, the optimization of ΔCjsw can be omitted.

  Regarding the difference, the intersection (STI perimeter length = 0) between the slope line and the Y axis (vertical axis) indicates the diffusion layer bottom surface capacitance parameter (Cj), so that the STI perimeter length = 0. Tpd sets the diffusion layer bottom surface capacitance parameter (Cj) so that the difference between the simulation values (Cj_delta (sim)) matches the difference between the actual measurement values (Cj_delta (meas)) so that the relationship of the following [Equation 6] holds. By adjusting, the diffusion layer bottom surface capacitance component-derived error (ΔCj) is optimized (see FIG. 17). If only the slopes do not match, the optimization of ΔCj can be omitted.

[Formula 6]
Cj_delta (meas) = Tpd_wire_load_meas−Tpd_CjSTI_load_meas
Cj_delta (sim) = Tpd_wire_load_sim−Tpd_CjSTI_load_sim
Cj_delta (meas) = Cj_delta (sim)
* Tpd_wire_load_meas: Measured value of Tpd of wiring load pattern
Tpd_CjSTI_load_meas: Measured value of Tpd when STI perimeter = 0
Tpd_wire_load_sim: Tpd simulation value of the wiring load pattern (after optimization)
Tpd_CjSTI_load_sim: Simulation value of Tpd with STI perimeter = 0 (after optimization)

  In the case of YES in Step A7 or after Step A8, the slopes of the measured values and the simulation values of the dependency of the Tpd on the gate circumference length of the diffusion layer load pattern (gate configuration; see FIGS. 9 to 11) are calculated, It is determined whether or not the inclinations match (step A9 in FIG. 12). Here, the gate perimeter is the perimeter of the diffusion layer adjacent to the gate. FIG. 18 shows measured values and simulation values of the dependency on the Tpd-gate circumference. Note that in step A9, it is determined whether or not the difference between the Tpd when the STI perimeter is 0 and the Tpd of the wiring load pattern (see FIGS. 3 and 4) matches. It is not determined whether or not the difference between the Tpd when T is 0 and the Tpd of the wiring load pattern (see FIGS. 3 and 4) matches, but it is determined whether or not the difference in Tpd matches at step A7. If not, it may be determined in step A9 whether or not the differences in Tpd match, and then the parameters may be optimized with respect to the difference (see FIG. 19). If the measured value of the dependency of Tpd on the gate circumference and the slope of the simulation value match (YES in step A9), the process ends.

  When the measured values of the Spd perimeter length dependence of Tpd and the slopes of the simulation values do not match (NO in step A9), the slope of the simulation values is changed in the same manner as the Tpd-gate number dependence (see FIGS. 14 and 15). By adjusting the diffusion layer gate peripheral length capacitance parameter (Cjswg) so as to match the slope of the actual measurement value, the diffusion layer gate peripheral length capacitance component-derived error (ΔCjswg) is optimized (step A10 in FIG. 12). finish.

  In step A10, regarding the inclination, “Cjswg + Cov” is indicated, and the inclination error indicates “ΔCjswg_load + ΔCov_load”. Adjust the diffusion layer gate perimeter capacitance parameter (Cjswg) so that the gate overlap capacitance matches the slope with the parameter optimized by the gate load pattern (see Fig. 4 and Fig. 5). To optimize the diffusion layer gate peripheral long capacitance component-derived error (ΔCjswg). On the other hand, regarding the difference, the intersection of the slope line and the Y axis (vertical axis), that is, the value of Tpd when the gate length = 0, is the difference between the simulation values (Cj_delta) so that the relationship of [Equation 7] below is satisfied. (sim)) is optimized by adjusting the diffusion layer bottom surface capacitance parameter (Cj) so that the difference between the measured values (Cj_delta (meas)) matches (Cj_delta (meas)). Since ΔCj is optimized in step A8, the values of [Formula 6] and [Formula 7] automatically match.

[Formula 7]
Cj_delta (meas) = Tpd_wire_load_meas−Tpd_CjGate_load_meas,
Cj_delta (sim) = Tpd_wire_load_sim−Tpd_CjGate_load_sim
Cj_delta (meas) = Cj_delta (sim)
* Tpd_wire_load_meas: Measured value of Tpd of wiring load pattern
Tpd_CjGate_load_meas: Measured value of Tpd when gate perimeter = 0
Tpd_wire_load_sim: Tpd simulation value of the wiring load pattern (after optimization)
Tpd_CjGate_load_sim: Tpd simulation value with gate perimeter = 0 (after optimization)

  According to the first embodiment, the ROSC unit 11 and the load unit 12 connected to the output unit of each inverter 11a of the ROSC unit 11 are dimensioned (number of gates, diffusion layer STI circumference, diffusion layer gate circumference). By using the Tpd sensitivity without optimizing the parameters directly from the LCR meter by optimizing the parameters so that the measured slope of the Tpd-number (or dimension) dependence matches the slope of the simulation. Indirect parameters can be optimized. Further, since the parameters can be optimized with a pattern close to an actual circuit, such as the ROSC pattern, errors during actual circuit operation can be minimized.

  In addition, when verifying the coincidence between silicon and SPICE, it is possible to determine the cause of the error in Tpd from the circuit characteristics, and it is also possible to feed back the parameters in SPICE. In particular, with the adoption of an external fabless maker, it is becoming difficult to collect the raw characteristics of the element from a contractual viewpoint, and this embodiment is effective. The reason is that an error in element characteristics (between silicon and SPICE) related to Tpd can be quantified from a combination of measurement results with a plurality of circuit characteristics. Furthermore, even in the case of an internal fabless manufacturer who has no legal restrictions on the collection of device characteristics, the Tpd measurement is more inspected than the analog electrical measurement (capacitance characteristic curve, etc.). From the viewpoint of

  It should be noted that the embodiments and examples may be changed and adjusted within the scope of the entire disclosure (including claims and drawings) of the present invention and based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

10A, 10B ROSC pattern 11 ROSC section 11a Inverter (primitive gate circuit)
DESCRIPTION OF SYMBOLS 12 Load part 12a Load capacity 21 Gate 22, 23, 24, 25 Diffusion layer 26 GND wiring 27 Vdd wiring 28 Vin wiring 29 Vout wiring 30, 31, 32, 33, 34 Contact 35 wiring 36 Contact 37 wiring 38 Contact 40 Gate 41 Contact 42 Diffusion layer 43 Wiring 44 Contact 46 Source terminal 47 Drain terminal 48 Substrate terminal 50, 52, 53 Diffusion layer 51 Contact 55 Gate

Claims (12)

A wiring load pattern having a first wiring electrically connected to an output portion of each of the primitive gate circuits of a first ring oscillator unit in which a primitive gate circuit composed of a MOS transistor is coupled in an odd-numbered stage in a ring shape;
The output part of each primitive gate circuit of the second ring oscillator unit having the same configuration as the first ring oscillator unit is electrically connected to the gate of the MOS transistor serving as the load unit via the second wiring having the same configuration as the first wiring. Multiple gate load patterns connected together,
The output part of each primitive gate circuit of the third ring oscillator unit having the same configuration as the first ring oscillator unit is electrically connected to the diffusion layer serving as the load unit via the third wiring having the same configuration as the first wiring. A plurality of connected diffusion layer load patterns;
With
The plurality of gate load patterns have different capacitive loads for each pattern,
The plurality of diffusion layer load patterns have different capacitive loads for each pattern.   2. The semiconductor device according to claim 1, wherein the plurality of gate load patterns have different numbers of gates electrically connected to the second wiring for each pattern.   3. The gate load pattern is configured so that an arbitrary potential can be applied to each terminal of a source, a drain, and a substrate of the MOS transistor serving as the load section. The semiconductor device described.   4. The semiconductor device according to claim 1, wherein the plurality of diffusion layer load patterns have different numbers of diffusion layers electrically connected to the third wiring.   The plurality of diffusion layer load patterns include an STI configuration in which an STI is arranged in a region around the diffusion layer serving as the load unit, and a gate arranged in a region around the diffusion layer serving as the load unit. The semiconductor device according to claim 1, further comprising: a gate configuration including: The substrate potential of the load portion in the plurality of diffusion layer load patterns is the same potential as the substrate potential of the third ring oscillator portion,
6. The semiconductor device according to claim 5, wherein the gate of the gate configuration in the plurality of diffusion layer load patterns is configured to be able to apply an arbitrary potential. The semiconductor device according to claim 1, a measuring device electrically connected to the semiconductor device, and a computer that is electrically connected to the measuring device and executes a circuit simulation program. A parameter optimization method for optimizing a parameter of a MOS transistor model in a circuit simulation program,
Measuring and simulating the propagation delay time of the gate load pattern or the diffusion layer load pattern;
A step of calculating an inclination of an actual measurement value and a simulation value of load dependency of the propagation delay time;
A step of optimizing a predetermined parameter so that the slope of the simulation value is matched with the slope of the actual measurement value when the slope of the actual measurement value and the simulation value does not match;
The parameter optimization method characterized by including.   8. The parameter optimization according to claim 7, wherein in the step of measuring and simulating the propagation delay time, the propagation delay time due to the gate capacitance or gate overlap capacitance of the load portion of the gate load pattern is measured and simulated. Method.   9. The parameter optimization method according to claim 7, wherein in the step of calculating the inclination, an inclination of an actual measurement value and a simulation value of the dependence of the propagation delay time on the gate load pattern on the number of gates is calculated. .   In the step of calculating the inclination, an actual measurement of the dependency of the propagation delay time related to the diffusion layer load pattern on the STI perimeter of the diffusion layer in contact with the STI or the gate perimeter of the diffusion layer adjacent to the gate. 8. The parameter optimization method according to claim 7, wherein the slope of the value and the simulation value is calculated.   When the difference between the measured value and the simulation value of the propagation delay time when the STI peripheral length or the gate peripheral length is 0 and the propagation delay time of the wiring load pattern do not match, the difference between the simulation values is calculated. 11. The parameter optimization method according to claim 10, further comprising the step of optimizing other predetermined parameters so as to match the difference in values. The semiconductor device according to claim 1, a measuring device electrically connected to the semiconductor device, and a computer that is electrically connected to the measuring device and executes a circuit simulation program. A program for optimizing parameters of a MOS transistor model in a circuit simulation program,
Actually measuring and simulating the propagation delay time of the gate load pattern or the diffusion layer load pattern;
Calculating an actual measured value of the load dependence of the propagation delay time and a slope of a simulation value;
Optimizing predetermined parameters so that the slope of the simulation value matches the slope of the actual measurement value when the actual measurement value and the slope of the simulation value do not match;
A program characterized by having executed.

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