JP2013074713A - Charge pump and power-supply device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge pump that allows achieving a reduction in mounting area on a printed wiring board and cost.SOLUTION: A charge pump 100 uses body diodes 111d and 112d of floating NMOSFETs 111 and 112 that are integrated in a semiconductor device 110, as a charge and discharge switch for a flying capacitor 120.

Description

  The present invention relates to a charge pump and a power supply device using the same.

  A charge pump that generates an output voltage by positively boosting or negatively boosting an input voltage (including an inverted output) is widely used as a power source for applications that do not require a very high current supply capability. In addition, the charge pump is often used in combination with a switching regulator.

  FIG. 9 is a diagram illustrating a conventional example of a power supply device. In the power supply device of this conventional example, both the positive charge pump CPP and the negative charge pump CPN are configured as external circuits of an IC that forms a step-up switching regulator.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 05-244766 A

  However, in the power supply device of the above conventional example, a large number of discrete components are required to form the positive charge pump CPP and the negative charge pump CPN as external circuits of the IC. Was a problem.

  When the diode is integrated in the IC, a body diode Z1 of a PMOSFET (P channel type metal oxide semiconductor field effect transistor) is generally used (see FIG. 10).

  However, when a body diode Z1 of a PMOSFET is used as a diode (capacitor charge / discharge switch) included in the charge pump, when the body diode Z1 is turned on, it passes through a PNP-type bipolar transistor Z2 that is parasitic on the PMOSFET. Since a current flows from the drain of the PMOSFET toward the semiconductor substrate along the path, this current becomes a loss.

  In particular, when both the diode and the capacitor included in the charge pump are integrated in the IC, the capacitance value of the capacitor becomes very small (for example, several pF), so that the current supply capability of the charge pump becomes very small. . Therefore, in the conventional configuration in which the current escapes from the drain of the PMOSFET to the semiconductor substrate side, there is a possibility that the boosting operation by the charge pump may be hindered.

  In addition, in order to use the body diode Z1 of the PMOSFET as the diode included in the negative charge pump CPN, a negative voltage must be applied to the semiconductor substrate, which is difficult to handle.

  In view of the above-mentioned problems found by the inventors of the present application, the present invention provides a charge pump capable of realizing a reduction in mounting area and cost on a printed wiring board, and a power supply device using the same. The purpose is to provide.

  In order to achieve the above object, a charge pump according to the present invention has a configuration (first configuration) in which a body diode of a floating NMOSFET integrated in a semiconductor device is used as a charge / discharge switch for a flying capacitor. .

  In the charge pump having the first configuration, the floating NMOSFET includes a p-type semiconductor substrate, an n-type well formed on the p-type semiconductor substrate, and a p-type formed in the n-type well. A well, an n-type source region and an n-type drain region formed in the p-type well, and a gate electrode formed on a channel region sandwiched between the n-type source region and the n-type drain region And (a second configuration).

  In the charge pump having the second configuration, the p-type well may be configured to be electrically insulated from the p-type semiconductor substrate by the n-type well (third configuration).

  In the charge pump having the third configuration, the p-type semiconductor substrate may be connected to a ground terminal (fourth configuration).

  In the charge pump having the fourth structure, the n-type well surrounds the n-type buried insulating layer buried in the p-type semiconductor substrate and the n-type buried insulating layer. It is preferable to have a configuration (fifth configuration) including an n-type epitaxial insulating layer stacked up to the surface layer of the p-type semiconductor substrate.

  In the charge pump having the fifth configuration, the floating NMOSFET has a p-type low insulating layer formed between the p-type well and the n-type buried insulating layer (sixth configuration). ).

  Further, the charge pump having any one of the second to sixth configurations may be configured to generate a positive output voltage higher than the input voltage by charging and discharging the flying capacitor (seventh configuration).

  Further, in the charge pump having the seventh configuration, the n-type well, the p-type well, the n-type source region, and the gate electrode are short-circuited to become an anode of the body diode, and A configuration (eighth configuration) may be employed in which the n-type drain region becomes the cathode of the body diode.

  The charge pump having any one of the second to sixth configurations may be configured to generate and output a negative output voltage from the input voltage by charging and discharging the flying capacitor.

  Further, in the charge pump having the ninth configuration, the p-type well, the n-type source region, and the gate electrode are short-circuited to become an anode of the body diode, and the n-type drain region is the body body. It is preferable to adopt a configuration (tenth configuration) in which the n-type well is connected to the ground terminal as the cathode of the diode.

  In the charge pump having the ninth configuration, the p-type well serves as an anode of the body diode, and the n-type source region, the n-type drain region, and the gate electrode are short-circuited to each other. It is preferable to adopt a configuration (eleventh configuration) in which the n-type well is connected to a ground terminal as a cathode of a diode.

  Further, the charge pump having any one of the ninth to eleventh configurations includes a floating NMOSFET integrated in the semiconductor device as an electrostatic protection element connected between the output voltage application terminal and a ground terminal. The body diode may be used (a twelfth configuration).

  In the charge pump having any one of the first to twelfth configurations, the flying capacitor may be externally connected to the semiconductor device (a thirteenth configuration).

  In the charge pump having any one of the first to twelfth configurations, the flying capacitor may be configured to be integrated in the semiconductor device (fourteenth configuration).

  Further, the power supply device according to the present invention has a configuration (fifteenth configuration) having a charge pump having any one of the first to fourteenth configurations.

  According to the present invention, it is possible to provide a charge pump capable of realizing a reduction in mounting area and cost on a printed wiring board, and a power supply device using the charge pump.

The figure which shows one structural example of a positive charge pump Vertical section of floating NMOSFET 111 The figure which shows the 1st structural example of a negative charge pump Vertical section of floating NMOSFET 211 The figure which shows the 2nd structural example of a negative charge pump. Vertical section of floating NMOSFET 311 The figure which shows one structural example of a power supply device The figure which shows the example of 1 structure of the positive charge pump 13 Figure showing a conventional example of a power supply PMOSFET vertical section

<Positive charge pump>
FIG. 1 is a diagram illustrating a configuration example of a positive charge pump. The positive charge pump 100 of this configuration example includes a semiconductor device 110, a flying capacitor 120, and an output capacitor 130.

  In the semiconductor device 110, floating NMOSFETs [N channel type MOSFETs] 111 and 112 are integrated. Body diodes 111d and 112d are attached between the source and drain of the floating NMOSFETs 111 and 112, respectively. The positive charge pump 100 of this configuration example is characterized in that these body diodes 111d and 112d are used as charging / discharging switches for the flying capacitor 120. The device structure of the floating NMOSFETs 111 and 112 will be described in detail later.

  The anode of the body diode 111d is connected to the application terminal for the input voltage IN. The cathode of the body diode 111 d is connected to the first end of the flying capacitor 120. A second end of the flying capacitor 120 is connected to an application end of a switch voltage SW (a rectangular wave voltage pulse-driven between the input voltage IN and the ground voltage GND). The anode of the body diode 112d is connected to the first end of the flying capacitor 120. The cathode of the body diode 112d is connected to the application terminal of the output voltage OUT and the first terminal of the output capacitor 130. A second terminal of the output capacitor 130 is connected to the ground terminal.

  In the positive charge pump 100 of the above configuration example, when the switch voltage SW is at the low level (GND), the body diode 111d is in the forward bias state, and the body diode 112d is in the reverse bias state. Therefore, the flying capacitor 120 is charged by the current flowing through the path from the application terminal of the input voltage IN to the application terminal of the switch voltage SW (GND) through the body diode 111d and the flying capacitor 120. At this time, the voltage V1 appearing at the first end of the flying capacitor 120 is substantially the input voltage IN.

  Thereafter, when the switch voltage SW rises from the low level (GND) to the high level (IN), the switch voltage SW also rises (GND → IN) to the voltage V1 due to the conservation law of the charge stored in the flying capacitor 120. A corresponding rise (IN → 2 × IN) occurs. At this time, the body diode 111d is in a reverse bias state, and the body diode 112d is in a forward bias state. Therefore, the output capacitor 130 is charged by the current flowing through the path from the voltage V1 application end to the ground end via the body diode 112d and the output capacitor 130. At this time, the output voltage OUT appearing at the first end of the output capacitor 130 is approximately the voltage V1 (= 2 × IN).

  Therefore, in the positive charge pump 100 of this configuration example, the positive output voltage OUT (= 2 × IN) higher than the input voltage IN can be generated by charging and discharging the flying capacitor 120 using the switch voltage SW. it can.

  FIG. 2 is a longitudinal sectional view of the floating NMOSFET 111. Since both floating NMOSFETs 111 and 112 have the same device structure, only the floating NMOSFET 111 will be described here as an example.

  The floating NMOSFET 111 includes a p-type semiconductor substrate A1, an n-type buried insulating layer A2, an n-type epitaxial insulating layer A3, a p-type low insulating layer A4, a p-type well A5, an n-type source region A6, n Type drain region A7, gate electrode A8, and contact regions A9 to A11.

  The p-type semiconductor substrate A1 is a base material for integrating circuit elements of the semiconductor device 110.

  The n-type buried insulating layer A2 is an n-type impurity layer (so-called B / L [buried layer] layer) buried in the p-type semiconductor substrate A1.

  The n-type epitaxial insulating layer A3 is an n-type impurity layer that is stacked up to the surface layer of the p-type semiconductor substrate A1 so as to surround the n-type buried insulating layer A2.

  That is, in the floating NMOSFET 111, the n-type well (A2 + A3) is formed on the p-type semiconductor substrate A1 by the n-type buried insulating layer A2 and the n-type epitaxial insulating layer A3.

  The p-type low insulating layer A4 is a p-type impurity layer (so-called L / I [low isolation] layer) formed between the p-type well A5 and the n-type buried insulating layer A2.

  The p-type well A5 is a p-type impurity layer formed in the n-type well (A2 + A3). That is, the p-type well A5 is electrically insulated from the p-type semiconductor substrate A1 by the n-type well (A2 + A3). The p-type well A5 corresponds to the back gate region (BG) of the floating NMOSFET 111.

  The n-type source region A6 is an n-type impurity region formed in the p-type well A5 as the source (S) of the floating NMOSFET 111.

  The n-type drain region A7 is an n-type impurity region formed in the p-type well A5 as the drain (D) of the floating NMOSFET 111.

  The gate electrode A8 is a metal electrode formed on the channel region sandwiched between the n-type source region A6 and the n-type drain region A7 as the gate (G) of the floating NMOSFET 111.

  The contact region A9 is a p-type impurity region formed in the p-type well A5 in order to establish electrical connection with the back gate (BG) of the floating NMOSFET 111.

  The contact region A10 is an n-type impurity region formed in the n-type epitaxial insulating layer A3 in order to establish electrical connection with the n-type well (A2 + A3).

  The contact region A11 is a p-type impurity region formed in the p-type semiconductor substrate A1 in order to establish electrical connection with the p-type semiconductor substrate A1. The p-type semiconductor substrate A1 is connected to the ground terminal via the contact region A11.

  In the floating NMOSFET 111 having the above device structure, the n-type well (A2 + A3), the p-type well A5, the n-type source region A6, and the gate electrode A8 are short-circuited to become the anode of the body diode 111d, and the n-type drain Region A7 becomes the cathode of body diode 111d.

  The floating NMOSFET 111 having the above device structure is accompanied by a pnp bipolar transistor 111p having a p-type semiconductor substrate A1 as a collector, an n-type buried insulating layer A2 as a base, and a p-type low insulating layer A4 as an emitter. To do. However, the transistor 111p is not turned on because the base and the emitter are short-circuited.

  Thus, if the positive charge pump 100 uses the body diode associated with the floating NMOSFET as the charging / discharging switch for the flying capacitor, the charging / discharging switch that has been conventionally configured as an external component without being affected by the parasitic element is used. Since the discharge switch can be integrated in the semiconductor device, it is possible to reduce the mounting area and cost on the printed wiring board.

  In order to avoid unintended on-transition of the pnp bipolar transistor 111p, it is desirable to design the contact regions A10 and A11 as large as possible.

<Negative charge pump>
FIG. 3 is a diagram illustrating a first configuration example of the negative charge pump. The negative charge pump 200 of the first configuration example includes a semiconductor device 210, a flying capacitor 220, and an output capacitor 230.

  In the semiconductor device 210, floating NMOSFETs 211 to 213 are integrated. Body diodes 211d to 213d are attached between the sources and drains of the floating NMOSFETs 211 to 213, respectively. The negative charge pump 200 of the first configuration example includes the body diodes 211d to 211d as charge / discharge switches of the flying capacitor 220 and electrostatic protection elements connected between the application terminal of the output voltage OUT and the ground terminal. It is characterized in that 213d is used. The device structure of the floating NMOSFETs 211 to 213 will be described in detail later.

  The cathode of the body diode 211d is connected to the ground terminal. The anode of the body diode 211 d is connected to the first end of the flying capacitor 220. A second end of the flying capacitor 220 is connected to an application end of a switch voltage SW (a rectangular wave voltage pulse-driven between the input voltage IN and the ground voltage GND). The cathode of the body diode 212d is connected to the first end of the flying capacitor 220. The anode of the body diode 212 d is connected to the application terminal of the output voltage OUT and the first terminal of the output capacitor 230. The second terminal of the output capacitor 230 is connected to the ground terminal. The cathode of the body diode 213d is connected to the ground terminal. The anode of the body diode 213d is connected to the application terminal of the output voltage OUT.

  In the negative charge pump 200 of the first configuration example described above, when the switch voltage SW is at a high level (IN), the body diode 211d is in a forward bias state and the body diode 212d is in a reverse bias state. Therefore, the flying capacitor 220 is charged by the current flowing through the path from the application terminal of the switch voltage SW (IN) to the ground terminal via the flying capacitor 220 and the body diode 211d. At this time, the voltage V2 appearing at the first end of the flying capacitor 120 is substantially the ground voltage GND.

  Thereafter, when the switch voltage SW decreases from the high level (IN) to the low level (GND), the voltage V2 also decreases (IN → GND) according to the conservation law of the charge stored in the flying capacitor 220. A corresponding decrease (GND → -IN) occurs. At this time, the body diode 211d is in a reverse bias state, and the body diode 212d is in a forward bias state. Therefore, the output capacitor 230 is charged by the current flowing through the path from the ground terminal to the application terminal of the voltage V2 via the output capacitor 230 and the body diode 212d. At this time, the output voltage OUT appearing at the first end of the output capacitor 230 is substantially the voltage V2 (= −IN).

  Therefore, in the negative charge pump 200 of this configuration example, the negative output voltage OUT (= −IN) lower than the input voltage IN can be generated by charging and discharging the flying capacitor 220 using the switch voltage SW. .

  FIG. 4 is a longitudinal sectional view of the floating NMOSFET 211. Since all the floating NMOSFETs 211 to 213 have the same device structure, only the floating NMOSFET 211 will be described here as an example. The device structure itself of the floating NMOSFETs 211 to 213 is the same as that of the above-described floating NMOSFETs 111 and 112, and the connection destination of the n-type well (A2 + A3) is not the n-type source region A6 but only the ground end. Is different.

  That is, in the floating NMOSFET 211, the p-type well A5, the n-type source region A6, and the gate electrode A8 are short-circuited to become the anode of the body diode 211d, and the n-type drain region A7 becomes the cathode of the body diode 211d. (A2 + A3) is connected to the ground terminal.

  In the floating NMOSFET 211 having the above device structure, similarly to the floating NMOSFET 111 described above, the p-type semiconductor substrate A1 is used as a collector, the n-type buried insulating layer A2 is used as a base, and the p-type low insulating layer A4 is used as an emitter. A pnp bipolar transistor 211p is attached. However, the transistor 211p is not turned on because the base potential is higher than the emitter potential.

  Thus, if the negative charge pump 200 using the body diode associated with the floating NMOSFET as the charging / discharging switch for the flying capacitor is used, the charging / discharging switch that has been conventionally configured as an external component without being affected by the parasitic element is used. Since the discharge switch can be integrated in the semiconductor device, it is possible to reduce the mounting area and cost on the printed wiring board.

  By the way, paying attention to the floating NMOSFET 212 connected between the flying capacitor 220 and the application terminal of the output voltage OUT, a negative output voltage OUT (for example, −10 V) is fixedly applied to the source (S). A voltage V2 (-10V to 0V) that is pulse-driven according to the switch voltage SW is applied to the drain (D). Therefore, when the high level of the switch voltage SW rises to a voltage value (for example, 12V) higher than the input voltage IN for some reason, the potential of the p-type well A5 is passed through the capacitor 211c and the resistor 211r associated with the p-type well A5. There was a risk of unintentional lifting. When such a potential increase in the p-type well A5 occurs, the n-type bipolar transistor 211n has the n-type buried insulating layer A2 as a collector, the p-type well A5 as a base, and the n-type source region A6 as an emitter. Current may flow, which may cause the negative charge pump 200 to malfunction. Therefore, in order to solve the above-described problems that may occur in the negative charge pump 200 of the first configuration example, the negative charge pump 300 of the second configuration example is proposed in the next section.

  FIG. 5 is a diagram illustrating a second configuration example of the negative charge pump. The negative charge pump 300 of the second configuration example includes a semiconductor device 310, a flying capacitor 320, and an output capacitor 330. In the semiconductor device 310, floating NMOSFETs 311 to 313 are integrated. The negative charge pump 300 of the second configuration example has basically the same configuration as that of the first configuration example, but the connection between the floating NMOSFETs 311 and 312 is different from that of the first configuration example.

  FIG. 6 is a longitudinal sectional view of the floating NMOSFET 311. Since floating NMOSFETs 311 and 312 both have the same device structure, only floating NMOSFET 311 will be described here as an example.

  In the floating NMOSFET 311, the p-type well A5 becomes the anode of the body diode 311d, and the n-type source region A6, the n-type drain region A7, and the gate electrode A8 are short-circuited to each other to become the cathode of the body diode 311d. ) Is connected to the ground terminal. With such a configuration, the npn-type bipolar transistor 211n shown in FIG. 4 does not function, and the above-described problem does not occur.

  The floating NMOSFET 311 is also accompanied by an npn bipolar transistor (not shown in FIG. 6) having an n-type buried insulating layer A2 as a collector, a p-type well A5 as a base, and an n-type drain region A6 as an emitter. However, in this case, since the switch voltage SW that causes the base potential to be raised is applied to the emitter, unnecessary current does not flow.

<Power supply unit>
FIG. 7 is a diagram illustrating a configuration example of a power supply device using a charge pump. The power supply device 1 of this configuration example includes a semiconductor device 10, a liquid crystal drive device 20, and a liquid crystal display device 30, and also includes a coil L1 and a Schottky barrier as discrete components externally connected to the semiconductor device 10. It has a diode D1, output capacitors C1 and C2, and a flying capacitor C3.

  The semiconductor device 10 is a multi-output power supply IC that generates two systems of output voltages OUT1 and OUT2 from the input voltage IN and supplies them to the liquid crystal driving device 20. In the semiconductor device 10, a switching regulator 11, a negative charge pump 12, a positive charge pump 13, an EEPROM (Electrically Erasable Programmable Read-Only Memory) 14, and a logic unit 15 are integrated.

  Outside the semiconductor device 10, the first end of the coil L1 is connected to the application end of the input voltage IN. The second end of the coil L1 and the anode of the Schottky barrier diode D1 are both connected to the application end of the switch voltage SW (one end of the output transistor included in the switching regulator 11). The cathode of the Schottky barrier diode D1 is connected to the application terminal of the output voltage OUT1. The output capacitor C1 is connected between the application terminal of the output voltage OUT1 and the ground terminal. The output capacitor C2 is connected between the application terminal of the output voltage OUT2 and the ground terminal. The flying capacitor C 3 is connected between the application terminal of the switch voltage SW and the negative charge pump 12.

  The switching regulator 11 functions as a component of a step-up DC / DC converter that generates an output voltage OUT1 higher than the input voltage IN by driving a coil L1 that is an energy storage element by on / off control of an output transistor. To do.

  The negative charge pump 12 generates a negative output voltage OUT2 (= −IN) lower than the input voltage IN by charging and discharging the flying capacitor C3 using the switch voltage SW. As the negative charge pump 12, the negative charge pump 200 or the negative charge pump 300 described above may be used. The negative charge pump 12 is required to have a large current supply capability as a power source for the liquid crystal driving device 20. For this reason, it is desirable that the flying capacitor C3 is externally connected to the semiconductor device 10 in view of increasing the capacity.

  The positive charge pump 13 generates a write voltage VPP to the EEPROM 14 in response to the enable signal EN from the logic unit 15.

  The EEPROM 14 receives access from the logic unit 15 and holds the setting information DATA (setting information such as output voltage and switching frequency) of the semiconductor device 10 in a nonvolatile manner.

  The logic unit 15 drives the positive charge pump 13 to generate the write voltage VPP by setting the enable signal EN to the positive charge pump 13 to the logic level at the time of writing when writing data to the EEPROM 14, and at the same time, the EEPROM 14. The setting information DATA is written to. As described above, if the positive charge pump 13 is driven only when data is written to the EEPROM 14, the power consumption of the semiconductor device 10 during normal operation can be reduced.

  FIG. 8 is a diagram illustrating a configuration example of the positive charge pump 13. The positive charge pump 13 of this configuration example includes floating NMOSFETs X1 to X5, flying capacitors X6 to X9, an output capacitor X10, regulators X11 and X12, a level shifter X13, and an inverter X14.

  In the positive charge pump 13 of this configuration example, body diodes associated with the floating NMOSFETs X1 to X5 are used as charging / discharging switches for the flying capacitors X6 to X9. The basic operation of the positive charge pump 13 is the same as that of the positive charge pump 100 described above, and charging and discharging of the flying capacitors X6 to X9 using the switch voltage SW (and its logic inversion signal) causes the regulator X11 to A voltage Vc (= about 4 × Vb) higher than the input voltage Vb is generated.

  The regulator X11 generates a voltage Vb (for example, 7V to 10V) from the voltage Va (for example, 10V to 40V). The regulator X12 generates a write voltage VPP (for example, 18.5 V) from the voltage Vc (for example, 24 V to 36 V).

  The level shifter X13 is pulse-driven between the voltage Vb and the ground voltage GND (0V) in response to the input of the clock signal CLK that is pulse-driven between the voltage V0 (for example, 3V) and the ground voltage GND (0V). The switch voltage SW is generated. The switch voltage SW is directly applied to one end of the flying capacitors X6 and X8, while being inverted and applied to each end of the flying capacitors X7 and X9 via the inverter X14. If the write voltage VPP is generated by the charge pump operation according to the clock signal CLK, the dependency of the write voltage VPP on the switch voltage SW can be eliminated.

  As described above, regarding the technical idea of using the body diode associated with the floating NMOSFET as the charging / discharging switch of the flying capacitor, a high voltage (the write voltage VPP of the EEPROM 14 in this configuration) is required inside the semiconductor device 10. It is also effective when

  Since the positive charge pump 13 is not required to have a large current supply capability, it is desirable that all of the flying capacitors X6 to X9 be integrated in the semiconductor device 10 with priority given to the reduction of discrete elements.

<Other variations>
In the above embodiment, the configuration in which the present invention is applied to the power supply device mounted on the liquid crystal display device has been described as an example. However, the application target of the present invention is not limited to this, The present invention can be widely applied to all power supply devices used for other purposes.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, mutual replacement of a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The power supply apparatus according to the present invention can be used as a power supply for various applications such as LCD-TV, PDP-TV, DVD recorder, and BD recorder.

DESCRIPTION OF SYMBOLS 1 Power supply device 10 Semiconductor device 11 Switching regulator 12 Negative charge pump 13 Positive charge pump 14 EEPROM
DESCRIPTION OF SYMBOLS 15 Logic part 20 Liquid crystal drive device 30 Liquid crystal display device 100 Positive charge pump 110 Semiconductor device 111,112 Floating NMOSFET
111d, 112d body diode 111p pnp type bipolar transistor 120 flying capacitor 130 output capacitor 200 negative charge pump 210 semiconductor device 211, 212, 213 floating NMOSFET
211d, 212d, 213d body diode 211p pnp bipolar transistor 211n npn bipolar transistor 211c capacitor 211r resistor 220 flying capacitor 230 output capacitor 300 negative charge pump 310 semiconductor device 311, 312, 313 floating NMOSFET
311d, 312d, 313d Body diode 320 Flying capacitor 330 Output capacitor A1 p-type semiconductor substrate A2 n-type buried insulating layer A3 n-type epitaxial insulating layer A4 p-type low insulating layer A5 p-type well (back gate region)
A6 n-type source region A7 n-type drain region A8 gate electrode A9 contact region A10 contact region A11 contact region X1 to X5 Floating NMOSFET
X6 to X10 Capacitor X11, X12 Regulator X13 Level Shifter X14 Inverter L1 Coil D1 Schottky Barrier Diode C1, C2 Output Capacitor C3 Flying Capacitor

Claims (15)

  A charge pump using a floating NMOSFET body diode integrated in a semiconductor device as a charge / discharge switch for a flying capacitor. The floating NMOSFET is
a p-type semiconductor substrate;
An n-type well formed on the p-type semiconductor substrate;
A p-type well formed in the n-type well;
An n-type source region and an n-type drain region formed in the p-type well;
A gate electrode formed on a channel region sandwiched between the n-type source region and the n-type drain region;
The charge pump according to claim 1, comprising:   The charge pump according to claim 2, wherein the p-type well is electrically insulated from the p-type semiconductor substrate by the n-type well.   The charge pump according to claim 3, wherein the p-type semiconductor substrate is connected to a ground terminal. The n-type well is
An n-type buried insulating layer buried in the p-type semiconductor substrate;
An n-type epitaxial insulating layer laminated up to a surface layer of the p-type semiconductor substrate so as to surround the n-type buried insulating layer;
The charge pump according to claim 4, comprising:   6. The charge pump according to claim 5, wherein the floating NMOSFET has a p-type low insulating layer formed between the p-type well and the n-type buried insulating layer.   The charge pump according to any one of claims 2 to 6, wherein the flying capacitor is charged / discharged to generate a positive output voltage higher than an input voltage.   The n-type well, the p-type well, the n-type source region, and the gate electrode are short-circuited to be an anode of the body diode, and the n-type drain region is a cathode of the body diode. The charge pump according to claim 7.   The charge pump according to any one of claims 2 to 6, wherein the flying capacitor is charged / discharged to generate a negative output voltage from an input voltage.   The p-type well, the n-type source region, and the gate electrode are short-circuited to be the anode of the body diode, the n-type drain region is the cathode of the body diode, and the n-type well is connected to the ground terminal The charge pump according to claim 9, wherein the charge pump is provided.   The p-type well becomes the anode of the body diode, the n-type source region, the n-type drain region, and the gate electrode are short-circuited to each other to become the cathode of the body diode, and the n-type well is connected to the ground terminal The charge pump according to claim 9, wherein the charge pump is provided.   12. The floating NMOSFET body diode integrated in the semiconductor device is used as an electrostatic protection element connected between the output voltage application terminal and the ground terminal. The charge pump as described in any one of Claims.   The charge pump according to claim 1, wherein the flying capacitor is externally connected to the semiconductor device.   The charge pump according to claim 1, wherein the flying capacitor is integrated in the semiconductor device.   A power supply device comprising the charge pump according to any one of claims 1 to 14.

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