JP2013074634A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter device that allows suppressing an adverse effect due to interference of a voltage between a plurality of inverters by a space-saving device.SOLUTION: An inverter device includes a first inverter connected to PN bus lines, a second inverter connected to the PN bus lines, and a clamp circuit connected between the first inverter and the second inverter in the PN bus lines. The clamp circuit includes a Zener diode and a switching element. A cathode of the Zener diode is connected to the P bus line of the PN bus lines and an anode is connected to the N bus line of the PN bus lines. The switching element is interposed between the P bus line and the N bus line, and a control terminal is connected to the anode of the Zener diode.

Description

  The present invention relates to an inverter device.

  Conventionally, as disclosed in, for example, Japanese Patent Application Laid-Open No. 6-225516, an inverter device in which a plurality of inverters are connected to a common PN bus and a diode clip circuit is provided between the inverters is known. When the switching element is turned on or off in the inverter, a switching surge voltage is generated at both ends of the element. If this voltage is excessive, the device will be damaged and other devices will be adversely affected, so it is necessary to suppress the generation of surge voltage. Therefore, in the above conventional technique, a diode clipper circuit is used to suppress such an adverse effect due to an excessive surge voltage.

  Further, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-92817, a snubber device for suppressing a surge voltage generated at the time of switching of a switch in a power conversion device or the like is known. The snubber device in the publication has a snubber device for each switching element (IGBT or the like) in the power converter. This snubber device includes a Zener diode as a voltage determination circuit and a switching element (IGBT or the like). The Zener diode is connected to the control terminal of this switching element. When a surge voltage is generated in response to turning off of the switching element in the power converter, when the surge voltage reaches the zener voltage (Vz), a voltage is applied to the gate of the switching element of the snubber device, and the switching element of the snubber device Current can be passed while maintaining the voltage constant.

JP-A-6-225516 JP 2008-199788 A JP 2000-92817 A JP 2000-324797 A JP 2001-245466 A JP 2000-12780 A

  In recent years, there has been an increasing demand for downsizing and cost reduction in inverter devices. In response to such a demand, there is still room for improvement in the conventional technology.

  For example, Japanese Patent Laid-Open No. 6-225516 discloses that a diode clipper circuit is connected as close as possible to a switching element with a DC power source, and absorbs the energy of the inductance of the DC circuit with a capacitor when the element is turned off. Have been described. However, when a capacitor for dealing with surge voltage is inserted between the inverter and the inverter as described above, a sufficient space for inserting the capacitor between the inverter and the inverter is required. Due to this, there is a problem that it is difficult to reduce the size, and when three-dimensional wiring is performed, there is a problem that performance is deteriorated due to the terminal space for connection and the inductance of the wiring.

  In addition, when the switching surge voltage suppression circuit of the inverter is attached to each of the plurality of switching elements as in the prior art (snubber device) according to the above Japanese Patent Laid-Open No. 2000-92817, it is proportional to the number of switching elements. Installation space will increase. An inverter is generally provided with a plurality of switching elements. For example, a three-phase inverter requires six switching elements. When it is necessary to attach a switching surge voltage suppression circuit to all switching elements, the number of members and assembly cost also increase.

  The present invention has been made to solve the above-described problems, and provides an inverter device capable of suppressing adverse effects due to voltage interference among a plurality of inverters in a space-saving device. With the goal.

The inverter device according to the present invention is
A first inverter comprising one or more first main switching elements connected to a PN bus;
A second inverter comprising one or more second main switching elements connected to the PN bus;
A clamp circuit connected between the first inverter and the second inverter in the PN bus, comprising a control terminal and two terminals that are switched between connection and disconnection by the control terminal, and of the two terminals A switching element having one terminal connected to the P bus and the other terminal connected to the N bus; a Zener diode having a cathode connected to the P bus in the PN bus and an anode connected to the control terminal of the switching element A clamp circuit including:
It is characterized by providing.

  According to the inverter device of the present invention, it is possible to achieve suppression of adverse effects due to voltage interference among a plurality of inverters in a space-saving device.

It is a circuit diagram which shows the structure of the inverter apparatus concerning Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 1 of this invention. It is a figure which shows operation | movement of the inverter apparatus concerning Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 3 of this invention. It is a perspective view which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 4 of this invention. It is a perspective view which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 5 of this invention. It is a circuit diagram which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 6 of this invention. It is a circuit diagram which shows the structure of the clamp circuit used with the inverter apparatus concerning Embodiment 7 of this invention. It is a circuit diagram which shows the structure of the inverter apparatus concerning the modification with respect to embodiment of this invention. It is a figure which shows operation | movement of the inverter apparatus concerning the modification with respect to embodiment of this invention.

Embodiment 1 FIG.
[Configuration of Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of an inverter device according to Embodiment 1 of the present invention. In FIG. 1, an inverter 10, an inverter 20 and an inverter 30 are provided as three inverters connected to the PN bus (P bus 2 and N bus 4). A filter capacitor 6 is inserted between the P bus 2 and the N bus 4. The inverter 10, the inverter 20, and the inverter 30 have a three-phase inverter circuit configuration including six switching elements SW therein. The inverter 10, the inverter 20, and the inverter 30 have the same configuration.

  As shown in FIG. 1, the inverter 10 includes switching elements SW1, SW2, SW3, SW4, SW5, and SW6 therein. The inverter 20 includes switching elements SW7, SW8, SW9, SW10, SW11, and SW12 therein. As shown in the circuit diagram of FIG. 1, each of the switching elements SW1 to 12 is an IGBT, and a free wheel diode is connected to each IGBT. The switching elements SW1 to SW12 perform PWM (Pulse Width Modulation) control by controlling the width of the pulse signal to each control terminal (the gate terminal of the IGBT). Hereinafter, the switching elements SW1 to SW12 are also referred to as “main switching elements”.

In the inverter 10, the switching elements SW2, SW4, and SW6 are three low-side switching elements each including a free wheel diode. The same applies to the switching elements SW8, SW10, and SW12 in the inverter 20. On the other hand, each of the switching elements SW1, SW3, and SW5 is a high-side switching element that includes a free wheel diode and is connected to the low-side switching elements (switching elements SW2, SW4, and SW6). The same applies to the switching elements SW7, SW9, and SW11 in the inverter 20.
Specifically, the low-side switching element is a main switching element that includes a control terminal (a gate terminal such as the switching element SW2 in the first embodiment) and two terminals that are controlled to be turned on and off by the control terminal. . The low-side switching element has one of its two terminals (emitter such as switching element SW2 in the first embodiment) connected to the N bus, and the other of the two terminals (such as switching element SW2 in the first embodiment). Collector) is connected to the high-side switching element. The high-side switching element is a main switching element having a control terminal (a gate terminal such as the switching element SW1 in the first embodiment) and two terminals whose on and off are controlled by the control terminal. The high-side switching element has one of its two terminals (collector such as switching element SW1 in the first embodiment) connected to the P bus, and the other of the two terminals (switching element SW1 and the like in the first embodiment). Are connected to the low-side switching element.

The three terminals (U phase, V phase, W phase) of the motor M1 are a terminal between the switching element SW1 and the switching element SW2, a terminal between the switching element SW3 and the switching element SW4, a switching element SW5, and a switching element. Each is connected to a terminal between SW6.
The three terminals (U phase, V phase, W phase) of the motor M2 are a terminal between the switching element SW7 and the switching element SW8, a terminal between the switching element SW9 and the switching element SW10, a switching element SW11 and a switching element. Each is connected to a terminal between SW12. Although not shown, the inverter 30 similarly includes six main switching elements, and terminals between the switching elements are connected to the motor M3.

  A clamp circuit 12 is provided between the inverter 10 and the inverter 20. A clamp circuit 22 is provided between the inverter 20 and the inverter 30. In the clamp circuits 12 and 22, the P terminal is connected to the P bus 2, and the N terminal is connected to the N bus 4. The clamp circuit 22 will be described below assuming that it has the same configuration as the clamp circuit 12.

  FIG. 2 is a circuit diagram showing a configuration of a clamp circuit used in the inverter device according to the first embodiment of the present invention, and more specifically, a circuit diagram of the clamp circuit 12. In the first embodiment, the high voltage switching element 14 is a field effect transistor (MOS-FET). The P terminal is connected to the drain terminal of the high voltage switching element (MOSFET) 14 and the cathode of the high voltage Zener diode 16. The anode of the high voltage Zener diode 16 is connected to the gate of the high voltage switching element (MOSFET) 14. The anode of the high voltage Zener diode 16 is connected to one terminal of the capacitor C1. The other terminal of the capacitor C1 is connected to the N terminal. A resistor R1 is connected in parallel with the capacitor C1. Specifically, one terminal of the resistor R1 is a connection point between one terminal of the capacitor C1 and the anode of the high voltage Zener diode 16, and the connection point and the high voltage switching element (MOSFET) 14 are connected. Connected between the gate. On the other hand, the other terminal of the resistor R1 is connected between the source terminal and the N terminal of the high voltage switching element (MOSFET) 14.

[Operation of Embodiment 1]
According to the circuit configuration shown in FIG. 2, when the voltage between the P bus 2 and the N bus 4 (hereinafter also referred to as “inter-PN voltage”) becomes Vpn in the following equation, the high voltage switching element (MOSFET) 14 is turned on.
Vpn = Zener voltage + Gate-on voltage of high-voltage switching element 14 On the other hand, when the voltage between PNs decreases, the high-voltage switching element (MOSFET) 14 becomes a linear operation region, so that the PN voltage that is apparently held at a specific voltage Is observed.
The lower limit voltage of Vpn described above is a value that takes into account an increase in the PN voltage due to the switching surge phenomenon of the inverter (inverter 10), and is greater than or equal to the value taken by the PN voltage during inverter operation. On the other hand, in order to protect the switching elements, the upper limit voltage of Vpn is set to be equal to or lower than the withstand voltage of the main switching elements (switching elements SW1 to SW12) used for the inverter.

  FIG. 3 is a diagram illustrating the operation of the inverter device according to the first embodiment of the present invention. FIG. 3 is a diagram for explaining a state during operation of the clamp circuit 12 when the voltage rises. When the switching element SW6 transitions from on to off (turns off) (that is, the WL phase of the motor M1 transitions from on to off), the voltage at the point denoted by the symbol A in FIG. 1 is shown in FIG. To change. At this time, the voltage at the point marked with B in FIG. 1 changes as shown in FIG. 3B by the operation of the clamp circuit 12. That is, the clamp circuit 12 suppresses voltage increase. Therefore, even if the switching element SW10 transitions from on to off (turns off) at the moment when the surge voltage rises, the surge voltage rise when the switching element SW10 is off is suppressed as shown in FIG.

(Comparative example for the embodiment)
Hereinafter, the effects of the inverter device according to the first embodiment will be described using a comparative example. FIG. 11 is a circuit diagram showing a configuration of an inverter device according to a modification to the embodiment of the present invention. The inverter device according to this comparative example does not include the clamp circuit 12. In FIG. 11, L1 to L6 indicate wiring inductances. FIG. 12 is a diagram illustrating an operation of the inverter device according to the comparative example illustrated in FIG. 11 and is a diagram for describing an example of mutual interference of surge voltages. When the switching element SW6 transitions from on to off (turns off) (that is, the WL phase of the motor M1 transitions from on to off), the voltage at the point marked with the symbol A in FIG. 11 is shown in FIG. To change. The voltage at the point marked with B in FIG. 11 changes as shown in FIG. 12B, and when the switching element SW10 changes (turns off) from on to off at the moment when the voltage rises in this way (that is, the motor M2). VL phase of the transition from ON to OFF), the voltage rises greatly as shown in FIG.

  As can be seen by comparing FIG. 3C and FIG. 12C, the influence of the surge voltage can be reduced by clamping in the inverter device according to the first embodiment. As a result, while the switching element has conventionally required high breakdown voltage performance in anticipation of safety against surge voltage, the breakdown voltage of the switching element SW can be optimized according to the first embodiment. As a result, the yield from the viewpoint of the pressure resistance performance can be improved and V in the VT curve can be reduced, which contributes to the extension of the life of the apparatus.

According to the inverter device according to the first embodiment, as compared with the case where a capacitor as a surge voltage countermeasure object is inserted between the inverters as in the diode clip circuit described in the above-mentioned JP-A-6-225516. The surge voltage can be dealt with by a space-saving device (clamp circuit 12).
Further, in the inverter device according to the first embodiment, it is not necessary to provide one protection circuit for each of the plurality of switching elements (switching elements SW1 to SW12). Specifically, the clamp circuit 12 is provided between the inverter 10 and the inverter 20 even when six switching elements are provided in one inverter like the inverters 10 and 20 according to the first embodiment. Thus, the influence of the surge voltage can be suppressed. This is different from a technique in which a protection circuit is provided in each switching element, such as a snubber device according to Japanese Patent Laid-Open No. 2000-92817. Therefore, as compared with the case where the switching surge voltage suppression circuit is attached to all the switching elements, the entire apparatus can be greatly reduced in size. Further, the space for installing the inverter device can be saved, and the number of members and the assembly cost can be reduced.

ただし、Ｌは配線インダクタンスであり、Ｉは主電流であり、ｆは繰り返し回数である。クランプ電圧までのエネルギーは主コンデンサが吸収し、通常サージではクランプ動作せずかつサージが重なった場合のみ動作するようにクランプ動作電圧を定めるという設計を行うことにより、繰り返し回数ｆを極端に小さくすることができる。そのため、クランプ回路１２に使用するスイッチング素子として、ＴＯ−３Ｐ規格サイズのものを用いたり、最適設計を実施すればＴＯ−２２０規格サイズのものを用いたりしてもよくなり、小型の素子を用いることによる装置の小型化が期待できる。 Further, in the switching element (high voltage switching element (MOSFET) 14 in the first embodiment) used for the clamp circuit 12, the voltage increase is consumed as heat. For this reason, the main loss is as follows:

Here, L is the wiring inductance, I is the main current, and f is the number of repetitions. The energy up to the clamp voltage is absorbed by the main capacitor, and the clamp operation voltage is set so that the normal capacitor does not perform the clamp operation and operates only when the surges overlap. be able to. For this reason, a switching element used in the clamp circuit 12 may be a TO-3P standard size, or if an optimum design is performed, a TO-220 standard size may be used, and a small element is used. This can be expected to reduce the size of the device.

  Although not shown, another inverter may be connected to the right side of the inverter 30 in FIG. In that case, the clamp circuit according to the first embodiment may be attached between the respective inverters.

Embodiment 2. FIG.
FIG. 4 is a circuit diagram showing a configuration of a clamp circuit used in the inverter device according to the first example of the second embodiment of the present invention. The inverter device according to the first example of the second embodiment of the present invention is obtained by replacing the clamp circuit 12 in the inverter device according to the first embodiment shown in FIG. 1 with the clamp circuit 112 shown in FIG. is there. The clamp circuit 112 shown in FIG. 4 uses an insulated gate bipolar transistor (IGBT) as the high voltage switching element 114, unlike the clamp circuit 12 of the first embodiment that uses the high voltage switching element (MOSFET) 14. ing.
The P terminal is connected to the collector terminal of the high voltage switching element (IGBT) 114 and the cathode of the high voltage Zener diode 116. The anode of the high voltage Zener diode 116 is connected to the gate of the high voltage switching element (IGBT) 114. The anode of the high voltage Zener diode 116 is connected to one terminal of the capacitor C11. The other terminal of the capacitor C11 is connected to the N terminal. A resistor R1 is connected in parallel with the capacitor C1. Specifically, one terminal of the resistor R11 is a connection point between one terminal of the capacitor C11 and the anode of the high voltage Zener diode 116, and the connection point and the high voltage switching element (IGBT) 114 are connected to each other. Connected to the gate terminal. On the other hand, the other terminal of the resistor R1 is connected between the emitter terminal and the N terminal of the high voltage switching element (IGBT) 114.
Since many IGBTs have a relatively high voltage, it is effective to use the clamp circuit 112 shown in FIG. 4 when the MOS-FET has insufficient breakdown voltage.

When a MOS-FET or IGBT is used for a clamp circuit, a resistor of 100 kΩ or less is connected between the gate and source (between the gate and emitter) from the viewpoint of preventing malfunction. That is, the resistor R1 and the resistor R11. This value of 100 kΩ or less is obtained from the leakage current of the high voltage Zener diode, and is specifically derived from the following equation.
R = V _off / I _ZD
However, V _off is the off voltage of the element, and I _ZD is the maximum value of the leakage current of the Zener diode.
The capacitor between the gate and source (between the gate and emitter) is caused by a rapid and long-term voltage change (for example, when the power supply between PN is turned on, the displacement current of the high-voltage Zener diode flows due to the rise of the P voltage). This is to prevent an erroneous ON operation of the MOS-FET or IGBT.

FIG. 5 is a circuit diagram showing a configuration of a clamp circuit used in the inverter device according to the second example of the second embodiment of the present invention. The inverter device according to the second example of the second embodiment of the present invention is obtained by replacing the clamp circuit 12 in the inverter device according to the first embodiment shown in FIG. 1 with the clamp circuit 212 shown in FIG. is there. The clamp circuit 212 shown in FIG. 5 uses a transistor (bipolar transistor) as the high voltage switching element 214, unlike the high voltage switching element (MOSFET) 14 used in the clamp circuit 12 of the first embodiment. .
The P terminal is connected to the collector terminal of the high voltage switching element (bipolar transistor) 214 and the cathode of the high voltage Zener diode 216. The anode of the high voltage Zener diode 216 is connected to the base terminal of the high voltage switching element (bipolar transistor) 214. The anode of the high voltage Zener diode 216 is connected to one terminal of the capacitor C2. The other terminal of the capacitor C2 is connected to the N terminal.
In the case of a bipolar transistor, if the leakage current of the high-voltage Zener diode is very small, a circuit without a resistor as shown in FIG. 5 (a circuit without a resistor corresponding to the resistor R11 in FIG. 4) may be used. . In addition, when a bipolar transistor is used, the cost of the element itself is relatively low, and the clamp circuit 212 can be configured at a low cost.

Embodiment 3 FIG.
FIG. 6 is a circuit diagram showing a configuration of a clamp circuit used in the inverter device according to the third embodiment of the present invention. The inverter device according to the third embodiment of the present invention is obtained by replacing the clamp circuit 12 in the inverter device according to the first embodiment shown in FIG. 1 with a clamp circuit 312 shown in FIG. The clamp circuit 312 shown in FIG. 6 uses a SiC-MOSFET as the high voltage switching element 314, unlike the high voltage switching element (MOSFET) 14 used in the clamp circuit 12 of the first embodiment. In addition, the clamp circuit 312 includes a high voltage Zener diode 316 corresponding to the high voltage Zener diode 16, a capacitor C3 corresponding to the capacitor C1, and a resistor R3 corresponding to the resistor R1. The connection relationship of these elements is the same as that of the clamp circuit 12 of FIG.

  The SiC-MOSFET is a MOSFET using SiC (silicon carbide) as a semiconductor material. SiC-MOSFET has various characteristics such as excellent high temperature characteristics and excellent breakdown voltage characteristics. Since the clamp circuit according to the second embodiment does not use a SiC-MOSFET, it is essential to perform design and arrangement in consideration of heat dissipation. On the other hand, since the SiC-MOSFET is used in the third embodiment, the importance of the heat dissipation can be reduced as compared with the case where the SiC-MOSFET is not used. Further, since the SiC-MOSFET has an excellent breakdown voltage characteristic, it is particularly suitable for use in an inverter device that uses a high voltage. In the third embodiment, focusing on these advantages of the SiC-MOSFET, the clamp circuit 312 is configured using a high-voltage switching element (SiC-MOSFET) 314.

Embodiment 4 FIG.
FIG. 7 is a perspective view illustrating a configuration of a clamp circuit used in the inverter device according to the fourth embodiment of the present invention. The inverter device according to the fourth embodiment of the present invention is obtained by replacing the clamp circuit 12 in the inverter device according to the first embodiment shown in FIG. 1 with the clamp circuit according to the fourth embodiment described below. is there.

  The clamp circuit according to the fourth embodiment is provided as a composite module sealed with a mold resin 412. Inside the mold resin 412, a high-voltage Zener diode, a high-voltage switching element, a capacitor, a resistor, and a wiring connecting them are sealed. In the fourth embodiment, as an example, the clamp circuit 12 (FIG. 2) according to the first embodiment is described as being sealed inside the mold resin 412. However, the present invention is not limited to this, and the clamp circuit to be sealed inside the mold resin 412 includes the circuits of the first to third embodiments (the circuits of FIGS. 2, 4, 5, and 6). One circuit can be selected from the group.

  In the fourth embodiment, electrodes are provided on both surfaces of the mold resin 412. In FIG. 7A, the electrode 413 appears on the front side of the paper surface, but the back side of the paper surface of the mold resin 412 (the bottom surface side of the mold resin 412 in the perspective view of FIG. 7A) is the same as the electrode 413. Are provided with electrodes. One of the electrodes on both sides is connected to the P bus as a P terminal, and the other of the electrodes on both sides is connected to the N bus as an N terminal.

FIG. 7B illustrates a state in which the mold resin 412 is sandwiched between the P bus bar 402 and the N bus bar 404. You may perform integral molding by mold resin with respect to the sandwich structure concerning FIG. 7 (B). As a result, the number of assembly steps can be reduced, and the degree of freedom in arrangement can be greatly improved.
The bus bar is a conductive plane body and has a certain extent in the plane direction. By sandwiching the clamp circuit in the bus bar as in the fourth embodiment, the clamp circuit can be arranged not on the outside of the bus bar but on the bus bar surface. Since the mounting location is the bus bar installation location, a dedicated mounting area is not required and space saving can be realized.
Note that the sandwich structure according to FIG. 7B may be housed in an IPM including a case, instead of being integrally molded with a mold resin.

  In particular, by using a SiC-MOSFET as a high voltage switching element (that is, a structure in which the clamp circuit 312 according to the third embodiment is sealed in the mold resin 412), no consideration is given to heat. Alternatively, the clamp circuit can be designed after lowering the priority for heat dissipation. As a result, there is an effect that the design freedom of the clamp circuit is increased.

Embodiment 5 FIG.
FIG. 8 is a perspective view illustrating a configuration of a clamp circuit used in the inverter device according to the fifth embodiment of the present invention. The inverter device according to the fifth embodiment of the present invention is obtained by replacing the clamp circuit 12 in the inverter device according to the first embodiment shown in FIG. 1 with the clamp circuit according to the fifth embodiment described below. is there.

  The clamp circuit according to the fifth embodiment is provided as a protection chip 512. That is, the protective chip 512 is formed with a high voltage Zener diode, a high voltage switching element, a capacitor, a resistor, and a wiring connecting them. In the fifth embodiment, as an example, a description will be given on the assumption that the clamp circuit 12 (FIG. 2) according to the first embodiment is formed on the protection chip 512. However, the present invention is not limited to this, and the clamp circuit to be formed on the protection chip 512 is a group consisting of the circuits of Embodiments 1 to 3 (the circuits of FIGS. 2, 4, 5, and 6). It can be a single selected circuit.

  In the fifth embodiment, electrodes are provided on both surfaces of the protective chip 512. In FIG. 8A, the electrode 513 appears on the front side of the paper surface, but the back side of the paper surface of the protective chip 512 (the bottom surface side of the protective chip 512 in the perspective view of FIG. 8A) is the same as the electrode 513. Are provided with electrodes. One of the electrodes on both sides is connected to the P bus as a P terminal, and the other of the electrodes on both sides is connected to the N bus as an N terminal. In the fifth embodiment, in particular, as shown in FIG. 8, the electrodes on both surfaces of the protection chip 512 are formed to a size that covers the entire area of the front surface and the back surface of the protection chip 512.

  FIG. 8B illustrates a state where the protection chip 512 is sandwiched between the P bus bar 502 and the N bus bar 504. Each of the P bus bar 502 and the N bus bar 504 has a shape in which a portion of the protective chip 512 that comes into contact with the electrode portion travels in a convex shape. Thereby, the protection chip 512 can be sandwiched locally.

  You may perform integral molding by mold resin with respect to the sandwich structure concerning FIG. 8 (B). As a result, the number of assembly steps can be reduced, and the degree of freedom in arrangement can be greatly improved. Further, as in the fourth embodiment, the mounting location of the clamp circuit is the installation location of the bus bar, so that a dedicated mounting area is not required and space saving can be realized. In addition, the sandwich structure concerning FIG. 8 (B) may be accommodated in the inside of IPM provided with a case.

  In addition, since the gap between the PNs of the bus bar can be made extremely small, the effect of reducing the bus bar inductance and the inductance leading to the clamp circuit formed in the protective chip 512 can be reduced, and the clamp performance is improved. To do. Further, with respect to heat dissipation, many effects that cannot be obtained by the prior art, such as heat dissipation via the bus bar, can be obtained.

Embodiment 6 FIG.
FIG. 9 is a circuit diagram showing a configuration of a clamp circuit used in the inverter device according to the sixth embodiment of the present invention. The inverter device according to the sixth embodiment of the present invention is obtained by replacing the clamp circuit 12 in the inverter device according to the first embodiment shown in FIG. 1 with a clamp circuit 612 shown in FIG. The clamp circuit 612 according to the sixth embodiment has a circuit configuration similar to that of the clamp circuit 12 according to the first embodiment except for the capacitor C61. That is, the clamp circuit 612 includes a high voltage switching element (MOSFET) 614 corresponding to the high voltage switching element (MOSFET) 14, a high voltage Zener diode 316 corresponding to the high voltage Zener diode 16, and a capacitor C3 corresponding to the capacitor C1. And a resistor R3 corresponding to the resistor R1. The connection relationship of these elements is the same as that of the clamp circuit 12 of FIG.

The clamp circuit 612 includes a capacitor C61 connected in parallel to the high voltage Zener diode 616. The capacitance value of the capacitor C61 is determined based on the following formula from the ratio of the gate-on voltage of the high voltage switching element 614 to the PN voltage.
Gate-on voltage: PN voltage≈capacitance of capacitor C61: capacitance of capacitor C62 In response to the occurrence of an instantaneous voltage increase, voltage division is performed in a circuit including capacitors C61 and C62. As a result of the voltage division, the gate voltage of the high voltage switching element 614 increases, but the gate voltage can be maintained at a level that does not turn on the high voltage switching element 614. On the other hand, when the voltage reaches the specified voltage (the Zener voltage) as it is, the high voltage switching element 614 can be turned on immediately. For this reason, the time lag until the gate voltage rises to the on level of the high voltage switching element 614 can be suppressed, and it is possible to appropriately cope with an instantaneous voltage rise.

Embodiment 7 FIG.
FIG. 10 is a circuit diagram showing a configuration of a clamp circuit used in the inverter device according to the seventh embodiment of the present invention. The inverter device according to the seventh embodiment of the present invention is obtained by replacing the clamp circuit 12 in the inverter device according to the first embodiment shown in FIG. 1 with a clamp circuit 712 shown in FIG. The clamp circuit 712 according to the seventh embodiment is the same as the clamp circuit 12 except that the “capacitor C1 in the clamp circuit 12 according to the first embodiment” is replaced with “a series circuit of a capacitor C71 and a capacitor C72”. The circuit configuration is provided. That is, the clamp circuit 712 includes a high voltage switching element (MOSFET) 714 corresponding to the high voltage switching element (MOSFET) 14, a high voltage Zener diode 716 corresponding to the high voltage Zener diode 16, and a resistor R7 corresponding to the resistor R1. And. The connection relationship of these elements is the same as that of the clamp circuit 12 of FIG.

In the clamp circuit 712 according to the seventh embodiment, a capacitor interposed between the high voltage Zener diode 716 and the N terminal is a series circuit of a capacitor C71 and a capacitor C72. A series circuit of two capacitors is used in response to a requirement for high reliability.
A component having a high failure rate in the clamp circuit is a capacitor. When a capacitor fails, a short circuit failure occurs with a fairly high probability. In this case, since the circuit is always turned off, the switching elements (SW1 to SW12) may fail due to the surge voltage without noticing the failure. Therefore, in the seventh embodiment, two capacitors in the clamp circuit are connected in series, and even when one capacitor C71 is short-circuited, the clamp operation can be continued by the other capacitor C72.
When the clamp circuit 712 according to the seventh embodiment is used in a composite inverter device for applications in which reliability is particularly required (for example, automobiles and electric railways), the high reliability required for those applications may be satisfied. it can.

  The inverter device according to the first to seventh embodiments is not only used as a general inverter device, but also is a composite inverter device for transportation, industrial, and consumer use, such as automobiles, electric railways, and the like that require reliability. Can be widely used as.

  Switching elements SW1 to SW12 may be Si power semiconductor elements, SiC power semiconductor elements, or power semiconductor elements using various compound semiconductor materials other than silicon (Si). You may form with a wide band gap semiconductor with a large band gap compared with silicon. Examples of the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride material, and diamond. Switching elements and diode elements formed by such wide band gap semiconductors have high voltage resistance and high allowable current density, so that switching elements and diode elements can be miniaturized. By using elements and diode elements, it is possible to reduce the size of a semiconductor module incorporating these elements. Further, since the heat resistance is also high, the heat sink fins of the heat sink can be miniaturized and the water cooling part can be air cooled, so that the semiconductor module including those configurations can be further miniaturized. Furthermore, since the power loss is low, it is possible to increase the efficiency of the switching element and the diode element, and consequently to increase the efficiency of the semiconductor module. In this case, it is desirable that both the switching elements SW1 to SW12 and the diode element (free wheel diode) are formed of a wide band gap semiconductor, but either one of the elements is formed of a wide band gap semiconductor. It may be.

2 P bus 4 N bus 6 Filter capacitor 10, 20, 30 Inverter 12, 22, 112, 212, 312, 612, 712 Clamp circuit 14, 114, 214, 314, 614, 714 High voltage switching elements 16, 116, 216 316, 616, 716 High voltage Zener diode 402, 502 P bus bar 404, 504 N bus bar 412 Mold resin 413, 513 Electrode 512 Protection chip C1, C2, C3, C11, C61, C62, C71, C72 Capacitors M1, M2, M3 Motors R1, R11, R3, R7 Resistance SW1-12 Switching element

Claims (10)

A first inverter comprising one or more first main switching elements connected to a PN bus;
A second inverter comprising one or more second main switching elements connected to the PN bus;
A clamp circuit connected between the first inverter and the second inverter in the PN bus, comprising a control terminal and two terminals that are switched between connection and disconnection by the control terminal, and of the two terminals A switching element having one terminal connected to the P bus and the other terminal connected to the N bus; a Zener diode having a cathode connected to the P bus in the PN bus and an anode connected to the control terminal of the switching element A clamp circuit including:
An inverter device comprising: The clamp circuit is provided as one clamp device including the Zener diode and the switching element,
A terminal electrode to be connected to the P bus is formed on one of two opposing surfaces of the clamping device, and a terminal electrode to be connected to the N bus is formed on the other one of the two surfaces. There,
A pair of bus bars sandwiching the two surfaces of the molded resin sealing body,
2. The inverter device according to claim 1, wherein one of the pair of bus bars is connected to the P bus, and the other of the pair of bus bars is connected to the N bus.   The clamp device is a mold resin sealing body that seals the Zener diode and the switching element, and is a terminal to be connected to the P bus on one of two opposing surfaces of the mold resin sealing body The inverter device according to claim 2, wherein an electrode is formed and a terminal electrode to be connected to the N bus is formed on the other one of the two surfaces.   The clamp device is a single chip on which the Zener diode and the switching element are formed, and a terminal electrode to be connected to the P bus is formed on one of two opposing surfaces of the chip, and the two surfaces The inverter device according to claim 2, wherein a terminal electrode to be connected to the N bus is formed on the other one.   5. The inverter device according to claim 1, wherein the clamp circuit includes a capacitor connected in parallel with the Zener diode. 6.   The clamp circuit further includes a series connection circuit of two or more capacitors in which a first terminal is connected between the Zener diode and a control terminal of the switching element, and a second terminal is connected to the N bus. The inverter device according to claim 1, comprising the inverter device.   The inverter device according to claim 1, wherein the switching element is an IGBT or a bipolar transistor.   The inverter device according to claim 1, wherein the switching element is a SiC-MOSFET. The first inverter is
A first low-side switching element group consisting of three low-side switching elements each comprising a freewheel diode;
A first high-side switching element group comprising three high-side switching elements each comprising a freewheel diode and each connected to the three low-side switching elements;
Is a three-phase inverter comprising the one or more first main switching elements,
The second inverter is
A second low side switching element group comprising three low side switching elements each comprising a freewheel diode;
A second high-side switching element group comprising three high-side switching elements each having a freewheel diode and connected to the three low-side switching elements;
Is a three-phase inverter provided as the one or more second main switching elements,
The clamp circuit is a timing of transition from on to off in one main switching element of the first low side switching element group, and is on to off in one main switching element of the second low side switching element group. The inverter device according to any one of claims 1 to 8, wherein a switching surge voltage at a connection portion between the first high-side switching element group and the P bus is clamped at a timing of transition to the inverter. . When the voltage between the P bus line and the N bus line reaches Vpn which is a total value of the Zener voltage of the Zener diode and the turn-on voltage of the high voltage switching element, the clamp circuit The switching element is turned on,
The lower limit voltage value of Vpn is a value determined based on a voltage value corresponding to a switching surge phenomenon of the first inverter or the second inverter between the P bus and the N bus,
10. The inverter device according to claim 1, wherein an upper limit voltage value of the Vpn is equal to or lower than a withstand voltage of the first main switching element and the second main switching element. 11. .

Images