JP2013074537A - Comparator, and control circuit for dc/dc converter and electronic apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compact and/or power saving comparator.SOLUTION: A comparator 10 for comparing a first voltage V1 and a second voltage V2 is provided. The first voltage V1 and the second voltage V2 are applied, respectively, to a source and a gate of a first transistor M1 comprising a depression type P channel MOSFET. A source and a gate of a second transistor M2 comprising a depression type P channel MOSFET are connected to a drain of the first transistor M1, and a potential at a drain of the second transistor M2 is fixed. The comparator 10 generates an output signal OUT depending on a potential Vat a node N1 between the first transistor M1 and the second transistor M2.

Description

  The present invention relates to a comparator.

  In order to determine the magnitude relationship between the two voltages, a voltage comparator (hereinafter simply referred to as a comparator) is used. A general comparator is configured using a differential amplifier. However, since the differential amplifier has a large number of elements such as transistors, there is a problem that the circuit area is large and an input voltage offset occurs due to variations in the elements. In order to reduce the offset voltage, it is necessary to increase the bias current, which causes a problem of increased power consumption.

  The present invention has been made in view of such a problem, and one of exemplary objects of an embodiment thereof is to reduce the size and / or power consumption of a comparator.

  One embodiment of the present invention relates to a comparator that compares a first voltage and a second voltage. This comparator has a first transistor of a depletion type P-channel MOSFET in which a first voltage is applied to its source and a second voltage is applied to its gate, and its source and gate are connected to the drain of the first transistor. And a second transistor of a depletion type P-channel MOSFET whose drain potential is fixed. The comparator generates an output signal corresponding to the potential at the connection point of the first transistor and the second transistor.

The gate-source voltage of the depletion type second transistor is 0 V, and a predetermined bias current flows. On the other hand, the gate-source voltage of the first transistor is a potential difference between the first voltage and the second voltage. The drain-source voltage of the first transistor changes so that the current flowing through the first transistor approaches the bias current.
In an equilibrium state in which the potential difference between the first voltage and the second voltage is zero, the gate-source voltages of the first transistor and the second transistor are equal, so the drain-source voltages of the first transistor and the second transistor are equal. Further, when the gate-source voltage of the first transistor is negative, the drain-source voltage of the first transistor becomes larger, and the potential at the connection point between the first transistor and the second transistor becomes low level. On the other hand, when the gate-source voltage of the first transistor is positive, the drain-source voltage of the first transistor is smaller, and the potential at the connection point between the first transistor and the second transistor is at a high level. Therefore, according to this configuration, voltage comparison can be performed using two depletion type transistors, and the circuit area can be reduced and / or power consumption can be reduced as compared with a comparator using a differential amplifier. it can.

  The comparator according to an aspect may further include a buffer or an inverter that receives a potential at a connection point between the first transistor and the second transistor and outputs an output signal.

  Another aspect of the present invention relates to a comparator that compares a third voltage with a fourth voltage. This comparator has a third transistor of a depletion type N-channel MOSFET in which a third voltage is applied to its gate and a fourth voltage is applied to its source, and its source and gate are connected to the drain of the third transistor. And a fourth transistor of a depletion type N-channel MOSFET whose drain potential is fixed. The comparator generates an output signal corresponding to the potential at the connection point between the third transistor and the fourth transistor.

The gate-source voltage of the depletion type fourth transistor is 0 V, and a predetermined bias current flows. On the other hand, the gate-source voltage of the third transistor is a potential difference between the third voltage and the fourth voltage. The drain-source voltage of the fourth transistor changes so that the current flowing through the fourth transistor approaches the bias current.
In an equilibrium state where the potential difference between the third voltage and the fourth voltage is zero, the gate-source voltages of the third transistor and the fourth transistor are equal, so the drain-source voltages of the third transistor and the fourth transistor are equal. Further, when the gate-source voltage of the third transistor is negative, the drain-source voltage of the third transistor becomes larger, and the potential at the connection point between the third transistor and the fourth transistor becomes high level. Conversely, when the gate-source voltage of the third transistor is positive, the drain-source voltage of the third transistor is smaller, and the potential at the connection point of the third transistor and the fourth transistor is at a low level. Therefore, according to this configuration, voltage comparison can be performed using two depletion type transistors, and the circuit area can be reduced and / or power consumption can be reduced as compared with a comparator using a differential amplifier. it can.

  The comparator according to an aspect may further include a buffer or an inverter that receives a potential at a connection point between the third transistor and the fourth transistor and outputs an output signal.

Another aspect of the present invention relates to a control circuit for a synchronous rectification step-up DC / DC converter having a switching transistor and a synchronous rectification transistor. The control circuit compares the potential at one end of the synchronous rectification transistor with the potential at the other end of the synchronous rectification transistor, and generates a comparison signal that is asserted when the two potentials are equal to each other. A pulse signal whose duty ratio is adjusted so that the output voltage of the converter approaches a predetermined target value, the pulse modulator generating a pulse signal that transitions to an on level when the comparison signal is asserted, and the pulse signal A driver that turns on the switching transistor when it is on, and turns on the synchronous rectification transistor when it is off.
According to this aspect, it is possible to detect the timing when the current flowing through the synchronous rectification transistor becomes zero and to turn on the switching transistor.

  Another aspect of the present invention relates to a control circuit for a synchronous rectification step-down DC / DC converter having a switching transistor and a synchronous rectification transistor. The control circuit compares the potential at one end of the synchronous rectification transistor with the potential at the other end of the synchronous rectification transistor, and generates a comparison signal that is asserted when the two potentials are equal to each other. A pulse modulator that generates a pulse signal that has a duty ratio adjusted so that the output voltage of the DC / DC converter approaches a predetermined target value, and transitions to an on level when the comparison signal is asserted; A driver that turns on the switching transistor when the signal is on level and turns on the synchronous rectification transistor when the signal is off level.

  According to this aspect, it is possible to detect the timing when the current flowing through the synchronous rectification transistor becomes zero and to turn on the switching transistor.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, the comparator can be downsized and / or reduced in power consumption.

It is a circuit diagram which shows the structure of the comparator which concerns on 1st Embodiment. 2A to 2E are diagrams illustrating the operation of the comparator in FIG. It is a circuit diagram which shows the structure of the comparator which concerns on 2nd Embodiment. 4A and 4B are circuit diagrams showing the configuration of a DC / DC converter using the comparator of FIGS.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a comparator 10 according to the first embodiment. The comparator 10 includes a first terminal P1, a second terminal P2, a first transistor M1, a second transistor M2, and an inverter 12. The comparator 10 has a first voltage V1 input to the first terminal P1 and an input to the second terminal P2. The second voltage V2 is compared, and an output signal OUT indicating the comparison result is output.

  The first transistor M1 is a depletion type P-channel MOSFET. The source of the first transistor M1 is connected to the first terminal P1, and the gate thereof is connected to the second terminal P2. The second transistor M2 is also a depletion type P-channel MOSFET of the same type as the first transistor M1. The source and gate of the second transistor M2 are connected to the drain of the first transistor M1. The drain of the second transistor M2 is connected to ground or the like, and its potential is fixed. The first transistor M1 and the second transistor M2 are preferably formed by pairing at adjacent locations on the semiconductor substrate.

The comparator 10 generates an output signal OUT corresponding to the potential V _N1 of the connection point N1 between the first transistor M1 and the second transistor M2. The inverter 12 receives the potential V _N1 at the connection point N1, inverts it, and outputs an output signal OUT. Instead of the inverter 12, a buffer that outputs the potential _VN1 non-inverted may be provided.

The above is the configuration of the comparator 10. Next, the operation will be described.
2A to 2E are diagrams illustrating the operation of the comparator 10 in FIG.
The gate-source voltage _{VGS_M2} of the depletion-type second transistor M2 is 0 V, and a predetermined bias current Ibias flows through the second transistor M2. On the other hand, the gate-source voltage _{VGS_M1} of the first transistor M1 is a potential difference V1-V2 between the first voltage V1 and the second voltage V2. Here, for convenience, the gate-source voltage _{VGS_M1} is positive when V2> V1, and the gate-source voltage _{VGS_M1} is negative when V2 <V1.

Since the first transistor M1 is provided on the same path as the second transistor M2, the comparator 10 operates so that the drain current I _M1 flowing through the first transistor M1 is equal to the bias current Ibias.
FIG. 2A shows the relationship between the drain-source voltage V _{DS_M1 of} the first transistor M1 and the drain current IM1. FIG. 2B shows the relationship between the gate-source voltage V _GS of the first transistor M1 and the current I _M1 flowing through the first transistor M1. 2 (c) shows the voltage _{V GS} between the gate and the source of the first transistor M1, the relationship of the drain-source voltage _{V DS_M1.} FIG. 2D shows the relationship between the gate-source voltage V _{GS of} the first transistor M1 and the potential V _{N1 at} the connection point N1. FIG. _2E shows the relationship between the gate-source voltage V _{GS of} the first transistor M1 and the output signal OUT.

As shown in FIG. 2A, when the gate-source voltage V _GS of the first transistor M1 changes, the drain-source voltage V _{DS_M1} of the first transistor M1 changes according to the relationship of FIG. The current flowing through M1 changes so as to approach the bias current Ibias. Specifically, in accordance with the gate-source voltage _{V GS} increases, the drain-source voltage _{V DS_M1} decreases.

  The state of the comparator 10 will be described in three parts: (1) V1 = V2, (2) V2> V1, and (3) V2 <V1.

(1) V1 = the first voltage V1 when V2 in equilibrium potential difference is zero in the second voltage V2, the gate-source voltage _{V GS} of the first transistor M1 becomes zero, and the bias state of the second transistor M2 Will be equal. At this time, the drain-source voltage V _{DS_M1 of} the first transistor M1 is equal to the drain-source voltage V _{DS_M2} of the second transistor M2.

(2) when this time of V2> V1, the gate-source voltage _{V GS} of the first transistor M1 is negative, toward the drain-source voltage _{V DS_M1} of the first transistor M1 is, the drain-source voltage of the second transistor M2 It becomes larger than _{VDS_M2} . Therefore, the potential V _{N1 at} the connection point N1 between the first transistor M1 and the second transistor M2 is at a low level (Vss).

(3) When V2 <V1 At this time, the gate-source voltage V _GS of the first transistor M1 is positive, and the drain-source voltage V _{DS_M1} of the first transistor M1 is higher than the drain-source voltage V of the second transistor M2. _{It becomes} smaller than _{DS_M2,} and the potential V _N1 of the connection point N1 between the first transistor M1 and the second transistor M2 becomes high level (V1).

The output signal OUT generated by the inverter 12 is a signal obtained by inverting the potential V _N1 at the connection point N1. That is, the output signal OUT is at a high level when V2> V1, and is at a low level when V2 <V1. When the inverter 12 is replaced with a buffer, the logic level of the output signal OUT is reversed.

The above is the operation of the comparator 10.
According to the comparator 10 of FIG. 1, voltage comparison can be performed using two depletion type transistors. According to the comparator 10, the circuit area can be reduced and the power consumption can be reduced as compared with a comparator using a differential amplifier.

  Further, since the comparator 10 includes the first transistor M1 and the second transistor M2 of the same type, the comparator 10 is hardly affected by variations, and therefore, the input offset voltage of the comparator 10 can be brought close to zero.

(Second Embodiment)
FIG. 3 is a circuit diagram showing a configuration of the comparator 20 according to the second embodiment. The comparator 20 includes a third terminal P3, a fourth terminal P4, a third transistor M3, a fourth transistor M4, and an inverter 22, and a third voltage V3 input to the third terminal P3 and an input to the fourth terminal P4. The fourth voltage V4 is compared, and an output signal OUT indicating the comparison result is output.

The third transistor M3 and the fourth transistor M4 are depletion type N-channel MOSFETs. The gate of the third transistor M3 is connected to the third terminal P3, and the source thereof is connected to the fourth terminal P4. The source and gate of the fourth transistor M4 are connected to the drain of the third transistor M3. The drain of the fourth transistor M4 is connected to, for example, the power supply line V _DD and its potential is fixed.

The comparator 20 generates an output signal OUT corresponding to the potential V _N2 of the connection point N2 between the third transistor M3 and the fourth transistor M4. The inverter 22 receives the potential V _N2 at the connection point N2, inverts it, and outputs an output signal OUT. Instead of the inverter 22, a buffer that outputs the potential _VN2 in a non-inverted manner may be provided.

The above is the configuration of the comparator 20.
The comparator 20 operates in the same manner as the comparator 10 in FIG. The state of the comparator 20 will be described in three parts: (1) V3 = V4, (2) V3 <V4, and (3) V3> V4.

(1) When V3 = V4 In the equilibrium state in which the potential difference between the third voltage V3 and the fourth voltage V4 is zero, the gate-source voltage V _GS of the third transistor M3 and the fourth transistor M4 becomes equal. The drain-source voltages V _{DS_M3} and V _{DS_M4} of M3 and the fourth transistor M4 are equal.

(2) When V3 <V4 When the gate-source voltage V _GS of the third transistor M3 is negative, the drain-source voltage V _{DS_M3} of the third transistor M3 is larger than that V _{DS_M4} of the fourth transistor M4, The potential V _{N2 at the} connection point N2 is at a high level (V _DD ).

(4) When V3> V4 When the gate-source voltage V _GS of the third transistor M3 is positive, the drain-source voltage VDS_M3 of the third transistor M3 is smaller than that of the fourth transistor M4, V _{DS_M4.} The potential V _{N2 at the} point N2 is at a low level.

  The above is the operation of the comparator 20.

  According to the comparator 20 of FIG. 3, voltage comparison can be performed using two depletion type transistors, and the circuit area can be reduced and / or power consumption can be reduced as compared with a comparator using a differential amplifier. Can be reduced.

  In addition, since the third transistor M3 and the fourth transistor M4 of the same type are used, the input offset voltage of the comparator 20 can be made close to zero because it is hardly affected by variations.

  Next, an example of a comparator application according to the first and second embodiments will be described.

4A and 4B are circuit diagrams showing the configuration of a DC / DC converter using the comparator of FIGS. The DC / DC converter is mounted on an electronic device such as a mobile phone terminal, a PDA (Personal Digital Assistant), an audio player, a notebook PC, etc., and boosts or steps down the input voltage _VIN from the battery, a microcomputer, an LCD panel, Supplied to loads such as LEDs (light emitting diodes).

  The DC / DC converter 30 in FIG. 4A is a synchronous rectification type boost converter. The DC / DC converter 30 includes a switching transistor M11, a synchronous rectification transistor M12, an inductor L1, an output capacitor C1, and a control circuit 40.

Since the topology of the part other than the control circuit 40 of the DC / DC converter 30 is general, a description thereof will be omitted. The control circuit 40 complementarily switches the switching transistor M11 and the synchronous rectification transistor M12, thereby boosting the input voltage _VIN and stabilizing the output voltage _VOUT to a target value.

  The control circuit 40 includes the comparator 10 according to the first embodiment, a pulse modulator 42, and a driver 44.

  The comparator 10 compares the potential V1 at one end of the synchronous rectification transistor M12 with the potential V2 at the other end of the synchronous rectification transistor M12, and generates a comparison signal S1 that is asserted when the two potentials are equal. When the comparator 10 has the inverter 12, the assertion is at a low level.

Synchronous rectification transistor M12 period on, the synchronous rectification transistor M12, flows current _{I L} of the inductor L1. If the on-resistance of the synchronous rectification transistor M12 and _{R ON,} the voltage drop across the synchronous rectification transistor M12 (V1-V2) is
V1-V2 = R _ON × _IL
Given in.

Immediately after the synchronous rectification transistor M12 is turned on, V1> V2 holds is, in accordance with the energy of inductor L1 is decreased, the coil current _{I L} is also reduced, the potential difference V1-V2 approaches zero. Comparison signal S1 output from the comparator 10 is asserted when the coil current I _L becomes zero.

The pulse modulator 42 generates a pulse signal S2 whose duty ratio is adjusted so that the output voltage _VOUT of the DC / DC converter 30 approaches a predetermined target value. When the comparison signal S1 is asserted, the pulse modulator 42 shifts the pulse signal S2 to the on level. The on level is a level corresponding to the on state of the switching transistor M11. The configuration of the pulse modulator 42 is not particularly limited, and a known circuit may be used.

  The driver 44 turns on the switching transistor M11 when the pulse signal S2 is on level, and turns on the synchronous rectification transistor M12 when it is off level.

The above is the configuration of the DC / DC converter 30.
According to the DC / DC converter 30, the comparator 10 can detect that the coil current _IL has become zero, and the switching transistor M12 can be turned off accordingly.

  The DC / DC converter 50 shown in FIG. 4B is a synchronous rectification step-down converter. The DC / DC converter 50 includes a switching transistor M21, a synchronous rectification transistor M22, an inductor L1, an output capacitor C1, and a control circuit 60.

Since the topology of the DC / DC converter 50 excluding the control circuit 60 is general, the description thereof is omitted. The control circuit 60 switches the switching transistor M21 and the synchronous rectification transistor M22 in a complementary manner, thereby stepping down the input voltage _VIN and stabilizing the output voltage _VOUT to a target value.

  The control circuit 60 includes a comparator 20 according to the second embodiment, a pulse modulator 62, and a driver 64.

  The comparator 20 compares the potential V3 at one end of the synchronous rectification transistor M22 with the potential V4 at the other end of the synchronous rectification transistor M22, and generates a comparison signal S3 that is asserted when the two potentials are equal.

Synchronous rectification transistor M22 period on, the synchronous rectification transistor M22, flows current _{I L} of the inductor L1. If the on-resistance of the synchronous rectification transistor M22 and _{R ON,} the voltage drop across the synchronous rectification transistor M22 (V4-V3) is
V4-V3 = R _ON × _IL
Given in.

Immediately after the synchronous rectification transistor M22 is turned on, V4> V3 is holds, in accordance with the energy of inductor L1 is decreased, the coil current _{I L} is also reduced, the potential difference V4-V3 approaches zero. The comparison signal S3 outputted from the comparator 20 is asserted when the coil current I _L becomes zero.

The pulse modulator 62 generates a pulse signal S4 whose duty ratio is adjusted so that the output voltage _VOUT of the DC / DC converter 50 approaches a predetermined target value. When the comparison signal S3 is asserted, the pulse modulator 62 shifts the pulse signal S4 to the on level. The on level is a level corresponding to the on state of the switching transistor M21. The configuration of the pulse modulator 62 is not particularly limited, and a known circuit may be used.

  The driver 64 turns on the switching transistor M21 when the pulse signal S4 is on level, and turns on the synchronous rectification transistor M22 when it is off level.

The above is the configuration of the DC / DC converter 50.
According to the DC / DC converter 50, the comparator 20 can detect that the coil current _IL has become zero, and the switching transistor M22 can be turned off accordingly.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

  In the embodiment, the inverter 12 (22) is provided in the comparator 10 (20), but the present invention is not limited thereto. When the input impedance of the circuit connected to the output terminal of the comparator 10 is sufficiently high, or when the current capability of the first transistor M1 (M3) and the second transistor M2 (M4) is sufficiently high, the inverter 12 (22 ) May be omitted.

  The application of the comparator 10 (20) is not limited to the DC / DC converter of FIGS. 4 (a) and 4 (b). The comparator 10 (20) can be widely used for detecting that the current in a certain path becomes zero. In this case, an impedance element, for example, a resistor or a transistor may be arranged on the path to be monitored, and the voltage across the impedance element may be compared by the comparator 10 (20).

  In addition, the comparator 10 (20) can be used in various applications for comparing the magnitudes of two voltages.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

M1 ... first transistor, P1 ... first terminal, C1 ... output capacitor, L1 ... inductor, M2 ... second transistor, P2 ... second terminal, M3 ... third transistor, P3 ... third terminal, M4 ... fourth transistor , P4 ... 4th terminal, 10 ... comparator, M11 ... switching transistor, 12 ... inverter, M12 ... synchronous rectification transistor, 20 ... comparator, 22 ... inverter, 30 ... DC / DC converter, 40 ... control circuit, 42 ... pulse modulation 44 ... driver 50 ... DC / DC converter 60 ... control circuit 62 ... pulse modulator 64 ... driver

Claims (7)

A comparator for comparing the first voltage and the second voltage,
A first transistor of a depletion type P-channel MOSFET in which the first voltage is applied to the source and the second voltage is applied to the gate;
A second transistor of a depletion type P-channel MOSFET whose source and gate are connected to the drain of the first transistor, and whose drain potential is fixed;
And a comparator for generating an output signal corresponding to a potential at a connection point between the first transistor and the second transistor.   The comparator according to claim 1, further comprising a buffer or an inverter that receives a potential at a connection point between the first transistor and the second transistor and outputs the output signal. A comparator for comparing the third voltage and the fourth voltage,
A third transistor of a depletion type N-channel MOSFET in which the third voltage is applied to the gate and the fourth voltage is applied to the source;
A fourth transistor of a depletion type N-channel MOSFET whose source and gate are connected to the drain of the third transistor, and whose drain potential is fixed;
And a comparator for generating an output signal corresponding to a potential at a connection point between the third transistor and the fourth transistor.   The comparator according to claim 3, further comprising a buffer or an inverter that receives a potential at a connection point between the third transistor and the fourth transistor and outputs the output signal. A control circuit for a synchronous rectification type step-up DC / DC converter having a switching transistor and a synchronous rectification transistor,
The comparator according to claim 1 or 2, wherein a potential of one end of the synchronous rectification transistor is compared with a potential of the other end of the synchronous rectification transistor, and a comparison signal that is asserted when the two potentials are equal to each other is generated.
A pulse modulator that generates a pulse signal whose duty ratio is adjusted so that the output voltage of the DC / DC converter approaches a predetermined target value, and transitions to an on level when the comparison signal is asserted When,
A driver that turns on the switching transistor when the pulse signal is on, and turns on the synchronous rectification transistor when the pulse signal is off;
A control circuit comprising: A control circuit for a synchronous rectification step-down DC / DC converter having a switching transistor and a synchronous rectification transistor,
The comparator according to claim 3 or 4, wherein a potential of one end of the synchronous rectification transistor is compared with a potential of the other end of the synchronous rectification transistor, and a comparison signal that is asserted when the two potentials are equal to each other is generated.
A pulse modulator that generates a pulse signal whose duty ratio is adjusted so that the output voltage of the DC / DC converter approaches a predetermined target value, and transitions to an on level when the comparison signal is asserted When,
A driver that turns on the switching transistor when the pulse signal is on, and turns on the synchronous rectification transistor when the pulse signal is off;
A control circuit comprising:   An electronic apparatus comprising a DC / DC converter having the control circuit according to claim 5.

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