JP2013074460A - Variable gain amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier that maintains an offset cancellation capability and has a variable voltage gain.SOLUTION: The variable gain amplifier includes: a differential amplification circuit 11 for differentially amplifying input signals; an offset cancellation circuit 12 for feeding back only predetermined low range components of an output signal of the differential amplification circuit 11 to the differential amplification circuit 11 to remove a DC component of the output signal; and a common mode feedback circuit 103 for adjusting a gate voltage of third and fourth transistors 3, 4 of the differential amplification circuit 11 such that a common output level at output terminals 21, 22 is a predetermined voltage set by a reference voltage Vref. The offset cancellation circuit 12 is configured to change only a zero point frequency without changing a cutoff frequency for the predetermined low range components.

Description

  The present invention relates to a variable gain amplifier, and more particularly, to an improvement in a DC offset cancel function in a variable gain amplifier having a DC offset cancel function used in a signal receiving apparatus or the like in wireless communication.

In wireless communication, in a circuit using a direct conversion method or a low-IF method, which is one of the reception methods, a signal offset is generated in the signal after the frequency is lowered. Therefore, it is necessary to remove this DC offset, and various countermeasures have been proposed and put into practical use (for example, see Non-Patent Document 1).
For example, FIG. 4 shows an example of the configuration of such a conventional variable gain amplifier. Hereinafter, the conventional circuit will be described with reference to FIG.
This variable gain amplifier is roughly divided into a differential amplifier circuit 101A, an offset cancel circuit 102A, and a common mode feedback (CMFB) circuit 103A.

The differential amplifier circuit 101A includes transistors M1 and M2 constituting a differential input unit, transistors M3 and M4 operating as load resistors, transistors M5 and M6 operating as constant current sources, and variable resistance elements for variable gain. VR1 is the main component.
In such a configuration, the drain of the transistor M1 is connected to the output terminal OUT +, and the drain of the transistor M2 is connected to the output terminal OUT−, so that a differential amplified signal is output.
The voltage gain Av with respect to the input signals IN + and IN− is as follows. The transconductance of the transistors M1 and M2 is gm, the resistance between the source and drain of the transistors M3 and M4 is ro, and the resistance value of the variable resistance element VR1 is VR. It is represented by the following formula 1.

  Av = gm × ro / (1 + gm × VR) Equation 1

  That is, it can be said that the voltage gain Av of the differential amplifier circuit can be varied by changing the resistance value VR of the variable resistance element VR1.

The offset cancel circuit 102A is configured mainly by transistors M9 and M10 that constitute a differential input section, transistors M7 and M8 that operate as resistors, and fixed capacitance elements C1 and C2.
The transistors M7 and M8 acting as resistors are connected in series with the fixed capacitance elements C1 and C2 so as to operate as a low-pass filter. For example, the transistors M7 and M8 exhibit characteristics as shown in FIG. It has become.
Of the output signals generated at the output terminals OUT + and OUT−, the low-pass filtered DC (direct current) component is the connection point A2 between the transistor M9 and the fixed capacitance element C1 and the transistor M7, the transistor M10 and the fixed capacitance. It occurs at the connection point B2 between the element C2 and the transistor M8, and is input to the differential input section composed of the transistors M9 and M10.

  When such an input occurs, the drains of the transistors M9 and M10 draw a current corresponding to the voltage at the connection points A2 and B2 from the sources of the transistors M1 and M2 in the differential input section of the differential amplifier circuit 101A, resulting in an offset. The cancel circuit 102A has the characteristics of a high-pass filter, and the DC component is cut.

  Here, the transfer function of the low-pass filter composed of the transistors M7 and M8 and the capacitive elements C1 and C2 is expressed as Equation 2 below.

  T (s) = 1 / (1 + s · Rt · C) Equation 2

In Equation 2, Rt is the resistance value of the transistors M7 and M8, and C is the capacitance value of the capacitive elements C1 and C2.
In the frequency band near DC below the cut-off frequency, the offset cancel circuit 102A functions. When the DC gain of the offset cancel circuit 102A is Avoc, the offset cancel capability, that is, the voltage gain Avdc near DC is expressed by the following equation. It becomes like 3.

  Avdc = Av / (1 + Avoc · Av) Equation 3

Here, Av is the voltage gain of the differential amplifier circuit 101A.
From Equation 3, it can be understood that Avdc also changes with changes in Av. The DC gain Avoc of the offset cancel circuit 102A is uniquely determined by the transconductance values of the transistors M9 and M10 and the current value of the constant current source 20A. In the frequency band sufficiently higher than the cut-off frequency, the voltage gain Av of the differential amplifier circuit 101A becomes dominant because it is not affected by the previous low-pass filter.

The common mode feedback circuit 103A has a configuration well known and disclosed in Non-Patent Document 2, for example.
The common mode feedback circuit 103A adjusts the gate voltages of the transistors M3 and M4 of the differential amplifier circuit 101A so that the common output level at the output terminals OUT + and OUT− becomes a predetermined voltage set by the reference voltage Vref. It is configured as follows.

FIG. 6 shows a simulation result regarding the frequency characteristics of the voltage gain when the resistance value VR of the variable resistance element VR1 is changed in the conventional circuit shown in FIG.
In the figure, the horizontal axis indicates the frequency of the input signal in logarithmic display, and the vertical axis indicates the reactive power level at the output OUT +.
According to the figure, it can be understood that the frequency characteristic of the voltage gain is that of a high-pass filter, and that the reactive power decreases as VR decreases, that is, the voltage gain increases.

Y. Zheng et al., “A Low Power Noncoherent CMOS UWB Transceiver ICs”, IEEE RFIC Symposium, 2005, p. 347-350 Akira Matsuzawa, “CMOS Operational Amplifier”, IEICE Transactions Vol. J84-C No.5, 2001, p. 357-373

  However, in the above conventional circuit, the voltage gain Avdc in the vicinity of DC also changes, and the voltage gain increases as the resistance value VR of the variable resistance element VR1 decreases. At the same time, the voltage gain Avdc in the vicinity of DC also increases, and the offset There is a problem that the canceling ability decreases.

  The present invention has been made in view of the above circumstances, and provides a variable gain amplifier that can maintain an offset canceling capability and can vary a voltage gain.

In order to achieve the above object of the present invention, a variable gain amplifier according to the present invention comprises:
A differential amplifier circuit that differentially amplifies an input signal, and an offset cancel that feeds back only a predetermined low-frequency component of the output signal of the differential amplifier circuit to the differential amplifier circuit and removes a DC component of the output signal A circuit,
The offset cancel circuit is configured to be able to vary only the zero point frequency without changing the cutoff frequency for the predetermined low frequency component.

  According to the present invention, the cutoff frequency of the offset cancellation circuit remains fixed, and only the zero point frequency is varied, so that the voltage due to the frequency change of the zero point of the offset cancellation circuit is constant while the gain of the differential amplifier circuit is constant. Since the gain is limited, it is possible to provide a variable gain amplifier that can change the voltage gain in a frequency band sufficiently higher than the cutoff frequency while the voltage gain near DC remains constant. is there.

It is a circuit diagram which shows the circuit structural example of the variable gain amplifier in embodiment of this invention. It is a characteristic diagram which shows the frequency characteristic of the low pass filter in the variable gain amplifier of embodiment of this invention. It is a characteristic diagram which shows the simulation result of the voltage gain characteristic in the variable gain amplifier of embodiment of this invention. It is a circuit diagram which shows the circuit structural example of the conventional variable gain amplifier. It is a characteristic diagram which shows the frequency characteristic of the low pass filter in the conventional variable gain amplifier. It is a characteristic diagram which shows the simulation result of the voltage gain characteristic in the conventional variable gain amplifier.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, the circuit configuration of the variable gain amplifier according to the embodiment of the present invention will be described with reference to FIG.
This variable gain amplifier circuit is roughly divided into a differential amplifier circuit 11, an offset cancel circuit 12, and a common mode feedback circuit (indicated as “CMFB” in FIG. 1) 103. .

  The differential amplifier circuit 11 includes first to sixth transistors (indicated as “M1”, “M2”, “M3”, “M4”, “M5”, and “M6” in FIG. 1) 1 to 6, respectively. Is the main component. In the embodiment of the present invention, the first and second transistors 1 and 2 and the fifth and sixth transistors 5 and 6 are n-channel MOS transistors. The third and fourth transistors The transistors 3 and 4 are p-channel MOS transistors.

The first and second transistors 1 and 2 constitute a differential input section. The input signal IN + is input to the gate of the first transistor 1 and the input signal IN is input to the gate of the second transistor 2. A signal IN− is applied to each.
The drain of the first transistor 1 is connected to the drain of the third transistor 3, and the output terminal 22 is connected to the connection point, while the drain of the second transistor 2 is connected to the drain of the first transistor 1. The drains of the four transistors 4 are connected, and an output terminal 21 is connected to the connection point.

Further, the source of the first transistor 1 is connected to the drain of the fifth transistor 5 and the drain of the ninth transistor 9 of the offset cancel circuit 12 described later, while the source of the second transistor 2 is 6 and the drain of the tenth transistor 9 of the offset cancel circuit 12 to be described later.
A fixed resistor (indicated as “R1” in FIG. 1) is provided between the connection point of the first transistor 1 and the fifth transistor 5 and the connection point of the second transistor 2 and the sixth transistor 6. ) 15 is connected.

The gates of the third and fourth transistors 3 and 4 are connected to each other and to the output stage of a common mode feedback circuit 103 described later.
Further, the power supply voltage VDD is applied to the sources of the third and fourth transistors 3 and 4.
The third and fourth transistors 3 and 4 operate as load resistors with respect to the first and second transistors 1 and 2 constituting the differential input unit.

On the other hand, the gates of the fifth and sixth transistors 5 and 6 are connected to each other so that the bias voltage VB1 is applied.
The sources of the fifth and sixth transistors 5 and 6 are both connected to the ground.
In the differential amplifier circuit 11 having such a configuration, the voltage gain Av with respect to the input signals IN + and IN− is such that the transconductance of the first and second transistors 1 and 2 is gm, and the sources of the third and fourth transistors 3 and 4 are. When the resistance between the drains is ro and the resistance value of the fixed resistor 15 is R, it can be expressed by the following equation 4.

  Av = gm · ro / (1 + gm · R) Equation 4

From Equation 4, it can be understood that the voltage gain of the differential amplifier circuit 11 is fixed.
Note that the fixed resistor 15 is not necessarily required and may be omitted.

Next, the offset cancel circuit 12 includes ninth and tenth transistors (represented as “M9” and “M10” in FIG. 1) 9 and 10 constituting a differential input section, and a first that functions as a resistance element. 7 and 8 transistors (represented in FIG. 1 as “M7” and “M8”, respectively) 7 and 8 and two variable capacitance elements (represented in FIG. 1 as “VC1” and “VC2”, respectively) 18 and 19 are the main components.
In the embodiment of the present invention, the seventh to tenth transistors 7 to 10 are n-channel MOS transistors.

First, the sources of the ninth and tenth transistors 9 and 10 are connected to each other, and a constant current source 20 is connected between the connection point and the ground.
In addition, a first fixed capacitance element (indicated as “C1” in FIG. 1) 16 is interposed between the gate of the tenth transistor 10 and the ground. Are connected to second fixed capacitance elements 17 (indicated as “C2” in FIG. 1), respectively.

Further, a seventh transistor 7 is connected in series between the gate of the ninth transistor 9 and the output terminal 22. That is, the drain of the seventh transistor 7 is connected to the output terminal 22, and the source is connected to the gate of the ninth transistor 9.
Similarly, an eighth transistor 8 is connected in series between the gate of the tenth transistor 10 and the output terminal 21. That is, the drain of the eighth transistor 8 is connected to the output terminal 21, and the source is connected to the gate of the tenth transistor 10.

The gates of the seventh and eighth transistors 7 and 8 are connected to each other so that the bias voltage VB2 is applied.
Further, between the drain of the seventh transistor 7 and the gate of the ninth transistor 9, a first variable capacitance element 18 (denoted as “VC1” in FIG. 1) is connected to the drain of the eighth transistor 8. Between the gates of the tenth transistors 10, second variable capacitance elements (indicated as “VC2” in FIG. 1) 19 are respectively connected.

In this configuration, the seventh and eighth transistors 7 and 8 act as resistance elements, and the seventh transistor 7 and the first fixed capacitance element 16 are connected in series to operate as a low-pass filter, while the eighth transistor The transistor 8 and the second fixed capacitance element 17 are connected in series to operate as a low-pass filter.
The resistance values of the seventh and eighth transistors 7 and 8 as resistance elements are 1 / {μn · Cox · (W / L) · (Vgs · Vth)}.
Here, μn is the electron mobility, Cox is the gate capacitance per unit area, W is the gate width, L is the gate length, Vgs is the gate-source voltage, and Vth is the threshold voltage.

In the offset cancel circuit 12, a low-pass filtered DC component among the signal components of the output signals OUT + and OUT− obtained at the output terminals 21 and 22 is generated at the connection points A1 and B1 (see FIG. 1). 9 and the tenth transistors 9 and 10 are input to a differential input section. The drains of the ninth and tenth transistors 9 and 10 are supplied with currents corresponding to the voltages at the connection points A1 and B1, and the first and second transistors 1 constituting the differential input section of the differential amplifier circuit 11 are used. , 2 are extracted from the source, resulting in high-pass filter characteristics and an offset canceling function for cutting DC components.
Note that the maximum capacitance value of the first variable capacitance element 18 is set to a value smaller than the capacitance value of the first fixed capacitance element 16, and similarly, the maximum capacitance value of the second variable capacitance element 19 is It is set to a value smaller than the capacitance value of the second fixed capacitance element 17.

Next, the common mode feedback circuit 103 has the same configuration as the conventional one.
That is, the common mode feedback circuit 103 includes the third and fourth transistors 3 and 4 of the differential amplifier circuit 11 so that the common output level at the output terminals 21 and 22 becomes a predetermined voltage set by the reference voltage Vref. The gate voltage is configured to be adjusted.

Next, the operation of the variable gain amplifier in the above-described embodiment of the present invention will be described mainly focusing on the offset cancel operation.
First, the transfer function of the low-pass filter in the offset cancel circuit 12 is as shown in Equation 5 below.

  T (s) = (1 + s · Rt · VC) / {1 + s · Rt · (VC + C)} Equation 5

Here, Rt is the resistance value of the seventh and eighth transistors 7 and 8, VC is the capacitance value of the variable capacitance elements 18 and 19, and C is the capacitance value of the fixed capacitance elements 16 and 17.
In Formula 5, when C >> VC, Formula 5 is expressed as Formula 6 below.

  T (s) = (1 + s · Rt · VC) / {1 + s · Rt · C)} Equation 6

In this case, the cut-off frequency is 1 / (2 · π · Rt · C), and both Rt and C are fixed, so that the cut-off frequency is naturally fixed.
The zero point frequency becomes 1 / (2 · π · Rt · VC), and the zero point frequency can be varied by changing VC.
FIG. 2 shows output voltage change characteristics when the capacitance VC of the first and second variable capacitors 18 and 19 is changed, that is, the seventh transistor 7 and the first fixed capacitor 16, and A characteristic diagram showing the frequency characteristics of the low-pass filter formed by each of the eighth transistor 8 and the second fixed capacitance element 17 is shown, which will be described below.

In the figure, the horizontal axis represents the logarithmic display frequency, and the vertical axis represents the voltage level at the output terminals 21 and 22, respectively.
The following can be said from the characteristics shown in FIG.
First, in general, the voltage gain in the differential amplifier circuit 11 is sufficiently large, and the output signals OUT + and OUT− are input to the low-pass filter configured in the offset cancel circuit 12, so that the frequency is sufficiently higher than the cutoff frequency. In the band, the voltage gain is limited at the zero point frequency of the low-pass filter described above.

On the other hand, in the frequency band equal to or lower than the cutoff frequency, the voltage gain Av of the differential amplifier circuit 11 is fixed and the cutoff frequency is also fixed as described above. Further, since the DC gain of the offset cancel circuit 12 is determined and fixed by the transconductance values of the ninth and tenth transistors 9 and 10 and the current value I1 of the constant current source 20, the voltage gain Avdc around DC is fixed. Is fixed.
Therefore, by changing the capacitance value VC of the variable capacitance elements 18 and 19, the voltage gain can be changed without reducing the offset cancellation capability.
Further, by fixing the cut-off frequency, it is possible to suppress the voltage gain of an extra frequency component (for example, a low-frequency noise component) in the low frequency range even if the voltage gain is changed.
For example, varactor diodes may be used as the variable capacitance elements 18 and 19, or a plurality of fixed capacitance elements may be arranged in parallel and switched by a switch. The seventh and eighth transistors 7 and 8 may be p-channel MOS transistors.

Next, the simulation result of the voltage gain characteristic of the variable gain amplifier in the embodiment of the present invention shown in FIG. 3 is shown, and this figure will be described below.
The figure shows the simulation result regarding the frequency characteristics of the voltage gain when the capacitance value VC of the variable capacitance elements 18 and 19 is changed. In the figure, the horizontal axis shows the frequency of the input signal by logarithmic display. The vertical axis indicates the reactive power level of the output signal OUT +.

According to the figure, by changing the capacitance value VC of the variable capacitance elements 18 and 19, the voltage gain in the vicinity of DC is not changed, and the voltage gain can be varied in a frequency band sufficiently higher than the cutoff frequency. I understand that.
That is, according to FIG. 3, the smaller the capacitance value VC, the smaller the value limited by the low-pass filter of the offset cancellation circuit 12, resulting in a smaller reactive power, in other words, a larger voltage gain. On the contrary, it can be understood that the larger the capacitance value VC, the larger the value limited by the low-pass filter of the offset cancel circuit 12, resulting in a larger reactive power, in other words, a smaller voltage gain.

  The present invention can be applied to a variable gain amplifier in which stable operation of the offset cancel function is desired.

DESCRIPTION OF SYMBOLS 11 ... Differential amplifier circuit 12 ... Offset cancellation circuit 18 ... 1st variable capacitance element 19 ... 2nd variable capacitance element 103 ... Common mode feedback circuit

Claims (2)

A differential amplifier circuit that differentially amplifies an input signal, and an offset cancel that feeds back only a predetermined low-frequency component of the output signal of the differential amplifier circuit to the differential amplifier circuit and removes a DC component of the output signal A circuit,
The variable offset amplifier, wherein the offset cancel circuit is configured to be able to vary only a zero point frequency without changing a cutoff frequency for the predetermined low frequency component.   The offset cancel circuit is connected between a differential input unit composed of two transistors connected to perform differential amplification, and an inverting input terminal of the differential input unit and one output terminal of the differential amplifier circuit. A first resistance element, a second resistance element connected between a non-inverting input terminal of the differential input section and the other output terminal of the differential amplifier circuit; and the first resistance element; A first fixed capacitive element connected between the ground, a first variable capacitive element connected in parallel to the first resistive element, and connected between the second resistive element and the ground; A second variable capacitance element connected in parallel to the second resistance element, and the capacitance value of the first variable capacitance element is the first variable capacitance element. A capacitance value smaller than that of the fixed capacitance element and the second variable capacitance element; Ryochi, the smaller than the capacitance value of the second fixed capacitance element, a variable gain amplifier according to claim 1, characterized by being configured respectively.

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