JP2013073649A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage that facilitates its analysis.SOLUTION: A semiconductor storage includes a memory part (100), a controller part (200) connected to the memory part (100), a first input/output part (300) connected to the controller part (200), a second input/output part (400) that is electrically connected to a node between the memory part (100) and the controller part (200) and is different from the first input/output part (300).

Description

  Embodiments described herein relate generally to a semiconductor memory device.

Conventionally, when an external terminal for accessing an internal node of a semiconductor module is provided, miniaturization of the module may be prevented. In order to solve this problem, for example, it is known that a plurality of input terminals of a switch are each connected to a corresponding internal node in the semiconductor module, and an output terminal is connected to a monitor terminal provided as an external terminal. Yes. This switch reduces the size of the module by conducting between any one of the plurality of input terminals selected and the output terminal.

JP 2010-62266 A

  The embodiment provides a semiconductor memory device that is easy to analyze.

According to the semiconductor memory device of the present embodiment, a memory unit, a controller unit connected to the memory unit, a first input / output unit connected to the controller unit, and between the memory unit and the controller unit A second input / output unit electrically connected to the node and different from the first input / output unit;

1 is a block diagram showing a semiconductor memory device according to a first embodiment. The block diagram which shows the memory part of 1st Embodiment. The figure which shows the threshold value distribution of the memory cell of 1st Embodiment. Sectional drawing which shows the package structure of the 1st input / output part and 2nd input / output part of 1st Embodiment. 4 is an enlarged view of the second terminals 400A to 400E and the protective film 700. FIG. Sectional drawing which shows the package structure of the 1st input / output part of the modification 1, and the 2nd input / output part.

(First embodiment)
Next, a first embodiment will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[Configuration of Semiconductor Memory Device]
The semiconductor memory device according to the first embodiment will be described with reference to FIGS. FIG.
As shown, the semiconductor memory device includes a memory unit (for example, NAND type) 100, a controller 200 that controls the entire memory unit 100, a first input / output unit 300, and a second input / output unit 40.
0.

<Memory part>
The memory unit 100 according to the present embodiment will be described with reference to FIGS. For convenience of explanation, the memory unit 100 includes a plurality of NAND flash memories (semiconductor chips). FIG. 2 shows the configuration of each NAND flash memory.

1. Overall Configuration As shown in FIG. 1, the semiconductor memory device according to this embodiment includes a memory cell array 1, row data 2, a driver circuit 3, a voltage generation circuit 4, a data input / output circuit 5, a control unit 6, and a source line driver circuit 7. And a sense amplifier 8.

1-1. Configuration example of the memory cell array 1
The memory cell array 1 includes blocks BLK0 to BLKs including a plurality of nonvolatile memory cells MT (s is a natural number). Each of the blocks BLK0 to BLKs includes a plurality of NAND strings 10 in which nonvolatile memory cells MT are connected in series. NAN
Each of the D strings 10 includes, for example, 64 memory cells MT and a select transistor ST1.
, ST2 are included.

The memory cell MT can hold binary or higher data. The structure of the memory cell MT includes a floating gate (charge conductive layer) formed on a p-type semiconductor substrate with a gate insulating film interposed therebetween,
The FG structure includes a control gate formed on a floating gate with an inter-gate insulating film interposed. The structure of the memory cell MT may be a MONOS type. What is MONOS type?
A charge storage layer (for example, an insulating film) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and an insulating film (hereinafter referred to as a block layer) formed on the charge storage layer and having a dielectric constant higher than that of the charge storage layer And a control gate formed on the block layer.

The control gate of the memory cell MT is electrically connected to the word line WL, the drain is electrically connected to the bit line BL, and the source is electrically connected to the source line SL. Memory cell MT is an n-channel MOS transistor. The number of memory cells MT is 64.
The number is not limited to 128, 256, 512, etc., and the number is not limited.

The adjacent memory cells MT share the source and drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cells MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

The control gates of the memory cells MT in the same row are commonly connected to any of the word lines WL0 to WL63, and the gate electrodes of the select transistors ST1 and ST2 of the memory cells MT in the same row are connected to the select gate lines SGD1 and SGS1, respectively. Commonly connected. For simplification of description, the word lines WL0 to WL63 may be simply referred to as word lines WL in the following when they are not distinguished. Further, the drains of the select transistors ST1 in the same column in the memory cell array 1 are commonly connected to any one of the bit lines BL1 to BL (n + 1).
Hereinafter, the bit lines BL1 to BL (n + 1) are collectively referred to as a bit line BL (n: natural number) unless they are distinguished. The source of the select transistor ST2 is the source line SL
Commonly connected to

Data is collectively written in the plurality of memory cells MT connected to the same word line WL, and this unit is called a page. Further, data is erased collectively from the plurality of memory cells MT in units of blocks BLK.

1-2. About threshold distribution of memory cell MT
The threshold distribution of the memory cell MT will be described with reference to FIG. FIG. 3 is a graph in which the horizontal axis indicates the threshold distribution (voltage) and the vertical axis indicates the number of memory cells MT.

As shown in the drawing, each memory cell MT can hold, for example, binary (2-levels) data (1-bit data). That is, the memory cell MT is “1” in ascending order of the threshold voltage Vth.
"And" 0 "can be stored.

The threshold voltage Vth0 of “1” data in the memory cell MT is Vth0 <V01. The threshold voltage Vth1 of “0” data is V01 <Vth1. Thus, the memory cell MT can hold 1-bit data of “0” data and “1” data according to the threshold value. The memory cell MT is set to “1” data (for example, negative voltage) in the erased state, and is set to a positive threshold voltage by writing data and injecting charge into the charge storage layer.

1-3. About row decoder 2
Returning to FIG. 2, the row decoder 2 will be described. The row decoder 2 includes a block decoder 20 and transfer transistors (N channel MOS transistors) 21 to 23.
The block decoder 20 decodes a block address given from the control unit 6 during a data write operation, a read operation, and an erase operation, and selects a block BLK based on the result. The block decoder 20 is provided for each block BLK.
Each of the block decoders 20 has a latch circuit. This latch circuit holds data indicating whether or not the block BLK corresponding to each block decoder 20 is a defective block. Block selection signals from the block decoder 20 are transferred from the transfer transistors 21 to 2.
3 is transferred. As a result, the transfer transistors 21 to 23 are turned on. Thus, based on the block selection signal supplied from the block decoder 20, the row decoder 2 transfers the voltage supplied from the driver circuit 3 to the select gate lines SGD1 and SGS1 and the word lines WL0 to WL63, respectively.

Further, the row decoder 2 decodes the row address given from the control unit 6, and based on the result, the desired word line WL among the plurality of word lines WL in the selected block.
Select.

1-4. About Driver Circuit 3 The driver circuit 3 includes select gate line drivers 31 and 32 provided for the select gate lines SGD1 and SGS1, and a word line driver 33 provided for each word line WL. In the present embodiment, the word line driver 33 and the select gate line drivers 31 and 32 are
The blocks BLK0 to BLKs are provided.

The select gate line driver 31 transfers, for example, a signal sgd to the gate of the select transistor ST1 via the select gate line SGD1 during data writing, reading, erasing, and data verification. The signal sgd is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD (for example, 1.8 [V] when the signal is at the “H” level.
V]).

Similarly to the select gate line driver 31, the select gate line driver 32 passes through the select gate line SGS <b> 1 of the selected block BLK during data writing, reading,
At the time of data verification, for example, the signal sgs is transferred to the gate of the selection transistor ST2 via the selection gate line SGS1. The signal sgs is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD when the signal is at the “H” level.

1-4. Voltage Generation Circuit 4 The voltage generation circuit 4 generates a voltage required for data programming, reading, and erasing by boosting or stepping down an externally applied voltage. The generated voltage is supplied to the driver circuit 3.

1-5. About the data input / output circuit 5 The data input / output circuit 5 is an address (row address, column address, block address; page including row address and column address) supplied from an external host via an I / O terminal (not shown). And the command are output to the control unit 6. The data input / output circuit 5 outputs write data to the sense amplifier 8 via the data line Dline.

Further, when outputting the data read from the memory cell array 1 to the host, the data input / output circuit 5 receives the data amplified by the sense amplifier 8 through the data line Dline based on the control of the control unit 6. After that, the data is output to the host via the I / O terminal.

1-6. About Control Unit 6 The control unit 6 controls the operation of the entire NAND flash memory. That is, the operation sequence in the data write operation, read operation, and erase operation is executed based on the address and command given from the host via the data input / output circuit 5.
The control unit 6 generates a block selection signal, a column selection signal, and a row selection signal based on the address and the operation sequence.

The control unit 6 outputs the block selection signal and the row selection signal described above to the row decoder 2.
Further, the control unit 6 outputs a column selection signal to a column decoder (not shown). The column selection signal is a signal for selecting the column direction of the sense amplifier 8.

The control unit 6 is given a control signal supplied from a memory controller connected to the semiconductor memory device. The control unit 6 distinguishes whether the signal supplied from the host to the data input / output circuit 5 via the I / O terminal is an address or data based on the supplied control signal.

1-7. Sense Amplifier 8 The sense amplifier 8 senses and amplifies data read from the memory cell MT to the bit line BL when reading data. Specifically, after precharging the bit line BL to a predetermined voltage, the bit line B is selected by the NAND string 11 selected by the row decoder 2.
L is discharged, and the discharge state of the bit line BL is sensed. That is, the sense amplifier 8 amplifies the voltage of the bit line BL and senses data stored in the memory cell MT.

  At the time of data writing, write data is transferred to the corresponding bit line BL.

1-8. Column Decoder A column decoder (not shown) decodes a column address given from the control unit 6 and outputs a column selection signal to the sense amplifier 8. Based on this column selection signal, a desired latch circuit in the sense amplifier 8 is selected.

1-9. Address Buffer An address buffer (not shown) has a function of holding an address input to the control unit 6. In the semiconductor memory device of this embodiment, the address is supplied to the address buffer via the control unit 6, but the present invention is not limited to this, and the address may be directly supplied from the data input / output circuit 5. .

<Controller>
Returning to FIG. 1, the controller 200 of the present embodiment will be described.

As shown in FIG. 1, the controller 200 has a function of controlling the entire memory unit 100. The controller 200 is connected to the memory unit 100 via wirings 500A to 500D. The controller 200 includes, for example, a host interface that exchanges data with an external host, an MPU, a circuit for CPRM (Copy Protection for Prerecorded Media), an R
It has a memory interface that exchanges data with the OM, the RAM, and the memory unit 100.

<First input / output unit>
Returning to FIG. 1, the first input / output unit 300 of this embodiment will be described. The first input / output unit 300 is connected to the controller 200. The first input / output unit 300 includes a plurality of input / output terminals (also referred to as first terminals) 300A to 300D. This first terminal (including I / O terminal)
From 300A to 300D, for example, command, address, data, chip enable signal /
CE, write enable signal / WE, read enable signal / RE, ready / busy signal RY / BY, and other external control signals are input and output.

<Second input / output unit>
The second input / output unit 400 of this embodiment will be described. The second input / output unit 400 has a function of directly controlling data exchange with the memory unit 100 without using the controller 200.

The second input / output unit 400 is connected to wirings 500 </ b> A to 500 </ b> D formed between the memory unit 100 and the controller 200. The second input / output unit 400 includes a plurality of input / output terminals (also referred to as second terminals) 400A to 400E. The second terminal 400A is connected to the wiring 500A,
The second terminal 400B is connected to the wiring 500B, the second terminal 400C is connected to the wiring 500C, and the second terminal 400D is connected to the wiring 500D. The second terminal 400E is directly connected to the memory unit 1
Connected to 00. The second terminals 400A to 400D are connected to the memory unit 100 and the controller 200.
Connected in common.

From the second terminals 400A to 400D (including I / O terminals), the first terminals 300A to 30A.
Like 0D, for example, command, address, data, chip enable signal / CE, write enable signal / WE, read enable signal / RE, ready / busy signal RY / B
Y and other external control signals are input and output.

The second terminal 400 </ b> E is a terminal for inputting a test signal for executing a test to the memory unit 100. The second terminal 400E is connected to the memory unit 100, and the controller 20
Not connected to 0. When the memory unit 100 receives the test signal, the memory unit 100 executes a desired test. For example, a test is performed to determine whether there is a short between the word lines WL.

By using the second terminals 400 </ b> A to 400 </ b> E, the memory unit 100 can be directly accessed without using the controller 200. As a result, the test can be executed on the memory unit 100 without using the controller 200, and the test result of the memory unit 100 can be displayed on the second terminals 400A to 400A-4.
It can be output via 00E.

[Package structure of first input / output unit and second input / output unit]
Next, the package structure of the first input / output unit 300 and the second input / output unit 400 of this embodiment will be described with reference to FIG. For convenience of explanation, description will be made using a package structure of a BGA type semiconductor memory device. The semiconductor memory device is not limited to the BGA type semiconductor memory device, but may be another type of semiconductor memory device. Solder balls are omitted from the drawing.

A plurality of semiconductor chips (not shown) in the memory unit 100 and the controller 200 are connected by a desired lower layer wiring. Although illustration of the semiconductor chip and the controller 200 is omitted in FIG. 4, after these are connected to the lower layer wiring, the mold resin is filled and cured.

The lower layer wiring includes wiring from the controller 200 to the first terminals 300A to 300D, wiring 500A to 500D, wiring from the wirings 500A to 500D to the second terminals 400A to 400D, and wiring from the memory unit 100 to the second terminal 400E. Take a role.

The lower layer wiring (for example, Cu wiring) shown in FIG. 4 has the first terminals 300A to 300D or the second terminals.
Connected to terminals 400A-400E. By making the lower layer wiring a desired layout, the first
The terminals 300A to 300D are connected to the controller 200, and the second terminals 400A to 400E are connected to the memory unit 100 and the controller 200 in common.

The second terminal 400E is connected only to the memory unit 100. This is also realized by the layout of the lower layer wiring.

As shown in FIG. 4, the first terminals 300A to 300D are exposed to the outside, but the second terminal 4
00A to 400E are coated with a protective film 700. A space is formed between the second terminals 400 </ b> A to 400 </ b> E and the protective film 700. A hole 800 is formed in a portion of the protective film 700 that covers the second terminals 400A to 400E. The hole 800 has second terminals 400A to 400E.
When testing using the second terminal 400A to 400E, the second terminals 400A to 400E have a function of preventing damage. In addition, since the hole 800 has a space formed between the second terminals 400A to 400E and the protective film 700, the air inside the space expands due to heat such as reflow, so that, for example, a solder resist that forms a space It also has a function of preventing cracks from entering.

FIG. 5 is an enlarged view of the second terminals 400A to 400E and the protective film 700 in FIG. As shown in FIG. 5, the protective film 700 is formed with a groove 900 for easily exposing the surfaces of the second terminals 400A to 400E to the outside.

When transferring data with the memory unit 100 using the second terminals 400A to 400E,
For example, a force is applied to the outside from the hole 800 to the protective film 700 to remove the protective film 700,
The surfaces of the second terminals 400A to 400E are exposed. The presence of the groove 900 can reduce the force applied to the outside.

[Effect of this embodiment]
As described above, the semiconductor memory device of this embodiment can provide a semiconductor memory device that can be easily analyzed.

For example, the second terminals 400 </ b> A to 400 </ b> E are not provided, and only the first terminals 300 </ b> A to 300 </ b> D connected to the controller 200 are provided in the semiconductor memory device, and the memory unit 100 is provided via the first terminals 300 </ b> A to 300 </ b> D. The effect of the semiconductor memory device of the present embodiment will be described by comparing the case of testing (Comparative Example) with the case of testing the memory unit 100 of the semiconductor memory device of the present embodiment.

In the case of the comparative example, it is necessary to test the memory unit 100 via the first terminals 300A to 300D. Therefore, when the test result output from the semiconductor memory device of the comparative example is a failure result, it cannot be determined whether the controller 200 is defective or the memory unit 100 is defective. For this reason, in order to determine whether the controller 200 is defective or the memory unit 100 is defective, it is necessary to remove the mold resin and perform a test on each.

When the mold resin is peeled off and the semiconductor memory device is disassembled, the package may be cracked and cannot be returned to the state before disassembly.

However, in the semiconductor memory device of the present embodiment, the second terminals 400A to 400E that can exchange data directly from the memory unit 100 are provided. As a result, a test can be executed on the memory unit 100 without disassembling the semiconductor memory device. A test can be similarly executed for the controller 200. As a result, package cracks do not occur. Therefore, the semiconductor memory device of this embodiment can provide a semiconductor memory device that can be easily analyzed as compared with the comparative example.

(Modification 1)
A first modification of the present embodiment will be described with reference to FIG. The semiconductor memory device according to Modification 1 is the same as the semiconductor memory device according to the first embodiment except for the shape of the second terminal with respect to the semiconductor memory device according to the first embodiment.

As shown in FIG. 6, the second terminals 400A to 400E are formed with a thicker film than the first terminals 300A to 300D. That is, the surface of the second terminals 400A to 400E is the first terminal 300.
It is formed outside the surface of A to 300D.

The second terminals 400A to 400E are coated with a solder resist film 1000 as a protective film.

When transferring data with the memory unit 100 using the second terminals 400A to 400E,
The solder resist film 1000 is etched back (for example, CMP) from the outside, and the process is performed until the surfaces of the second terminals 400A to 400E are exposed to the outside.

After the surfaces of the second terminals 400A to 400E are exposed, the second terminals 400A to 400E are exposed.
E is used to exchange data with the memory unit 100.

Even in the case of the first modification, the same effects as those of the first embodiment can be obtained. That is, in the semiconductor memory device of the present embodiment, the second terminal 40 that can exchange data directly from the memory unit 100.
0A to 400E were provided. As a result, a test can be executed on the memory unit 100 without disassembling the semiconductor memory device. A test can be similarly executed for the controller 200. As a result, package cracks do not occur. Therefore, the semiconductor memory device of this embodiment can provide a semiconductor memory device that can be easily analyzed as compared with the comparative example.

Note that the second terminals 400A to 400E may be formed between the plurality of first terminals 300A to 300D. Also in this case, the same effects as those of the first embodiment can be obtained.

Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Row decoder 3 ... Driver circuit 4 ... Voltage generation circuit 5 ... Data input / output circuit 6 ... Control part 7 ... Source line driver circuit 8 ... Sense amplifier MT ... Memory cell ST1, ST2 ... Selection transistor

Claims (5)

A memory section;
A controller unit connected to the memory unit;
A first input / output unit connected to the controller unit;
A semiconductor memory device comprising: a second input / output unit that is electrically connected to a node between the memory unit and the controller unit and is different from the first input / output unit. At the time of shipment, the first terminal of the first input / output unit is exposed to the outside,
2. The semiconductor memory device according to claim 1, wherein the second terminal of the second input / output unit is coated with a protective film. Forming a space between the second terminal and the protective film;
The semiconductor memory device according to claim 1, wherein a hole is formed in a part of the second terminal. 4. The semiconductor memory device according to claim 1, wherein the first terminal is thinner than the second terminal. 5. 5. The semiconductor memory device according to claim 1, wherein the coated second terminal is provided between the adjacent first terminals. 6.

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