JP2013073117A - Active matrix substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix substrate having an electrostatic protection circuit that negates the need of potential control by an external power source during active operation.SOLUTION: An active matrix substrate 1 comprises: a plurality of pieces of gate wiring 22; a plurality of pieces of source wiring 21; a high potential side ESD ring 31 and a low potential side ESD ring 32; ESD diodes 42 disposed corresponding to individual ones of the plurality of pieces of gate wiring 22 and the plurality of pieces of source wiring 21 in which anode electrodes are connected to a low potential side ESD ring 32 and each of cathode electrodes is connected to the gate wiring 22 and to one of the source wiring 21; ESD diodes 41 in which each of anode electrodes is connected to the one of the source wiring 21 and cathode electrodes are connected to the high potential side ESD ring 31; and a low potential fixing diode 43 disposed corresponding to two or more individual ones of the gate wiring 22 in which an anode electrode is connected to the low potential side ESD ring 32 and a cathode electrode is connected to the gate wiring 22 corresponding thereto.

Description

  The present invention relates to an active matrix substrate, and more particularly to an active matrix substrate having an electrostatic protection function.

  With the recent demand for higher quality display devices, liquid crystal display panels and organic electroluminescence (EL) display panels having a plurality of pixels arranged two-dimensionally are attracting attention as thin and low power consumption display panels. ing. Among these display panels, an active matrix type display panel is provided with a thin film transistor (TFT) at the intersection of a plurality of scanning lines and a plurality of data lines, and this TFT is turned on through a selected gate wiring. The light emission luminance and the light emission timing of the light emitting element are controlled by inputting a data signal or the like from the source wiring to the driving transistor and the storage capacitor element connected to the TFT. Thus, in the active matrix display panel, the light emitting element can emit light until the next scanning (selection), so that the luminance of the display is not reduced even if the duty ratio is increased.

  However, since the active matrix display panel is a charging method in which the data capacitor is held in the storage capacitor element of the selected pixel, a large amount of electrostatic charge is generated during the manufacturing and display operation, so that the TFT, the gate wiring And has the property of being easily accumulated in the source wiring. The accumulated electrostatic charge causes a problem that the constituent elements of the pixel circuit represented by the gate insulating layer of the TFT are electrostatically destroyed.

  Patent Document 1 discloses an electronic device including an ESD (Electrostatic Discharge) protection circuit that protects a pixel circuit from electrostatic charges generated during display panel manufacture and display operation.

  FIG. 8 is a configuration diagram of an ESD protection circuit included in the electronic device described in Patent Document 1. The electronic device 500 shown in the figure includes a plurality of pixels 510 arranged in a matrix, a source wiring 501 arranged for each pixel column, a gate wiring 502 arranged for each pixel row, and a discharge ring 503. And 504, and discharge devices 523 and 524 arranged for each source wiring 501 and each gate wiring 502. The discharge device 523 is a current limiting element that allows a forward current to flow from the discharge ring 503 to the source wiring 501 or the gate wiring 502. The discharge device 524 is a current limiting element that allows a forward current to flow from the source line 501 or the gate line 502 to the discharge ring 504.

  The pixel 510 includes a selection transistor 511 and a pixel circuit 512. The gate electrode of the selection transistor 511 is connected to the gate wiring 502, and the source electrode is connected to the source wiring 501. From this connection relationship, during the writing operation and the display operation, that is, the active operation, the selection transistor 511 is turned on in a row sequential manner by the voltage of the gate wiring 502 which is the gate voltage of the selection transistor 511. In the conduction period of the selection transistor 511, the data voltage of the source wiring 501 that is the source voltage of the selection transistor 511 is supplied to the pixel circuit 512.

  During the active operation, the discharge ring 503 is set to a voltage equal to or lower than the minimum voltage set to the source wiring 501 and to a voltage equal to or lower than the minimum voltage set to the gate wiring 502. In addition, the discharge ring 504 is set to a voltage equal to or higher than the maximum voltage set for the source wiring 501 and to a voltage equal to or higher than the maximum voltage set for the gate wiring 502. Thus, during the active operation of the electronic apparatus 500, the discharge devices 523 and 524 do not flow forward current due to the voltage change for writing the data voltage of the source wiring 501 and the gate wiring 502.

  On the other hand, if electrostatic charges are abnormally accumulated in the source wiring 501 and the gate wiring 502, the selection transistor 511 and the pixel circuit 512 may be electrostatically damaged. At this time, if the accumulated electrostatic charge is a positive charge, the potential of the source wiring 501 or the gate wiring 502 in which the positive charge is accumulated becomes higher than the potential of the discharge ring 504. As a result, a forward current flows through the discharge device 524 and the positive charge is discharged to the discharge ring 504, so that electrostatic breakdown is avoided. Further, when the accumulated electrostatic charge is a negative charge, the potential of the source wiring 501 or the gate wiring 502 where the negative charge is accumulated becomes lower than the potential of the discharge ring 503. As a result, a forward current flows through the discharge device 523 and the negative charge is discharged to the discharge ring 503, so that electrostatic breakdown is avoided.

  As described above, the electronic apparatus 500 described in Patent Document 1 can avoid electrostatic breakdown during an active operation by setting appropriate potentials for each of the two discharge lines.

JP-T-2004-538512

  However, in the electronic apparatus 500 described in Patent Document 1, during the active operation for writing the data voltage, a state in which no forward current flows through the discharge devices 523 and 524, that is, the discharge devices 523 and 524 are set to a non-operation state. In order to achieve this, the above-described predetermined potential must be set and maintained by the external power supply for the two discharge rings 503 and 504. In addition, a terminal for setting the potential from an external power source needs to be secured on the display panel.

  In view of the above problems, an object of the present invention is to provide an active matrix substrate having an electrostatic protection circuit that does not require potential control by an external power source during an active operation.

  In order to achieve the above object, an active matrix substrate according to one embodiment of the present invention includes a substrate, a plurality of gate wirings arranged on the substrate, and a plurality of gate wirings for selecting a pixel to which a data signal is to be written among the plurality of pixels. A plurality of source wirings arranged on the substrate in a direction orthogonal to the plurality of gate wirings and writing the data signals to the selected pixels, and arranged in a peripheral region on the substrate; The first electrostatic discharge ring and the second electrostatic discharge ring are arranged corresponding to at least each of the plurality of gate lines or each of the plurality of source lines, and an anode electrode is connected to the first electrostatic discharge ring A first diode having a cathode electrode connected to one of the plurality of gate lines and the plurality of source lines, and an anode electrode A current limiting unit including a second diode connected to one wiring and having a cathode electrode connected to the second electrostatic discharge ring; and corresponding to each of at least two of the plurality of gate wirings And a third diode having an anode electrode connected to the first electrostatic discharge ring and a cathode electrode connected to a corresponding gate wiring of the two gate wirings. To do.

  According to the active matrix substrate of the present invention, by utilizing the potential necessary for the active operation, the electrostatic protection circuit during the active operation can be brought into a non-operating state without potential control by an external power supply. .

1 is a block diagram showing a configuration of an active matrix substrate according to Embodiment 1 of the present invention. 3 is a diagram illustrating an example of a circuit configuration of a pixel according to Embodiment 1. FIG. It is a figure showing the circuit state at the time of active operation | movement of the active matrix substrate which concerns on Embodiment 1 of this invention, and ESD non-operation. It is a figure showing the circuit state at the time of ESD protection operation | movement of the active matrix substrate which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the active matrix substrate which concerns on Embodiment 2 of this invention. 6 is a diagram illustrating an example of a circuit configuration of a pixel according to Embodiment 2. FIG. It is a figure showing the circuit state at the time of normal active operation | movement of the active matrix substrate which concerns on Embodiment 2 of this invention. It is a figure showing the circuit state at the time of ESD protection operation | movement of the active matrix substrate which concerns on Embodiment 2 of this invention. 1 is an external view of a thin flat TV incorporating an active matrix substrate of the present invention. 10 is a configuration diagram of an ESD circuit included in an electronic device described in Patent Document 1. FIG.

  An active matrix substrate according to an aspect of the present invention includes a substrate, a plurality of gate wirings arranged on the substrate for selecting a pixel to which a data signal is written, and the substrate. A plurality of source wirings arranged in a direction orthogonal to the plurality of gate wirings and writing the data signal to the selected pixel; a first electrostatic discharge ring and a first electrostatic discharge ring arranged in a peripheral region on the substrate; Two electrostatic discharge rings, at least corresponding to each of the plurality of gate wirings or each of the plurality of source wirings, an anode electrode is connected to the first electrostatic discharge ring, and a cathode electrode is A gate diode and a first diode connected to one of the plurality of source lines and an anode electrode are connected to the one line, and a cathode A current limiting portion comprising a second diode connected to the second electrostatic discharge ring, and an anode electrode disposed corresponding to each of at least two gate wirings of the plurality of gate wirings. Is connected to the first electrostatic discharge ring, and a cathode is provided with a third diode connected to a corresponding gate wiring of the two gate wirings.

  According to this aspect, the first electrostatic discharge ring for negative charge discharge can be fixed to the non-selection potential of the gate wiring by two or more third diodes arranged corresponding to the gate wiring. Therefore, the first diode during the active operation can be brought into a non-operating state without controlling the potential of the first electrostatic discharge ring by the external power supply. Therefore, it is not necessary to separately provide an external power supply and a connection terminal as a circuit for preventing discharge breakdown due to negative electrostatic charges, and the configuration of the active matrix substrate and the display device including the same can be simplified.

  In the active matrix substrate according to one embodiment of the present invention, the second electrostatic discharge ring is connected to a power supply line on a high potential side among power supply lines for supplying a power supply voltage to the plurality of pixels. May be.

  Accordingly, the second electrostatic discharge ring for positive charge discharge can be fixed to the high potential side potential by utilizing the high potential side potential of the power supply potential supplied to the pixel circuit. Therefore, the second diode during the active operation can be inactivated without controlling the potential of the second electrostatic discharge ring by the external power supply. Therefore, it is not necessary to separately provide an external power supply and a connection terminal as a circuit for preventing discharge breakdown due to positive electrostatic charges, and the configuration of the active matrix substrate and the display device including the active matrix substrate can be simplified.

  In the active matrix substrate according to one embodiment of the present invention, each of the first diode, the second diode, and the third diode is formed of an n-type thin film transistor, and the first diode, The anode electrode of each of the second diode and the third diode is an electrode in which a gate electrode and a drain electrode of the n-type thin film transistor are short-circuited, and the cathode electrode is a source electrode of the n-type thin film transistor. It is preferable.

  The active matrix substrate according to one embodiment of the present invention is used as a display substrate for a pixel including a circuit using n-type thin film transistors. Therefore, by forming the first, second, and third diodes using similar n-type thin film transistors, the manufacturing process can be simplified and the manufacturing yield can be improved.

  In the active matrix substrate according to one embodiment of the present invention, it is preferable that the third diode has a built-in voltage lower than that of the first diode.

  The third diode causes a forward current to flow preferentially from the first electrostatic discharge ring to the gate wiring that is at the low level non-selection potential, and the first electrostatic discharge ring always passes through the non-selection potential of the gate wiring. Must be set to Therefore, the built-in voltage of the third diode is set small. On the other hand, since the first diode only needs to be in an operating state when negative electrostatic charges are abnormally accumulated, the built-in voltage is set larger than the built-in voltage of the third diode. Thereby, the potential fixing operation and the ESD protection operation of the discharge ring are executed at an appropriate timing.

  In the active matrix substrate according to one embodiment of the present invention, the third diode causes a gate when no pixel is selected by flowing a forward current from the first electrostatic discharge ring to the one gate wiring. The potential of the wiring is fixed to the first electrostatic discharge ring.

  Accordingly, it is not necessary to separately provide an external power supply and a connection terminal as a circuit for preventing discharge breakdown due to negative electrostatic charges, and thus the configuration of the active matrix substrate and the display device including the active matrix substrate can be simplified.

  An active matrix substrate according to one embodiment of the present invention includes a substrate, a plurality of gate wirings arranged on the substrate for selecting a pixel to which a data signal is written, and the substrate. And a plurality of source lines for writing the data signal to the selected pixel, and a first electrostatic discharge ring disposed in a peripheral region on the substrate. And a second electrostatic discharge ring, at least corresponding to each of the plurality of gate wirings or each of the plurality of source wirings, an anode electrode connected to the first electrostatic discharge ring, and a cathode electrode A first diode connected to one of the plurality of gate lines and the plurality of source lines, and an anode electrode are connected to the one line. A cathode electrode is disposed corresponding to each of at least two gate wirings among the plurality of gate wirings, and a current limiting unit comprising a second diode connected to the second electrostatic discharge ring, and an anode electrode Is connected to a corresponding one of the two gate lines, and a cathode is provided with a third diode connected to the second electrostatic discharge ring.

  According to this aspect, the second electrostatic discharge ring for positive charge discharge can be fixed to the non-selection potential of the gate wiring by two or more third diodes arranged corresponding to the gate wiring. Therefore, the second diode during the active operation can be inactivated without controlling the potential of the second electrostatic discharge ring by the external power supply. Therefore, it is not necessary to separately provide an external power supply and a connection terminal as a circuit for preventing discharge breakdown due to positive electrostatic charges, and the configuration of the active matrix substrate and the display device including the active matrix substrate can be simplified.

  In the active matrix substrate according to one embodiment of the present invention, the first electrostatic discharge ring is connected to a low-potential-side power line among power lines for supplying a power voltage to the plurality of pixels. May be.

  Thus, the first electrostatic discharge ring for negative charge discharge can be fixed to the low potential side potential by utilizing the low potential side potential of the power supply potential supplied to the pixel circuit. Therefore, the first diode during the active operation can be brought into a non-operating state without controlling the potential of the first electrostatic discharge ring by the external power supply. Therefore, it is not necessary to separately provide an external power supply and a connection terminal as a circuit for preventing discharge breakdown due to negative electrostatic charges, and the configuration of the active matrix substrate and the display device including the same can be simplified.

  In the active matrix substrate according to one embodiment of the present invention, each of the first diode, the second diode, and the third diode is formed of a p-type thin film transistor, and the first diode, The anode electrode of each of the second diode and the third diode is a source electrode of the p-type thin film transistor, and the cathode electrode is an electrode in which a gate electrode and a drain electrode of the p-type thin film transistor are short-circuited. It is preferable.

  An active matrix substrate according to one embodiment of the present invention is used as a display substrate for a pixel including a p-type thin film transistor. Therefore, by forming the first, second, and third diodes using similar p-type thin film transistors, the manufacturing process can be simplified and the manufacturing yield can be improved.

  In the active matrix substrate according to one embodiment of the present invention, it is preferable that the third diode has a built-in voltage lower than that of the second diode.

  The third diode causes a forward current to flow preferentially from the gate line, which is a high level non-selection potential, to the second electrostatic discharge ring, so that the second electrostatic discharge ring always passes through the non-selection potential of the gate line. Must be set to Therefore, the built-in voltage of the third diode is set small. On the other hand, since the second diode only needs to be in an operating state when the positive electrostatic charge is abnormally accumulated, the built-in voltage is set larger than the built-in voltage of the third diode. Thereby, the potential fixing operation and the ESD protection operation of the discharge ring are executed at an appropriate timing.

  Further, in the active matrix substrate according to one embodiment of the present invention, the third diode causes the forward gate current to flow from the one gate wiring to the second electrostatic discharge ring, thereby preventing a gate when no pixel is selected. The potential of the wiring is fixed to the second electrostatic discharge ring.

  Accordingly, it is not necessary to separately provide an external power supply and a connection terminal as a circuit for preventing discharge breakdown due to positive electrostatic charges, and thus the configuration of the active matrix substrate and the display device including the active matrix substrate can be simplified.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments and drawings, the same components will be described with the same reference numerals.

(Embodiment 1)
The active matrix substrate in this embodiment includes a plurality of gate wirings and a plurality of source wirings arranged on the substrate, and a first electrostatic discharge ring and a second electrostatic discharge ring arranged in a peripheral region on the substrate. And at least one of the plurality of gate lines or each of the plurality of source lines, the anode electrode is connected to the first electrostatic discharge ring, and the cathode electrode is formed of the plurality of gate lines and the plurality of source lines. A current limiting unit including a first diode connected to one wiring, and a second diode having an anode electrode connected to the one wiring and a cathode electrode connected to a second electrostatic discharge ring; Arranged corresponding to each of at least two of the plurality of gate lines, the anode electrode is connected to the first electrostatic discharge ring. A cathode electrode and a third diode connected to one gate line of said two gate lines.

  As a result, the first electrostatic discharge ring for negative charge discharge can be fixed to the non-selection potential of the gate wiring. Therefore, the first diode during the active operation can be brought into a non-operating state without controlling the potential of the first electrostatic discharge ring by the external power supply.

  Embodiment 1 of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an active matrix substrate according to Embodiment 1 of the present invention. The active matrix substrate 1 in FIG. 1 includes a plurality of pixels 10 arranged on the substrate, a source wiring 21 arranged for each pixel column, a gate wiring 22 arranged for each pixel row, and a high potential side ESD ring. 31, a low potential side ESD ring 32, ESD diodes 41 and 42, and a low potential fixed diode 43. The substrate is, for example, a glass substrate. The active matrix substrate 1 constitutes a display panel that is a part of a display device such as an organic EL display.

  The gate wiring 22 is disposed on the substrate and has a function of giving a gate signal for selecting a pixel to which a data voltage, which is a source signal, is written among the plurality of pixels 10 to the pixel.

  The source wiring 21 is arranged on the substrate in a direction orthogonal to the gate wiring 22 and has a function of writing a data voltage to the pixel selected by the gate signal.

  The high potential side ESD ring 31 is a second electrostatic discharge ring disposed in the peripheral region on the substrate. The high potential side ESD ring 31 flows in from the gate terminal and the source terminal, or releases the positive electrostatic charges accumulated in the gate wiring 22 and the source wiring 21, so that the positive electrostatic charge is generated in the pixel 10. It has a function to avoid discharging and electrostatically destroying the pixel circuit.

  The low potential side ESD ring 32 is a first electrostatic discharge ring arranged in a peripheral region on the substrate. The low potential side ESD ring 32 flows in from the gate terminal and the source terminal, or releases the negative electrostatic charge accumulated in the gate wiring 22 and the source wiring 21, so that the negative electrostatic charge is generated in the pixel 10. It has a function to avoid discharging and electrostatically destroying the pixel circuit.

  The active matrix substrate 1 is connected to a gate driver through gate terminals G1 to Gm, and is connected to a source driver through source terminals S1 to Sn.

  Here, the configuration of the pixel 10 will be described in detail.

FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel according to the first embodiment. Pixels 10 shown in the figure are arranged in a matrix on a substrate, and include a selection transistor 101, a drive transistor 102, a capacitor 103, and an organic EL element 104. Here, the selection transistor 101 and the drive transistor 102 are n-type thin film transistors. The drain electrode of the selection transistor 101 is connected to the source wiring 21, the gate electrode is connected to the gate wiring 22, and the source electrode is connected to the capacitor 103 and the gate electrode of the driving transistor 102. The drain electrode of the driving transistor 102 is connected to the power supply line 23 that supplies the power supply potential _VTFT , and the source electrode is connected to the anode electrode of the organic EL element 104.

In this configuration, the gate when the pixel gate signal potential V _H of the high level is selected potential is sequentially input row select transistor 101 is turned on in line 22, the data voltage supplied through the source line 21 V _DT Is written into the capacitor 103. The holding voltage written in the capacitor 103 is held for one frame period, and the conductance of the driving transistor 102 changes in analog by the holding voltage, and the driving current corresponding to the light emission gradation is changed from the power supply line 23 to the driving transistor. 102 → Supplied to the organic EL element 104. Thereby, the organic EL element 104 emits light and is displayed as an image.

  Note that the pixel 10 is not limited to the circuit configuration described above. That is, the selection transistor 101, the drive transistor 102, and the capacitor 103 are circuit components necessary for flowing a drive current corresponding to the data voltage to the organic EL element 104. However, another circuit component is included in the circuit component. The case where it is added is also included in the pixel 10 according to the present invention.

  Returning to FIG. 1 again, the configuration and function of the ESD protection circuit which is the main part of the present invention will be described.

  In the active matrix substrate 1 according to the first embodiment, a high potential side ESD ring 31 and a low potential side ESD ring 32 are disposed so as to surround a display region in which a plurality of pixels 10 are disposed. The high potential side ESD ring 31 is connected to a power supply line 23 for supplying a plurality of pixels 10 with a high potential side power supply potential.

  Further, ESD diodes 41 and 42 connected in series with each other are arranged for each of the gate wiring 22 and the source wiring 21. The anode electrode of the ESD diode 41 and the cathode electrode of the ESD diode 42 are connected to the gate wiring 22. The cathode electrode of the ESD diode 41 is connected to the high potential side ESD ring 31. The anode electrode of the ESD diode 42 is connected to the low potential side ESD ring 32. The ESD diode 42 that is the first diode and the ESD diode 41 that is the second diode constitute a current limiting unit.

  Furthermore, a low-potential fixed diode 43 that is a third diode is arranged corresponding to the gate wiring 22 in the first row and the gate wiring 22 in the second row. The anode electrode of the low potential fixed diode 43 is connected to the low potential side ESD ring 32, and the cathode electrode is connected to the gate wiring 22.

  With the above configuration, the low potential fixing diode 43 fixes the low potential side ESD ring 32 to a low potential which is a pixel non-selection potential during a writing operation to the display region and a display operation of the display region, that is, a normal active operation. It has a function. Further, during normal active operation, forward current does not flow through the ESD diodes 41 and 42. That is, the ESD diodes 41 and 42 are not operating.

  On the other hand, during the active operation, when there is a possibility that the electrostatic charge is abnormally accumulated and discharged, a forward current flows through one of the ESD diodes 41 and 42. That is, when the electrostatic charge is discharged to the high potential side ESD ring 31 or the low potential side ESD ring 32, the source wiring 21, the gate wiring 22, and the pixel 10 are protected.

  In the present embodiment, the low-potential fixed diodes 43 are arranged corresponding to the gate wirings 22 in the first row and the second row. However, the present invention is not limited to this, and any two or more gate wirings 22 are arranged. It is sufficient that two or more are arranged corresponding to the above.

  Each of the ESD diodes 41 and 42 and the low potential fixed diode 43 is preferably composed of an n-type thin film transistor. In this case, the anode electrodes of the ESD diodes 41 and 42 and the low potential fixed diode 43 are electrodes in which the gate electrode and the drain electrode of the n-type thin film transistor are short-circuited, and the cathode electrode is the source of the n-type thin film transistor. An electrode may be used. Thereby, since all the thin film transistors which are the constituent elements of the active matrix substrate 1 including the selection transistor 101 and the drive transistor 102 of the pixel 10 can be made n-type, the manufacturing process can be simplified and the manufacturing yield can be improved.

  In the above configuration, the circuit operation during the writing operation to the display region constituted by the pixels 10 and the display region display operation, that is, the active operation will be described in detail.

  FIG. 3A is a diagram showing a circuit state in a normal active operation of the active matrix substrate according to Embodiment 1 of the present invention. In the figure, a normal state is assumed in which abnormal electrostatic charges are not accumulated in the source wiring 21 and the gate wiring 22 during the active operation.

In this case, the high potential side ESD ring 31 is set to _VTFT which is the potential of the power supply line 23. On the other hand, the low potential side ESD ring 32 is connected to the gate wirings 22 in the first and second rows via the low potential fixed diode 43. Here, since the selection transistor 101 which is a component of the pixel 10 is an n-type TFT, the selection transistor 101 is turned on when the potential of the gate wiring 22 is the high level potential V _H , and the gate wiring 22 Is in the off state when the potential of the transistor is at the low-level potential _VL . During the active operation, the potential of only one gate wiring 22 is always V _H in the row order, and the potentials of the other gate wirings 22 are _VL . That is, at least one of the gate wirings 22 in the first row and the second row to which the low potential fixed diode 43 is connected is always at the low level potential _VL . Therefore, the low potential side ESD ring 32, by the low potential side ESD ring 32 to the gate line 22 that is the potential _{V L} forward current flows to converge to the potential _{V L.} On the other hand, no current flows from the gate line 22 having the high-level potential V _H to the low-potential side ESD ring 32, so that no current flows, and the potential of the low-potential side ESD ring 32 is Does not vary with potential.

Note that the threshold voltage of the low-potential fixed diode 43 is set so that the threshold voltage of the ESD diode 42 is also small. When the negative electrostatic charge is abnormally accumulated in the gate wiring 22 or the source wiring 21, that is, the ESD diode 42 is connected to the low potential side ESD ring 32 whose potential is _VL . When the potential becomes much lower, a forward current is passed to discharge negative electrostatic charges to the low potential side ESD ring 32. Therefore, the threshold voltage is set large because the ESD diode 42 is in an operating state only when there is an abnormality. On the other hand, the low-potential fixed diode 43 is disposed in order to keep the potential of the low-potential side ESD ring 32 during active operation always at _VL . Therefore, since it is necessary to preferentially flow forward current from the low potential side ESD ring 32 to the gate wiring 22 having the potential _VL through the low potential fixed diode 43, the threshold value of the low potential fixed diode 43 is reduced. The voltage is set small.

  The threshold voltage of the ESD diode is a built-in voltage of the diode, and is a voltage at which a forward current is substantially generated (exponentially increases) in the current-voltage characteristic of the diode.

Also, the potential _{V TFT} of the power supply line 23, the potential _{V H} or _{V L} of the gate line 22, the height relationship between the potential _V DT ~V _L of the source wiring _is referred _{V TFT ≧ V H> V DT} > V L The relationship is established. Thereby, during the active operation, the potential of the high potential side ESD ring 31 is set to _VTFT , the potential of the low potential side ESD ring 32 is set to _VL, and the potentials of the gate line 22 and the source line 21 are set to 2 above. It is between the potentials of two ESD rings. Therefore, a forward current does not flow through the ESD diodes 41 and 42, that is, the ESD diodes 41 and 42 are in a non-operating state.

  FIG. 3B is a diagram showing a circuit state in the ESD protection operation of the active matrix substrate according to Embodiment 1 of the present invention. In the figure, it is assumed that abnormal electrostatic charges are accumulated in the source wiring 21 and the gate wiring 22 during the active operation.

For example, when a positive electrostatic charge to the gate terminal G1 and the first row of the gate line 22 is abnormal accumulation, greater than the first line of the potential V _TFT of the high potential side ESD ring 31 and the potential of the gate wiring 22 state It becomes. In this case, a forward current flows through the ESD diode 41. That is, the ESD diode 41 is in an operating state, and the positive electrostatic charge is discharged to the high potential side ESD ring 31, and the ESD protection function is activated.

For example, when negative electrostatic charges are abnormally accumulated in the gate terminal G2 and the gate wiring 22 in the second row, the potential of the gate wiring 22 in the second row is higher than the potential _VL of the low potential side ESD ring 32. It becomes a low state. In this case, a forward current flows through the ESD diode 42. That is, the ESD diode 42 is activated, and the negative electrostatic charge is discharged to the low potential side ESD ring 32, and the ESD protection function is activated.

As described above, according to the active matrix substrate 1 according to the present embodiment, during active operation, (1) the internal power supply (V _TFT ) of the pixel circuit composed of n-type TFTs is used to perform positive charge discharge. The ESD ring is fixed at a high potential, (2) the ESD ring for negative charge discharge is fixed at a low potential by two or more low-potential fixed diodes arranged corresponding to the gate wiring, and (3) the gate wiring and By arranging the ESD diodes connected in series corresponding to the source wiring, the electrostatic protection circuit during the active operation can be inactivated without controlling the potential of the ESD ring by the external power supply. Therefore, it is not necessary to provide an external power supply and a connection terminal separately, so that the configuration of the active matrix substrate and the display device including the active matrix substrate can be simplified.

(Embodiment 2)
In this embodiment, an active matrix substrate in the case where a pixel circuit is formed using a p-type TFT will be described with reference to the drawings. Note that description of the same components and functions as those of the active matrix substrate 1 according to Embodiment 1 is omitted, and only different characteristic points will be described in detail.

  FIG. 4 is a block diagram showing the configuration of the active matrix substrate according to Embodiment 2 of the present invention. The active matrix substrate 2 in the figure includes a plurality of pixels 11, source wirings 21 arranged for each pixel column, gate wirings 22 arranged for each pixel row, a high potential side ESD ring 31, and a low potential side. An ESD ring 32, ESD diodes 41 and 42, and a high potential fixed diode 53 are provided.

  Here, the configuration of the pixel 11 will be described in detail.

FIG. 5 is a diagram illustrating an example of a circuit configuration of a pixel according to the second embodiment. The pixels 11 shown in the figure are arranged in a matrix on the substrate, and include a selection transistor 111, a drive transistor 112, a capacitor 113, and an organic EL element 114. Here, the selection transistor 111 and the drive transistor 112 are p-type thin film transistors. The source electrode of the selection transistor 111 is connected to the source wiring 21, the gate electrode is connected to the gate wiring 22, and the drain electrode is connected to the capacitor 113 and the gate electrode of the driving transistor 112. The source electrode of the drive transistor 112 is connected to the power supply line 23 that supplies the power supply potential _VTFT , and the drain electrode is connected to the anode electrode of the organic EL element 114. The cathode electrode of the organic EL element 114 is connected to the reference potential line 24. The reference potential line 24 is a line that is set to a common reference potential across all the pixels 11, and the reference potential is, for example, a ground potential.

In this configuration, when a gate signal of a low level potential _VL , which is a pixel selection potential, is sequentially input to the gate wiring 22 and the selection transistor 111 is turned on, the data voltage V _DT supplied through the source wiring 21 is turned on. Is written into the capacitor 113. The holding voltage written in the capacitor 113 is held throughout one frame period, and the conductance of the driving transistor 112 changes in an analog manner by this holding voltage, and the driving current corresponding to the light emission gradation is changed from the power supply line 23 to the driving transistor. The current flows from 112 to the organic EL element 114 to the reference potential line 24. Thereby, the organic EL element 114 emits light and is displayed as an image.

  Note that the pixel 11 is not limited to the circuit configuration described above. In other words, the selection transistor 111, the drive transistor 112, and the capacitor 113 are circuit components necessary for flowing a drive current corresponding to the data voltage to the organic EL element 114, but other circuit components are included in the circuit component. The case where it is added is also included in the pixel 11 according to the present invention.

  Returning to FIG. 4 again, the configuration and function of the ESD protection circuit which is the main part of the present invention will be described.

  In the active matrix substrate 2 according to the second embodiment, a high potential side ESD ring 31 and a low potential side ESD ring 32 are disposed so as to surround a display region in which a plurality of pixels 11 are disposed. The low potential side ESD ring 32 is connected to the reference potential line 24.

  Further, ESD diodes 41 and 42 connected in series with each other are arranged for each of the gate wiring 22 and the source wiring 21. The connection relationship between the ESD diodes 41 and 42 is the same as that of the first embodiment.

  Further, a high-potential fixed diode 53 is arranged corresponding to the gate wiring 22 in the first row and the gate wiring 22 in the second row. The cathode electrode of the high potential fixed diode 53 is connected to the high potential side ESD ring 31, and the anode electrode is connected to the gate wiring 22.

  With the above configuration, during a normal active operation, the high potential fixing diode 53 has a function of fixing the high potential side ESD ring 31 to a high potential that is a pixel non-selection potential. Further, during normal active operation, forward current does not flow through the ESD diodes 41 and 42. That is, the ESD diodes 41 and 42 are not operating.

  On the other hand, during the active operation, when there is a possibility that the electrostatic charge is abnormally accumulated and discharged, a forward current flows through one of the ESD diodes 41 and 42. That is, the electrostatic charge is discharged to the high potential side ESD ring 31 or the low potential side ESD ring 32, thereby protecting the source wiring 21, the gate wiring 22, and the pixel 11.

  In the present embodiment, the high-potential fixed diodes 53 are arranged corresponding to the gate wirings 22 in the first row and the second row, but not limited to this, any two or more gate wirings 22 are arranged. It is sufficient that two or more are arranged corresponding to the above.

  Each of the ESD diodes 41 and 42 and the high potential fixed diode 53 is preferably composed of a p-type thin film transistor. In this case, the anode electrodes of the ESD diodes 41 and 42 and the high potential fixed diode 53 are the source electrodes of the p-type thin film transistor, and the cathode electrode is a short circuit between the gate electrode and the drain electrode of the p-type thin film transistor. An electrode may be used. Thereby, since all the thin film transistors which are the constituent elements of the active matrix substrate 2 including the selection transistor 111 and the drive transistor 112 of the pixel 11 can be made p-type, the manufacturing process can be simplified and the manufacturing yield can be improved.

  In the above configuration, a circuit operation at the time of an active operation of the display area configured by the pixels 11 will be described in detail.

  FIG. 6A is a diagram illustrating a circuit state in a normal active operation of the active matrix substrate according to Embodiment 2 of the present invention. In the figure, a normal state is assumed in which abnormal electrostatic charges are not accumulated in the source wiring 21 and the gate wiring 22 during the active operation.

In this case, the low potential side ESD ring 32 is set to V _EL which is the potential of the reference potential line 24. On the other hand, the high potential side ESD ring 31 is connected to the gate wirings 22 in the first and second rows via a high potential fixed diode 53. Here, since the selection transistor 111 which is a component of the pixel 11 is a p-type TFT, the selection transistor 111 is turned on when the potential of the gate wiring 22 is a low-level potential _VL , and the gate wiring 22 turned off when the potential of a high-level potential V _H. During the active operation, the potential of only one gate wiring 22 is always _VL in the row order, and the potentials of the other gate wirings 22 are V _H. That is, of the high-voltage clamp diode 53 1 is connected and second lines of the gate lines 22, and has a potential V _H of the always high levels of at least one one is. Therefore, the high potential side ESD ring 31 converges to the potential V _H when a forward current flows from the gate wiring 22 having the potential V _H to the low potential side ESD ring 32. On the other hand, the current does not flow from the gate line 22 having the low-level potential _VL to the high-potential side ESD ring 31 because it is in the reverse direction, and the potential of the high-potential side ESD ring 31 Does not vary with potential.

Note that the threshold voltage of the high-potential fixed diode 53 is set so that the threshold voltage of the ESD diode 41 is also small. In the ESD diode 41, when positive electrostatic charges are abnormally accumulated in the gate wiring 22 or the source wiring 21, that is, the high potential side ESD ring 31 whose potential is _VH , When the potential becomes much higher, a forward current is passed to discharge positive electrostatic charges to the high potential side ESD ring 31. Therefore, since the ESD diode 41 is in an operating state only at the time of abnormality, the threshold voltage is set large. On the other hand, the high-potential fixed diode 53 is arranged to always maintain the potential of the high-potential side ESD ring 31 during the active operation at _VH . Therefore, since it is necessary to preferentially flow a forward current from the gate wiring 22 having the potential V _H to the high potential side ESD ring 31 via the high potential fixed diode 53, the threshold value of the high potential fixed diode 53 is set. The voltage is set small.

The level relationship among the potential V _EL of the reference potential line 24, the potential V _L or V _{H of} the gate wiring 22, and the potentials V _{H to} V _DT of the source wiring is V _H > V _DT > V _L ≧ V _EL The relationship is established. Thus, during the active operation, the potential of the low potential side ESD ring 32 is set to V _EL , the potential of the high potential side ESD ring 31 is set to V _H, and the potentials of the gate wiring 22 and the source wiring 21 are 2 It is between the potentials of two ESD rings. Therefore, a forward current does not flow through the ESD diodes 41 and 42, that is, the ESD diodes 41 and 42 are in a non-operating state.

  FIG. 6B is a diagram illustrating a circuit state during an ESD protection operation of the active matrix substrate according to Embodiment 2 of the present invention. In the figure, it is assumed that abnormal electrostatic charges are accumulated in the source wiring 21 and the gate wiring 22 during the active operation.

For example, when positive electrostatic charges are abnormally accumulated in the gate terminal G1 and the gate wiring 22 in the first row, the potential of the gate wiring 22 in the first row is higher than the potential V _H of the high potential side ESD ring 31. It becomes. In this case, a forward current flows through the ESD diode 41. That is, the ESD diode 41 is in an operating state, and the positive electrostatic charge is discharged to the high potential side ESD ring 31, and the ESD protection function is activated.

For example, when negative electrostatic charges are abnormally accumulated in the gate terminal G2 and the gate wiring 22 in the second row, the potential of the gate wiring 22 in the second row is higher than the potential V _EL of the low potential side ESD ring 32. It becomes a low state. In this case, a forward current flows through the ESD diode 42. That is, the ESD diode 42 is activated, and the negative electrostatic charge is discharged to the low potential side ESD ring 32, and the ESD protection function is activated.

As described above, according to the active matrix substrate 2 according to the present embodiment, during the active operation, (1) the internal power supply (V _EL ) of the pixel circuit composed of the p-type TFT is used to discharge the negative charge. The ESD ring is fixed at a low potential, (2) the ESD ring for positive charge discharge is fixed at a high potential by two or more high-potential fixed diodes arranged corresponding to the gate wiring, and (3) the gate wiring and By arranging the ESD diodes connected in series corresponding to the source wiring, the electrostatic protection circuit during the active operation can be inactivated without controlling the potential of the ESD ring by the external power supply. Therefore, it is not necessary to provide an external power supply and a connection terminal separately, so that the configuration of the active matrix substrate and the display device including the active matrix substrate can be simplified.

  Although the first and second embodiments have been described above, the active matrix substrate according to the present invention is not limited to the above-described embodiments. Another embodiment realized by combining arbitrary constituent elements in the first and second embodiments, and various modifications conceivable by those skilled in the art without departing from the gist of the present invention. Modifications and various devices incorporating the active matrix substrate according to the present invention are also included in the present invention.

  For example, the active matrix substrate according to the present invention is built in a thin flat TV as shown in FIG. By incorporating the active matrix substrate according to the present invention, a thin flat TV that does not require the potential control of the ESD ring by an external power source is realized.

  The active matrix substrate of the present invention is particularly useful for an active organic EL flat panel display in which the luminance is varied by controlling the light emission intensity of the light emitting pixel by the pixel signal current corresponding to the display gradation.

1, 2 Active matrix substrate 10, 11, 510 Pixel 21, 501 Source wiring 22, 502 Gate wiring 23 Power supply line 24 Reference potential line 31 High potential side ESD ring 32 Low potential side ESD ring 41, 42 ESD diode 43 Low potential fixed Diode 53 High-potential fixed diode 101, 111, 511 Select transistor 102, 112 Drive transistor 103, 113 Capacitor 104, 114 Organic EL element 503, 504 Discharge ring 500 Electronic device 512 Pixel circuit 523, 524 Discharge device

Claims (10)

A substrate,
A plurality of gate wirings arranged on the substrate for selecting a pixel to which a data signal is written out of the plurality of pixels;
A plurality of source lines arranged on the substrate in a direction orthogonal to the plurality of gate lines and for writing the data signals to the selected pixels;
A first electrostatic discharge ring and a second electrostatic discharge ring disposed in a peripheral region on the substrate;
At least corresponding to each of the plurality of gate wirings or each of the plurality of source wirings, an anode electrode is connected to the first electrostatic discharge ring, and a cathode electrode is connected to the plurality of gate wirings and the plurality of sources. A current composed of a first diode connected to one of the wirings and a second diode having an anode electrode connected to the one wiring and a cathode electrode connected to the second electrostatic discharge ring. A restriction section;
Arranged corresponding to each of at least two of the plurality of gate lines, an anode electrode connected to the first electrostatic discharge ring, and a cathode electrode corresponding to one of the two gate lines. A third diode connected to the gate wiring to be
Active matrix substrate. The second electrostatic discharge ring is connected to a high-potential-side power line among power lines for supplying a power voltage to the plurality of pixels.
The active matrix substrate according to claim 1. Each of the first diode, the second diode, and the third diode is composed of an n-type thin film transistor,
The anode electrode of each of the first diode, the second diode, and the third diode is an electrode in which a gate electrode and a drain electrode of the n-type thin film transistor are short-circuited, and a cathode electrode is the n-type electrode A source electrode of a thin film transistor;
The active matrix substrate according to claim 1. The third diode has a lower built-in voltage than the first diode;
The active matrix substrate according to claim 1. The third diode fixes a potential of the gate wiring when the pixel is not selected to the first electrostatic discharge ring by flowing a forward current from the first electrostatic discharge ring to the one gate wiring. ,
The active matrix substrate according to claim 1. A substrate,
A plurality of gate wirings arranged on the substrate for selecting a pixel to which a data signal is written out of the plurality of pixels;
A plurality of source lines arranged on the substrate in a direction orthogonal to the plurality of gate lines and for writing the data signals to the selected pixels;
A first electrostatic discharge ring and a second electrostatic discharge ring disposed in a peripheral region on the substrate;
At least corresponding to each of the plurality of gate wirings or each of the plurality of source wirings, an anode electrode is connected to the first electrostatic discharge ring, and a cathode electrode is connected to the plurality of gate wirings and the plurality of sources. A current composed of a first diode connected to one of the wirings and a second diode having an anode electrode connected to the one wiring and a cathode electrode connected to the second electrostatic discharge ring. A restriction section;
The plurality of gate wirings are arranged corresponding to each of at least two gate wirings, the anode electrode is connected to the corresponding gate wiring of the two gate wirings, and the cathode electrode is connected to the second gate wiring. A third diode connected to the electrostatic discharge ring;
Active matrix substrate. The first electrostatic discharge ring is connected to a low-potential-side power line among power lines for supplying a power voltage to the plurality of pixels.
The active matrix substrate according to claim 6. Each of the first diode, the second diode, and the third diode is composed of a p-type thin film transistor,
The anode electrode of each of the first diode, the second diode, and the third diode is a source electrode of the p-type thin film transistor, and the cathode electrode includes a gate electrode and a drain electrode of the p-type thin film transistor. A shorted electrode,
The active matrix substrate according to claim 6. The third diode has a lower built-in voltage than the second diode;
The active matrix substrate according to claim 6. The third diode fixes a potential of the gate wiring when the pixel is not selected to the second electrostatic discharge ring by flowing a forward current from the one gate wiring to the second electrostatic discharge ring. ,
The active matrix substrate according to claim 6.

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