JP2013070156A - Comparator system, analog-digital converter, and method for correcting threshold of comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparator system that corrects a deviation of a threshold.SOLUTION: A comparator has a pair of input nodes for receiving input signals from input terminals via a pair of capacitors, and an output node for outputting an output signal indicating a voltage difference between the input signals. A first control circuit, in a correction period for correcting a threshold of the comparator, changes a common voltage set at the pair of input nodes until the logic of the output signal inverts while a predetermined amount of load is connected to the output node and determines the value of the common voltage when the logic of the output signal inverts, and in a normal operation period following the correction period, uses the determined common voltage. A second control circuit sets the amount of load connected to the output node. A third control circuit, in the correction period, supplies the input terminals with respective first and second voltages having a voltage difference corresponding to a variation in a standard threshold of the comparator with the predetermined amount of load connected to the output node.

Description

  The present invention relates to a comparator system having a comparator, an analog-digital converter having a comparator system, and a threshold correction method for the comparator.

  A comparator mounted on an analog-digital converter or the like receives a pair of input signals at an input terminal and outputs a signal indicating a voltage difference between the input signals from an output terminal. For example, it has been proposed to connect a variable capacitance circuit to the output node in order to adjust the offset voltage (see, for example, Patent Document 1). In addition, a method of dynamically changing the offset voltage according to the voltage of the input signal has been proposed (see, for example, Patent Document 2).

JP 2010-213042 A JP-A-8-116243

  When the electrical characteristics of the comparator change due to fluctuations in manufacturing conditions such as transistors formed in the comparator or due to temperature fluctuations, the offset voltage, which is the voltage difference of the input signal when the logic of the output signal is inverted, and the comparator threshold are Deviation from the standard value. In particular, in a comparator system in which the threshold value can be changed according to the amount of load connected to the output node, a method for correcting a shift in the threshold value due to a change in manufacturing conditions has not been proposed.

  An object of the present invention is to provide a comparator system capable of correcting a threshold shift.

  In one embodiment of the present invention, a comparator system includes a pair of capacitors connected to a pair of input terminals each receiving an input signal, a pair of input nodes receiving an input signal via the capacitor, and an output indicating a voltage difference between the input signals. At least one comparator having an output node for outputting a signal; a first control circuit for setting a common voltage at a pair of input nodes; a second control circuit for setting an amount of a load connected to the output node; and a comparator The first voltage and the second voltage having a voltage difference corresponding to the amount of fluctuation of the threshold when a predetermined amount of load is connected to the output node of the reference comparator in the correction period for correcting the threshold of A third control circuit for supplying the output signal, and the first control circuit outputs the output signal while a predetermined amount of load is connected to the output node during the correction period. Logical changes the common voltage to be inverted and used for normal operation period after the correction period common voltage when the logic of the output signal is inverted.

  In the comparator system in which the threshold value can be changed according to the amount of load connected to the output node, it is possible to correct the shift in the threshold value due to variations in manufacturing conditions.

2 illustrates an example of a comparator system in one embodiment. 6 illustrates an example of a comparator system in another embodiment. 6 illustrates an example of a comparator system in another embodiment. 4 shows an example of the comparator shown in FIG. 5 shows an example of the operation of the comparator shown in FIG. In the comparator shown in FIG. 4, an example of the relationship between the amount of load connected to the output node and the amount of fluctuation of the threshold is shown. In the comparator shown in FIG. 4, the example of the relationship between a common voltage and the variation amount of a threshold value is shown. In the comparator shown in FIG. 4, another example of the relationship between the common voltage and the threshold fluctuation amount is shown. 4 shows an example of the operation of the comparator system shown in FIG. 10 shows an example of the operation in step S100 shown in FIG. 10 shows an example of operation waveforms of the comparator system that executes step S100 shown in FIG. 10 shows an example of the operation in step S200 shown in FIG. 10 illustrates an example of operation waveforms of the comparator system that executes Step S200 illustrated in FIG. 9. 10 shows another example of operation waveforms of the comparator system that executes Step S200 shown in FIG. 4 shows an example of an analog-digital converter to which the comparator system shown in FIG. 3 is applied. 16 shows an example of setting a threshold value during normal operation of the comparator shown in FIG. 16 shows an example of the operation of the analog-digital converter shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals as the signal names are used for signal lines through which signals are transmitted.

  FIG. 1 shows an example of a comparator system CSYS in one embodiment. The comparator system CSYS includes a comparator COMPa, capacitors CPa and CNa, and control circuits CNT1, CNT2, and CNT3.

  The input node VIPa on the “+” side of the comparator COMPa is connected to an input terminal VIP that receives an input signal VIP through a capacitor CPa. The input node VINa on the “−” side of the comparator COMPa is connected to an input terminal VIN that receives an input signal VIN via a capacitor CNa. The output node OPa of the comparator COMPa is connected to the output terminal OUTa and outputs an output signal OUTa indicating the voltage difference between the input signals VIP and VIN.

  The control circuit CNT1 sets the common voltage VCMa at the input nodes VIPa and VINa. DC components of the input signals VIP and VIN are not transmitted to the input nodes VIPa and VINa by the capacitors CPa and CNa. Thereby, the input nodes VIPa and VINa can be initialized to an arbitrary common voltage VCMa using the control circuit CNT1. In other words, the voltages of the input signals VIP and VIN can be shifted to an input voltage range in which the comparator COMPa operates normally. Note that the control circuit CNT1 may be disposed outside the comparator system CSYS (for example, outside the chip on which the comparator system CSYS is mounted).

  The control circuit CNT2 sets the amount of load connected to the output node OPa. In this embodiment, the threshold value of the comparator COMPa is switched according to the amount of load connected to the output node OPa. The threshold value is a difference VIP-VIN between the input voltages VIP and VIN when the logic of the output node OPa changes from logic 0 to logic 1 or from logic 1 to logic 0. Here, a logic 1 indicates a high-side voltage (high level), and a logic 0 indicates a low-side voltage (low level). Note that the control circuit CNT2 may be formed inside the comparator COMPa.

  When the threshold is set to zero by the control circuit CNT2, the comparator COMPa outputs a logic 0 to the output node OPa when the input voltage VIP is higher than the input voltage VIN, and when the input voltage VIP is lower than the input voltage VIN. A logic 1 is output to the output node OPa. For example, when the threshold value is set to +100 mV by the control circuit CNT2, the output signal OUTa becomes logic 0 when the difference “VIP−VIN” between the input voltage VIP and the input voltage VIN is higher than 100 mV, and the voltage difference “VIP− Logic 1 when VIN ″ is below 100 mV. When the threshold value is set to −100 mV by the control circuit CNT2, the output signal OUTa becomes logic 0 when the voltage difference “VIP−VIN” is −100 mV or more (for example, −80 mV or +20 mV), and the voltage difference “ When VIP-VIN "is lower than -100 mV (for example, -110 mV), it becomes logic 1.

  The control circuit CNT3 supplies voltages VP and VN having a predetermined voltage difference to the input terminals VIP and VIN, respectively, during a correction period for correcting the threshold value of the comparator COMPa. The voltages VP and VN may be generated using a signal generation circuit that generates the input signals VIP and VIN during the normal operation period. The correction period is set before the normal operation period in which the comparator COMPa performs the comparison operation of the voltages of the input signals VIP and VIN.

  The predetermined voltage difference between the voltages VP and VN corresponds to the amount of change in the threshold value of the reference comparator when a predetermined amount of load is connected to the output node of the reference comparator. For example, the reference comparator is the same circuit as the comparator COMPa and is another comparator formed in the comparator system CSYS. Alternatively, the reference comparator is a comparator having a standard electrical characteristic. The electrical characteristics (threshold voltage and the like) of the transistor formed in the standard comparator indicate a standard value (Typical), for example. In this case, the fluctuation amount of the threshold value of the standard comparator may be obtained in advance at the time of designing or manufacturing the comparator system CSYS.

  For example, when the threshold value of the reference comparator changes by 100 mV before and after connecting a predetermined amount of load to the output node of the reference comparator, the control circuit CNT3 controls the voltages VP and VN having a voltage difference of 100 mV. Is output to the input terminals VIP and VIN. As a result, the variation amount of the threshold value that changes due to the connection of a predetermined amount of load can be canceled by the voltages VP and VN having a predetermined voltage difference. In other words, a predetermined amount of load is connected to the output node OPa, voltages VP and VN having a predetermined voltage difference are supplied to the input terminals VIP and VIN, and the logic of the output signal OUTa is monitored by changing the common voltage VCMa. By doing so, it is possible to detect a shift in threshold value between the comparator COMP and the reference comparator.

  During the correction period, the control circuit CNT1 gradually changes the common voltage VCMa until the logic of the output signal OUTa is inverted while a predetermined amount of load is connected to the output node OPa. The control circuit CNT1 detects the difference between the common voltage VCMa and the reference common voltage when the logic of the output signal OUTa is inverted as a threshold deviation between the comparator COMP and the reference comparator. In other words, the threshold shift is canceled by the common voltage VCMa when the logic of the output signal OUTa is inverted, and the threshold is corrected to the same value as the threshold of the reference comparator. The control circuit CNT1 uses the common voltage VCMa when the logic of the output signal OUTa is inverted in the normal operation period after the correction period.

  The threshold value varies according to variations in electrical characteristics of elements such as transistors and resistors that form the comparator COMPa. The electrical characteristics of the element vary due to variations in manufacturing conditions in the manufacturing process of the comparator system CSYS. Even when the comparator system CSYS has a plurality of comparators COMPa, the threshold values of the comparators COMPa may be shifted from each other.

  When the logic of the output signal OUTa is not inverted even when the common voltage VCMa is changed within a predetermined range, the control circuit CNT1 determines that the threshold value of the comparator COMPa is equal to the threshold value of the reference comparator, and the reference common voltage VCMa. Are used during normal operation. For example, the reference common voltage VCMa is a common voltage used at the time of evaluating the fluctuation amount of the threshold value of the reference comparator.

  As described above, in this embodiment, in the comparator system CSYS in which the threshold value can be changed according to the amount of the load connected to the output node OPa, the value of the common voltage VCMa is adjusted by the control circuit CNT1, thereby The deviation can be corrected according to the threshold value of the reference comparator. As a result, it is possible to provide a comparator system CSYS that can compare the difference between the input voltages VIP and VIN with high accuracy.

  FIG. 2 shows an example of a comparator system CSYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The comparator system CSYS of this embodiment includes a comparator COMP (COMPa, COMPb), control circuits CNT1, CNT2, and CNT3 and capacitors CPa, CNa, CPb, and CNb.

  The comparators COMPa and COMPb are the same circuits as each other, for example, the same circuit as the comparator COMPa in FIG. The input node VIPb of the comparator COMPb is connected to the input terminal VIP via the capacitor CPb. The input node VINb of the comparator COMPb is connected to the input terminal VIN via the capacitor CNb. The output node OPb of the comparator COMPb is connected to the output terminal OUTb, and outputs an output signal OUTb indicating the voltage difference between the input signals VIP and VIN. The operations of the comparators COMPa and COMPb are the same as the operations of the comparator COMPa in FIG.

  In this embodiment, one threshold value of the comparators COMPA and COMPb is obtained in the detection period before the correction period as the amount of change in the threshold value, and the other threshold value of the comparators COMPA and COMPb is the same as the threshold value obtained in the detection period. It is corrected to the value. In the following description, an example will be described in which the threshold fluctuation amount of the comparator COMPa (reference comparator) is obtained during the detection period, and the threshold value of the comparator COMPb excluding the reference comparator is corrected during the correction period.

  The control circuit CNT1 adds a function of setting the common voltage VCMb to the input nodes VIPb and VINb in the control circuit CNT1 of FIG. Note that the control circuit CNT1 may be disposed outside the comparator system CSYS (for example, outside the chip on which the comparator system CSYS is mounted). The control circuit CNT2 adds a function of setting the amount of load connected to the output node OPb of the comparator COMPb to the control circuit CNT2 of FIG.

  During the detection period, the control circuit CNT3 gradually changes the voltage difference between the voltages VP and VN while a predetermined amount of load is connected to the output node OPa of the comparator COMMPa. Then, the control circuit CNT3 determines the voltage difference between the voltages VP and VN when the logic of the output signal OUTa of the comparator COMPa is inverted, when the predetermined amount of load is connected to the output node OPa of the comparator COMA by the control circuit CNT2. It is detected as a threshold fluctuation amount.

  In the correction period, the control circuit CNT3 supplies voltages VP and VN having a voltage difference detected in the detection period to the input terminals VIP and VIN, respectively. In the detection period and the correction period, the voltages VP and VN may be generated using a signal generation circuit that generates the input signals VIP and VIN during the normal operation period. The control circuit CNT2 connects the same amount of load as that connected to the output node OPa of the comparator COMPa during the detection period to the output node OPb of the comparator COMPb.

  Then, similarly to the operation of FIG. 1, the control circuit 1 gradually changes the common voltage VCMb until the logic of the output signal OUTb is inverted with a predetermined amount of load connected to the output node OPb. The control circuit CNT1 detects the difference between the common voltage VCMb when the logic of the output signal OUTb is inverted and the reference common voltage used in the detection period as a threshold deviation between the comparator COMPb and the reference comparator COMPa. In other words, the shift of the threshold values of the comparators COMPA and COMPb is canceled by the common voltage VCMb when the logic of the output signal OUTb is inverted, and the threshold values are set to the same value. In the normal operation period after the correction period, the control circuit CNT1 sets the common voltage VCMb obtained in the correction period to the input nodes VIPb and VINb of the comparator COMPb, and sets the reference common voltage as the common voltage VCMa to the input node VIPa of the comparator COMPa. , Used for VINa.

  As with the comparator system CSYS in FIG. 1, the control circuit CNT3 has a threshold fluctuation amount (preliminarily obtained when a predetermined amount of load is connected to a reference comparator other than the comparators COMPA and COMPb of the comparator system CSYS. The voltages VP and VN having a voltage difference corresponding to the above may be generated. In this case, the above-described detection period is not necessary, and in the correction period, the threshold values of the comparators COMPA and COMPb are matched with the threshold values of the reference comparator.

  Although the example in which the comparator system CSYS has two comparators COMP (COMPa, COMPb) has been described in FIG. 2, the comparator system CSYS may include three or more comparators COMP. In this case, one of the comparators COMP is treated as a reference comparator, and the threshold value of the comparator COMP excluding the reference comparator is adjusted to the threshold value of the reference comparator.

  For example, a 2-bit flash type analog-digital converter can be formed by three comparators COMP, and a 4-bit flash type analog-digital converter can be formed by 15 comparators COMP. In the flash type analog-digital converter, the threshold values of the plurality of comparators COMP are set to different values by the control circuit CNT2, and the digital value indicating the voltage difference between the input signals VIP and VIN according to the logic of the output signal of each comparator COMP Is generated.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in the comparator system CSYS in which the threshold values can be changed according to the amounts of loads connected to the output nodes OPa and OPb of the plurality of comparators COMPA and COMPb, the threshold values of the comparators COMPA and COMPb can be adjusted to each other.

  FIG. 3 shows an example of a comparator system CSYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The comparator system CSYS of this embodiment includes a comparator COMP (COMPa, COMPb, COMPc), an input voltage generation circuit VIGEN, a common voltage generation circuit VCMGEN, capacitors CPa, CNa, CPb, CNb, CPc, CNc, switch circuits SW1, SW2, It has SW3 and control circuit CNT. The comparators COMPA, COMPb, COMPc are the same circuit, and the operations of the comparators COMPA, COMPb, COMPc are the same as those of the comparator COMPa in FIG.

  Each comparator COMP includes a function of connecting a predetermined amount of load to the output nodes OP (OPa, OPb, OPc), ON (ONa, ONb, ONc). That is, each comparator COMP includes a part of the function of the control circuit CNT2 shown in FIGS. Each comparator COMP includes a function of connecting a predetermined amount of load, operates in synchronization with the clock CLK, and differential output nodes OP (OPa, OPb, OPc), ON (ONa, ONb, The circuit is similar to the comparator COMPa shown in FIG. 1 and the comparator COMPb shown in FIG. 2 except that it has ONc).

  The input node VIPc of the comparator COMPc is connected to the input terminal VIP via the capacitor CPc. The input node VINc of the comparator COMPc is connected to the input terminal VIN via the capacitor CNc. The output nodes OP and ON of each comparator COMP output complementary output signals indicating the voltage difference between the input signals VIP and VIN according to the set threshold value.

  The input voltage generation circuit VIGEN includes a part of the function of the control circuit CNT3 shown in FIG. The input voltage generation circuit VIGEN generates voltages VP and VN according to the value of the control signal VCNT set in the register REG of the control circuit CNT. The voltages VP and VN may be generated using a signal generation circuit that generates the input signals VIP and VIN during the normal operation period without forming the input voltage generation circuit VIGEN.

  The common voltage generation circuit VCMGEN generates the common voltage VCMa set to the input nodes VIPa and VINa according to the value of the control signal CNT1a, and sets the common voltage VCMb set to the input nodes VIPb and VINb to the value of the control signal CNT1b. Generate accordingly. The common voltage generation circuit VCMGEN generates the common voltage VCMc set to the input nodes VIPc and VINc according to the value of the control signal CNT1c. For example, the common voltage generation circuit VCMGEN is formed using a resistance type digital analog converter or a capacitance type digital analog converter. The common voltage generation circuit VCMGEN may be disposed outside the comparator system CSYS (for example, outside the chip on which the comparator system CSYS is mounted).

  The control circuit CNT includes control signals VCNT, CNT1a, CNT1b, CNT1c, control signals CPa (CPa1-CPa16), CNa (CNa1-CNa16), CPb (CPb1-CPb16), CNb (CNb1-CNb16), CPc (CPc1-CPc16). ), A register REG for holding a value to be output as CNc (CNc1-CNc16). The control signals CPa and CNa control the operation of the load generation circuit formed in the comparator COMPa. The control signals CPb and CNb control the operation of the load generation circuit formed in the comparator COMPb. The control signals CPc and CNc control the operation of the load generation circuit formed in the comparator COMPc. The control circuit CNT has a function of outputting switch control signals SCNT1, SCNT2, and SCNT3.

  The switch circuit SW1 includes switches that connect the input terminal VIP to nodes VIP0a, VIP0b, and VIP0c, which are one ends of the capacitors CPa, CPb, and CPc, respectively. Further, the switch circuit SW1 includes switches that connect the input terminal VIN to nodes VIN0a, VIN0b, and VIN0c, which are one ends of the capacitors CNa, CNb, and CNc, respectively. Each switch of the switch circuit SW1 is formed by, for example, a CMOS transmission gate, and is turned on or off by a switch control signal SCNT1 generated by the control circuit CNT.

  The switch circuit SW2 includes switches that connect the nodes VIP0a, VIN0a, VIP0b, VIN0b, VIP0c, and VIN0c to the ground line VSS, respectively. Each switch of the switch circuit SW2 is formed by an nMOS transistor, for example, and is turned on or off by a switch control signal SCNT2 generated by the control circuit CNT.

  The switch circuit SW3 is a switch that connects the input nodes VIPa and VINa to the common voltage line VCMa, a switch that connects the input nodes VIPb and VINb to the common voltage line VCBM, and a switch that connects the input nodes VIPc and VINc to the common voltage line VCCM. have. Each switch of the switch circuit SW3 is formed by, for example, a CMOS transmission gate, and is turned on or off by a switch control signal SCNT3 generated by the control circuit CNT. For example, the control circuit CNT generates the switch control signals SCNT1, SCNT2, and SCNT3 in synchronization with the clock CLK.

  The control circuit CNT, the common voltage generation circuit VCMGEN, and the switch circuit SW3 are examples of a first control circuit that sets a common voltage (VCMa, etc.) to a pair of input nodes (VIPa, VINa, etc.) of the comparator COMP. The control circuit CNT, the input voltage generation circuit VIGEN, and the switch circuit SW1 are examples of a third control circuit that supplies the voltages VP and VN to the input terminals VIP and VIN, respectively.

  FIG. 4 shows an example of the comparator COMPa shown in FIG. The comparators COMPb and COMPc are the same as the comparator COMPa except that “a” in the reference numeral shown in FIG. 4 is changed to “b” or “c”.

  The comparator COMPa includes pMOS transistors P1 and P2, nMOS transistors N1, N2, N3 and N4, switch circuits SW4 and SW5, and load generation circuits LDGEN-Pa and LDGEN-Na. The pMOS transistor P1 and the nMOS transistors N1 and N3 are connected in series between the power supply line VDD and the node SS. The pMOS transistor P2 and the nMOS transistors N2 and N4 are connected in series between the power supply line VDD and the node SS.

  The pMOS transistors P1 and P2 and the nMOS transistors N1 and N2 form a latch circuit in which one input is connected to the other output. The drains of pMOS transistor P1 and nMOS transistor N1 and the gates of pMOS transistor P2 and nMOS transistor N2 are connected to output node OPa. The drains of pMOS transistor P2 and nMOS transistor N2 and the gates of pMOS transistor P1 and nMOS transistor N1 are connected to output node OPb. The nMOS transistor N3 has a gate connected to the input node VIPa and a drain connected to the source of the nMOS transistor N1 via the node DP. The nMOS transistor N4 has a gate connected to the input node VINa and a drain connected to the source of the nMOS transistor N2 via the node DN.

  The switch circuit SW4 has a switch that is turned on during the high level period of the clock CLK, connects the node SS to the ground line VSS, and is turned off during the low level period of the clock CLK. For example, the switch circuit SW4 is formed of an nMOS transistor that receives a clock CLK at its gate. The switch circuit SW5 has switches that connect the power supply line VDD to the output nodes OPa and ONa and the nodes DP and DN, respectively. For example, each switch of the switch circuit SW5 is formed of a pMOS transistor that receives the clock CLK at the gate, and is turned on during the low level period of the clock CLK and turned off during the high level period of the clock CLK.

  The load generation circuit LDGEN-Pa includes 16 capacitors CP connected to the output node OPa, and 16 switches SP (SP1, SP2,..., Arranged between the capacitors CP and the ground line VSS. SP16). Each switch SP is formed of, for example, an nMOS transistor that receives a control signal CPa (CPa1, CPa2,..., CPa16) at its gate. Each switch SP is turned on when the corresponding control signal CPa is logic 1, and turned off when the corresponding control signal CPa is logic 0. The capacitance values of the capacitors CP are designed to be the same. The load generation circuit LDGEN-Pa changes the amount of load connected to the output node OPa according to the number of control signals CPa set to logic 1.

  The load generation circuit LDGEN-Na includes 16 capacitors CN connected to the output node ONa, and 16 switches SN (SN1, SN2,..., Arranged between each capacitor CN and the ground line VSS. SN16). Each switch SN is formed by, for example, an nMOS transistor that receives a control signal CNa (CNa1, CNa2,..., CNa16) at its gate. Each switch SN is turned on when the corresponding control signal CNa is logic 1, and turned off when the corresponding control signal CNa is logic 0. The capacitance value of the capacitor CN is designed to be the same as each other, and is the same as the capacitance value of the capacitor CP. The load generation circuit LDGEN-Na changes the amount of load connected to the output node ONa according to the number of control signals CNa of logic 1.

  The control circuit CNT illustrated in FIG. 3 and the load generation circuits LDGEN-Pa and LDGEN-Na illustrated in FIG. 4 are examples of a second control circuit that sets the amount of load connected to the output node of each comparator COMP. . Note that the load generation circuits LDGEN-Pa and LDGEN-Na may be connected to the nodes DP and DN, respectively. Alternatively, the load generation circuits LDGEN-Pa and LDGEN-Na may be formed outside each comparator COMP.

  Further, the number of switches SP and the number of switches SN are not limited to 16. For example, the capacitance values of the capacitors CP and CN may be halved, the number of capacitors CP and CN may be doubled, and the number of switches SP and SN may be doubled. In the load generation circuit LDGEN-Pa, each capacitor CP may be arranged between the switch SP and the ground line VSS. In the load generation circuit LDGEN-Na, each capacitor CN may be disposed between the switch SN and the ground line VSS.

  Further, the load generation circuit LDGEN-Pa may be provided with a current source instead of the capacitor CP, and the inverted logic of the control signal CPa may be received by the switches SP1 to SP16. Also in this case, the amount of load connected to the output node ONa can be changed according to the control signal CPa. Similarly, in the load generation circuit LDGEN-Na, a current source may be arranged instead of the capacitor CN, and the inverted logic of the control signal CNa may be received by the switches SN1 to SN16.

  FIG. 5 shows an example of the operation of the comparator COMPa shown in FIG. The operations of the comparators COMPb and COMPc are represented by replacing the codes OPa and ONa in FIG. 5 with the codes OPb and ONb or the codes OPc and ONc. When the input voltage VIP is higher than the input voltage VIN (in the direction of the sign + in FIG. 5), the comparator COMPa outputs a logic 0 to the output node OPa and outputs a logic 1 to the output node ONa. When the input voltage VIP is lower than the input voltage VIN (in the direction of the sign-in FIG. 5), the comparator COMPa outputs a logic 1 to the output node OPa and outputs a logic 0 to the output node ONa.

  FIG. 6 shows an example of the relationship between the amount of load connected to the output nodes OPa and ONa and the variation amount of the threshold in the comparator COMPa shown in FIG. FIG. 6 shows an example of characteristics when the common voltage VCMa is set to 600 mV. The characteristics of the comparators COMPb and COMPc are the same as in FIG.

  In FIG. 6, the comparator COMPa showing the electric characteristic “fast” has a larger operating current than the comparator COMA showing the electric characteristic “typ”. The comparator COMA which shows the electrical characteristic of “slow” has a smaller operating current than the comparator COMa which shows the electrical characteristic of “typ”. For example, “fast” is a characteristic when the threshold voltage (absolute value) of the pMOS transistor and the threshold voltage of the nMOS transistor in the comparator COMPa are relatively low, or a characteristic when the operating temperature is relatively low. “Slow” is a characteristic when the pMOS transistor threshold voltage (absolute value) and the threshold voltage of the nMOS transistor in the comparator COMPa are relatively high, or a characteristic when the operating temperature is relatively high.

  In this embodiment, all switches SN1-SN16 are turned off when at least one of the switches SP1-SP16 is turned on. When at least one of the switches SN1-SN16 is turned on, all the switches SP1-SP16 are turned off. In FIG. 6, the number of ON of the switches SN1 to SN16 is indicated by a negative value.

  As the number of switches SP1-SP16 turned on increases and the amount of load connected to the output node OPa increases, the threshold value of the comparator COMPa increases. On the other hand, when the number of switches SN1-SN16 to be turned on increases and the amount of load connected to the output node ONa increases, the threshold value of the comparator COMPa decreases and shows a negative value.

  In the “fast” characteristic, the amount of change in the threshold accompanying the change in the number of switches SP and SN that are turned on is larger than the amount of change in the threshold at “typ”. On the other hand, in the “slow” characteristic, the amount of variation in the threshold accompanying the change in the number of switches SP and SN that are turned on is smaller than the amount of variation in the threshold at “typ”. In this embodiment, for example, when the electrical characteristics such as the operating currents of the comparators COMPA, COMPb, and COMPc vary and the threshold values are different from each other, in order to match the threshold values of the comparators COMPA and COMPc with the threshold values of the comparator COMPb, FIG. The common voltages VCMb and VCMc shown are adjusted.

  FIG. 7 shows an example of the relationship between the common voltage VCMa and the threshold fluctuation amount in the comparator COMPa shown in FIG. In FIG. 7, the symbol of the common voltage VCMa is expressed as “Vcm”. The characteristics of the comparators COMPb and COMPc are the same as in FIG.

  The rhombic symbols in FIG. 7 indicate the characteristics when the common voltage VCMa is set to 600 mV in the comparator COMPa indicating the “typ” characteristics, as in FIG. 6. Symbols other than the rhombus indicate the characteristics when the common voltage VCMa is changed in the comparator COMMPa having the characteristics “fast”.

  The threshold value of the comparator COMPa is lowered by lowering the common voltage VCMa and is raised by raising the common voltage VCMa. For example, the threshold value of the comparator COMPA having the characteristic “fast” is set to the threshold value of the comparator COMPA having the characteristic “typ” by setting the common voltage VCM to 545 mV, which is lower than the reference value (600 mV).

  FIG. 8 shows another example of the relationship between the common voltage VCMa and the threshold fluctuation amount in the comparator COMPa shown in FIG. In FIG. 8, the code of the common voltage VCMa is represented as “Vcm”. The characteristics of the comparators COMPb and COMPc are the same as those in FIG.

  The rhombic symbols in FIG. 8 indicate the characteristics when the common voltage VCMa is set to 600 mV in the comparator COMPa whose characteristics are “typ”, as in FIG. 6. Symbols other than the rhombus indicate characteristics when the common voltage VCMa is changed in the comparator COMPA whose characteristics are “slow”.

  Similar to FIG. 7, the threshold value of the comparator COMPa is lowered by lowering the common voltage VCMa and is raised by raising the common voltage VCMa. For example, the threshold value of the comparator COMPA having the characteristic “slow” is set to the threshold value of the comparator COMPA having the characteristic “typ” by setting the common voltage VCMa to 665 mV, which is higher than the reference value (600 mV).

  FIG. 9 shows an example of the operation of the comparator system CSYS shown in FIG. For example, the comparator system CSYS shifts to the normal operation period after an initialization period including a detection period and a correction period after power-on. Steps S100 to S300 shown in FIG. 9 are divisions for convenience to make the explanation easy to understand. In practice, the operation shown in FIG. 9 is continuously performed by the circuit of the comparator system CSYS. Note that the initialization period may be performed, for example, when the temperature changes during the normal operation period, or may be performed at a predetermined frequency during the normal operation period.

  Step S100 is performed during the detection period. In step S100, a threshold fluctuation amount when a predetermined amount of load is connected to the output node OPb is detected for one of the plurality of comparators COMP (for example, the comparator COMPb as a reference). Specific examples of step S100 are shown in FIGS.

  Step S200 is performed during the correction period. In step S200, the common voltage VCM (eg, VCMa, VCCMc) is obtained in order to match the threshold value of the comparators (eg, comparators COMPA, COMPc) excluding the reference comparator used in the detection period to the threshold value of the comparator COMPb. Specific examples of step S200 are shown in FIGS.

  In step S300, a threshold value is set using the load generation circuit LDGEN (LDGEN-Pa, LDGEN-Na, etc.) of each comparator COMPa, COMPb, COMPc. For example, in the comparator system CSYS built in the flash type analog-digital converter, the threshold values of the comparators COMPA, COMPb, COMPc are set to different values.

  Thereafter, the comparator system CSYS shifts to a normal operation period, and in step S400, the comparators COMPA, COMPb, COMPc are used to compare the voltages of the input signals VIP, VIN.

  FIG. 10 shows an example of the operation of step S100 shown in FIG. In FIG. 10, the description of the operation of the switch circuits SW1, SW2, and SW3 shown in FIG. 3 is omitted to simplify the description. The operation of the switch circuits SW1, SW2, and SW3 will be described with reference to FIG.

  First, in step S102, the control circuit CNT shown in FIG. 3 outputs the control signal CNT1b to the common voltage generating circuit VCMGEN, and sets the common voltage VCMb set to the input nodes VIPb and VINb of the comparator COMPb to the value V1. The voltage value V1 is a reference common voltage (for example, 600 mV) for correctly determining the voltage difference between the input nodes VIPb and VINb, and is determined in advance according to the electrical characteristics of the comparators COMPA, COMPb, and COMPc.

  In step S104, the control circuit CNT sets the control signals CPb1-CPb16 to logic 1, and sets the control signals CNb1-CNb16 to logic 0. Thereby, in the comparator COMPb, all the switches CP (FIG. 4) of the load generation circuit LDGEN-Pb are turned on, and all the switches CN (FIG. 4) of the load generation circuit LDGEN-Nb are turned off.

  The comparator COMPb is in a state where the maximum load that can be connected to the output node OPb is connected, and the threshold value is shifted to the positive side as shown in FIG. For example, when the electrical characteristic of the comparator COMPb is “typ”, the threshold fluctuation amount is +160 mV. In this state, the output node OPb becomes logic 0 when the voltage difference (VIPb−VINb) between the input nodes VIPb and VINb is 160 mV or more, and becomes logic 1 when the voltage difference is smaller than 160 mV.

  The control circuit CNT outputs a control signal VCNT in order to make the voltages VP and VN generated by the input voltage generation circuit VIGEN equal to each other. As a result, the voltages of the input nodes VIPb and VINb become equal to each other, and the output node OPb becomes logic 1.

  Next, in step S106, the control circuit CNT changes the value of the control signal VCNT in order to increase the voltage VP by one step and decrease the voltage VN by one step. For example, one step is 5 mV. In step S108, the control circuit CNT determines whether or not the output node OPb has changed to logic zero.

  When the output node OPb is held at logic 1, the control circuit CNT determines that the difference between the voltages VP and VN has not reached the threshold fluctuation amount due to the load connected to the output node OPb, and proceeds to step S106. Return. In the control circuit CNT, when the output node OPb changes to logic 0, the difference VP−VN between the voltages VP and VN becomes equal to the threshold fluctuation amount (160 mV in this example) due to the load connected to the output node OPb. The process proceeds to step S110.

  In step S110, the values of the current voltages VP and VN and the number of switches CP that are turned on are held in the register REG. For example, the values of the voltages VP and VN and the number of the switches CP that are turned on are held in the register REG as the value of the control signal VCNT and the values of the control signals CPb1 to CPb16. The difference between the voltages VP and VN held in the register REG is a value for canceling out the amount of change in the threshold that changes depending on the connection of the load. When the number of switches CP to be turned on and the values of the voltages VP and VN are set using the values set in the register REG, the register REG is turned on when steps S102 and S106 are performed. The number of switches CP and the values of voltages VP and VN are held.

  In this embodiment, the voltage difference VP−VN corresponding to the threshold fluctuation amount is obtained by the comparator COMPb in a state where the maximum load that can be connected to the output node OPb is connected. As shown in FIG. 6, the threshold fluctuation amount increases as the load amount connected to the output node increases. The required voltage difference VP-VN increases following the amount of change in the threshold. For this reason, by connecting the maximum amount of load to the output node OPb, the error between the threshold fluctuation amount and the voltage difference VP-VN corresponding to the threshold fluctuation amount can be reduced. That is, by connecting the maximum amount of load to the output node OPb, the threshold fluctuation amount can be accurately obtained.

  As an operation in step S100, all the switches CN of the load generation circuit LDGEN-Nb may be turned on, and all the switches CP of the load generation circuit LDGEN-Pb may be turned off. In this case, the threshold value of the comparator COMPb is shifted to the negative side, and the output node OPb outputs logic 0 when the voltages VP and VN are equal to each other. Then, the voltage VP is sequentially decreased and the voltage VN is sequentially increased until the output node OPb changes to logic 1. In the control circuit CNT, when the output node OPb changes to logic 1, the difference between the voltages VP and VN becomes equal to the threshold fluctuation amount (−160 mV in this example) due to the load connected to the output node ONb. to decide. The values of the voltages VP and VN at this time and the number of switches CN that are turned on are held in the register REG.

  FIG. 11 shows an example of operation waveforms of the comparator system CSYS that executes step S100 shown in FIG. The control circuit CNT sets the switch control signals SCNT2 and SCNT3 to logic 1 in order to turn on the switches of the switch circuits SW2 and SW3 during the high level period of the clock CLK. When the switch of the switch circuit SW2 is turned on, the nodes VIP0b and VIN0b shown in FIG. 3 are set to the ground voltage VSS. When the switch of the switch circuit SW3 is turned on, the capacitors CPb and CNb shown in FIG. 3 are charged with the common voltage VCMb, and the input nodes VIPb and VINb are set to the common voltage VCMb. For example, the value V1 of the common voltage VCMb is a reference value (600 mV).

  At the start of execution of step S100, the control circuit CNT sets the control signals CPb1-CPb16 to logic 1 and the control signals CNb1-CNb16 to logic 0. In this example, since the initial voltages of the input nodes VIPb and VINb are equal to each other, the output node OPb changes to logic 1.

  The control circuit CNT sets the switch control signal SCNT1 to logic 1 in order to turn on the switch of the switch circuit SW1 during the low level period of the clock CLK. Further, the control circuit CNT sequentially increases the voltage VP and sequentially decreases the voltage VN every clock cycle. In each clock cycle, the input nodes VIPb and VINb are set to the common voltage VCMb (= V1) during the high level period of the clock CLK, and the difference between the voltages VP and VN is the input nodes VIPb and VINb during the low level period of the clock CLK. Appears as a voltage difference.

  In this example, when the voltage difference between the input nodes VIPb and VINb reaches the value VT, the output node OPb changes from logic 1 to logic 0. The voltage difference VT is equal to the amount of fluctuation of the threshold due to the load connected to the output node ONb. The control circuit CNT obtains the value of the control signal VCNT indicating the values of the voltages VP and VN when the output node OPb changes to logic 0, and the value of the control signals CPb1 to CPb16 indicating the number of the switches CP that are turned on. Stored in the register REG.

  FIG. 12 shows an example of the operation of step S200 shown in FIG. FIG. 12 shows an operation of matching the threshold value of the comparator COMPa with the threshold value of the comparator COMPb. The operation of adjusting the threshold value of the comparator COMPc to the threshold value of the comparator COMPb is performed following the operation of adjusting the threshold value of the comparator COMPb. The operation to match the threshold value of the comparator COMPc is realized by changing “a” in the code shown in FIG. 12 to “c”. The operation of the switch circuits SW1, SW2, and SW3 will be described with reference to FIGS.

  In order to simplify the following description, it is assumed that the characteristic of the comparator COMPb is “typ”, the characteristic of the comparator COMPa is “fast”, and the characteristic of the comparator COMPc is “slow”.

  First, in step S202, the control circuit CNT sets the switch CP of the load generation circuit LDGEN-Pa by the same number (for example, 16) as the number of ON of the switch CP of the load generation circuit LDGEN-Pb held in the register REG. Is set in the register REG as the number of ON. The control circuit CNT outputs a control signal VCNT indicating the values of the voltages VP and VN held in the register REG in order to set the voltages VP and VN.

  In step S204, the control circuit CNT outputs the control signal CNT1a to the common voltage generation circuit VCMGEN, and sets the common voltage VCMa set to the input nodes VIPa and VINa of the comparator COMPa to a reference value V1 (for example, 600 mV). In the comparator COMPa, the increase amount of the threshold value due to the switch CP being turned on is canceled by the application of the voltages VP and VN corresponding to the increase amount. In other words, the comparator COMPa is in the same state as when the voltages at the input nodes VIPa and VINa are equal.

  In this example, the characteristic of the comparator COMPa is “fast”. For this reason, the fluctuation amount of the threshold value of the comparator COMPa when the switch CP is on is higher than the threshold value of the comparator COMPb whose electrical characteristics are “typ”, as indicated by a square symbol in FIG. Shift to. Since the comparator COMPa is in the same state as when the voltages of the input nodes VIPa and VINa are equal, the output node OPa of the comparator COMPa having a relatively high threshold becomes logic 1 after the processing of step S204.

  In step S206, when the output node OPa is logic 1, the process proceeds to step S208. When the output node OPa is logic 0, the process proceeds to step S212. In step S208, the control circuit CNT changes the value of the control signal CNT1a and lowers the common voltage VCMa in order to bring the threshold value of the comparator COMPa close to the threshold value of the comparator COMPb.

  In step S210, the control circuit CNT determines whether or not the output node OPa has changed to logic zero. When the output node OPa maintains the logic 1, the control circuit CNT determines that the threshold correction by the adjustment of the common voltage VCMa is not completed, and returns to step S208.

  When the output node OPa changes to logic 0, the control circuit CNT determines that the correction of the threshold value by adjusting the common voltage VCMa is completed, and the threshold value of the comparator COMPa is equal to the threshold value of the comparator COMPb, and the process proceeds to step S216. . For example, as shown in FIG. 7, when the common voltage Vcm (VCMa) reaches 545 mV, the determination in step S210 is “Yes”. In step S216, the control circuit CNT holds the value of the control signal CNT1a for setting the current common voltage VCMa in the register REG.

  On the other hand, when the electrical characteristic of the comparator COMPa is “slow”, the threshold value of the comparator COMPa is lower than the threshold value of the comparator COMPb whose electrical characteristic is “typ”, as indicated by a square symbol in FIG. Shift to. Since the comparator COMPa is in the same state as when the voltages of the input nodes VIPa and VINa are equal, the output node OPa of the comparator COMPA having a relatively low threshold after the processing of step S204 becomes logic 0, and steps S212 and S214. Is executed. Note that the processing in steps S214 and S216 also shows processing for setting the common voltage VCMc of the comparator COMPc having an electrical characteristic of “slow”.

  In step S212, the control circuit CNT changes the value of the control signal CNT1a and raises the common voltage VCMa in order to bring the threshold value of the comparator COMPa closer to the threshold value of the comparator COMPb. In step S214, the control circuit CNT determines whether or not the output node OPa has changed to logic 1. When the output node OPa maintains the logic 0, the control circuit CNT determines that the threshold correction by adjusting the common voltage VCMa is not completed, and the process returns to step S212.

  When the output node OPa changes to logic 1, the control circuit CNT determines that the correction of the threshold value by adjusting the common voltage VCMa is completed, and the threshold value of the comparator COMPa is equal to the threshold value of the comparator COMPb, and the process proceeds to step S216. . For example, as shown in FIG. 8, when the common voltage Vcm (VCMa) becomes 665 mV, the determination in step S214 is “Yes”.

  FIG. 13 shows an example of operation waveforms of the comparator system CSYS that executes step S200 shown in FIG. FIG. 13 shows an operation waveform for setting the common voltage VCMa of the comparator COMPa having the electrical characteristic “fast”. That is, FIG. 13 shows operations of steps S202 to S210 and S216 shown in FIG. Detailed descriptions of the same operations as those in FIG. 11 are omitted. The waveforms of the switch control signals SCNT1, SCNT2, and SCNT3 are the same as those in FIG.

  First, the control circuit CNT sets the control signals CPa1-CPa16 to logic 1, and sets the control signals CNa1-CNa16 to logic 0. The control circuit CNT outputs a control signal CNT1a in order to set the common voltage VCMa set to the input nodes VIPa and VINa of the comparator COMPa to a reference value V1 (for example, 600 mV). In this example, since the initial voltages of the input nodes VIPa and VINa are equal to each other, the output node OPa is set to logic 1.

  Next, in the first clock cycle, the control circuit CNT outputs the value of the control signal VCNT held in the register REG in step S110 of FIG. The input voltage generation circuit VIGEN increases the voltage VP according to the control signal VCNT, decreases the voltage VN, and generates voltages VP and VN having a voltage difference VT (for example, 160 mV). The voltage difference between the voltages VP and VN is transmitted to the input nodes VIPa and VINa during the high level period of the switch control signal SCNT1. Since the characteristic of the comparator COMPa is “fast”, the output node OPa maintains the logic 1 in the first clock cycle.

  Thereafter, the control circuit CNT sequentially decreases the common voltage VCMa every clock cycle until the logic of the output node OPa is inverted. For example, the control circuit CNT determines the logic of the output node OPa in synchronization with the rising edge of the clock CLK. Then, the control circuit CNT holds the value of the control signal CNT1a indicating the value VSETa of the common voltage VCMa when the output node OPa changes to logic 0 in the register REG. The held common voltage VSETa is used in a normal operation period after the initialization period shown in FIG.

  FIG. 14 shows another example of operation waveforms of the comparator system CSYS that executes step S200 shown in FIG. FIG. 14 shows an operation waveform for setting the common voltage VCMc of the comparator COMPc having an electrical characteristic of “slow”. That is, FIG. 14 shows operations of steps S202 to S206 and S212 to S216 shown in FIG. Detailed descriptions of the same operations as those in FIGS. 11 and 13 are omitted. The waveforms of the switch control signals SCNT1, SCNT2, and SCNT3 are the same as those in FIG.

  First, the control circuit CNT sets the control signals CPc1 to CPc16 to logic 1 and sets the control signals CNc1 to CNc16 to logic 0 as in FIG. The control circuit CNT outputs a control signal CNT1c in order to set the common voltage VCMc set to the input nodes VIPc and VINc of the comparator COMPc to a reference value V1 (for example, 600 mV). In this example, since the initial voltages of the input nodes VIPc and VINc are equal to each other, the output node OPc is set to logic 1.

  Next, as in FIG. 13, the control circuit CNT holds the voltage VP and VN having the voltage difference VT (for example, 160 mV) in the register REG in step S110 of FIG. 10 in the first clock cycle. The value of the control signal VCNT is output. The voltage difference between the voltages VP and VN is transmitted to the input nodes VIPc and VINc during the high level period of the switch control signal SCNT1. Since the electrical characteristic of the comparator COMPc is “slow”, the output node OPc changes to logic 0 in the first clock cycle.

  Thereafter, the control circuit CNT sequentially increases the common voltage VCMc every clock cycle until the logic of the output node OPc is inverted. For example, the control circuit CNT determines the logic of the output node OPc in synchronization with the rising edge of the clock CLK. The control circuit CNT holds the value of the control signal CNT1c indicating the value VSETc of the common voltage VCMc when the output node OPc changes to logic 1 in the register REG.

  FIG. 15 shows an example of an analog-digital converter ADC to which the comparator system CSYS shown in FIG. 3 is applied. For example, the analog-digital converter ADC is a 4-bit flash analog-digital converter, and includes a comparator system CSYS and an encoder ENC.

  For example, the comparator system CSYS has 15 comparators COMP (COMPa-COMPo), and the number of circuits and signal lines corresponding to the increased comparators COMP are increased compared to FIG. Each switch circuit SW1, SW2, SW3 has a switch corresponding to the comparator COMPA-COMPo, as in FIG. The connection relationship with other elements of the switch circuits SW1, SW2, and SW3 is the same as that in FIG.

  The input voltage generation circuit VIGEN generates voltages VP and VN according to the value of the control signal VCNT set in the register REG. The common voltage generation circuit VCCMGEN generates 15 types of common voltages VCMa-VCMo according to the control signals CNT1a-CNT1o corresponding to the comparators COMPa-COMPo, respectively. The values of the control signals CNT1a to CNT1o are held in the register REG. The generated common voltages VCMa, VCMb, VCMC,..., VCMo are respectively transmitted to the input nodes VIPa / VINa, VIPb / VINb, VIPc / VINc,..., VIPo / VINo via the switch circuit SW3. .

  Each comparator COMPA-COMPo has a pair of load generation circuits LDGEN-Pa and LDGEN-Na as in FIG. The value of the control signal (CPa1-CPa16 etc.) for controlling the switches SP1-SP16 of the load generation circuit LDGEN-Pa of each comparator COMPa-COMPo is held in the register REG. The value of the control signal (CNa1-CNa16 etc.) for controlling the switches SN1-SN16 of the load generation circuit LDGEN-Na of each comparator COMPA-COMPo is held in the register REG. Then, control signals (CPa1-CPa16, CNa1-CNa16, etc.) for controlling on / off of the switches SP, SN according to the values held in the register REG are output.

  Similarly to FIG. 3, the control circuit CNT generates switch control signals SCNT1, SCNT2, and SCNT3 for controlling the switch circuits SW1, SW2, and SW3, respectively, in synchronization with the clock CLK. The control circuit CNT determines the output signal OPa, OPb, OPc,... Of each comparator COMPA-COMPo during the processing of steps S100 and S200 shown in FIG. Receive OPo.

  In the comparator system CSYS shown in FIG. 15, the threshold value when a predetermined amount of load is connected to the output node of the reference comparator COMP, which is one of the comparators COMPA-COMPo, is implemented by performing step S100 shown in FIG. The fluctuation amount is obtained as a difference between the voltages VP and VN. Next, by executing S200 shown in FIG. 7 for each comparator COMP excluding the reference comparator COMP, the common voltage VCM (the advisory voltage of the reference comparator COMP is set to equalize the thresholds of the comparators COMPA-COMPo). Excluding) is required.

  Thereafter, by performing step S300 shown in FIG. 7, the threshold value of the comparator COMPA-COMPo is switched to a predetermined value using the load generation circuits LDGEN-Pa and LDGEN-Na. Then, during the normal operation period, step S400 is performed using the common voltage VCMa-VCMo obtained in step S200. Each comparator COMPA-COMPo has a logical 0 or logical 1 output signal OP (OPa, OPb, OPc,..., OPo), ON (ONa, ONb, ONc, etc.) depending on the voltage difference between the input signals VIP and VIN. ..., ONo) is output.

  For example, the encoder ENC receives the logic of the output nodes ONa, ONb, ONc,..., ONo as output values VO15, VO14, VO13,..., VO1, and represents a digital value indicating the voltage difference between the input signals VIP, VIN. D3-D0 is output.

  FIG. 16 shows a setting example of threshold values during normal operation of the comparator COMPA-COMPo shown in FIG. The threshold values shown in FIG. 16 are set in step S300 shown in FIG.

  For example, in the comparator COMPa-COMPg, the number of switches SP1-SP16 (FIG. 4) to be turned on is sequentially reduced, and in the comparator COMPi-COMPo, the number of switches SN1-SN16 (FIG. 4) to be turned on is sequentially increased. In the comparator COMPa-COMPh, all the switches SN1-SN16 are turned off, and in the comparator COMPh-COMPo, all the switches SP1-SP16 are turned off.

  Thereby, according to the characteristic shown in FIG. 6, the threshold values of the comparators COMP1-COMPo increase in order from the bottom to the top of FIG. The threshold value of the comparator COMPa-COMPg is positive, and the threshold value of the comparator COMPi-COMPo is negative. In FIG. 16, the number of switches SP and SN that are turned on is changed by two, but may be changed one by one around the comparator COMPh. At this time, the number of switches SP turned on in the comparator COMPa and the number of switches SN turned on in the comparator COMPo are each seven.

  FIG. 17 shows an example of the operation of the analog-digital converter ADC shown in FIG. For example, the threshold value of the comparator COMPA-COMPo is set to the state shown in FIG. The analog-digital converter ADC receives differential input signals VIP and VIN during a normal operation period.

  The greater the voltage difference VIP-VIN between the input signals VIP and VIN, the greater the number of logic 1s output from the output nodes ONa-ONo of the comparators COMPA1-COMPo. On the other hand, the smaller the voltage difference VIP-VIN between the input signals VIP and VIN, the greater the number of logic 0s output from the output nodes ONa-ONo of the comparators COMPA1-COMPo.

  The encoder ENC obtains a digital value D3-D0 based on the boundary between the output nodes ON that outputs logic 0 and logic 1, and outputs the obtained value. However, the encoder ENC outputs the digital value D3-D0 = "0" when all the output nodes ONa-ONo are logic 0, and outputs the digital value D3-D0 when all the output nodes ONa-ONo are logic 1. = "15" is output.

  The digital value D3-D0 decreases as the voltage difference VIP-VIN decreases, and increases as the voltage difference VIP-VIN increases. Digital values D3 to D0 from “0” to “7” are output when the voltage difference VIP−VIN is negative. Digital values D3-D0 from “8” to “15” are output when the voltage difference VIP-VIN is positive. In this way, the voltage difference VIP-VIN between the input signals VIP and VIN is converted into a 4-bit digital value D4-D0.

  In the analog-digital converter ADC shown in FIG. 15, the input terminal VIN may receive a reference voltage, and the input terminal VIP may receive a signal that changes positive and negative with respect to the reference voltage. In addition, 31 comparators COMP are formed in the comparator system CSYS shown in FIG. 15, and the number of switches SP and SN that are turned on in the 31 comparators COMP is changed one by one during the normal operation period. The voltage difference VIP-VIN between VIP and VIN can be converted into a 5-bit digital value D4-D0.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, by performing the process of step S200 shown in FIG. 12 for each comparator COMPA1-COMPc formed in the comparator system CSYS, the threshold values of the comparators COMPA1-COMPc can be adjusted to each other.

  By generating the common voltage VCM for each comparator COMP by the common voltage generation circuit VCMGEN, the common voltage VCM for correcting the threshold value during the correction period can be obtained for each comparator COMP, and different common voltages VCM are used. The threshold values of the comparators COMPA1-COMPc can be adjusted to each other.

  By connecting the maximum amount of load to the output node OPb during the detection period, the error between the threshold fluctuation amount and the voltage difference VP-VN corresponding to the threshold fluctuation amount can be reduced, and the threshold fluctuation amount can be accurately determined. Can be sought.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A pair of capacitors connected to a pair of input terminals each receiving an input signal;
At least one comparator having a pair of input nodes that receive the input signal via the capacitor and an output node that outputs an output signal indicating a voltage difference between the input signals;
A first control circuit for setting a common voltage at the pair of input nodes;
A second control circuit for setting the amount of load connected to the output node;
In the correction period for correcting the threshold value of the comparator, the first voltage and the second voltage having a voltage difference corresponding to the amount of fluctuation of the threshold value when a predetermined amount of load is connected to the output node of the reference comparator A third control circuit for supplying to each of the input terminals,
The first control circuit changes the common voltage until the logic of the output signal is inverted while the predetermined amount of load is connected to the output node during the correction period. A comparator system, wherein the common voltage at the time of inversion is used in a normal operation period after the correction period.
(Appendix 2)
The second control circuit connects the predetermined amount of load to the output node of the reference comparator, which is one of the comparators, in a detection period before the correction period,
The third control circuit changes a voltage difference between the first voltage and the second voltage during the detection period, and a voltage difference between the first voltage and the second voltage when the logic of the output signal is inverted. As a threshold fluctuation amount when a predetermined amount of load is connected to the output node of the reference comparator, and the first voltage and the second voltage when the logic of the output signal is inverted, The comparator system according to claim 1, wherein the comparator system is used for a comparator other than the reference comparator in the correction period.
(Appendix 3)
The first control circuit obtains the value of the common voltage when the logic of the output signal is inverted for each of the comparators excluding the reference comparator during the correction period, and calculates the calculated common voltage after the correction period. The comparator system according to appendix 2, wherein the comparator system is used during each of the normal operation periods.
(Appendix 4)
The comparator system according to claim 3, wherein the first control circuit includes a common voltage generation circuit that generates the common voltage for each comparator.
(Appendix 5)
The comparator system according to any one of appendix 1 to appendix 4, wherein the predetermined amount of load is a maximum amount of load that can be connected to the output node.
(Appendix 6)
A first switch disposed at a first node between the input terminal and the capacitor and turned on when the input signal is supplied to the input node;
A second switch disposed between the first node and a ground line and turned on when setting the input node to the common voltage;
And a third switch that is disposed between the input node and the first control circuit and is turned on when the input node is set to the common voltage. The comparator system according to any one of the above.
(Appendix 7)
The comparator system according to any one of appendix 1 to appendix 6, wherein the second control circuit includes a variable capacitance circuit connected to the output node.
(Appendix 8)
The comparator system according to any one of appendix 1 to appendix 7,
An encoder that generates a digital value indicating a voltage difference of the input signal based on the logic of the output signal from the comparator system;
The second control circuit is characterized in that the amounts of loads respectively connected to the output nodes during the normal operation period are made different from each other by the plurality of comparators.
(Appendix 9)
A threshold adjustment method for a comparator, comprising: a pair of input nodes respectively connected to a pair of input terminals that receive input signals via a pair of capacitors; and an output node that outputs an output signal indicating a voltage difference between the input signals. There,
In the correction period for correcting the threshold value of the comparator,
A predetermined amount of load is connected to the output node;
Supplying a first voltage and a second voltage having a voltage difference corresponding to a variation amount of a threshold when the predetermined amount of load is connected to an output node of a reference comparator to the pair of input terminals, respectively;
With the predetermined amount of load connected to the output node, change the common voltage until the logic of the output signal is inverted,
The comparator threshold value correction method, wherein the common voltage when the logic of the output signal is inverted is used in a normal operation period after the correction period.
(Appendix 10)
In the detection period before the correction period,
Connecting the predetermined amount of load to the output node of a reference comparator which is one of the comparators;
Changing the voltage difference between the first voltage and the second voltage;
A voltage difference between the first voltage and the second voltage when the logic of the output signal is inverted is detected as a threshold fluctuation amount when a predetermined amount of load is connected to the output node of the reference comparator. 10. The comparator threshold value correction method according to claim 9, wherein the first voltage and the second voltage when the logic of the output signal is inverted are used for a comparator other than the reference comparator in the correction period.
(Appendix 11)
For each comparator other than the reference comparator during the correction period, the value of the common voltage when the logic of the output signal is inverted is obtained, and the obtained common voltage is used for the normal operation period after the correction period. The comparator threshold value correcting method as set forth in appendix 10, wherein:

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  CNT, CNT1, CNT2, CNT3, control circuit; CNa-CNo, capacitor; COMPa-COMPo, comparator; CPa-CPo, capacitor; CSYS, comparator system; ENC, encoder; LDGEN-Pa, LDGEN-Na, load generation circuit; OPa-OPo: output node; REG: register; SW1-SW5: switch circuit; VCMa-VCMo: common voltage; VCMGEN: common voltage generation circuit; VIGEN: input voltage generation circuit: VIP, VIN: input terminal; VINa-VINo Input node

Claims (9)

A pair of capacitors connected to a pair of input terminals each receiving an input signal;
At least one comparator having a pair of input nodes that receive the input signal via the capacitor and an output node that outputs an output signal indicating a voltage difference between the input signals;
A first control circuit for setting a common voltage at the pair of input nodes;
A second control circuit for setting the amount of load connected to the output node;
In the correction period for correcting the threshold value of the comparator, the first voltage and the second voltage having a voltage difference corresponding to the amount of fluctuation of the threshold value when a predetermined amount of load is connected to the output node of the reference comparator A third control circuit for supplying to each of the input terminals,
The first control circuit changes the common voltage until the logic of the output signal is inverted while the predetermined amount of load is connected to the output node during the correction period. A comparator system, wherein the common voltage at the time of inversion is used in a normal operation period after the correction period. The second control circuit connects the predetermined amount of load to the output node of the reference comparator, which is one of the comparators, in a detection period before the correction period,
The third control circuit changes a voltage difference between the first voltage and the second voltage during the detection period, and a voltage difference between the first voltage and the second voltage when the logic of the output signal is inverted. As a threshold fluctuation amount when a predetermined amount of load is connected to the output node of the reference comparator, and the first voltage and the second voltage when the logic of the output signal is inverted, The comparator system according to claim 1, wherein the comparator system is used for a comparator other than the reference comparator in the correction period. The first control circuit obtains the value of the common voltage when the logic of the output signal is inverted for each of the comparators excluding the reference comparator during the correction period, and calculates the calculated common voltage after the correction period. The comparator system according to claim 2, wherein the comparator system is used during each of the normal operation periods. The comparator system according to claim 3, wherein the first control circuit includes a common voltage generation circuit that generates the common voltage for each comparator. The comparator system according to any one of claims 1 to 4, wherein the predetermined amount of load is a maximum amount of load that can be connected to the output node. A comparator system according to any one of claims 1 to 5,
An encoder that generates a digital value indicating a voltage difference of the input signal based on the logic of the output signal from the comparator system;
The second control circuit is characterized in that the amounts of loads respectively connected to the output nodes during the normal operation period are made different from each other by the plurality of comparators. A threshold adjustment method for a comparator, comprising: a pair of input nodes respectively connected to a pair of input terminals that receive input signals via a pair of capacitors; and an output node that outputs an output signal indicating a voltage difference between the input signals. There,
In the correction period for correcting the threshold value of the comparator,
A predetermined amount of load is connected to the output node;
Supplying a first voltage and a second voltage having a voltage difference corresponding to a variation amount of a threshold when the predetermined amount of load is connected to an output node of a reference comparator to the pair of input terminals, respectively;
With the predetermined amount of load connected to the output node, change the common voltage until the logic of the output signal is inverted,
The comparator threshold value correction method, wherein the common voltage when the logic of the output signal is inverted is used in a normal operation period after the correction period. In the detection period before the correction period,
Connecting the predetermined amount of load to the output node of a reference comparator which is one of the comparators;
Changing the voltage difference between the first voltage and the second voltage;
A voltage difference between the first voltage and the second voltage when the logic of the output signal is inverted is detected as a threshold fluctuation amount when a predetermined amount of load is connected to the output node of the reference comparator. 8. The comparator threshold value correction method according to claim 7, wherein the first voltage and the second voltage when the logic of the output signal is inverted are used for a comparator other than the reference comparator in the correction period. . For each comparator other than the reference comparator during the correction period, the value of the common voltage when the logic of the output signal is inverted is obtained, and the obtained common voltage is used for the normal operation period after the correction period. The comparator threshold value correcting method according to claim 8, wherein:

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