JP2013069939A - Semiconductor substrate and manufacturing method for semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the dislocation density of a semiconductor crystal layer composed of a nitride semiconductor in formation of a semiconductor crystal layer above a base substrate such as a silicon wafer.SOLUTION: There is provided a semiconductor substrate which includes a base substrate, an adhesive layer, a buffer layer, and an active layer arranged in this order and in which an Si exists in a region where the base substrate touches the adhesive layer and the adhesive layer, the buffer layer, and the active layer are composed of a nitride semiconductor. The buffer layer is a laminated structure in which each of a plurality of first crystal layers and each of a plurality of second crystal layers are alternately laminated. The first crystal layer is composed of a crystal represented by AlGaN (where 0≤m≤1). The second crystal layer is composed of a crystal represented by AlGaN (where 0≤n≤1, m>n). A lattice relaxation degree of the first crystal layer is greater than a lattice relaxation degree of the second crystal layer.

Description

  The present invention relates to a semiconductor substrate and a method for manufacturing a semiconductor substrate.

  Nitride semiconductors such as GaN and AlGaN have excellent physical properties such as a high dielectric breakdown voltage, a high saturation drift velocity, chemical and thermal stability, and a large band gap. For this reason, it is expected that the nitride semiconductor is applied to an active layer of an electronic device such as a transistor.

  A nitride semiconductor is generally formed using an epitaxial crystal growth method such as a MOCVD (Metal Organic Chemical Vapor Deposition) method. That is, a base substrate is installed in a growth chamber of an epitaxial crystal growth apparatus, and a crystal layer made of a nitride semiconductor is formed on the base substrate by utilizing a thermal reaction between a group 3 source gas and a nitrogen source gas in the growth chamber. Form.

  Note that in order to reduce the cost of an electronic device using a crystal layer made of a nitride semiconductor as an active layer, it is preferable to use a silicon substrate that can be diverted to a mass production apparatus for silicon devices and has a low price as a base substrate. Therefore, an attempt has been made to form a nitride semiconductor on a base substrate made of silicon.

  Non-Patent Document 1 discloses that when an AlGaN layer and a GaN layer are repeatedly formed on a silicon substrate using an epitaxial growth method, and an active layer formed of an InGaN multiple quantum well is formed thereon using the epitaxial growth method, the active layer It is disclosed that the dislocation density decreases.

  Patent Document 1 discloses a repetitive structure of a laminate in which crystal layers having different lattice constants or different thermal expansion coefficients are laminated, and controls the stress generated by controlling the combination of crystal layers constituting the repetitive structure. Disclosed is a technique capable of avoiding the destruction of the device.

S.A.Nikishin, et.al., Jpn. J. Appl. Phys. 40 (2001) pp. L738-L740

JP 2009-289956 A

  However, if a crystal layer made of a nitride semiconductor (hereinafter simply referred to as “semiconductor crystal layer”) is simply formed by an epitaxial growth method, high-density dislocations are generated in the semiconductor crystal layer, and a transistor is formed using the semiconductor crystal layer. Even when an electronic device such as the above is manufactured, it is often much lower than theoretically expected values in device characteristics such as withstand voltage characteristics and electron mobility characteristics. Therefore, a technique for reducing the dislocation density of the semiconductor crystal layer is desired.

  The semiconductor crystal layer is a compound semiconductor of a group 3 atom such as aluminum or gallium and a nitrogen atom. The thermal expansion coefficient and lattice constant differ depending on the composition ratio of the group 3 atom, for example, the ratio of aluminum to gallium. For this reason, when semiconductor crystal layers having different compositions are stacked, stress is generated in each layer, and the stress may exceed the elastic limit and the crystal may be broken. In order to avoid crystal breakage, it is necessary to control the generated stress so as not to exceed the elastic limit.

  In response to the above demand for reducing the dislocation density, the repetitive structure described in Non-Patent Document 1 may reduce the dislocation density of the active layer made of a nitride semiconductor. Further, in response to the above-described demand for suppressing crystal breakdown, the repeating structure described in Patent Document 1 can be expected to control the stress of the nitride semiconductor crystal and avoid the crystal breakdown.

  However, it cannot be said that the dislocation density at present is sufficiently low, and further reduction of the dislocation density is necessary. In addition, if a silicon substrate is used as the base substrate, the substrate and the crystal layer do not lattice match, so a buffer layer is required, while the silicon substrate has been conventionally used as a substrate for forming a crystal layer. Since the insulating property is inferior to that of a sapphire substrate, an SiC substrate, or the like, it is necessary to increase the buffer layer to ensure the insulating property. When the buffer layer is thickened, the entire crystal layer including the buffer layer becomes thick, and crystal breakage due to stress of the entire crystal layer is likely to occur. For this reason, a technique for further suppressing crystal breakage is desired. Since crystal breakage frequently occurs when the adhesion with the underlying layer is poor, development of a technique for improving the adhesion between the buffer layer and the base substrate is also desired.

  An object of the present invention is to improve the crystallinity of a semiconductor crystal layer when a semiconductor crystal layer made of a nitride semiconductor is formed above a base substrate such as a silicon wafer. Improvement of crystallinity contributes to reduction of dislocation density, and improvement of device performance can be expected. Another object of the present invention is to suppress crystal breakdown of the buffer layer formed between the base substrate and the semiconductor crystal layer when a semiconductor crystal layer made of a nitride semiconductor is formed above the base substrate such as a silicon wafer. There is to do.

In order to solve the above-described problem, in the first aspect of the present invention, a base substrate, an adhesive layer, a buffer layer, and an active layer are provided, and the base substrate, the adhesive layer, the buffer layer, and the active layer include Si is present in a region in contact with the adhesive layer of the base substrate, and the adhesive layer, the buffer layer, and the active layer are a semiconductor substrate made of a nitride semiconductor, and the buffer layer is A stacked structure in which a plurality of one crystal layers and a plurality of second crystal layers are alternately stacked, wherein the first crystal layer is made of a crystal represented by Al _m Ga _1-m N (where 0 ≦ m ≦ 1). The second crystal layer is made of a crystal represented by Al _n Ga _1-n N (where 0 ≦ n ≦ 1, m> n), and the lattice relaxation degree of the first crystal layer is A semiconductor substrate having a lattice relaxation degree greater than that of a two-crystal layer is provided.

It is preferable that the aluminum composition ratio m of the first crystal layer and the aluminum composition ratio n of the second crystal layer satisfy a relationship of mn> 0.5. The number of repetitions of the first crystal layer and the second crystal layer in the stacked structure is preferably 2 or more and 160 or less. When the active layer is made of a crystal represented by Al _z Ga _1-z N (where 0 ≦ z ≦ 1), the aluminum composition ratio z of the active layer is 0 or more and 0.3 or less. preferable.

  According to a second aspect of the present invention, there is provided a semiconductor substrate manufacturing method as described above, wherein the base substrate is placed in a cleaning chamber of a cleaning apparatus, and the surface of the base substrate is cleaned with an HF aqueous solution. And a layer forming step of sequentially forming the adhesive layer, the buffer layer, and the active layer on the base substrate by an epitaxial growth method after the base substrate is installed in a growth chamber of an epitaxial crystal growth apparatus. A method for manufacturing a substrate is provided.

  Prior to the first cleaning step, there may be further provided a second cleaning step of cleaning the surface of the base substrate with nitric acid and hydrogen peroxide solution. The first cleaning step and the second cleaning step are preferably performed repeatedly. After the first cleaning step, the base substrate can be transferred from the cleaning chamber to the growth chamber and transferred to the layer forming step. Or after the said 1st washing | cleaning process, it further has the water washing process of washing the said base substrate, The said base substrate can be transferred to the said growth chamber after the said water washing process, and it can transfer to the said layer formation process. .

  Hydrogen gas exposure that exposes the surface of the base substrate to hydrogen gas while maintaining the temperature of the base substrate at 1000 ° C. or higher and 1150 ° C. or lower after the base substrate is installed in the growth chamber and before the layer forming step. You may have a process further. After the hydrogen gas exposure step and before the layer formation step, the surface of the base substrate is exposed to a mixed gas of ammonia gas and carrier gas while maintaining the temperature of the base substrate at 1000 ° C. or higher. You may have a process further. When the partial pressure of ammonia gas in the mixed gas is 0.5 kPa or more and less than 1.5 kPa, the time for exposing the surface of the base substrate to the mixed gas is preferably 30 seconds or more and 120 seconds or less. When the partial pressure of ammonia gas in the mixed gas is 1.5 kPa or more and less than 4.5 kPa, it is preferable that the time for exposing the surface of the base substrate to the mixed gas is 10 seconds or more and 60 seconds or less. When the partial pressure of ammonia gas in the mixed gas is 4.5 kPa or more and less than 8.0 kPa, the time for exposing the surface of the base substrate to the mixed gas is preferably 10 seconds or more and 45 seconds or less. After the ammonia gas exposure step and before the layer formation step, a second hydrogen gas exposure step of exposing the surface of the base substrate to hydrogen gas while maintaining the temperature of the base substrate at 1000 ° C. or higher and 1150 ° C. or lower. May further be included. Examples of the time for exposing the surface of the base substrate to hydrogen gas include 1 minute to 40 minutes.

The adhesive layer may include a third crystal layer in contact with the base substrate, and a fourth crystal layer positioned between the third crystal layer and the buffer layer. In this case, as the third crystal layer, , Al _x Ga _1-x N (where 0 <x ≦ 1), and the fourth crystal layer may be Al _y Ga _1-y N (where 0 ≦ y <1, x > Y), and the step of forming the adhesive layer in the layer forming step includes the step of forming the third crystal layer by supplying a Group 3 source gas and ammonia gas, and 3 Forming a fourth crystal layer by supplying a group source gas and an ammonia gas, the first crystal layer after the formation of the third crystal layer and before the formation of the fourth crystal layer. And the formation of the buffer layer after the formation of the fourth crystal layer. An atmosphere in which the supply of the Group 3 source gas is stopped and the inside of the growth chamber is maintained in a gas atmosphere containing ammonia for a certain period of time in at least one stage selected from the group consisting of You may have a maintenance process. In any of the first stage and the second stage, when the atmosphere maintaining step is included, the fixed time T1 for maintaining the inside of the growth chamber in the atmosphere in the first stage is the second stage. In the stage, it is preferable that the predetermined time T2 during which the inside of the growth chamber is maintained in the atmosphere is shorter.

A cross section of a semiconductor substrate 100 is shown.

  FIG. 1 shows a cross section of a semiconductor substrate 100. The semiconductor substrate 100 includes a base substrate 102, an adhesive layer 104, a buffer layer 106, and an active layer 108. The base substrate 102, the adhesive layer 104, the buffer layer 106, and the active layer 108 are positioned in the order of the base substrate 102, the adhesive layer 104, the buffer layer 106, and the active layer 108. The adhesive layer 104, the buffer layer 106, and the active layer 108 are made of a nitride semiconductor.

  The base substrate 102 has Si in a region in contact with the adhesive layer 104 of the base substrate 102. Examples of the base substrate 102 include a silicon substrate (for example, a silicon wafer) and an SOI (Silicon on Insulator) substrate. By using a silicon substrate as the base substrate 102, it is not necessary to use an expensive substrate such as a sapphire substrate or a SiC substrate, and an existing manufacturing apparatus and an existing manufacturing process for silicon devices can be used, thereby reducing manufacturing costs. be able to.

The adhesive layer 104 is a crystal layer formed between the base substrate 102 and the buffer layer 106 in order to increase the crystallinity of the buffer layer 106. The adhesive layer 104 may include a third crystal layer 110 in contact with the base substrate 102 and a fourth crystal layer 112 located between the third crystal layer 110 and the buffer layer 106. As the third crystal layer 110, a crystal layer represented by Al _x Ga _1-x N (where 0 <x ≦ 1) can be given, and as the fourth crystal layer 112, Al _y Ga _1-y N, (however, Examples thereof include a crystal layer represented by 0 ≦ y <1, x> y). More specifically, the third crystal layer 110 may be an AlN layer, and the fourth crystal layer 112 may be an AlGaN layer. When the third crystal layer 110 is an AlN layer, the thickness may be 5 nm or more and 500 nm or less. In the case where the fourth crystal layer 112 is an AlGaN layer, the thickness may be 5 nm or more and 500 nm or less.

  The crystallinity of the adhesive layer 104 is not necessarily high. The adhesive layer 104 is preferably a non-doped layer that is not doped with impurity atoms. By using a non-doped layer as the adhesive layer 104, the electric resistance of the adhesive layer 104 can be increased, and the electronic device formed in the active layer 108 and the base substrate 102 can be electrically separated.

The buffer layer 106 is a crystal layer formed between the adhesive layer 104 and the active layer 108 in order to increase the crystallinity of the active layer 108. By forming the buffer layer 106, the crystallinity of the active layer 108 is increased, and the dislocation density of the active layer 108 is reduced. The buffer layer 106 may be a stacked structure in which a plurality of first crystal layers 114 and second crystal layers 116 are alternately stacked. As the first crystal layer 114, Al _m Ga _1-m N (provided that 0 ≦ m ≦ 1), and the second crystal layer 116 includes a crystal layer represented by Al _n Ga _1-n N (where 0 ≦ n ≦ 1, m> n). . More specifically, the first crystal layer 114 may be an AlN layer, and the second crystal layer 116 may be a GaN layer. In the case where the first crystal layer 114 is an AlN layer, the thickness may be 2 nm or more and 10 nm or less. In the case where the second crystal layer 116 is a GaN layer, the thickness may be 5 nm or more and 40 nm or less.

  The lattice relaxation degree of the first crystal layer 114 is larger than the lattice relaxation degree of the second crystal layer 116. Here, the degree of lattice relaxation (X) is defined as a value obtained by normalizing the average lattice constant (d1) of the crystal layer with the lattice constant (d2) when there is no strain, and is expressed as X = d1 / d2. Is done. In general, when the crystal layer forms a heterointerface with the base crystal, the lattice constant of one or both of the base crystal and the crystal layer is determined from the original lattice constant (lattice constant when there is no strain) at the heterointerface. As a result, strain (stress) is built in one or both of the base crystal and the crystal layer. However, such a shift in lattice constant is not necessarily generated over the entire surface of the heterointerface, and as a result of the bond between the base crystal and the crystal layer being broken at a portion of the heterointerface, The present inventor believes that a partial lattice relaxation state in which strain (stress) is partially released occurs. The degree of lattice relaxation is a quantitative representation of such a partial lattice relaxation state, and the strain (stress) between the base crystal and the crystal layer changes according to the degree of lattice relaxation. Note that the lattice relaxation degree can be obtained by calculation from an actual lattice constant measured by an X-ray analysis method or the like, and a value of the measured lattice constant and a lattice constant specific to the substance.

  Whether the stress of the crystal layer is a compressive stress or a tensile stress, or the magnitude of the stress is intricately related to the difference in thermal expansion coefficient and thickness of the base substrate 102 and other crystal layers. It cannot be specified. However, when the base substrate 102 is a silicon substrate and the active layer 108 is a GaN layer, tensile stress is generated in the active layer 108 due to the difference in the thermal expansion coefficient of each material at the temperature at which the crystal layer is formed and at room temperature. Conceivable. Therefore, if compressive stress is generated in the buffer layer 106, it is preferably offset by the tensile stress of the active layer 108, and the overall stress of the semiconductor substrate 100 is reduced. As a condition for generating a compressive stress in the buffer layer 106, the present inventors have found that the lattice relaxation degree of the first crystal layer 114 is larger than the lattice relaxation degree of the second crystal layer 116. That is, by making the lattice relaxation degree of the first crystal layer 114 greater than the lattice relaxation degree of the second crystal layer 116, the stress of the buffer layer 106 is controlled to a compressive stress, and the overall stress (stress) of the semiconductor substrate 100 is reduced. Thus, the crystal breakage of the buffer layer 106 and the active layer 108 can be avoided.

  The buffer layer 106 has a repeating structure of the first crystal layer 114 and the second crystal layer 116 as described above. By adopting a repeating structure, the crystallinity of the active layer 108 is increased, and the dislocation density of the active layer 108 is reduced. The number of repetitions of the first crystal layer 114 and the second crystal layer 116 in the buffer layer 106 is preferably 2 or more and 160 or less. By setting the number of repetitions to 2 or more, a repeating structure can be formed. However, the number of repetitions is more preferably set to such a degree that the effects of the above-described repetition structure (an effect of reducing the dislocation density of the active layer 108 and an effect of avoiding crystal breakdown of the buffer layer 106 itself) are exhibited. If the number of repetitions exceeds 160, the effect of the repeating structure is almost saturated, while the manufacturing cost increases. Therefore, it is appropriate that the number of repetitions is 160 or less.

  The buffer layer 106 is formed in the order of the first crystal layer 114 / second crystal layer 116 /... / First crystal layer 114 / second crystal layer 116 along the direction from the base substrate 102 toward the active layer 108. The first case (shown in FIG. 1) and the second case where the second crystal layer 116 / first crystal layer 114 /... / Second crystal layer 116 / first crystal layer 114 are formed in this order. It may be any case (not shown).

The first crystal layer 114 is made of Al _m Ga _1-m N (where 0 ≦ m ≦ 1), and the second crystal layer 116 is made of Al _n Ga _1-n N (where 0 ≦ n ≦ 1, m > N). Although the first crystal layer 114 and the second crystal layer 116 have different compositions, both are crystal layers of an aluminum / gallium nitrogen compound semiconductor. The stress and crystallinity of the buffer layer 106 can be controlled by controlling the composition and thickness of the first crystal layer 114 and the second crystal layer 116. In addition, the aluminum composition ratio of the first crystal layer 114 can be increased to increase the band gap, and the insulating property of the buffer layer 106 can be increased. Alternatively, the composition ratio of the layer in contact with the active layer 108 can be made closer to the active layer 108 by increasing the gallium composition ratio of the second crystal layer 116, and the dislocation density of the active layer 108 can be reduced. For example, the aluminum composition ratio m of the first crystal layer 114 and the aluminum composition ratio n of the second crystal layer 116 can satisfy the relationship of mn> 0.5. If mn exceeds 0.5, both the stress control of the buffer layer 106 and the reduction of the dislocation density of the active layer 108 can be satisfied.

  Note that the degree of lattice relaxation is defined by the ratio (m / n) of the aluminum compositions of the first crystal layer 114 and the second crystal layer 116, the thickness t1 of the first crystal layer 114, and the thickness t2 of the second crystal layer 116. Ratio (t1 / t2), a method of forming the first crystal layer 114 and the second crystal layer 116, for example, a growth temperature, a growth pressure when the first crystal layer 114 and the second crystal layer 116 are formed by an epitaxial growth method, It can be controlled by the ratio of the Group 5 source gas to the Group 3 source gas.

The active layer 108 is made of Al _z Ga _1-z N (where 0 ≦ z ≦ 1). The active layer 108 is a crystal layer that functions as an active layer of an electronic device, and is required to be a high-quality crystal with few dislocations. In consideration of functioning as an active layer, the aluminum composition ratio z of the active layer 108 is preferably 0 or more and 0.3 or less.

  Examples of the thickness of the active layer 108 include 0.5 μm or more and 3 μm or less. When the thickness of the active layer 108 is 0.5 μm or more, the film stress of the active layer 108 becomes large, and problems such as a decrease in crystallinity due to dislocations and film peeling (crystal breakage) become obvious. The present invention improves the crystallinity of the active layer 108 and suppresses peeling even in such a situation, and the effect of the present invention is more remarkable when the thickness of the active layer 108 is 0.5 μm or more. Is done. However, if the thickness of the active layer 108 exceeds 3 μm, it is difficult to adjust the stress balance with the buffer layer 106, and film peeling (crystal breakdown) occurs. Therefore, the thickness of the active layer 108 is preferably 3 μm or less. Note that an intermediate layer 118 may be formed between the active layer 108 and the buffer layer 106.

  Next, a method for manufacturing the semiconductor substrate 100 will be described. First, the base substrate 102 is set in a cleaning chamber of a cleaning apparatus, and a first cleaning process is performed in which the surface of the base substrate 102 is cleaned with an HF aqueous solution. The HF concentration of the aqueous HF solution can be between 0.1% and 10%, for example 5%. The cleaning time with the HF aqueous solution can be 0.5 to 10 minutes, for example, 1 minute. By the first cleaning step, it is possible to suppress the silicon surface of the base substrate 102 from being oxidized even in an environment where oxygen exists such as an air atmosphere by terminating the silicon surface with H atoms or F atoms.

  Prior to the first cleaning step, a second cleaning step of cleaning the surface of the base substrate 102 with nitric acid and hydrogen peroxide solution may be performed. By the second cleaning step, organic substances attached to the surface of the base substrate 102 are removed, and the surface of the base substrate 102 after the first cleaning step can be made cleaner. In addition, the convex portions on the silicon surface, which is the base substrate 102, are oxidized by cleaning with nitric acid and hydrogen peroxide, and thereafter the convex portions oxidized by the cleaning with the HF nest aqueous solution in the first cleaning step are etched and removed. Here, the first cleaning step and the second cleaning step are preferably performed repeatedly. By repeatedly performing the first cleaning step and the second cleaning step, the surface of the base substrate 102 can be further cleaned, and the above-described convex portions are etched more flatly, and the silicon surface is smoothed to the atomic level. Can be.

  After the first cleaning process, the base substrate 102 is transferred from the cleaning chamber to the growth chamber, and the process proceeds to the layer forming process after the adhesive layer 104. Alternatively, the base substrate 102 may be further washed with water after the first washing step. After the water washing step, the base substrate 102 is transferred to the growth chamber of the epitaxial crystal growth apparatus, and the adhesive layer 104 and the subsequent layers. You may transfer to the layer forming step. After the first cleaning process, when the process proceeds to the layer forming process without passing through the water washing process, the surface of the base substrate 102 is not oxidized by the water washing, and the process of forming the adhesive layer 104 is performed while maintaining a clean surface. Can be migrated. On the other hand, when the base substrate 102 is washed with water after the first cleaning step, HF molecules remaining on the surface of the base substrate 102 can be removed.

After the first cleaning process, the process proceeds to a layer forming process in which the adhesive layer 104, the buffer layer 106, and the active layer 108 are sequentially formed on the base substrate 102 by the epitaxial growth method. As the procedure from the washing step to the layer forming step, the following procedures (1) to (5) (4 ways × 2 = 8 ways) are possible.
(1) Procedure for shifting from the first cleaning step to the layer forming step (2) Procedure for shifting from the second cleaning step to the first cleaning step and shifting to the layer forming step (3) From the first cleaning step to the second cleaning step (4) Procedure for transferring the first cleaning process and the second cleaning process to the first cleaning process and shifting to the layer forming process (4) Moving from the second cleaning process to the first cleaning process, The process moves to the process, the first washing process and the second washing process are repeated, the process moves to the first washing process, and the process moves to the layer forming process. (5) In each of the above steps (1) to (4), the final Procedure through the water washing process during the transition from the first washing process to the layer formation process

  After the above-described cleaning process, the base substrate 102 is placed in the growth chamber of the epitaxial crystal growth apparatus, and the surface of the base substrate 102 is exposed to hydrogen gas while maintaining the temperature of the base substrate 102 at 1000 ° C. or higher and 1150 ° C. or lower. Implement a hydrogen gas exposure process. Through the hydrogen gas exposure step, the oxide layer present on the surface of the base substrate 102 can be removed. By removing the oxide layer, a good quality nitride semiconductor crystal layer can be formed on the base substrate 102.

  In the hydrogen gas exposure step, the silicon oxide film on the surface of the base substrate 102 is removed by a thermal reaction with hydrogen which is a reducing gas. If the reaction is not sufficient, the silicon oxide film is not removed, and if the reaction is too strong, the surface of the base substrate 102 is undesirably roughened. Therefore, there is an optimum range for the exposure temperature in the hydrogen gas exposure step, and the lower limit of 1000 ° C. is selected from the temperature at which the silicon oxide film can be sufficiently removed, and the upper limit of 1150 ° C. is on the surface of the base substrate 102. The temperature is selected so as not to cause roughening.

  After the hydrogen gas exposure step, an ammonia gas exposure step is performed in which the surface of the base substrate 102 is exposed to a mixed gas of ammonia gas and carrier gas while maintaining the temperature of the base substrate 102 at 1000 ° C. or higher. Examples of the carrier gas include hydrogen gas or nitrogen gas. Through the ammonia gas exposure step, a silicon nitride film that partially covers the surface of the base substrate 102 can be formed. With such a silicon nitride film partially covering the surface of the base substrate 102, an adhesive layer 104 to be formed later can be formed under high temperature conditions.

  When a GaN layer is formed on a silicon substrate, if the supply of ammonia, which is a Group 5 material, is started before trimethyl gallium (TMG) or trimethylaluminum (TMA), which is a Group 3 material, the GaN single crystal layer cannot grow Are known. This is considered to be because the surface of the silicon substrate is nitrided before the growth of the GaN single crystal layer. Therefore, when a GaN layer, an AlGaN layer, or an AlN layer is formed on the surface of the silicon substrate, supply of the Group 3 material is started before the Group 5 material, and in many cases, the AlN layer is formed as an intermediate layer. However, such an AlN intermediate layer cannot be formed unless the growth temperature is set to a low temperature condition, and an AlN layer formed under a low temperature condition is inferior to an AlN layer formed under a high temperature condition in terms of pinch-off property and on / off ratio. It was.

  However, the present inventor has found that a nitride semiconductor crystal layer such as an AlN layer can be formed even under high temperature conditions by forming a silicon nitride film that partially covers the surface of the base substrate 102. Even in the case of the base substrate 102 made of a silicon substrate, the nitride semiconductor crystal layer can be formed under high temperature conditions because the crystal of the nitride semiconductor crystal layer starts from the silicon (exposed portion) that is not covered with the silicon nitride film. This is probably because the growth started and the nitride semiconductor crystal layer was laterally grown in the portion covered with the silicon nitride film.

  As described above, by performing the ammonia gas exposure step, it is possible to form the high-quality adhesive layer 104. Note that the ammonia gas exposure step is performed after the hydrogen gas exposure step because a silicon nitride film (SiN mask) that partially covers the surface of the base substrate 102 is uniformly applied to the entire surface of the base substrate 102 with the same roughness. It contributes to being able to form. That is, since the surface of the base substrate 102 is extremely cleaned by the hydrogen gas exposure process, the SiN mask is formed with uniform roughness, and therefore, it can be said that the high-quality adhesive layer 104 can be formed uniformly.

  From the above mechanism, the nitridation of the surface of the base substrate 102 in the ammonia gas exposure step is not preferable if it is too little or too much. It is necessary to moderately control the nitridation of the surface of the base substrate 102. For this reason, ammonia can be diluted with a carrier gas to reduce the reaction rate. Examples of the carrier gas include hydrogen gas or nitrogen gas. Since the nitridation reaction on the surface of the base substrate 102 can be controlled by the partial pressure of ammonia gas and the reaction time, there is an optimum range for each parameter combination.

  When the partial pressure of ammonia gas in the mixed gas is 0.5 kPa or more and less than 1.5 kPa, it is preferable that the time for exposing the surface of the base substrate 102 to the mixed gas is 30 seconds or more and 120 seconds or less. Alternatively, when the partial pressure of ammonia gas in the mixed gas is 1.5 kPa or more and less than 4.5 kPa, the time for exposing the surface of the base substrate 102 to the mixed gas is preferably 10 seconds or more and 60 seconds or less. Alternatively, when the partial pressure of ammonia gas in the mixed gas is 4.5 kPa or more and less than 8.0 kPa, the time for exposing the surface of the base substrate 102 to the mixed gas is preferably 10 seconds or more and 45 seconds or less.

  After the ammonia gas exposure step, a second hydrogen gas exposure step of exposing the surface of the base substrate 102 to hydrogen gas while maintaining the temperature of the base substrate 102 at 1000 ° C. or higher and 1150 ° C. or lower can be further performed. By carrying out the hydrogen gas exposure process after the ammonia gas exposure process, a trace amount of polycrystalline or non-crystalline group 3 nitridation generated by the reaction of the group 3 material volatilized from the reaction chamber wall surface with ammonia in the ammonia gas exposure process Physical substances can be removed from the surface of the base substrate 102.

After the ammonia gas exposure step, a second hydrogen gas exposure step is performed as necessary, and an adhesive layer 104, a buffer layer 106, and an active layer 108 are sequentially formed on the base substrate 102 by an epitaxial growth method. When the MOCVD method is used as the epitaxial crystal growth method, TMA (trimethylaluminum), TMG (trimethylgallium), NH ₃ (ammonia) can be used as the source gas, and Si ₂ H ₆ (disilane), SiH ₄ (silane) can be used, and H ₂ (hydrogen gas) and N ₂ (nitrogen gas) can be used as the carrier gas.

  In the step of forming the adhesive layer 104, the step of forming the third crystal layer 110 is performed by supplying the Group 3 source gas and ammonia gas, and then the fourth step is performed by supplying the Group 3 source gas and ammonia gas. A step of forming the crystal layer 112 is performed. However, the first stage after the formation of the third crystal layer 110 and before the formation of the fourth crystal layer 112 and the second stage after the formation of the fourth crystal layer 112 and before the formation of the buffer layer 106 are performed. In at least one stage selected from the group consisting of the stages, there is an atmosphere maintaining step of stopping the supply of the Group 3 source gas and maintaining the inside of the growth chamber in a gas atmosphere containing ammonia for a certain period of time. Here, the atmosphere of the gas containing ammonia includes an atmosphere of ammonia gas alone and an atmosphere composed of ammonia gas and hydrogen gas.

That is, the adhesive layer 104 is formed by any of the following patterns.
(1) After the formation process of the third crystal layer 110, the first-stage atmosphere maintenance process is performed, the formation process of the fourth crystal layer 112 is performed, and the process proceeds to the formation process of the buffer layer 106 continuously. First Pattern (2) After the formation process of the third crystal layer 110, the formation process of the fourth crystal layer 112 is continuously performed without performing the atmosphere maintenance process, and the atmosphere maintenance process of the second stage is performed. 2nd pattern which transfers to the formation process of the buffer layer 106 after implementing (3) After the formation process of the 3rd crystal layer 110, the atmosphere maintenance process of the 1st step is implemented and the 4th crystal layer 112 is formed The third pattern which shifts to the formation process of the buffer layer 106 after performing the process and performing the atmosphere maintaining process of the second stage

There is an advantage that the facet of the growth surface is formed by the atmosphere maintaining process in the first stage or the second stage, and the resistance of the crystal layer can be increased by hydrogen passivation. On the other hand, the surface may be roughened by the atmosphere maintaining step. Therefore, each of the patterns (1) to (3) has advantages and disadvantages. That is, in the first pattern of (1), reduction of defects due to facet formation of the third crystal layer 110 and lateral growth of the fourth crystal layer 112 based on the facet plane can be expected.
In the second pattern (2), it is possible to increase the resistance of the fourth crystal layer 112, which is considered to have a lower resistivity than the third crystal layer 110. In the third pattern (3), both the facet formation and the high resistance of the third crystal layer 110 and the fourth crystal layer 112 can be achieved. However, since it is predicted that the surface will be roughened by the atmosphere maintenance process, it is necessary to compare and examine whether or not the atmosphere maintenance process can be performed depending on the required characteristics. In the third pattern of (3), when the purpose is to increase the resistance of the third crystal layer 110 and the fourth crystal layer 112, the band gap of the fourth crystal layer 112 is narrower than that of the third crystal layer 110. Therefore, the time required for increasing the resistance is longer in the fourth crystal layer 112. Therefore, the fixed time T1 for maintaining the inside of the growth chamber in the atmosphere in the first stage is preferably shorter than the fixed time T2 for maintaining the inside of the growth chamber in the atmosphere in the second stage.

  According to the semiconductor substrate 100 and the manufacturing method thereof described above, since the first cleaning process of cleaning the surface of the base substrate 102 with the HF aqueous solution is performed, the base substrate 102 is subsequently subjected to a hydrogen gas exposure process and an ammonia gas exposure process. The adhesive layer 104 formed thereon can have good crystallinity and adhesiveness. As a result, the quality of the buffer layer 106 and the active layer 108 formed above the adhesive layer 104 can be improved, and the dislocation density in the active layer 108 can be reduced.

  In addition, by performing the hydrogen gas exposure step, the nitride opening size on the surface of the base substrate 102 formed in the ammonia gas exposure step can be made uniform, and the third crystal layer 110 of the adhesive layer 104 can be formed. It can have good crystallinity and adhesiveness. As a result, the quality of the fourth crystal layer 112, the buffer layer 106, and the active layer 108 can be improved, and the dislocation density in the active layer 108 can be reduced.

  Further, by performing the ammonia gas exposure step, a nitride covering a part of the surface of the base substrate 102 can be formed, and the third crystal layer 110 of the adhesive layer 104 is formed under a high temperature condition. It can have crystallinity and adhesiveness. As a result, the quality of the fourth crystal layer 112, the buffer layer 106, and the active layer 108 can be improved, and the dislocation density in the active layer 108 can be reduced.

  In addition, after the formation of the third crystal layer 110, the formation of the fourth crystal layer 112, or both in the formation process of the adhesive layer 104, the supply of the group 3 source gas is stopped, and the inside of the growth chamber is made to contain ammonia. By performing the atmosphere maintaining step of maintaining the atmosphere of the contained gas for a certain period of time, the crystallinity of the adhesive layer 104 can be improved or the resistivity of the adhesive layer 104 can be increased. As a result, the quality of the buffer layer 106 and the active layer 108 can be improved, the dislocation density in the active layer 108 can be reduced, and the insulation from the base substrate 102 when the active layer 108 is applied to an electronic device can be improved.

  The present invention can also be understood as an electronic device having a part of the active layer 108 as an active region. A field effect transistor can be illustrated as an electronic device. Further, taking advantage of the fact that the active layer 108 can be formed to a thickness of 0.5 μm or more and 3 μm or less, an electronic device having a vertical structure in which carriers in the active region move in the vertical direction of the semiconductor substrate 100 is obtained. You can also. Examples of the electronic device having the vertical structure include a Schottky barrier diode, a PIN diode, and an insulated gate bipolar transistor.

  100 semiconductor substrate, 102 base substrate, 104 adhesive layer, 106 buffer layer, 108 active layer, 110 third crystal layer, 112 fourth crystal layer, 114 first crystal layer, 116 second crystal layer, 118 intermediate layer.

Claims (18)

A base substrate, an adhesive layer, a buffer layer and an active layer, wherein the base substrate, the adhesive layer, the buffer layer and the active layer are positioned in this order;
Si exists in a region in contact with the adhesive layer of the base substrate,
The adhesive layer, the buffer layer, and the active layer are semiconductor substrates made of a nitride semiconductor,
The buffer layer is a laminated structure in which a plurality of first crystal layers and second crystal layers are alternately laminated;
The first crystal layer is made of a crystal represented by Al _m Ga _1-m N (where 0 ≦ m ≦ 1),
The second crystal layer is made of a crystal represented by Al _n Ga _1-n N (where 0 ≦ n ≦ 1, m>n);
A semiconductor substrate, wherein the lattice relaxation degree of the first crystal layer is larger than the lattice relaxation degree of the second crystal layer. The semiconductor substrate according to claim 1, wherein an aluminum composition ratio m of the first crystal layer and an aluminum composition ratio n of the second crystal layer satisfy a relationship of mn> 0.5. The semiconductor substrate according to claim 1, wherein the number of repetitions of the first crystal layer and the second crystal layer in the stacked structure is 2 or more and 160 or less. The active layer is made of a crystal represented by Al _z Ga _1-z N (where 0 ≦ z ≦ 1),
The semiconductor substrate according to any one of claims 1 to 3, wherein an aluminum composition ratio z of the active layer is 0 or more and 0.3 or less. A method for manufacturing a semiconductor substrate according to any one of claims 1 to 4,
A first cleaning step of installing the base substrate in a cleaning chamber of a cleaning apparatus, and cleaning the surface of the base substrate with an HF aqueous solution;
A layer forming step of sequentially forming the adhesive layer, the buffer layer, and the active layer on the base substrate by an epitaxial growth method after the base substrate is installed in a growth chamber of an epitaxial crystal growth apparatus;
The manufacturing method of the semiconductor substrate which has this. The method for manufacturing a semiconductor substrate according to claim 5, further comprising a second cleaning step of cleaning the surface of the base substrate with nitric acid and hydrogen peroxide before the first cleaning step. The method for manufacturing a semiconductor substrate according to claim 6, wherein the first cleaning step and the second cleaning step are repeatedly performed. The method for manufacturing a semiconductor substrate according to claim 5, wherein, after the first cleaning step, the base substrate is transferred from the cleaning chamber to the growth chamber, and is transferred to the layer forming step. . After the first cleaning step, further comprising a water washing step of washing the base substrate with water,
The method for manufacturing a semiconductor substrate according to claim 5, wherein after the water washing step, the base substrate is transferred to the growth chamber and transferred to the layer forming step. Hydrogen gas exposure that exposes the surface of the base substrate to hydrogen gas while maintaining the temperature of the base substrate at 1000 ° C. or higher and 1150 ° C. or lower after the base substrate is installed in the growth chamber and before the layer forming step. The method for manufacturing a semiconductor substrate according to claim 5, further comprising a step. After the hydrogen gas exposure step and before the layer formation step, the surface of the base substrate is exposed to a mixed gas of ammonia gas and carrier gas while maintaining the temperature of the base substrate at 1000 ° C. or higher. The method for manufacturing a semiconductor substrate according to claim 10, further comprising a step. The semiconductor according to claim 11, wherein a partial pressure of ammonia gas in the mixed gas is 0.5 kPa or more and less than 1.5 kPa, and a time for exposing the surface of the base substrate to the mixed gas is 30 seconds or more and 120 seconds or less. A method for manufacturing a substrate. The semiconductor according to claim 11, wherein a partial pressure of ammonia gas in the mixed gas is 1.5 kPa or more and less than 4.5 kPa, and a time for exposing the surface of the base substrate to the mixed gas is 10 seconds or more and 60 seconds or less. A method for manufacturing a substrate. The partial pressure of ammonia gas in the mixed gas is 4.5 kPa or more and less than 8.0 kPa, and the time for exposing the surface of the base substrate to the mixed gas is 10 seconds or more and 45 seconds or less,
A method for manufacturing a semiconductor substrate according to claim 11. After the ammonia gas exposure step, before the layer formation step, a second hydrogen gas exposure step of exposing the surface of the base substrate to hydrogen gas while maintaining the temperature of the base substrate at 1000 ° C. or higher and 1150 ° C. or lower. The method for manufacturing a semiconductor substrate according to any one of claims 11 to 14, further comprising: The method for manufacturing a semiconductor substrate according to any one of claims 10 to 15, wherein a time during which the surface of the base substrate is exposed to hydrogen gas is not less than 1 minute and not more than 40 minutes. The adhesive layer includes a third crystal layer in contact with the base substrate, and a fourth crystal layer positioned between the third crystal layer and the buffer layer;
The third crystal layer is made of a crystal represented by Al _x Ga _1-x N (where 0 <x ≦ 1);
The fourth crystal layer is made of a crystal represented by Al _y Ga _1-y N (where 0 ≦ y <1, x> y),
The step of forming the adhesive layer in the layer forming step includes forming the third crystal layer by supplying a Group 3 source gas and ammonia gas, and supplying the Group 3 source gas and ammonia gas. Forming a fourth crystal layer,
A first stage after the formation of the third crystal layer and before the formation of the fourth crystal layer; and a second stage after the formation of the fourth crystal layer and before the formation of the buffer layer; And at least one stage selected from the group consisting of: an atmosphere maintaining step of stopping the supply of the Group 3 source gas and maintaining the inside of the growth chamber in a gas atmosphere containing ammonia for a certain period of time. The method for manufacturing a semiconductor substrate according to any one of claims 5 to 16. In any of the first stage and the second stage, when the atmosphere maintaining step is included, the fixed time T1 for maintaining the inside of the growth chamber in the atmosphere in the first stage is the second stage. The method for manufacturing a semiconductor substrate according to claim 17, wherein in the step, the inside of the growth chamber is maintained in the atmosphere for less than a predetermined time T2.

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