JP2013069210A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system capable of securing the maximum number of combinations allowing parallel driving even when a defective memory chip is generated.SOLUTION: The combination of a plurality of physical banks constituting a logical bank is dynamically set on the basis of defective memory chip information by which defective memory chips within physical banks can be identified so as to maximize the number of memory chips allowing parallel access within each lane without using the defective memory chips.

Description

  Embodiments described herein relate generally to a memory system including a nonvolatile semiconductor memory.

  In recent years, flash memory packages are often configured by stacking a plurality of memory chips. As represented by SSD (Solid State Drive), when a large-capacity storage device is configured using a flash memory, it is often configured by using a plurality of such packages.

  For example, when an SSD is configured by using 8 packages stacked in 8 stacks, one system is composed of 64 chips, and even if the defect rate of a single chip is 0.1%, the system is defective. The rate is about 6%, and the failure rate as a system is larger than the failure rate of a single chip.

JP 2009-266125 A

  An object of one embodiment of the present invention is to provide a memory system that can secure the maximum number of combinations that can be driven in parallel even when a defective chip or a defective block occurs.

  According to one embodiment of the present invention, a nonvolatile semiconductor memory has a plurality of channel parallel operation elements capable of parallel operation, each channel parallel operation element has a plurality of physical banks capable of bank interleaving, The physical bank has a plurality of memory chips, and each memory chip has a plurality of physical blocks which are data erasing units. A plurality of memory controllers are provided, and one memory controller is allocated corresponding to a lane composed of a plurality of channel parallel operation elements. A memory controller is connected individually to each physical bank, and a plurality of channel parallel operation elements in a lane are selected by selecting a physical bank by a plurality of chip enable signals commonly connected to a plurality of memory chips in one physical bank. The memory chips in each physical bank included in are driven in parallel. Based on the defective memory chip information that can identify the defective memory chip in each physical bank, the controller is configured to increase the number of memory chips that can be accessed in parallel in each lane without using the defective memory chip. The logical / physical bank information indicating the combination of a plurality of physical banks that constitutes is dynamically set. Each memory controller drives and controls a chip enable signal based on logical / physical bank information set by the controller.

FIG. 1 is a block diagram illustrating a configuration example of an SSD. FIG. 2 is a block diagram showing a configuration example of the NAND flash in one lane. FIG. 3 is a diagram illustrating an internal configuration example of a one-channel NAND flash. FIG. 4 is a block diagram illustrating an internal configuration example of the NAND controller. FIG. 5 is a diagram illustrating an example of data arrangement of ECC codes in the CH configuration and an example of data arrangement of ECC codes in the lane configuration. FIG. 6 is a diagram showing a configuration example of access information for the NAND flash of each channel. FIG. 7 is a flowchart showing an example of an access operation procedure for the NAND flash in one lane. FIG. 8 is a diagram showing an example of chip selection when there is a chip failure when selecting a chip that performs channel parallel operation from banks having the same bank number. FIG. 9 is a diagram illustrating an example of chip selection when the technique of the first embodiment is used when there is a chip failure. FIG. 10 is a diagram showing an example of chip selection when there is a chip failure when selecting a chip that performs channel parallel operation from banks having the same bank number. FIG. 11 is a diagram showing access information and the like when the chip selection of FIG. 10 is performed. FIG. 12 is a diagram showing an example of chip selection when the technique of the first embodiment is used when there is a chip failure. FIG. 13 is a diagram showing access information and the like when the chip selection of FIG. 12 is performed. FIG. 14 is a diagram illustrating an example of chip selection when the method of the second embodiment is used when there is a chip failure and a block failure. FIG. 15 is a diagram showing access information and the like when the chip selection of FIG. 14 is performed. FIG. 16 is a diagram showing a block capacity capable of channel parallel when there is a block failure when a block for performing channel parallel operation is selected from banks having the same bank number. FIG. 17 is a diagram illustrating a block capacity capable of channel paralleling when the method of the second embodiment is used when there is a block failure.

  In SSD (Solid State Drive), a plurality of flash memories are connected in parallel through a plurality of channels, and the plurality of flash memories are driven in parallel to enable high-speed access. In the SSD, the flash memory of each channel is composed of a plurality of banks capable of bank interleaving, and bank interleaving is performed in addition to the channel parallel operation to enable further high-speed access.

  In the flash memory of each channel, each bank is constituted by a plurality of memory chips, and each memory chip is constituted by arranging a plurality of physical blocks which are data erasing units. In such an SSD, a physical block of each channel driven in parallel is combined to form a virtual block called a logical block to enable access in units of logical blocks.

  When a logical block is configured by selecting one physical block from a plurality of channels as described above, the logical block is managed by providing a constraint that the logical block is configured by physical blocks having the same bank number. There is a case where a method of facilitating the correspondence to the change in the number of physical blocks constituting the logical block is sometimes adopted.

  On the other hand, in the SSD, generally, one memory controller is arranged for each channel, and one memory controller drives and controls the flash memory of one channel. Functions performed by the memory controller include driving processing of the flash memory of the connected channel, error correction processing (ECC processing), bank interleaving processing, and the like, and these processing are executed under the control of the host controller.

  However, when one memory controller is provided for each channel, the gate scale of the memory controller increases as the number of channels increases and error correction processing becomes complicated. Therefore, it is considered that one memory controller is arranged in a plurality of channels of flash memory, and a plurality of channels of flash memories are driven in parallel by one memory controller. In this specification, a plurality of channels connected to one memory controller is referred to as a lane. In the configuration using this lane, for example, error correction processing can be shared by a plurality of channels, and the gate scale can be reduced.

  However, when the restriction that a logical block is configured by physical blocks having the same bank number is applied to each lane, if there is a defective chip or a defective block, the physical block that can be used in each lane cannot be effectively used. There is a problem that the combined capacity of usable physical blocks is reduced (see FIG. 8).

  Therefore, in this embodiment, within the lane, there is no restriction that a logical block is configured by physical blocks having the same bank number, and when a defective chip or a defective block exists, the usable physical block is effectively used. It is possible to ensure the maximum combined capacity of usable physical blocks (see FIG. 9). That is, in the present embodiment, the concept of a virtual logical bank composed of a plurality of physical banks is introduced in the lane, and the lanes are paralleled without using the defective memory chip based on the defective memory chip information. A combination of a plurality of physical banks constituting a logical bank can be dynamically set so that the number of accessible memory chips is maximized. Note that how to combine logical banks between lanes is not mentioned in the present embodiment.

  Hereinafter, a memory system according to an embodiment will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of an SSD 100 as a memory system. The SSD 100 includes a drive control circuit 4 as a controller, a NAND flash memory (hereinafter abbreviated as a NAND flash) 10 as a nonvolatile semiconductor memory, a RAM 20 as a randomly accessible semiconductor memory, and an ATA interface (ATA I / O). F) A memory connection interface such as 2 is provided. The SSD 100 is connected to a host device (hereinafter abbreviated as “host”) 1 such as a personal computer or a CPU core via the ATA I / F 2 and functions as an external memory of the host 1.

  The NAND flash 10 stores user data designated by the host 1, and stores management information managed by the RAM 20 for backup. The NAND flash 10 has a memory cell array in which a plurality of memory cells are arranged in a matrix, and each memory cell can store multiple values using an upper page and a lower page. The NAND flash 10 is constituted by a plurality of memory chips, and each memory chip is constituted by arranging a plurality of physical blocks which are data erasing units. In the NAND flash 10, data is written and data is read for each physical page. A physical block is composed of a plurality of physical pages. In FIG. 1, the NAND flash 10 is connected in parallel to the NAND controller 110 in the drive control circuit 4 via four channels (4ch: CH0 to CH3), and the four channel parallel operation elements 10a to 10d are operated in parallel. It is possible to make it. The number of channels is not limited to four, and any number of channels can be employed.

  For example, a volatile semiconductor memory is employed as the RAM 20. As the RAM 20, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), etc. can be adopted. . The RAM 20 is used as a storage unit for data transfer, management information recording, or work area. Specifically, as a data transfer storage unit (data transfer cache), data requested to be written from the host 1 is temporarily stored before being written to the NAND flash 10, or read from the host 1. It is used to read out requested data from the NAND flash 10 and store it temporarily. As a storage unit for recording management information, management information for managing the storage location of data stored in the NAND flash 10 (various management tables stored in the NAND flash 10 are expanded at the time of startup or the like). Used to store a master table, a log that is change difference information of a management table, and the like.

  The drive control circuit 4 controls data transfer between the host 1 and the NAND flash 10 via the RAM 20 and controls each component in the SSD 100.

  The drive control circuit 4 includes a data access bus 101 and a circuit control bus 102. A processor 104 that controls the entire drive control circuit 4 is connected to the circuit control bus 102. A boot ROM 105 storing a boot program for booting each management program (FW: firmware) stored in the NAND flash 10 is connected to the circuit control bus 102 via a ROM controller 106.

  The ATA interface controller (ATA controller) 111, the NAND controller 110, and the RAM controller 114 are connected to both the data access bus 101 and the circuit control bus 102. The ATA controller 111 transmits and receives data to and from the host 1 via the ATA interface 2. An SRAM 115 used as a data work area and a firmware development area is connected to the data access bus 101 via an SRAM controller 116. The firmware stored in the NAND flash 10 is transferred to the SRAM 115 by a boot program stored in the boot ROM 105 at startup. The processor 104 operates as the highest controller in the SSD 100 by executing the firmware transferred to the SRAM 115, and controls the components in the drive control circuit 4.

  The RAM controller 114 executes interface processing between the processor 104 and the RAM 20, data transfer control between the ATA I / F2 and RAM 20, data transfer control between the NAND flash 10 and RAM 20, and the like. The NAND controller 110 executes interface processing between the processor 104 and the NAND flash 10, data transfer control between the NAND flash 10 and the RAM 20, encoding / decoding processing of error correction codes, and the like.

  FIG. 2 shows an example of the internal configuration of the NAND flash 10. FIG. 2 shows a channel parallel operation element 10a for channel 0 (CH0) and a channel parallel operation element 10b for channel 1 (CH1). The channel parallel operation element 10c of the channel 2 (CH2) and the channel parallel operation element 10d of the channel 3 (CH3), which are not shown, have the same configuration. Each of the channel parallel operation elements 10a to 10d is configured by a plurality of physical banks (four banks in FIG. 2, Bank 0 to Bank 3) capable of bank interleaving, and each physical bank has a plurality of memory chips (in FIG. 2). 4 memory chips, Chip 0 to Chip 3). Banks 0 to 3 indicating bank numbers indicate physical bank numbers indicating physical positions on the NAND flash 10. Bank interleaving is an effective use of time by issuing an access request to the next bank during a delay time when data of a certain bank is being accessed, that is, when a ready busy signal (RyBy) of a certain bank is busy. It is a technique.

  FIG. 3 shows an internal configuration example of one bank (in this case, bank0) in the channel parallel operation element 10a of channel 0 (CH0). As shown in FIG. 3, each memory chip (chip0 to chip3) in one bank is composed of, for example, a plurality of physical blocks (in FIG. 4, for convenience, four physical blocks Blk0 to Blk3 are arranged). Indicated).

  FIG. 4 shows an example of the internal configuration of the NAND controller 110. The NAND controller (NANDC) 110 includes a NAND controller for NAND 0 (NANDC-LN0) 110a that controls driving of the NAND flash 10 in Lane 0 and a NAND controller for NAND 1 (NANDC-LN0) that controls driving of the NAND flash 10 in Lane 1. 110b. A plurality of channels in which one lane NAND controller performs drive control is referred to as a lane. In this embodiment, a NAND flash 10 composed of four channels is divided into lane 0 (CH0 and CH1) and lane 1 (CH2 and CH3), and the NAND flash 10 in lane 0 (channel parallel operation elements 10a and 10b). Is controlled by one NANDC-LN0 110a, and the NAND flash 10 (channel parallel operation elements 10c and 10d) in lane 1 is controlled by the other NANDC-LN1 110b. That is, in this embodiment, one lane is composed of two channels.

  The lane 0 NAND controller 110a includes a DMA controller (DMAC) 30a that performs DMA transfer control with the RAM 20, an error correction circuit (ECC circuit) 31a, a NAND I / F 32a, and a lane 0 controller 33a. The lane 0 controller 33a includes a CH0 access information setting register 34a, a CH1 access information setting register 35a, an operation permission register 36a, an I / F controller 37a, and a controller 38a. The lane 1 NAND controller 110b has the same configuration, and includes a DMAC 30b, an ECC circuit 31b, a NAND I / F 32b, and a lane 1 controller 33b. The lane 1 controller 33b has the same configuration, and includes a CH2 access information setting register 34b, a CH3 access information setting register 35b, an operation permission register 36b, an I / F controller 37b, and a controller 38b.

  Signal lines for two channels (CH0, CH1) are connected to the NAND / IF 32a of the NAND controller 110a for lane 0. That is, the NAND / IF 32a includes a control I / O signal, a chip enable signal (CE00-03) and a ready / busy signal (RyBy00-03) connected to the CH0 channel parallel operation element 10a, and a CH1 channel parallel operation element 10b. A control I / O signal, a chip enable signal (CE10-13), and a ready / busy signal (RyBy10-13) are connected. Control I / O signals are CLE (command latch enable), ALE (address latch enable), WE (write enable), RE (read enable), DQS (data strobe signal), I / O0 to I / O7 (input / output). Terminal). Similarly, the NAND / IF 32b of the NAND controller 110b for lane 1 has control I / O signals for two channels (CH2, CH3), chip enable signals (CE20-23, CE30-33), and a ready busy signal (RyBy20-23). , RyBy30-33) are connected.

  In FIG. 2, the signal line connection between the NAND I / F 32a of the lane 0 controller 33a and the channel parallel operation element 10a of CH0 and the channel parallel operation element 10b of CH1 is shown in more detail. As shown in FIG. 2, in each channel, the control I / O signal is shared among a plurality of banks (Bank 0 to Bank 3), but the chip enable signal CE0-3 and the ready busy signal RyBy0-3 are provided to each bank. Connected individually. That is, in each channel, the chip enable signal CE0 (CE00, CE10, CE20, CE30) is commonly connected to each memory chip of the bank (Bank0) with bank number 0, and the chip enable signal CE1 (CE01, CE11, CE21, CE31). Are commonly connected to each memory chip of the bank (Bank 1) of bank number 1, and the chip enable signal CE2 (CE02, CE12, CE22, CE32) is commonly connected to each memory chip of the bank (Bank 2) of bank number 2. The enable signal CE3 (CE03, CE13, CE23, CE33) is commonly connected to each memory chip of the bank (Bank3) with the bank number 3, and a plurality of banks (Bank0 to Bank3) are connected to the plurality of chip enable signals (CE0-3). ) Van To control individually for each. As described above, when selecting the physical bank of bank number n in each channel, a method is adopted in which the chip enable signal CEn is asserted.

  Similarly, in each channel, from each bank of the NAND flash 10, a ready / busy signal RyBy0-3 (RyBy00 to RyBy33) indicating whether the bank is busy or ready is input to the NAND I / F. RyBy signal lines of a plurality of memory chips included in each bank of each channel are connected in common.

  One ECC circuit 31a is mounted on the NAND controller 110a for lane 0, and ECC processing for two channels is executed by one ECC circuit 31a. As shown in FIG. 5, an ECC code is added to each 512B sector data. FIG. 5A shows an ECC process when one ECC circuit is provided for one channel. In this case, an ECC code is added to the 512B sector data to be written to the NAND flash 10 of CH0, An ECC code is added to 512B sector data to be written to the NAND flash 10 of CH1. FIG. 5B shows ECC processing when one ECC circuit is provided for two channels. In this case, 256B data to be written to the CH0 NAND flash 10 and CH1 NAND flash 10 are written. On the other hand, 256B data to be written constitutes one sector data, and an ECC code is added to 512B one sector data distributed to CH0 and CH1. The ECC circuit 31a executes ECC processing as shown in FIG.

  In the case of reading sector data, in the case of FIG. 5A, it is necessary to read the sector data from 1 channel to 512B, but in the case of FIG. 5B, the data from 2 channels that can be operated in parallel is 256B. It is only necessary to read data one by one, and there is an advantage that the read time is halved. Further, since only one ECC circuit needs to be provided for two channels, there is an advantage that the gate scale of the NAND controller 110 is reduced.

  Next, the lane 0 controller 33a will be described. The lane 1 controller 33b has a similar configuration. Control information for driving and controlling lane 0 of the NAND flash 10 from the host processor 104 is input to the controller 38a of the lane 0 controller 33a from the upper processor 104. The controller 38a controls the internal configuration circuit of the lane 0 controller 33a based on the control information input from the processor 104. The control information input from the processor 104 includes access information for accessing the NAND flash 10 in lane 0 (channel 0 and channel 1).

  Access information for CH0 input from the processor 104 is set in the CH0 access information setting register 34a by the controller 38a. Access information for CH1 input from the processor 104 is set in the CH1 access information setting register 35a by the controller 38a. The CH0 access information setting register 34a and the CH1 access information setting register 35a have a queue structure and can store a plurality of access information. FIG. 6 shows an example of access information input from the processor 104. The access information of channel 0 includes a bank number, a chip number, a block number, and an instruction (write, read, erase, etc.). Similarly, the access information of channel 1 includes a bank number, a chip number, a block number, and an instruction (write, read, erase, etc.).

  The access information of each channel set in the CH0 access information setting register 34a and the CH1 access information setting register 35a is set in the operation permission register 36a by the controller 38a. Based on the RyBy signal (RyBy00-03, RyBy10-13) and the like, the controller 38a sets the access information of each channel in the operation permission register 36a when the channel 0 and the channel 1 can be operated in parallel. The I / F controller 37a responds to the access information by controlling the NAND I / F 32a based on the access information for channel 0 and channel 1 set in the operation permission register 36a under the control of the controller 38a. A control I / O signal and a chip enable signal (CE0-3) are output to the channels 0 and 1.

  Next, the operation procedure of the lane 0 controller 33a will be described with reference to FIG. First, the controller 38a sets the access information for channel 0 and the access information for channel 1 input from the processor 104 in the CH0 access information setting register 34a and the CH1 access information setting register 35a (steps S100 and S110). The controller 38a determines whether or not the parallel operation of the channel 0 and the channel 1 may be permitted based on the control information from the processor 104, the RyBy signal (RyBy0-3), and the like (step S120). Is permitted, the channel access information set in the CH0 access information setting register 34a and the CH1 access information setting register 35a is set in the operation permission register 36a.

  The I / F controller 37a responds to the access information by controlling the NAND I / F 32a based on the access information for channel 0 and channel 1 set in the operation permission register 36a under the control of the controller 38a. A control I / O signal and a chip enable signal (CE0-3) are output to the channels 0 and 1. As a result, access is made to the data of each block of the NAND flash 10 of channels 0 and 1 corresponding to the access information (step S130). The controller 38a determines whether or not this access is completed based on the RyBy signal or the like (step S140). If the access is completed, the unprocessed instruction is sent to the CH0 access information setting register 34a and CH1 access information setting register 35a. Is left (step S150), and if there is an unprocessed instruction, the above process is repeated. When there are no more unprocessed instructions, the process is terminated.

  As described above, the processor 104 performs an operation of outputting the access information set in the CH0 access information setting register 34a and the CH1 access information setting register 35a to the NAND controller 110. Based on the defective chip information, the processor 104 can perform bank parallel and bank interleaving using as many non-defective chips as possible in each lane even when a defective chip is generated. The access information including the combination (bank number combination) is output to the NAND controller 110. The processor 104 configures the logical bank so that the number of memory chips that can be accessed in parallel in each lane is maximized without using the defective chip, based on the defective chip information that can identify the defective chip in the physical bank. The logical / physical bank information indicating a combination of a plurality of physical banks Bank0 to Bank3 is dynamically set. The access information shown in FIG. 6 is formed based on the set logical / physical bank information. As will be described later, a logical bank refers to a virtual bank formed by a combination of a plurality of physical banks.

  Defective chip information indicating in which memory chip the defective chip is generated is registered in the NAND flash 10 as management information at the time of product shipment. Further, a defective chip (for example, a chip in which a defective block is generated at a predetermined threshold value or more) after the product shipment is also detected by the processor 104, and the defective chip information generated later is also updated and added as management information. Based on such defective chip information, the processor 104 dynamically sets combinations of physical banks Bank 0 to 3 that can secure the maximum number of combinations that can be accessed in parallel. Details thereof will be described later.

  Next, a combination of banks between channels in a lane will be described with reference to FIGS. FIG. 8 shows a case where there is a rule of selecting a chip that performs channel parallel operation from chips having the same bank number. On the other hand, in FIG. 9, the combination of chips that perform channel parallel operation is not defined as a chip having the same bank number, and a combination of bank numbers that can secure as many chips as possible in parallel is selected. doing. In FIGS. 8 and 9, Bank # 0 to Bank # 3, which are bank numbers with “#” above, indicate the numbers of the above-described virtual logical banks.

  In FIG. 8 and FIG. 9, white indicates a non-defective chip, and hatched indicates a defective chip. 8 and 9, the occurrence of defective chips is the same. 8 and 9, in the NAND flash 10 of channel 0, three defective chips are generated from four chips of bank number 0, and two defective chips are generated from four chips of bank number 1. One defective chip is generated from four chips, and no defective chip is generated from four chips of bank number 3. In the NAND flash 10 of the channel 1, no defective chip is generated from the four chips of the bank number 0, one defective chip is generated from the four chips of the bank number 1, and two chips from the four chips of the bank number 2 are generated. A defective chip is generated, and three defective chips are generated from the four chips of the bank number 3.

  In the case of FIG. 8, since a chip having the same bank number is selected between channels, the logical bank number (Bank # 0 to # 3) and the physical bank number (Bank 0 to 3) match. That is, the chip enable signal CE00 of channel 0 is connected to 4 chips of bank number 0 of channel 0, and the chip enable signal CE10 of channel 1 is connected to 4 chips of bank number 0 of channel 1. Similarly, the channel 0 chip enable signal CE01 is connected to the four chips of the channel 0 bank number 1, the channel 1 chip enable signal CE11 is connected to the channel 1 bank number 1 of 4 chips, and so on. The chip enable signal CE03 is connected to the four chips of the bank number 3 of the channel 0, and the chip enable signal CE13 of the channel 1 is connected to the four chips of the bank number 3 of the channel 1.

  In the case of FIG. 8, with respect to Bank # 0, the number of non-defective chips in Bank 0 of CH0 is 1 and the number of non-defective chips in Bank 0 of CH1 is 4. I can't. For Bank # 1, the number of channels that can be paralleled is 2 stacks, for Bank # 2, the number of channels that can be paralleled is 2 stacks, and for Bank # 3, the number of channels that can be paralleled is 1 stack. Therefore, the total number of possible channels in the case of FIG. 8 is 6 stacks.

  On the other hand, in FIG. 9, as described above, a combination of chips that perform channel parallel operation is not defined as a chip having the same bank number, and a bank that can secure as many chips as possible in channel parallel is ensured. A combination of numbers is selected. Therefore, the logical bank number (Bank # 0 to # 3) and the physical bank number (Bank 0 to 3) may not match. That is, in channel 0, the number of good chips decreases in the order of bank number 3, bank number 2, bank number 1, and bank number 0. In channel 1, the number of good chips is bank number 0, bank number 1, and bank number. 2. Since the bank numbers are decreased in the order of bank number 3, the banks of channels 0 and 1 are selected so that the number of non-defective chips is increased from the largest. That is, Bank # 0 is a combination of Bank3 of CH0 and Bank0 of CH1, Bank # 1 is a combination of Bank2 of CH0 and Bank1 of CH1, Bank # 2 is a combination of Bank1 of CH0 and Bank2 of CH1, Bank # 3 is a combination of Bank0 of CH0 and Bank3 of CH1. As a result, the number of channels parallel to Bank # 0 is 4 stacks, the number of channels parallel to Bank # 1 is 3 stacks, the number of channels parallel to Bank # 2 is 2 stacks, and the channel of Bank # 3 The number of parallel possible is 1 stack, and the number of parallel channels possible in the case of FIG. 9 is 10 stacks, which is increased by 4 stacks compared to FIG.

  FIG. 10 shows data to be written to each block when the lane is composed of 2 channels of CH0 and CH1, 1 channel is composed of 2 banks, 1 bank is composed of 4 chips, and 1 chip is composed of 4 blocks. An example is given. It is assumed that parallel operation is performed with a pair of “x” and “y” (for example, a0-x and a0-y) having the same data name (a0, b0, etc.). FIG. 11 shows channel parallel operation and bank interleaving operation when the data shown in FIG. 10 is written. In such a configuration, as shown in FIG. 10, it is assumed that a chip defect has occurred in chip 2 in bank 0 of channel 0, chip 2 in bank 1 of channel 1, and chip 3 in bank 1 of channel 1. .

  10 and FIG. 11, as in FIG. 8, shows the case where the same bank number is selected in CH0 and CH1 to perform channel parallel operation. When the restriction that the same bank number is selected is provided, the chip of the other channel having the same bank number as the chip in which the chip defect has occurred is not used. The number is 20 blocks.

  FIG. 12 shows an example of data to be written in each block in the case where the same bank number is selected and the restriction that the channel parallel operation is performed is eliminated and the number of unused chips is reduced as much as possible. FIG. 13 shows a channel parallel operation and a bank interleave operation when the data shown in FIG. 12 is written. In FIG. 12 and FIG. 13, after selecting the same bank number and the same chip number and selecting the combination for performing the channel parallel operation, the bank is arranged so that the non-defective chips remaining due to the defective chip are combined. Number and chip number are selected. Therefore, in this example, as shown in FIG. 13, it is possible to add a write operation from the 21st write block to the 24th write operation. In the 21st to 24th write operations, combinations of chips having different bank numbers are performed. That is, channel parallel and bank interleaving are performed by chip 2 in bank 1 of channel 0 and chip 2 in bank 0 of channel 1, and the total number of blocks for channel parallel writing is increased to 24 blocks.

  The bank number, chip number, and block number shown in FIGS. 11 and 13 indicate part of the contents of the access information that the processor 104 outputs to the lane 0 controller 33a of the NAND controller 110, for example. That is, the Bank number, Chip number, and Block number shown in FIGS. 11 and 13 show specific examples of the contents of the access information shown in FIG.

  For example, taking the 22nd write operation of FIG. 13 as an example, the operation of the NAND controller 110a for lane 0 will be described.

(22nd write operation)
Bank number = 1, Chip number = 2, and Block number = 1 are set in the CH0 access information setting register 34a, and Bank number = 0, Chip number = 2, Block number = 1 in the CH1 access information setting register 35a. Are set, and then these set data are set in the operation permission register 36a. The I / F controller 37a controls the NAND I / F 32a based on the set contents of the operation permission register 36a. As a result, the chip enable signal CE01 corresponding to the bank number = 1 of CH0 is asserted, the chip enable signal CE10 corresponding to the bank number = 0 of CH1 is asserted, and channel parallel drive of blocks having different bank numbers is performed. .

  Next, setting of access information performed by the processor 104 will be described. First, the management information managed by the processor 104 includes a defective chip table that can identify a chip defective portion as shown in FIG. In such a defective chip table, information for specifying a defective chip is registered in advance before product shipment.

  The processor 104 is shown in FIGS. 9, 12, and 13 so that the maximum number of memory chips that can be accessed in parallel in each lane without using a defective memory chip is based on the registered contents of the defective chip table. As described above, the logical / physical bank information indicating the combination of the plurality of physical banks Bank0 to 3 constituting the logical bank is determined. As a method for securing the maximum number, for example, as shown in FIG. 9, the number of good chips is changed from a large number to a small number, or the number of good chips is reduced to a large number. In addition, there is a method of sequentially selecting banks of channels 0 and 1 that are driven in parallel.

  The logical / physical bank information indicating the determined relationship between the logical bank and the physical bank is stored and registered in the NAND flash 10 and the RAM 20 as management information, and this logical / physical bank information is used until a new defective chip is generated. Thus, the access information shown in FIG. 6 is formed.

  Further, the processor 104 also detects defective chips that occur later after product shipment. For example, when all the blocks in the chip become defective blocks, or when a defective block exceeding the threshold value in the chip occurs, it is determined that a later defective chip has occurred. Then, when a late defective chip occurs, the processor 104 additionally registers the defective chip information in the defective chip table.

  In addition, when a new defective chip is generated, the processor 104 determines whether a memory chip that can be accessed in parallel in each lane without using the defective memory chip, based on the updated registered contents of the defective chip table. Re-combination is performed so that the maximum number is reached, and logical / physical bank information indicating the correspondence between the logical bank and the physical bank is determined again. The logical / physical bank information indicating the correspondence between the re-determined logical bank and physical bank is stored and registered as management information, and is shown in FIG. 6 using this logical / physical bank information until a new defective chip is generated. Access information is formed.

  As described above, in the first embodiment, a combination of a plurality of physical banks constituting a logical bank is set so that the number of memory chips that can be accessed in parallel in each lane is maximized based on the updated defective chip information. Since the logical / physical bank information to be shown is dynamically determined, it is possible to provide a memory system capable of ensuring the maximum number of combination chips that can be driven in parallel even when a defective chip occurs.

(Second Embodiment)
In the second embodiment, even when a block failure occurs, a plurality of physical banks constituting the logical bank are configured so that the number of blocks that can be accessed in parallel in each lane without using the defective block is maximized. The combination is determined dynamically.

  FIG. 14 shows an example in which a countermeasure against a block defect is further added to the countermeasure against the chip defect shown in FIG. FIG. 15 shows a channel parallel operation and a bank interleave operation when the data shown in FIG. 14 is written. In the case of FIG. 14, block 0 and block 1 in chip 2 of channel 0 bank 0, chip 3 in bank 1 of channel 0, block 0 and block 1 in chip 2 of bank 1 of channel 1, and channel 1 It is assumed that a chip defect has occurred in the chip 3 of the bank 1. In FIG. 14 and FIG. 15, after selecting the same bank number and the same chip number and selecting the combination for performing the channel parallel operation, the bank is set so that the non-defective chips remaining due to the defective chip are combined. Then, the bank number, the chip number, and the block number are selected so that the non-defective blocks remaining due to the defective block are combined. Therefore, in this example, a write operation in which the number of write blocks is 25th to 26th can be added. In the 25th to 26th write operations, combinations of in-chip blocks having different bank numbers are performed. That is, the block 2 of the chip 2 in the bank 0 of the channel 0 and the block 2 of the chip 2 of the bank 1 of the channel 1 are channel-paralleled, and the block 3 of the chip 2 of the bank 0 of the channel 0 and the channel 1 Channel parallelism is performed with the block 3 of the chip 2 of the bank 1, and the total number of blocks for channel parallel writing is increased to 26 blocks.

  14 and 15, in the 25th to 26th write operations, blocks having different bank numbers but the same chip number are set as a channel parallel operation group, but blocks having different bank numbers and chip numbers. May be a set of channel parallel operations.

Taking the 26th write operation of FIG. 15 as an example, the operation of the NAND controller 110a for lane 0 will be described.
(26th writing operation)
Bank number = 0, Chip number = 2, and Block number = 3 are set in the CH0 access information setting register 34a, and Bank number = 1, Chip number = 2, and Block number = 3 are set in the CH1 access information setting register 35a. Are set, and then these set data are set in the operation permission register 36a. The I / F controller 37a controls the NAND I / F 32a based on the set contents of the operation permission register 36a. As a result, the chip enable signal CE00 corresponding to the bank number = 0 of CH0 is asserted, the chip enable signal CE11 corresponding to the bank number = 1 of CH1 is asserted, and the channels in different bank numbers are channel-parallel driven. .

  FIGS. 16 and 17 show examples of dealing with block failures, similar to the operation examples shown in FIGS. 14 and 15. 16 and 17 show a case where each bank is configured by one chip. 16 and 17, two channels (CH0, CH1) in one lane are shown as in FIGS. FIG. 16 shows a case where there is a rule of selecting a chip that performs channel parallel operation from blocks having the same bank number. On the other hand, in FIG. 17, the combination of blocks for performing channel parallel operation is not defined as a block having the same bank number, and a combination of bank numbers that can secure as many blocks as possible in parallel with the channel is selected. doing.

  In FIG. 16 and FIG. 17, white portions indicate non-defective blocks, and hatched portions indicate defective blocks. In FIG. 16 and FIG. 17, the occurrence state of the defective chip is the same. Assume that the storage capacity of one chip in one bank is 8000 KB. 16 and 17, in the NAND flash 10 of the channel 0, no defective block is generated at the bank number 0, a defective block of 1000 KB is generated at the bank number 1, and a defective block of 2000 KB is generated at the bank number 2. In the bank number 3, a defective block of 3000 KB is generated. Further, in the NAND flash 10 of channel 1, a bad block of 3000 KB occurs at bank number 0, a bad block of 2000 KB occurs at bank number 1, a bad block of 1000 KB occurs at bank number 2, and a bank number 3 No bad block has occurred.

  In the case of FIG. 16, the block capacity capable of channel parallel is 5000 KB for Bank # 0, the block capacity capable of channel parallel is 6000 KB for Bank # 1, and the block capacity capable of channel parallel is for Bank # 2. Is 6000 KB, and with respect to Bank # 3, the block capacity capable of channel parallel is 5000 KB. Their total block capacity is 22000 KB.

  On the other hand, in FIG. 17, the combination of blocks for performing channel parallel operation is not defined as a block having the same bank number, and a combination of bank numbers that can secure as many blocks as possible used in channel parallel. Is selected. That is, in channel 0, the non-defective block capacity increases in the order of bank number 3, bank number 2, bank number 1, and bank number 0. In channel 1, the non-defective block capacity is bank number 0, bank number 1, bank number 2, Since the number increases in the order of bank number 3, the banks of channels 0 and 1 are selected so that the number of non-defective chips increases from the largest to the smallest. That is, Bank # 0 is a combination of Bank3 of CH0 and Bank0 of CH1, Bank # 1 is a combination of Bank2 of CH0 and Bank1 of CH1, Bank # 2 is a combination of Bank1 of CH0 and Bank2 of CH1, Bank # 3 is a combination of Bank0 of CH0 and Bank3 of CH1.

  As a result, in the case of FIG. 17, the block capacity capable of channel parallel is 5000 KB for Bank # 0, and the block capacity capable of channel parallel is 6000 KB for Bank # 1, which is the same as in FIG. For Bank # 2, the block capacity capable of channel parallel is 7000KB, and for Bank # 3, the block capacity capable of channel parallel is 8000KB. Compared with the case of FIG. Capacity is increasing.

  Next, setting of access information performed by the processor 104 will be described. First, the management information managed by the processor 104 includes a defect position table as shown in FIG. 14 that can identify a chip defect location and an in-chip block failure location. In such a defective position table, information for specifying defective chips and defective blocks is registered in advance before product shipment.

  Based on the registration contents of the defect location table, the processor 104 can change the maximum number of blocks that can be accessed in parallel in each lane without using a defective memory chip and a defective block. As shown, logical / physical bank information indicating a combination of a plurality of physical banks Bank0 to 3 constituting a logical bank is determined. As a technique for securing the maximum number, for example, as shown in FIG. 17, the number of non-defective blocks is changed from a large number to a small number, or the number of non-defective blocks is changed to a large number. In addition, there is a method of sequentially selecting banks of channels 0 and 1 that are driven in parallel.

  The logical / physical bank information indicating the determined correspondence relationship between the logical bank and the physical bank is stored and registered as management information, and this logical / physical bank information is used to generate a new defective chip as shown in FIG. Access information is formed.

  Further, the processor 104 also detects defective blocks that occur later after product shipment. For example, when all the blocks in the chip become defective blocks, or when a defective block exceeding the threshold value in the chip occurs, it is determined that a later defective chip has occurred. In addition, for a chip in which a defective block less than the threshold has occurred, it is determined that a subsequent defective block has occurred in a non-defective chip without causing a chip defect. Then, when a later defective chip occurs, the processor 104 additionally registers the defective chip information in the defect position table. Further, when a later defective block occurs in the non-defective chip, this defective block information is additionally registered in the defect position table.

  Further, when a new defective chip occurs or when a new defective block occurs, the processor 104 uses the defective memory chip and the defective block as described above based on the registered contents of the updated defect position table. Instead, recombination is performed so that the maximum number of blocks that can be accessed in parallel in each lane is determined, and logical / physical bank information indicating the correspondence between the logical bank and the physical bank is determined again. The logical / physical bank information indicating the correspondence between the re-determined logical bank and the physical bank is stored and registered as management information, and the logical / bank information is used until new defective chips or defective blocks are generated. 6 is formed.

  As described above, in the second embodiment, a plurality of physical banks constituting a logical bank are set so that the number of blocks that can be accessed in parallel in each lane is maximized based on the updated defective chip information and defective block information. Since the logical / physical bank information indicating the combination of these is dynamically determined, even when a defective chip or a defective block occurs, it is possible to provide a memory system that can secure the maximum number of combination blocks that can be driven in parallel. it can.

  In the second embodiment, when no defective chip is generated, or when one bank is composed of one memory chip, the processor 104 does not use a defective block as shown in FIG. In order to maximize the number of blocks that can be accessed in parallel in each lane, logical / bank information indicating a combination of a plurality of physical banks constituting the logical bank is dynamically determined, and based on the logical / bank information. Set access information.

  In the first and second embodiments, the processor 104 (firmware) dynamically determines logical / physical bank information indicating a combination of a plurality of physical banks constituting a logical bank. Although the access information is set based on the logical / physical bank information, the NAND controller 110 may be equipped with a function for dynamically determining the logical / physical bank information and setting the access information based on the logical / physical bank information. Good.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 host, 2 ATA interface, 4 drive control circuit, 10 NAND flash, 10a to 10d channel parallel operation elements, 20 RAM, 31a, 31b ECC circuit, 33a lane 0 controller, 33b lane 1 controller, 34a CH0 access information setting register, 32a, 32b NAND I / F 35a CH1 access information setting register, 36a, 36b operation enable register, 37a, 37b I / F controller, 38a, 38b controller, 104 processor, 110 NAND controller, 110a NAND controller for lane 0, 110b lane 1 NAND controller.

Claims (6)

Non-volatile semiconductor memory having a plurality of channel parallel operation elements capable of operating in parallel, each channel parallel operation element has a plurality of physical banks that can be bank interleaved, each physical bank has a plurality of memory chips, Each memory chip has a non-volatile semiconductor memory having a plurality of physical blocks which are data erasing units, and
One is assigned corresponding to a lane composed of a plurality of channel parallel operation elements, is individually connected in units of physical banks, and is connected by a plurality of chip enable signals that are commonly connected to a plurality of memory chips in one physical bank. A plurality of memory controllers that drive the memory chips in each physical bank included in the plurality of channel parallel operation elements in the lane in parallel by selecting a physical bank; and
Based on the defective memory chip information that can identify the defective memory chip in each physical bank, the logical bank is configured so that the number of memory chips that can be accessed in parallel in each lane without using the defective memory chip is maximized. A controller that dynamically sets logical / physical bank information indicating a combination of a plurality of physical banks;
The memory system, wherein the plurality of memory controllers drive and control the chip enable signal based on logical / physical bank information set by the controller.   The controller is based on the defective memory chip information that can identify the defective memory chip in each physical bank and the defective block information that can identify the defective block in each memory chip, without using the defective memory chip and the defective block. The logical / physical bank information indicating a combination of a plurality of physical banks constituting a logical bank is dynamically set so that the number of blocks that can be accessed in parallel in the lane is maximized. Memory system.   The controller selects the physical bank information by sequentially selecting physical banks having a smaller number of defective memory chips or physical banks having a larger number of defective memory chips from a plurality of channel parallel operation elements constituting one lane. The memory system according to claim 1, wherein the memory system is formed.   The controller forms the logical / physical bank information by sequentially selecting memory chips having a smaller number of defective blocks or memory chips having a larger number of defective blocks from a plurality of channel parallel operation elements constituting one lane. The memory system according to claim 2, wherein:   5. The memory controller according to claim 1, wherein an error correction code is added to a plurality of data units accessed in parallel to a plurality of channel parallel operation elements constituting one lane. Memory system described in one.   6. The controller according to claim 1, wherein the controller determines that a memory chip having a defective block equal to or greater than a predetermined threshold is defective, and updates and adds information on the memory chip determined to be defective to the defective memory chip information. The memory system according to any one of the above.

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