JP2013062668A - Phase adjustment circuit with duty correction, and serializer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase adjustment circuit with duty correction that suppress jitter caused by variations in clock, and a serializer.SOLUTION: A phase adjustment circuit with duty correction receives input of a positive clock signal and a negative clock signal, and outputs a positive clock output signal and a negative clock output signal obtained by adjusting duty and phases of the positive clock signal and the negative clock signal.

Description

  The present invention relates to a phase adjustment circuit and a serializer with a duty correction, which are inputted with a positive clock signal and a negative clock signal, and which output a positive clock output signal and a negative clock output signal obtained by adjusting the duty and phase of the positive clock signal and the negative clock signal. About.

  In recent communication systems, differential high-speed serial communication is common. In serial communication, parallel data is serialized by synchronizing with a high-speed differential clock.

  By the way, in recent years, the variation in the performance of transistors in the same chip cannot be ignored due to the increase in clock speed and device miniaturization. Due to variations in the performance of transistors in the same chip, it has been regarded as a problem that the duty and edge positions of clocks that should originally have a differential relationship also differ. This is because the variation in the duty of the clock that is the reference of operation becomes deterministic jitter of the serial data.

  As a method for suppressing deterministic jitter, for example, Patent Document 1 discloses a method of constantly reducing current consumption by filling a difference in current consumption of an output circuit caused by a data pattern to reduce jitter caused by power supply fluctuations. Is described.

  Japanese Patent Application Laid-Open No. H10-228688 describes that a CPU detects a phase detection method as a method for correcting a phase difference generated between differential signals.

  However, the invention described in Patent Document 1 cannot suppress jitter due to clock duty and phase variations. In the invention described in Patent Document 2, since there is no correction for duty variation, jitter caused by duty variation cannot be suppressed.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a phase adjustment circuit with a duty correction and a serializer capable of suppressing jitter caused by clock variation.

  In order to achieve the above object, the present invention employs the following configuration.

  The present invention relates to a phase adjustment circuit with a duty correction, which receives a positive clock signal and a negative clock signal and outputs a positive clock output signal and a negative clock output signal obtained by adjusting the duty and phase of the positive clock signal and the negative clock signal. An average voltage detector that detects an average voltage value of the positive clock output signal, a comparator that compares a reference voltage with the average voltage value, and outputs a control signal according to a comparison result, and the positive clock signal is input. A duty adjustment unit that changes the duty of the positive clock signal that is input so that the average voltage value and the reference voltage are equal to each other according to the control signal; and a positive that detects a rise time of the positive clock output signal A rising edge detecting section; a positive falling edge detecting section that detects a falling time of the positive clock output signal; and A negative rise detection unit for detecting a rise time of the lock output signal; a negative fall detection unit for detecting a fall time of the negative clock output signal; and the positive rise time and the negative fall time. A positive phase detector that outputs a positive phase difference signal, a negative phase detector that outputs a negative phase difference signal between the positive fall time and the negative rise time, and the positive phase difference signal A fall time adjusting unit that changes a fall time of the negative clock signal according to the delay time, and a rise time of the negative clock signal output from the fall time adjusting unit is changed according to the negative phase difference signal. And a rise time adjustment unit that serves as the negative clock output signal.

  The present invention is connected to a phase adjustment circuit with a duty correction that outputs a positive clock output signal and a negative clock output signal in which the duty and phase of the positive clock signal and the negative clock signal are adjusted. A serializer that converts parallel data into serial data in synchronization with an output signal, wherein the phase adjustment circuit with duty correction includes an average voltage detection unit that detects an average voltage value of the positive clock output signal, a reference voltage, and the average A comparator that compares voltage values and outputs a control signal according to the comparison result, and the positive clock signal are input, and the average voltage value and the reference voltage are input to be equal to each other according to the control signal A duty adjustment unit for changing the duty of the positive clock signal and a rise time of the positive clock output signal are detected. A positive rising edge detector, a positive falling edge detector for detecting a falling time of the positive clock output signal, a negative rising edge detector for detecting a rising time of the negative clock output signal, and the negative clock output A negative fall detection unit for detecting a fall time of the signal, a positive phase detection unit for outputting a positive phase difference signal between the positive rise time and the negative fall time, and the positive fall A negative phase detection unit that outputs a negative phase difference signal between time and the negative rise time; and a fall time adjustment unit that changes the fall time of the negative clock signal according to the positive phase difference signal; The rise time of the negative clock signal output from the fall time adjustment unit is changed in accordance with the negative phase difference signal to rise as the negative clock output signal. Having a time adjuster.

  The present invention provides a serializer that converts parallel data into serial data in synchronization with a positive clock signal and a negative clock signal, and serializes the parallel data as serial data in synchronization with the positive clock signal and the negative clock signal. And serial data synchronized with a positive clock signal by the serializing means and negative serial data synchronized with the negative clock signal, and the duty and phase of the positive serial data and the negative serial data are adjusted. A phase adjustment circuit with duty correction that outputs positive serial output data and negative serial output data, and the phase adjustment circuit with duty correction detects an average voltage value of the positive serial output data. And the reference voltage and the average voltage value A comparator for outputting a control signal, and a duty for changing the duty of the positive serial data inputted so that the average serial voltage value is equal to the reference voltage in accordance with the control signal. An adjustment unit; a positive rise detection unit that detects a rise time of the positive serial output data; a positive fall detection unit that detects a fall time of the positive serial output data; and a rise time of the negative serial output data A negative rise detection unit for detecting the negative serial output data, a negative fall detection unit for detecting the fall time of the negative serial output data, and a positive phase difference signal between the positive rise time and the negative fall time. Outputs a positive phase detector and outputs a negative phase difference signal between the positive fall time and the negative rise time Phase detection unit, a fall time adjustment unit that changes the fall time of the negative serial data according to the positive phase difference signal, and a rise time of the negative serial data output from the fall time adjustment unit. And a rise time adjustment unit that changes the negative phase difference signal to generate the negative serial output data.

  According to the present invention, jitter caused by clock variation can be suppressed.

It is a figure explaining the phase adjustment circuit with a duty correction of 1st embodiment. It is a figure explaining the functional structure of the phase adjustment circuit with a duty correction of 1st embodiment. It is a flowchart explaining operation | movement of the duty adjustment function part of 1st embodiment. It is a figure explaining the adjustment by a duty adjustment part. It is a flowchart explaining the fall time function part of 1st embodiment. It is a flowchart explaining the rise time function part of 1st embodiment. It is a figure which shows the phase adjustment circuit with a duty correction by which arrangement | positioning of the fall time adjustment part and the rise time adjustment part is reverse in 1st embodiment. It is a figure explaining the phase adjustment circuit with a duty correction of 2nd embodiment. It is a figure explaining the role of the delay circuit in 2nd embodiment. It is a figure explaining the phase adjustment circuit with a duty correction of 3rd embodiment. It is a figure explaining the phase adjustment circuit with a duty correction of 4th embodiment. It is a flowchart explaining operation | movement of the duty adjustment function part of 4th embodiment. It is a flowchart explaining the fall time adjustment function part of 4th embodiment. It is a flowchart explaining the rise time adjustment function part of 4th embodiment. It is a figure explaining the serializer of 5th embodiment. It is a figure which shows a mode that parallel data is serialized synchronizing with a positive clock output signal and a negative clock output signal. It is a figure explaining the case where it serializes with the clock with a dispersion | variation in a duty. It is a figure explaining the case where it serializes with the clock from which the edge of a clock has dispersion | variation. It is a figure explaining the serializer of 6th embodiment. It is a flowchart explaining operation | movement of the serializer and phase adjustment circuit with a duty correction of 6th Embodiment. It is a figure which shows the communication system of 7th embodiment.

The present invention adjusts the differential phase difference while optimally controlling the duty of the differential clock or differential serial data.
(First embodiment)
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a phase adjustment circuit with duty correction according to the first embodiment.

  The phase adjustment circuit 100 with duty correction of this embodiment has an input terminal IN1 to which a positive clock signal CK1 is input and an input terminal IN2 to which a negative clock signal CK2 is input. The phase adjustment circuit 100 with duty correction includes an output terminal OUT1 from which a positive clock output signal CK10 is output, and an output terminal OUT2 from which a negative clock output signal CK20 is output.

  In the present embodiment, the positive clock signal CK1 and the negative clock signal CK2 are signals in which binary voltage levels of a high level (hereinafter referred to as H level) and a low level (hereinafter referred to as L level) transition at a constant cycle. The phase adjustment circuit 100 with duty correction of the present embodiment has a function of adjusting the duty and phase of the positive clock signal CK1 and the negative clock signal CK2, and the positive clock output signal CK10 and the negative clock output whose phase and duty are adjusted. The signal CK20 is output.

  The phase adjustment circuit 100 with duty correction of the present embodiment includes an average voltage detection unit 110, a reference voltage generation unit 120, a comparator 130, a duty adjustment unit 140, a positive rising detection unit 150, a positive falling detection unit 151, a negative Falling detection section 152, negative rising detection section 153, positive phase detection section 160, negative phase detection section 161, falling time adjustment section 170, and rise time adjustment section 171.

  The average voltage detector 110 detects the average value voltage Vav of the positive clock signal CK1. The comparator 130 compares the reference voltage Vref generated by the reference voltage generation unit 120 with the average value voltage Vav, and outputs a control signal Vcnt according to the comparison result. The duty adjustment unit 140 adjusts the duty of the positive clock output signal CK10 according to the control signal Vcnt.

  The positive rising edge detection unit 150 detects the time when the positive clock output signal CK10 transitions from the L level to the H level as a positive rising time, and the positive falling edge detection unit 151 detects the positive clock output signal CK10 from the H level. The transition time to the L level is detected as a positive fall time.

  The negative falling detection unit 152 detects the time when the negative clock output signal CK20 transits from the H level to the L level as a negative falling time, and the negative rising detection unit 153 detects the negative clock output signal CK20 from the L level. The time to transition to the H level is detected as a negative rise time.

  The positive phase detector 160 is a positive phase difference signal corresponding to the difference between the positive rise time detected by the positive rise detector 150 and the negative fall time detected by the negative fall detector 152. Output vdphp. The negative phase detection unit 161 compares the positive fall time detected by the positive fall detection unit 151 with the negative rise time detected by the negative rise detection unit 153, and determines the negative phase according to the comparison result. The phase difference signal vdphm is output.

  The fall time adjustment unit 170 receives the negative clock signal CK2, and changes the time during which the negative clock output signal CK20 transitions from the H level to the L level according to the positive phase difference signal vdphp, and outputs the signal.

  The rise time adjustment unit 171 receives the negative clock signal CK2 and changes the time during which the negative clock output signal CK20 transits from the L level to the H level according to the negative phase difference signal vdphm and outputs the changed signal.

  The functional configuration of the phase adjustment circuit 100 with duty correction according to this embodiment will be described below with reference to FIG. FIG. 2 is a diagram illustrating a functional configuration of the phase adjustment circuit with duty correction according to the first embodiment.

  The phase adjustment circuit 100 with duty correction according to the present embodiment includes a duty adjustment function unit 200, a fall time adjustment function unit 300, and a rise time adjustment function unit 400.

  The duty adjustment function unit 200 sets the clock duty of the positive clock signal CK1 to an appropriate value. The duty adjustment function unit 200 of this embodiment includes an average voltage detection unit 110, a reference voltage generation unit 120, a comparator 130, and a duty adjustment unit 140.

  The fall time adjustment function unit 300 performs control to make the fall time of the negative clock output signal CK20 equal to the rise time of the positive clock output signal CK10. The fall time adjustment function unit 300 of this embodiment includes a positive rise detection unit 150, a negative fall detection unit 152, a positive phase detection unit 160, and a fall time adjustment unit 170.

  The rise time adjustment function unit 400 performs control to make the rise time of the negative clock output signal CK20 equal to the fall time of the positive clock output signal CK10. The rise time adjustment function unit 400 of the present embodiment includes a positive fall detection unit 151, a negative rise detection unit 153, a negative phase detection unit 161, and a rise time adjustment unit 171.

  The operation of the duty adjustment function unit 200 of this embodiment will be described below with reference to FIG. FIG. 3 is a flowchart for explaining the operation of the duty adjustment function unit of the first embodiment. FIG. 3 shows a case where it is assumed that the duty of the positive clock output signal CK10 is not 50%.

  In the duty adjustment function unit 200 of the present embodiment, the positive clock output signal CK10 is taken into the average voltage detection unit 110, and the average voltage Vav is detected (step S301). Note that the average voltage detection unit 110 of the present embodiment may be realized by a low-pass filter circuit having a sufficiently low cutoff frequency with respect to the positive clock output signal CK10.

  Subsequently, the duty adjustment function unit 200 compares the reference voltage Vref and the average voltage Vav with the comparator 130 (step S302), and determines whether or not the reference voltage Vref and the average voltage Vav are equal (step S303).

  In step S303, when the reference voltage Vref and the average voltage Vav are equal, the duty adjustment function unit 200 ends the process.

  When the reference voltage Vref and the average voltage Vav are not equal in step S303 and the reference voltage Vref> average voltage Vav (step S304), the duty adjustment function unit 200 uses the duty adjustment unit 140 to set the duty ratio of the positive clock output signal CK10. Increase (step S305) and return to step S302.

  If the reference voltage Vref> the average voltage Vav is not satisfied in step S304, the duty adjustment unit 140 decreases the duty ratio of the positive clock output signal CK10 (step S306), and the process returns to step S302.

  Note that the duty adjustment unit 140 of the present embodiment may be realized by adjusting the current value by, for example, connecting an inverter that can change the current value, and is not necessarily a digital using a CPU (Central Processing Unit) or the like. Control is not required. The reference voltage Vref of the present embodiment is preferably set to a value that is equal to the threshold value of the driver to which the positive clock output signal CK10 is input. In the present embodiment shown in FIG. 1, the driver to which the positive clock output signal CK10 is input is shown as an inverter.

Hereinafter, an adjustment method of the duty adjustment unit 140 when the duty of the positive clock output signal CK10 is larger than 50 will be described with reference to FIG. FIG. 4 is a diagram illustrating adjustment by the duty adjustment unit. FIG. 4A illustrates the average voltage detected by the average voltage detection unit 110 when the duty is greater than 50%. FIG. 4 (B)
These are figures which show adjustment of the duty by the duty adjustment part 140. FIG. FIG. 4C is a diagram for explaining the positive clock output signal CK10 after the duty adjustment.

  As shown in FIG. 4A, when the duty of the positive clock output signal CK10 is greater than 50%, the average voltage Vav is higher than (H level voltage−L level voltage) / 2. In this embodiment, since the reference voltage Vref is (H level voltage−L level voltage) / 2, in this case, when the average voltage Vav and the reference voltage Vref are compared, the reference voltage Vref <average voltage Vav.

  Hereinafter, the configuration of the duty adjustment unit 140 of this embodiment will be described with reference to FIG. The duty adjustment unit 140 of this embodiment includes an input terminal IN1, an output terminal OUT1, P channel transistors M1 and M2, n channel transistors M3 and M4, and current sources 141 and 142.

  The source of the transistor M1 is connected to the power supply line via the current source 141, and the drain of the transistor M1 is connected to the drain of the transistor M3. The source of the transistor M3 is grounded. The gate of the transistor M1 and the gate of the transistor M3 are connected to the input terminal IN1, and the positive clock signal CK1 is input. A connection point between the drain of the transistor M1 and the drain of the transistor M3 is connected to the gate of the transistor M2 and the gate of the transistor M4.

  The source of the transistor M2 is connected to the power supply line, and the drain of the transistor M2 is connected to the drain of the transistor M4. The source of the transistor M4 is grounded via the current source 142. A connection point between the drain of the transistor M1 and the drain of the transistor M3 is connected to the output terminal OUT1, and outputs a positive clock output signal CK10.

  In the duty adjustment unit 140 of this embodiment, when the average voltage Vav is higher than the reference voltage, the duty of the positive clock output signal CK10 is decreased. Specifically, the duty adjustment unit 140 controls the current sources 141 and 142 to increase the current values flowing through the transistors M1 and M3 from before the control, and to decrease the current values flowing through the transistors M2 and M4 from before the control. . The value of the current flowing through the transistors M1 to M4 is controlled by a control signal Vcnt output from the comparator 130. In the duty adjustment unit 140 of the present embodiment, for example, every time a control signal Vcnt instructing control of the current value is received, the current value is changed by a predetermined value so that the average voltage Vav and the reference voltage Vref are equal. Also good.

  In this embodiment, by this control, as shown in FIG. 4C, the rising of the positive clock output signal CK10 is delayed, the falling is accelerated, and the duty is improved to 50%.

  Although FIG. 4 illustrates the case where the duty is greater than 50%, the same control can be performed when the duty is smaller than 50%. When the duty is smaller than 50%, the average voltage Vav is smaller than the reference voltage Vref. Therefore, the duty adjustment unit 140 may increase the rising edge of the positive clock output signal CK10 and delay the falling edge.

  Next, operations of the fall time adjustment function unit 300 and the rise time adjustment function unit 400 of this embodiment will be described with reference to FIGS.

  FIG. 5 is a flowchart for explaining the fall time function unit of the first embodiment. In the fall time adjustment function unit 300 of this embodiment, the positive rise detection unit 150 detects the rise time of the positive clock output signal CK10, and the negative fall detection unit 152 sets the fall time of the negative clock output signal CK20. Detection is performed (step S501). Subsequently, the positive phase detector 160 outputs the difference value between the rising time of the positive clock output signal CK10 and the falling time of the negative clock output signal CK20 to the falling time adjustment unit 170 as a positive phase difference signal vdphp ( Step S502).

  The fall time adjustment unit 170 determines whether the rise time of the positive clock output signal CK10 is equal to the fall time of the negative clock output signal CK20 based on the phase difference signal vdphp (step S503). If both are equal in step S503, the fall time adjustment unit 170 ends the process.

  If they are not equal in step S503, the fall time adjustment unit 170 changes the time for the negative clock output signal CK20 to transition from the H level to the L level, that is, the fall time of the negative clock output signal CK20 (step S504). . In the present embodiment, the fall time adjustment unit 170 is based on the phase difference signal vdphp, until the rise time of the positive clock output signal CK10 and the fall time of the negative clock output signal CK20 are equal. Adjust the fall time. Then, the fall time adjustment unit 170 returns to step S501.

  FIG. 6 is a flowchart illustrating the rise time function unit of the first embodiment. In the rise time adjustment function unit 400 of this embodiment, the positive fall detection unit 151 detects the fall time of the positive clock output signal CK10, and the negative rise detection unit 153 detects the rise time of the negative clock output signal CK20. (Step S601). Subsequently, the negative phase detection unit 161 outputs a difference value between the falling time of the positive clock output signal CK10 and the rising time of the negative clock output signal CK20 to the rising time adjustment unit 171 as a negative phase difference signal vdphm (step S1). S602).

  Based on the phase difference signal vdphm, the rising time adjustment unit 171 determines whether the falling time of the positive clock output signal CK10 is equal to the rising time of the negative clock output signal CK20 (step S603). If both are equal in step S603, the rise time adjustment unit 171 ends the process.

  If they are not equal in step S603, the rise time adjustment unit 171 changes the time for the negative clock output signal CK20 to transition from the L level to the H level, that is, the rise time of the negative clock output signal CK20 (step S604). In the present embodiment, the rise time adjustment unit 171 increases the rise time of the negative clock output signal CK20 until the fall time of the positive clock output signal CK10 is equal to the rise time of the negative clock output signal CK20 based on the phase difference signal vdphm. Adjust. Then, the rise time adjustment unit 171 returns to Step S601.

  As described above, in this embodiment, the duty adjustment function unit 200 controls the duty of the positive clock output signal CK10 to be 50%. In the present embodiment, the falling time adjustment function unit 300 adjusts the rising time of the positive clock output signal CK10 and the falling time of the negative clock output signal CK20 to be equal. Further, in the present embodiment, the rise time adjustment function unit 400 adjusts the fall time of the positive clock output signal CK10 and the rise time of the negative clock output signal CK20 to be equal. That is, in this embodiment, adjustment is made so that the phases of the positive clock output signal CK10 and the negative clock output signal CK20 are equal.

  Therefore, in the present embodiment, the phase difference between the differential clocks can be adjusted while optimally controlling the duties of the positive clock output signal CK10 and the negative clock output signal CK20, which are differential clocks, and jitter caused by clock variations. Can be suppressed.

  In this embodiment, the fall time adjustment unit 170 is arranged on the input terminal IN2 side, and the rise time adjustment unit 171 is arranged on the output terminal OUT2 side. However, the arrangement of both is not limited to this. For example, the arrangement of the fall time adjustment unit 170 and the rise time adjustment unit 171 may be reversed.

  FIG. 7 is a diagram illustrating a phase adjustment circuit with duty correction in which the arrangement of the fall time adjustment unit and the rise time adjustment unit is reversed in the first embodiment.

  In the phase adjustment circuit 100A with duty correction shown in FIG. 7, the rise time adjustment unit 171 is arranged on the input terminal IN2 side, and the phase difference signal output from the positive phase detection unit 160 is input. The fall time adjustment unit 170 is disposed on the output terminal OUT2 side, and the phase difference signal output from the negative phase detection unit 161 is input thereto.

  The phase adjustment circuit 100A with duty correction can achieve the same effect as the phase adjustment circuit 100 with duty correction even in the above configuration.

(Second embodiment)
A second embodiment of the present invention will be described below with reference to the drawings. The second embodiment of the present invention is different from the first embodiment in that a delay circuit is provided. In the following description of the second embodiment of the present invention, the same reference numerals as those used in the description of the first embodiment are given to those having the same functional configuration as the first embodiment, and the description thereof Is omitted.

  FIG. 8 is a diagram for explaining the phase adjustment circuit with duty correction according to the second embodiment. The phase adjustment circuit 100B with duty correction according to the present embodiment includes a delay circuit 180 on the output side of the duty adjustment unit 140. The positive clock output signal CK10 output from the duty adjustment unit 140 is output from the output terminal OUT1 via the delay circuit 180.

  The difference between the case where the delay circuit 180 is provided and the case where the delay circuit 180 is not provided will be described below with reference to FIG. FIG. 9 is a diagram for explaining the role of the delay circuit in the second embodiment.

  When the delay circuit 180 is not provided, the time difference t1 [s] is increased in the duty adjustment unit 140 until the positive clock signal CK1 is input from the input terminal IN1 to the duty adjustment unit 140 and output as the positive clock output signal CK10. Arise.

  On the other hand, a time difference t2 [s] is generated before the negative clock signal CK2 is input from the input terminal IN2 to the falling time adjustment unit 170 and output as the negative clock output signal CK21. Further, a time difference t3 [s] occurs until the negative clock output signal CK21 is input to the rise time adjustment unit 171 and output as the negative clock output signal CK20.

  That is, the negative clock output signal CK2 has a time difference of t2 + t3 [s] before being output from the output terminal OUT2.

  In the delay circuit 180 of the present embodiment, the time difference t2 + t3 [s] generated when the positive clock output signal CK10 is output and the time difference t2 + t3 [s] generated when the negative clock output signal CK20 is output are the duty adjustment function unit. 200, the case where adjustment is not possible by the control of the fall time adjustment function unit 300 and the rise time adjustment function unit 400 is considered.

  In the present embodiment, the delay circuit 180 delays the positive clock output signal CK10 output from the duty adjustment unit 140 by t4 [s]. In the delay circuit 180 of this embodiment, the time difference t1 + t4 [s] from when the positive clock signal CK1 is input to the duty adjustment unit 140 until the positive clock output signal CK10 is output from the output terminal OUT1 is the time difference t2 + t3 [s. It is preferable to set it to be the same as

  By providing the delay circuit 180 in this manner, jitter caused by clock variation can be suppressed.

(Third embodiment)
A third embodiment of the present invention will be described below with reference to the drawings. The third embodiment of the present invention is different from the first embodiment in that a frequency divider is provided. In the following description of the third embodiment of the present invention, the same reference numerals as those used in the description of the first embodiment are given to those having the same functional configuration as the first embodiment, and the description thereof Is omitted.

  FIG. 10 is a diagram illustrating a phase adjustment circuit with duty correction according to the third embodiment.

  The phase adjustment circuit 100C with duty correction of the present embodiment includes frequency dividers 190 and 191 that divide the positive clock output signal CK10 output from the duty adjustment unit 140, and a negative clock output signal output from the rise time adjustment unit 171. Frequency dividers 192 and 193 for dividing the frequency of CK20 are included.

  The frequency dividers 190 to 193 of this embodiment all have the same configuration. In the present embodiment, the positive clock output signal CK10 divided by the frequency divider 190 is supplied to the positive rising edge detection unit 150. The positive clock output signal CK10 divided by the frequency divider 191 is supplied to the positive falling edge detection unit 151.

  In this embodiment, the negative clock output signal CK20 divided by the frequency divider 192 is supplied to the negative falling detection unit 152, and the negative clock output signal CK20 divided by the frequency divider 193 is negative rising. This is supplied to the detection unit 153.

  Therefore, in this embodiment, the positive phase detector 160 compares the rising time and the falling time of the divided positive clock output signal CK10. The negative phase detector 161 compares the fall time and the rise time of the divided negative clock output signal CK10. Therefore, in this embodiment, the comparison time becomes longer in the positive phase detection unit 160 and the negative phase detection unit 161. For this reason, in this embodiment, the operation speeds of the positive phase detection unit 160 and the negative phase detection unit 161 may be slower than those in the case where no frequency division is performed.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. The fourth embodiment of the present invention is different from the first embodiment in that a DAC (Digital to Analog Converter) is provided on the output side of the phase detector. In the following description of the fourth embodiment of the present invention, the same reference numerals as those used in the description of the first embodiment are assigned to those having the same functional configuration as the first embodiment, and the description thereof Is omitted.

  FIG. 11 is a diagram illustrating a phase adjustment circuit with duty correction according to the fourth embodiment. The phase adjustment circuit with duty correction 100D of the present embodiment includes a terminal INC to which a calibration signal is input, and DACs 195, 196, and 197.

  The output of the comparator 130 is supplied to the DAC 195. The output of the DAC 195 is supplied to the duty adjustment unit 140. The output of the positive phase detector 160 is supplied to the DAC 196. The output of the DAC 196 is supplied to the fall time adjustment unit 170. The output of the negative phase detector 161 is supplied to the DAC 197. The output of the DAC 197 is supplied to the rise time adjustment unit 171.

  The DACs 195 to 197 hold values to be output according to the calibration signal. The calibration signal is a signal input in order to match the level of serial data synchronized with the positive clock output signal CK10 and the negative clock output signal CK20. The frequency of the calibration signal is a frequency selected from a plurality of preset frequencies.

  The operation of the duty adjustment function unit of this embodiment will be described below with reference to FIGS. FIG. 12 is a flowchart for explaining the operation of the duty adjustment function unit of the fourth embodiment.

  In FIG. 12, when the calibration signal is turned on, the duty adjustment function unit starts its operation.

  The processing in step S1201 and the processing in step S1202 in FIG. 12 are the same as the processing in step S301 and the processing in step S302 in FIG.

  Subsequently, in the present embodiment, it is determined whether or not the reference voltage Vref and the average voltage Vav are equal or whether or not the magnitude relationship between the reference voltage Vref and the average voltage Vav is reversed (step S1203).

  In step S1203, when the reference voltage Vref and the average voltage Vav are equal, or when the magnitude relationship between the reference voltage Vref and the average voltage Vav is reversed, the duty adjustment processing in the present embodiment is terminated and the calibration signal is turned off. The

  In step S1203, if the reference voltage Vref and the average voltage Vav are not equal, or the magnitude relationship between the reference voltage Vref and the average voltage Vav is not reversed, it is determined whether or not the reference voltage Vref> the average voltage Vav. (Step S1204).

  If reference voltage Vref> average voltage Vav in step S1204, DAC 195 moves 1 LSB (Least Significant Bit) to increase the duty of positive clock output signal CK10 (step S1205), and returns to step S1202.

  When the reference voltage Vref> the average voltage Vav is not satisfied in step S1204, the DAC 195 moves 1LSB (moves (step S1206) to decrease the duty of the positive clock output signal CK10), and returns to step S1202. Works accordingly.

  Next, operations of the fall time adjustment function unit and the rise time adjustment function unit according to this embodiment will be described with reference to FIGS.

  FIG. 13 is a flowchart for explaining the fall time adjustment function unit of the fourth embodiment.

  In this embodiment, when the calibration signal is turned on, the positive rising edge detection unit 150 detects the rising time of the positive clock output signal CK10, and the negative falling edge detection unit 152 determines the falling time of the negative clock output signal CK20. Detection is performed (step S1301).

  Subsequently, the positive phase detector 160 outputs a difference value between the rising time of the positive clock output signal CK10 and the falling time of the negative clock output signal CK20 as a positive phase difference signal vdphp, and the output of the DAC 196 is set to a positive level. Move 1 LSB to decrease the phase difference (step S1302).

  The fall time adjustment unit 170 is based on the phase difference signal vdphp output from the DAC 196, and the rise time of the positive clock output signal CK10 and the fall time of the negative clock output signal CK20 are equal or the magnitude relationship between the two is reversed. It is determined whether or not (step S1303). If both are equal or the magnitude relationship is reversed in step S1303, the calibration signal is turned off, and the fall time adjustment unit 170 ends the process. If both are not equal or the magnitude relationship is not reversed in step S1303, the process returns to step S1301.

  FIG. 14 is a flowchart illustrating the rise time adjustment function unit according to the fourth embodiment.

  In the present embodiment, when the calibration signal is turned on, the positive falling detection unit 151 detects the falling time of the positive clock output signal CK10, and the negative rising detection unit 153 determines the rising time of the negative clock output signal CK20. It is detected (step S1401).

  Subsequently, the negative phase detector 161 outputs a difference value between the falling time of the positive clock output signal CK10 and the rising time of the negative clock output signal CK20 as a negative phase difference signal vdphm, and outputs the output of the DAC 197 to a positive level. Move 1 LSB to decrease the phase difference (step S1402).

  Based on the phase difference signal vdphm output from the DAC 197, the rising time adjustment unit 171 determines whether the rising time of the positive clock output signal CK10 is equal to the falling time of the negative clock output signal CK20, or the magnitude relationship between the two is reversed. It is determined whether or not (step S1403). If both are equal or the magnitude relationship is reversed in step S1403, the calibration signal is turned off, and the rise time adjustment unit 171 ends the process. If both are not equal or the magnitude relationship is not reversed in step S1403, the process returns to step S1401.

  In the present embodiment, an effect equivalent to that of the first embodiment can be obtained by the above control.

(Fifth embodiment)
The fifth embodiment of the present invention will be described below with reference to the drawings. In the fifth embodiment of the present invention, any of the phase adjustment circuits with duty correction of the first to fourth embodiments is applied to a serializer that converts 4-bit parallel data into serial data. In the following description of the fifth embodiment of the present invention, the same reference numerals as those used in the description of the first embodiment are assigned to those having the same functional configuration as the first embodiment, and the description thereof Is omitted.

  FIG. 15 is a diagram illustrating the serializer according to the fifth embodiment. FIG. 15 shows an example in which the phase adjustment circuit 100 with duty correction of the first embodiment is applied.

  The serializer 500 shown in FIG. 15 converts 4-bit parallel data d [0; 3] into differential serial data D1 and D2. The serializer 500 converts the parallel data d [0; 3] into serial data D1 and D2 in synchronization with the positive clock output signal CK10 and the negative clock output signal CK20 output from the phase adjustment circuit 100 with duty correction. The effect of the phase adjustment circuit 100 with duty correction will be described below with reference to FIG.

FIG. 16 is a diagram illustrating a state in which parallel data is serialized in synchronization with the positive clock output signal and the negative clock output signal. In FIG. 16, the dotted line indicates that the parallel data is synchronized with the edge of either the positive clock output signal CK10 or the negative clock output signal CK20. The numbers described in the serial data in FIG. 16 indicate which data is output from the parallel data d [0; 3].

  Since the phase adjustment circuit 100 with duty correction is controlled so that the edges of the positive clock output signal CK10 and the negative clock output signal CK20 are equal and the duty is 50%, there is no jitter due to clock variations in FIG. I understand that.

  The effects of the present embodiment will be described below with reference to FIGS. FIG. 17 is a diagram for explaining a case where serialization is performed using clocks with varying duty.

  In the example of FIG. 17, the edges of the positive clock signal 11 and the negative clock signal CK21 that synchronize the parallel data d [0; 3] are aligned, but the duties are not aligned.

  When the duty ratios of the positive clock signal CK11 and the negative clock signal CK21 are not 50%, a deviation from 50% of the duty ratios of both clock signals becomes the deterministic jitter 17 as it is. Deterministic jitter is jitter in which the waveform timing of a received signal changes depending on data or a clock.

  FIG. 18 is a diagram for explaining a case where serialization is performed using a clock having a variation in the clock edge.

  In the example of FIG. 18, the positive clock signal CK12 and the negative clock signal CK22 have the same duty but not the same edge.

  In this case, the phase difference between the positive clock signal CK12 and the negative clock signal CK22 becomes the deterministic jitter 18 as it is.

  In the present embodiment, the positive clock output signal CK10 and the negative clock output signal CK20 are adjusted so that the duty is 50% and the edges of both clock output signals are aligned. Generation of theoretical jitter can be suppressed.

(Sixth embodiment)
The sixth embodiment of the present invention will be described below with reference to the drawings. The sixth embodiment of the present invention is a form in which the phase adjustment circuit with duty correction of the fourth embodiment is applied to a serializer that converts 4-bit parallel data into serial data. In the following description of the sixth embodiment of the present invention, the same reference numerals as those used in the description of the fourth embodiment are given to those having the same functional configuration as the fourth embodiment, and the description thereof Is omitted.

  FIG. 19 is a diagram for explaining the serializer of the sixth embodiment. FIG. 19 shows an example in which the phase adjustment circuit with duty correction 100D of the fourth embodiment is applied.

  The serializer 600 of this embodiment is configured to include a serializer 610 and a phase adjustment circuit 100D with duty correction. In the serializer 600 of the present embodiment, the serializer 610 serializes the parallel data d [0; 3] in synchronization with the positive clock signal CK1 and the negative clock signal CK2, and outputs the serial data as positive serial data D10 and negative serial data D20. Further, in the serializer 600 of this embodiment, the phase adjustment circuit with duty correction 100D controls the duty, the rise time, and the fall time for the positive serial data D10 and the negative serial data D20. The phase adjustment circuit 100D with duty correction uses the positive serial output data D11 and the negative serial output data D21 having a duty of 50% and aligned edges as outputs of the serializer 600.

  Hereinafter, operations of the serializer 600 and the phase adjustment circuit 100D with duty correction according to the present embodiment will be described with reference to FIG. FIG. 20 is a flowchart for explaining the operation of the serializer and the phase adjustment circuit with duty correction according to the sixth embodiment.

  When serialization of parallel data starts, a calibration signal input to the phase adjustment circuit with duty correction 100D is turned on, and serial data calibration is started. At this time, the parallel data d [3; 0] is inputted with a fixed voltage so that the serial data is outputted as 0101 (step S2001). The calibration signal is external to the phase adjustment circuit 100D with duty correction. It was supplied from the circuit.

  Subsequent to step S2001, the phase adjustment circuit with duty correction 100D adjusts the duty, the fall time adjustment, and the rise time adjustment of the positive serial data D10 and the negative serial data D20 output from the serializer 610 (step S2002). The adjustment of the duty in step S2002 is as described in FIG. The fall time adjustment in step S2002 is as described in FIG. The rise time adjustment in step S2002 is as described in FIG.

  Subsequently, the phase adjustment circuit 100D with duty correction determines whether or not each of the above adjustments has been completed (step S2003). If each adjustment is not completed in step S2003, the process returns to step S2001.

  If each adjustment has been completed in step S2003, the calibration signal is turned off, input of parallel data to the serializer is started, and normal operation of the realizer is started (step S2004).

  As described above, in this embodiment, the positive serial data D10 and the negative serial data D20 are adjusted only at the time of calibration, and the control is not performed during the normal operation. Therefore, the duty is not adjusted by the data pattern. Further, in this embodiment, when the serial data has a predetermined pattern, the duty is kept at 50%, and control is performed so that the rising time and falling time of the positive serial data D10 and the negative serial data D20 are aligned. The predetermined pattern is, for example, a serial data pattern such as 1010 or 1010.

  In this embodiment, by applying the phase adjustment circuit 100D with duty correction to serial data transmission in this way, data transmission with low jitter becomes possible.

(Seventh embodiment)
The seventh embodiment of the present invention will be described below with reference to the drawings. The seventh embodiment of the present invention is a communication system to which the serializer 600 of the sixth embodiment is applied. In the following description of the seventh embodiment of the present invention, the same reference numerals as those used in the description of the sixth embodiment are assigned to those having the same functional configuration as the sixth embodiment, and the description thereof Is omitted.

  FIG. 21 is a diagram illustrating a communication system according to the seventh embodiment.

  A communication system 2100 according to this embodiment includes a driver circuit 620, a receiving circuit 700, and a transmission line 800.

  In this embodiment, by applying the serializer 600 of the sixth embodiment to the driver circuit 620, data transmission with low jitter is possible, so the communication system 2100 can have low jitter.

  As mentioned above, although this invention has been demonstrated based on each embodiment, this invention is not limited to the requirements shown in the said embodiment. With respect to these points, the gist of the present invention can be changed without departing from the scope of the present invention, and can be appropriately determined according to the application form.

100, 100A to 100D Phase adjustment circuit with duty correction 110 Average voltage detection unit 120 Reference voltage control generation unit 130 Comparator
140 Duty Adjustment Unit 150 Positive Rising Detection Unit 151 Negative Falling Detection Unit 152 Positive Falling Detection Unit 153 Negative Rising Detection Unit 160 Positive Phase Detection Unit 161 Negative Phase Detection Unit 170 Falling Time Adjustment Unit 171 Rising Time adjustment section

JP 2011-010066 A JP 2004-208004 A

Claims (7)

In a phase adjustment circuit with a duty correction, which receives a positive clock signal and a negative clock signal and outputs a positive clock output signal and a negative clock output signal in which the duty and phase of the positive clock signal and the negative clock signal are adjusted,
An average voltage detector for detecting an average voltage value of the positive clock output signal;
A comparator that compares a reference voltage with the average voltage value and outputs a control signal according to the comparison result;
A duty adjustment unit that receives the positive clock signal and changes the duty of the positive clock signal input so that the average voltage value and the reference voltage are equal to each other according to the control signal;
A positive rise detector for detecting the rise time of the positive clock output signal;
A positive fall detector for detecting a fall time of the positive clock output signal;
A negative rise detection unit for detecting the rise time of the negative clock output signal;
A negative falling detection unit for detecting a falling time of the negative clock output signal;
A positive phase detector that outputs a positive phase difference signal between the positive rise time and the negative fall time;
A negative phase detector that outputs a negative phase difference signal between the positive fall time and the negative rise time;
A fall time adjustment unit that changes a fall time of the negative clock signal in accordance with the positive phase difference signal;
A phase adjustment circuit with a duty correction, comprising: a rise time adjustment unit that changes the rise time of the negative clock signal output from the fall time adjustment unit according to the negative phase difference signal and sets the negative clock output signal as the negative clock output signal . The rise time adjustment unit
Changing the rise time of the negative clock signal in response to the positive phase difference signal;
The fall time adjusting unit is
2. The phase adjustment circuit with duty correction according to claim 1, wherein a fall time of the negative clock signal output from the rise time adjustment unit is changed according to the negative phase difference signal and is output as the negative clock output signal.   The phase adjustment circuit with duty correction according to claim 1, wherein a delay circuit is connected to an output side of the duty adjustment unit.   Frequency division on the input side of the positive rise detection unit, the input side of the positive fall detection unit, the input side of the negative rise detection unit, and the input side of the negative fall detection unit, respectively 3. A phase adjustment circuit with duty correction according to claim 1, wherein frequency dividers having the same ratio are connected. Digital analog converters are respectively connected to the output side of the comparator, the output side of the positive phase detection unit, and the output side of the negative phase detection unit,
3. The phase adjustment circuit with duty correction according to claim 1, wherein the digital-analog converter holds an output value corresponding to a calibration signal. It is connected to a phase adjustment circuit with duty correction that outputs a positive clock output signal and a negative clock output signal in which the duty and phase of the positive clock signal and the negative clock signal are adjusted, and is synchronized with the positive clock output signal and the negative clock output signal. A serializer that converts parallel data into serial data,
The duty correction phase adjustment circuit includes:
An average voltage detector for detecting an average voltage value of the positive clock output signal;
A comparator that compares a reference voltage with the average voltage value and outputs a control signal according to the comparison result;
A duty adjustment unit that receives the positive clock signal and changes the duty of the positive clock signal input so that the average voltage value and the reference voltage are equal to each other according to the control signal;
A positive rise detector for detecting the rise time of the positive clock output signal;
A positive fall detector for detecting a fall time of the positive clock output signal;
A negative rise detection unit for detecting the rise time of the negative clock output signal;
A negative falling detection unit for detecting a falling time of the negative clock output signal;
A positive phase detector that outputs a positive phase difference signal between the positive rise time and the negative fall time;
A negative phase detector that outputs a negative phase difference signal between the positive fall time and the negative rise time;
A fall time adjustment unit that changes a fall time of the negative clock signal in accordance with the positive phase difference signal;
A serializer, comprising: a rise time adjustment unit that changes a rise time of a negative clock signal output from the fall time adjustment unit according to the negative phase difference signal and uses the negative clock output signal as the negative clock output signal. A serializer that converts parallel data into serial data in synchronization with a positive clock signal and a negative clock signal,
Serializing means for converting the parallel data into the serial data in synchronization with the positive clock signal and the negative clock signal;
Positive serial data synchronized with the positive clock signal by the serialization means and negative serial data synchronized with the negative clock signal are input, and the positive serial data is adjusted by adjusting the duty and phase of the positive serial data and the negative serial data. A phase adjustment circuit with duty correction for outputting output data and negative serial output data,
The duty correction phase adjustment circuit includes:
An average voltage detector for detecting an average voltage value of the positive serial output data;
A comparator that compares a reference voltage with the average voltage value and outputs a control signal according to the comparison result;
A duty adjustment unit that receives the positive serial data and changes the duty of the positive serial data that is input so that the average voltage value and the reference voltage are equal to each other according to the control signal;
A positive rise detector for detecting the rise time of the positive serial output data;
A positive fall detector for detecting a fall time of the positive serial output data;
A negative rise detection unit for detecting the rise time of the negative serial output data;
A negative fall detection unit for detecting a fall time of the negative serial output data;
A positive phase detector that outputs a positive phase difference signal between the positive rise time and the negative fall time;
A negative phase detector that outputs a negative phase difference signal between the positive fall time and the negative rise time;
A fall time adjusting unit that changes the fall time of the negative serial data in accordance with the positive phase difference signal;
A serializer, comprising: a rise time adjustment unit that changes the rise time of the negative serial data output from the fall time adjustment unit in accordance with the negative phase difference signal to obtain the negative serial output data.

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