JP2013062568A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a skew of a timing signal while suppressing an increase in power consumption.SOLUTION: A main clock distribution circuit distributively ramifies a timing signal into a plurality of main timing signals. A sub clock distribution circuit distributively ramifies the timing signal into a plurality of sub timing signals when instructed to distribute the timing signal. A minimum delay timing signal output section outputs as a minimum delay timing signal the one distributed earlier of any one of the plurality of main timing signals and any one of the plurality of sub timing signals. A synchronous operation circuit operates in synchronism with the minimum delay timing signal. A measurement section measures a value indicating a delay variation in any one of the plurality of main timing signals. A clock distribution circuit control section instructs the sub distribution circuit to distribute the timing signal if the variation indicated by the measured value is equal to or greater than a predetermined value.

Description

  The present technology relates to integrated circuits. Specifically, the present invention relates to an integrated circuit that operates in synchronization with a timing signal.

  Conventionally, in an integrated circuit, a clock distribution circuit such as a clock tree is provided in order to distribute a timing signal to each element (for example, flip-flop) that operates in synchronization with a timing signal such as a clock signal. When the timing signal is distributed to a plurality of elements using this clock tree, the skew may increase in each element. Here, the skew is a difference between a delay time until a timing signal arrives at a certain element and a delay time until a timing signal arrives at an element different from the element. For example, in a configuration in which a circuit is connected to a leaf of a clock tree, if the wiring length from the root of the clock tree to each leaf and the number of buffer stages are different, a difference is likely to occur in the delay time of the timing signal distributed to each leaf. It is also known that skew variation increases when the driving voltage of an integrated circuit decreases.

  When the skew variation increases, a malfunction may occur in the integrated circuit. For example, in a flip-flop, a timing error such as a hold violation or a setup violation may occur, and the integrated circuit may malfunction. The hold violation means that a time during which data of the same value is maintained (held) in the flip-flop becomes shorter than a design value (hold time) after data fetching is instructed by a timing signal such as a clock signal. . The setup violation means that the timing of inputting data to the flip-flop prior to the instruction to fetch data by the clock signal is later than the design timing (setup time). When the skew variation increases, the timing signal arrives at the flip-flop too early or too late, and a timing error is likely to occur.

  In order to reduce the clock skew, there is also a method of distributing the timing signal not by the clock tree but by mesh mesh wiring. In the mesh wiring, since the clock signal is distributed by the grid-like wiring without using the buffer, the wiring resistance is smaller than that of the clock tree, and the skew variation is reduced. However, mesh wiring requires a larger circuit area for wiring than the clock tree. Therefore, a clock distribution circuit using a clock tree and mesh wiring in combination has been proposed (see, for example, Patent Document 1). With this configuration, an increase in circuit area is suppressed and skew is reduced.

Japanese Patent Laid-Open No. 8-11605

  However, the above-described conventional technology may increase the power consumption of the integrated circuit. For example, when timing signals having different values are distributed to the mesh wiring, a short circuit current may flow between the circuits connected to the mesh wiring. The occurrence of this short circuit current may increase power consumption.

  The present technology has been made to solve the above-described problems, and a first aspect thereof is a main timing signal distribution in which a timing signal instructing a predetermined timing is branched and distributed to a plurality of main timing signals. A circuit, a sub-timing signal distribution circuit that divides the timing signal into a plurality of sub-timing signals when distribution of the timing signal is instructed, and one of the plurality of main timing signals and the plurality of sub-timing signals A minimum delay timing signal output unit that outputs a signal distributed earlier with any one of the timing signals as a minimum delay timing signal; a synchronous operation circuit that operates in synchronization with the minimum delay timing signal; and the plurality of main timings A measurement unit that measures a value indicating any variation in delay of the signal, and the variation indicated by the measured value is An integrated circuit comprising a timing signal distribution circuit control unit for instructing the distribution of said timing signal to said auxiliary timing signal distribution circuit when a predetermined value or more. As a result, there is an effect that the timing signal distribution is instructed to the sub-timing signal distribution circuit when the delay variation of any of the plurality of main timing signals is equal to or greater than a predetermined value.

  In the first aspect, the minimum delay timing signal output unit includes a plurality of timing signal generation units, and each of the plurality of timing signal generation units includes a main input terminal and a sub input terminal. The minimum delay timing signal is generated and output from signals input to the input terminal and the sub input terminal, and the main timing signal distribution circuit is different from each of the main input terminals of the plurality of timing signal generation units. The plurality of main timing signals are distributed, and the sub-timing signal distribution circuit distributes the plurality of sub-timing signals different from each other to the sub-input terminals of the plurality of timing signal generation units according to the timing signal distribution instruction. And the measurement unit indicates the variation for each of the plurality of main timing signals. The timing signal distribution circuit control unit measures the sub timing signal with respect to the sub input terminal of the timing signal generation unit to which the main timing signal in which the variation is equal to or greater than the predetermined value is distributed. May be directed to distribute. As a result, there is an effect that the distribution of the sub-timing signal is instructed to the sub-input terminal of the timing signal generation unit to which the main timing signal whose delay variation is equal to or greater than a predetermined value is distributed.

  In the first aspect, the main timing signal distribution circuit and the sub-timing signal distribution circuit may transmit the main timing signal and the sub-timing signal distribution circuit to any one of the plurality of timing signal generation units via the same number of stages of buffers. The sub timing signal may be distributed. This brings about the effect that the main timing signal and the sub-timing signal are distributed to any one of the plurality of timing signal generation units via the same number of buffers.

  In the first aspect, the measurement unit may measure a value indicating the variation when a voltage supplied to the main timing signal distribution circuit becomes a predetermined voltage or less. As a result, there is an effect that measurement of a value indicating variation is performed when the voltage becomes a predetermined voltage.

  In the first aspect, the measurement unit includes an error detection unit that detects a timing error in the synchronous operation circuit, and an error detection frequency measurement unit that measures the detection frequency of the timing error as a value indicating the variation. May be provided. This brings about the effect that the detection frequency of the timing error is measured as a value indicating variation.

  In the first aspect, the minimum delay timing signal output unit outputs a logical sum of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal. The synchronous operation circuit may operate in synchronization with the rising edge of the minimum delay timing signal. As a result, the logical sum of the main timing signal and the sub-timing signal is output as the minimum timing signal, and the synchronous operation circuit operates in synchronization with the rising edge of the minimum delay timing signal.

  In the first aspect, the minimum delay timing signal output unit outputs a logical sum of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal. The synchronous operation circuit may include an inverter that inverts and outputs the minimum delay timing signal, and a flip-flop that operates in synchronization with a rising edge of the inverted minimum delay timing signal. As a result, the negative logical sum of the main timing signal and the sub timing signal is output as the minimum timing signal, and the synchronous operation circuit operates in synchronization with the rising edge of the inverted minimum delay timing signal.

  In the first aspect, the minimum delay timing signal output unit outputs a logical product of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal. The synchronous operation circuit may operate in synchronization with the falling edge of the minimum delay timing signal. As a result, the logical product of the main timing signal and the sub timing signal is output as the minimum timing signal, and the synchronous operation circuit operates in synchronization with the falling edge of the minimum delay timing signal.

  In the first aspect, the minimum delay timing signal output unit outputs a logical product of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal. The synchronous operation circuit may include an inverter that inverts and outputs the minimum delay timing signal, and a flip-flop that operates in synchronization with a falling edge of the inverted minimum delay timing signal. As a result, a negative logical product of the main timing signal and the sub timing signal is output as the minimum timing signal, and the synchronous operation circuit operates in synchronization with the rising edge of the inverted minimum delay timing signal.

  In the first aspect, the synchronous operation circuit includes a mesh wiring that distributes the minimum delay timing signal to a plurality of regions arranged in a grid pattern, and the minimum circuit that is distributed to any of the plurality of regions. And a flip-flop that operates in synchronization with the delay timing signal. This brings about the effect that the minimum delay timing signal is distributed by the mesh wiring.

  In this first aspect, the timing signal is a clock signal, and the main timing signal distribution circuit branches the timing signal into the plurality of main timing signals via a predetermined number of stages of first buffers. The sub-timing signal distribution circuit may be a clock tree that branches the timing signal into the plurality of sub-timing signals via a predetermined number of second buffers. As a result, the clock signal is distributed through a predetermined number of stages of buffers.

  According to the present technology, it is possible to achieve an excellent effect of reducing variations in timing signal delay while suppressing an increase in power consumption.

1 is a block diagram illustrating a configuration example of an integrated circuit according to a first embodiment. It is a figure which shows the example of 1 structure of the clock distribution part in 1st Embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a clock distribution unit and a synchronous operation circuit in the first embodiment. 4 is a timing chart illustrating an example of the operation of the synchronous operation circuit synchronized with the rising edge of the clock signal according to the first embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 1st modification in 1st Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 2nd modification in 1st Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 3rd modification in 1st Embodiment. It is a timing chart which shows an example of operation | movement of the synchronous operation circuit synchronized with the fall of the clock signal in the 3rd modification in 1st Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 4th modification in 1st Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 5th modification in 1st Embodiment. It is a block diagram which shows one structural example of the integrated circuit in 2nd Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in 2nd Embodiment. It is a circuit diagram which shows one structural example of the flip-flop in 2nd Embodiment. FIG. 6 is a circuit diagram illustrating a configuration example of a main clock distribution circuit according to a second embodiment. It is a circuit diagram which shows one structural example of the subclock distribution circuit in 2nd Embodiment. It is a block diagram which shows one structural example of the error measurement part in 2nd Embodiment. It is a circuit diagram which shows the example of 1 structure of the error detection circuit in 2nd Embodiment. It is a block diagram which shows the example of 1 structure of the clock distribution circuit control part in 2nd Embodiment. 10 is a flowchart illustrating an example of an operation of a clock distribution circuit control unit according to the second embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 1st modification in 2nd Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 2nd modification in 2nd Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 3rd modification in 2nd Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 4th modification in 2nd Embodiment. It is a circuit diagram which shows one structural example of the clock distribution part and synchronous operation circuit in the 5th modification in 2nd Embodiment. It is a block diagram which shows one structural example of the integrated circuit in 3rd Embodiment. It is a circuit diagram which shows one structural example of the clock distribution circuit and synchronous operation circuit in 3rd Embodiment. It is a block diagram which shows one structural example of the error measurement part in 3rd Embodiment. It is a figure which shows the example of mounting of the clock distribution circuit, synchronous operation circuit, and combinational logic circuit in 3rd Embodiment. It is a block diagram which shows one structural example of the power supply part in 3rd Embodiment. It is a block diagram which shows the example of 1 structure of the clock distribution circuit drive voltage control part in 3rd Embodiment. It is a figure which shows an example of operation | movement of the clock distribution circuit drive voltage control circuit in 3rd Embodiment. It is a circuit diagram which shows one structural example of the voltage control register | resistor and variable resistor in 3rd Embodiment. It is a block diagram which shows the example of 1 structure of the logic circuit drive voltage control part in 3rd Embodiment. It is a figure which shows an example of operation | movement of the logic circuit drive voltage control circuit in 3rd Embodiment. 14 is a flowchart illustrating an example of an operation of a clock distribution circuit drive voltage control unit according to the third embodiment. 14 is a flowchart illustrating an example of an operation of a logic circuit drive voltage control unit according to the third embodiment. It is a graph which shows the 1st example of a setting of the clock distribution circuit drive voltage and logic circuit drive voltage in 3rd Embodiment. It is a graph which shows the 2nd example of a clock distribution circuit drive voltage and a logic circuit drive voltage in 3rd Embodiment. It is a graph which shows the 2nd example of a clock distribution circuit drive voltage and a logic circuit drive voltage in 3rd Embodiment. It is a block diagram which shows one structural example of the integrated circuit in the 1st modification in 3rd Embodiment. It is a block diagram which shows the example of 1 structure of the power supply part in the 2nd modification in 3rd Embodiment. It is a block diagram which shows one structural example of the integrated circuit in the 3rd modification in 3rd Embodiment. It is a block diagram which shows one structural example of the power supply part in the 4th modification in 3rd Embodiment. It is a block diagram which shows one structural example of the integrated circuit in 4th Embodiment. It is a circuit diagram which shows the example of 1 structure of the error measurement part in 4th Embodiment, a synchronous operation circuit, and a clock distribution circuit. It is a block diagram which shows the example of 1 structure of the error compensation control part in 4th Embodiment. It is a figure which shows an example of operation | movement of the error analysis part in 4th Embodiment. It is a figure which shows an example of operation | movement of the power supply part in 4th Embodiment. 16 is a timing chart illustrating an example of an operation of the error detection circuit when both error flags ERR1 and ERR2 are “0” in the fourth embodiment. 16 is a timing chart illustrating an example of an operation of the error detection circuit when only an error flag ERR2 is “1” in the fourth embodiment. 16 is a timing chart illustrating an example of the operation of the error detection circuit when both error flags ERR1 and ERR2 are “1” in the fourth embodiment. It is a figure which shows an example of the trap window of the error detection circuit in 4th Embodiment, and the update timing of data. It is a block diagram which shows one structural example of the integrated circuit in the 1st modification in 4th Embodiment. It is a block diagram which shows the example of 1 structure of the error compensation control part in the 1st modification in 4th Embodiment. It is a block diagram which shows one structural example of the error counting part in the 1st modification in 4th Embodiment. It is a figure which shows an example of operation | movement of the error analysis part in the 1st modification in 4th Embodiment. It is an example of the trap window and data update timing of the error detection circuit in the first modification example of the fourth embodiment. It is a circuit diagram which shows one structural example of the error detection circuit, flip-flop, and clock distribution circuit in the 2nd modification in 4th Embodiment. It is a figure which shows an example of the trap window of the error detection circuit in the 2nd modification in 4th Embodiment.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (example of clock distribution circuit for reducing clock skew)
2. Second Embodiment (Example of Main / Sub Clock Distribution Circuit for Adaptively Reducing Clock Signal Delay Variation)
3. Third Embodiment (Example of voltage control for controlling clock distribution circuit drive voltage lower than logic circuit drive voltage)
4). Fourth Embodiment (Example of voltage control for controlling the drive voltage by determining the type of timing error)

<1. First Embodiment>
[Configuration example of integrated circuit]
FIG. 1 is a block diagram illustrating a configuration example of the integrated circuit 100 according to the first embodiment. The integrated circuit 100 according to the first embodiment includes a power supply unit 200, a clock generation unit 300, a clock distribution unit 400, and a synchronous operation circuit 500.

  The power supply unit 200 supplies the power supply voltage VDD to the clock generation unit 300, the clock distribution unit 400, and the synchronous operation circuit 500 through the signal line 209.

  The clock generation unit 300 generates a clock signal CLK having a predetermined frequency using a PLL (Phase Locked Loop) or the like. The clock signal CLK is generated as a signal for instructing the synchronous operation circuit 500 at a predetermined timing. The clock generation unit 300 outputs the generated clock signal CLK to the clock distribution unit 400 via the signal line 309.

  The clock distribution unit 400 distributes the clock signal CLK to the synchronous operation circuit 500. The clock distribution unit 400 generates a minimum delay clock signal mCLK from the clock signal CLK. Details of the minimum delay clock signal mCLK will be described later. The clock distribution unit 400 outputs the minimum delay clock signal mCLK to the synchronous operation circuit 500 via the signal line 409. The synchronous operation circuit 500 is a circuit that operates in synchronization with the minimum delay clock signal mCLK.

[Configuration example of clock distribution unit]
FIG. 2 is a diagram illustrating a configuration example of the clock distribution unit 400 according to the first embodiment. FIG. 2A is a diagram illustrating an arrangement example of wirings up to each of a plurality of distribution points in the clock distribution unit 400. As illustrated in FIG. 2A, the clock distribution unit 400 includes a clock tree wired in an H-tree shape. A plurality of buffers are inserted in the path in the clock tree as necessary. The clock signal CLK from the clock generator 300 is input to the root portion of the clock tree, and the clock signal CLK is distributed to each of the distribution points corresponding to the leaf portions of the clock tree. A synchronous operation circuit 500 or the like is connected to each distribution point. FIG. 2B is an enlarged view of a portion surrounded by a one-dot chain line in FIG. As shown in FIG. 2B, among the distribution points, distribution points P1 and P2 are connected to an input terminal of an OR (logical sum) gate 430. The output terminal of the OR gate 430 is connected to the synchronous operation circuit 500. Details of the configuration of the synchronous operation circuit 500 will be described later.

  The OR gate 430 generates a logical sum of input values. The OR gate 430 outputs a logical sum of the clock signal from the distribution point P1 and the clock signal from the distribution point P2 to the synchronous operation circuit 500. Here, since each of the wiring branches in the clock tree does not merge before reaching the distribution point, the circuit from the root of the clock tree to the distribution point P1 and the circuit from the root to the distribution point P2 are mutually connected. The configuration will be different. For example, the wiring length and the number of stages of the buffer through which the line passes are different. For this reason, a difference (that is, clock skew) may occur in the delay time of the clock signal CLK distributed to each of the distribution points P1 and P2. Regardless of whether the Euclidean distance between the distribution points P1 and P2 is short or not, if the topological distance in the clock tree is large, the clock skew tends to increase at those distribution points. In addition, when the supply voltage VDD from the power supply unit 200 decreases, there is a possibility that the variation in clock skew may be further increased. However, since OR gate 430 outputs a logical sum of clock signals CLK distributed to distribution points P1 and P2, the rising edge with the smaller delay among the rising edges of clock signals CLK is output. Will be. The clock signal with the smaller delay output from the OR gate 430 is hereinafter referred to as “minimum delay clock signal mCLK”.

  FIG. 3 is a circuit diagram illustrating a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 according to the first embodiment. The clock distribution unit 400 includes clock distribution circuits 410 and 420 and an OR gate 430. The clock distribution circuit 410 includes a buffer 411 having a predetermined number of stages. The clock distribution circuit 420 includes buffers 421 having a predetermined number of stages. The clock distribution circuit 410 distributes the clock signal CLK to any distribution point (for example, P1) in the clock tree. The clock distribution circuit 410 outputs one of the distributed clock signals as a delayed clock signal CLK_D1 to the input terminal of the OR gate 430 via the signal line 419. The clock distribution circuit 420 distributes the clock signal CLK to a distribution point (for example, P2) different from the distribution point distributed by the clock distribution circuit 410. The clock distribution circuit 420 outputs one of the distributed clock signals as a delayed clock signal CLK_D2 to the input terminal of the OR gate 430 via the signal line 429. The clock distribution circuit 410 is an example of a first timing signal distribution circuit described in the claims. The clock distribution circuit 420 is an example of a second timing signal distribution circuit described in the claims.

  The OR gate 430 outputs the logical sum of the delayed clock signals CLK_D1 and CLK_D2 as the minimum delayed clock signal mCLK to the synchronous operation circuit 500 via the signal line 409. The OR gate 430 is an example of a minimum delay clock signal output unit described in the claims.

  The synchronous operation circuit 500 operates in synchronization with the minimum delay clock signal mCLK. The synchronous operation circuit 500 includes flip-flops 510 and 520, for example. The flip-flops 510 and 520 capture and hold data in synchronization with the minimum delay clock signal mCLK. For example, the flip-flop 510 captures and holds the data of the input signal D0 in synchronization with the rising edge of the minimum delay clock signal mCLK, and outputs the held data to the flip-flop 520 as the output signal Q0. Then, flip-flop 520 takes in and holds the data of output signal Q0 in synchronization with the rising edge of minimum delay clock signal mCLK, and outputs the held data as output signal Q1.

  FIG. 4 is a timing chart showing an example of the operation of the synchronous operation circuit 500 synchronized with the rising edge of the clock signal in the first embodiment. Consider a case where a rising edge occurs in the clock signal CLK at a certain timing before the value of the input signal D0 is updated from “d2” to “d3”. The clock signal CLK is distributed by the clock distribution circuit 410, and a rising edge occurs in the delayed clock signal CLK_D1 with a delay with respect to the clock signal CLK. Further, the clock signal CLK is distributed by the clock distribution circuit 420, and a rising edge is generated in the delayed clock signal CLK_D2. The delay of the delayed clock signal CLK_D1 is greater than the delayed clock signal CLK_D2. The OR gate 430 outputs a logical sum of these delayed clock signals as a minimum delayed clock signal mCLK. If a rising edge occurs in any of the delayed clock signals, the value of the logical sum is “1”. Therefore, a rising edge occurs in the minimum delay clock signal mCLK according to the rising edge of the delayed clock signal CLK_D2 having the smallest delay. . The flip-flop 510 takes in the value of “d2” in synchronization with the rising edge of the minimum delay clock signal mCLK, and outputs it as the output signal Q 0 to the flip-flop 520. The flip-flop 520 takes in the value of “d2” in synchronization with the rising edge of the next minimum delay clock signal mCLK.

  If the delayed clock signals CLK_D1 and CLK_D2 are supplied to the flip-flops 510 and 520 without passing through the OR gate 430, a difference (clock skew) may occur between the delay times of the delayed clock signals. When this clock skew increases, there is a possibility that data transfer between the flip-flops 510 and 520 will be hindered and malfunction may occur. In particular, when the drive voltage is lowered, the variation in clock skew increases, so the probability of malfunctions increases. However, in the integrated circuit 100, since the clock signal mCLK with the minimum delay is supplied to the flip-flops 510 and 520 by the OR gate 430, the clock skew is reduced. As a result, the occurrence rate of malfunction of the integrated circuit 100 is reduced.

  The measured value of the clock skew variation (for example, standard deviation) of the clock tree with the OR gate 430 inserted is smaller than that of the clock tree with no OR gate 430 inserted. For example, when simulation is performed under a predetermined condition with 10 stages of buffers, the result that the measured value of the standard deviation is reduced by about 0.7 times before the insertion by inserting the OR gate 430 is obtained. Yes. In a clock tree, variation in clock skew generally decreases when the buffer size is increased or the number of buffer stages is decreased. In order to increase the clock skew variation by 0.7, for example, it is necessary to double the buffer size or halve the number of buffer stages. By inserting the OR gate 430, the clock skew can be reduced without changing the buffer size or the number of buffer stages. Further, even if the OR gate 430 is inserted, no short circuit current is generated unlike the mesh wiring, so that the power consumption is not increased.

  Thus, according to the first embodiment, the clock distribution circuit 410 distributes the clock signal CLK to the distribution point P1, and the clock distribution circuit 420 distributes the clock signal CLK to the distribution point P2. Then, the OR gate 430 outputs the signal having the smaller delay among the clock signals CLK distributed to these distribution points as the minimum delay timing signal mCLK. The synchronous operation circuit 500 operates in synchronization with the minimum delay timing signal mCLK. As a result, the signal with the smaller delay among the clock signals CLK distributed by the clock distribution circuits 410 and 420 is output to the synchronous operation circuit 500 as the minimum delay timing signal mCLK. Thereby, the clock skew in the synchronous operation circuit 500 is reduced. Further, even when the values of the clock signals CLK from the clock distribution circuits 410 and 420 are different from each other, a short-circuit current is not generated unlike the mesh wiring, so that an increase in power consumption is suppressed.

  Although the OR gate 430 generates the minimum delay timing signal mCLK from the two delay clock signals CLK_D1 and CLK_D2, the OR gate 430 may generate the minimum delay timing signal mCLK from three or more delay clock signals.

  Further, although the synchronous operation circuit 500 includes two flip-flops 510 and 520, the circuit configuration of the synchronous operation circuit 500 is not limited to this configuration. For example, one or three or more flip-flops may be provided.

  Further, although the integrated circuit 100 is configured to generate the minimum delay timing signal mCLK using the OR gate 430, the minimum delay timing signal mCLK may be generated using a logic gate other than the OR gate. For example, when the synchronous operation circuit 500 operates in synchronization with the falling edge, the integrated circuit 100 may generate the minimum delay timing signal mCLK by an AND gate instead of the OR gate.

  The clock distribution unit 400 is configured to include a clock tree previously wired in an H-tree shape. For example, a clock tree generated using CTS (Clock Tree Synthesis), which is a technique for automatically synthesizing a clock tree, is used. You may prepare.

[First Modification]
FIG. 5 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the first modification example of the first embodiment. The configuration of the clock distribution unit 400 in the first modified example is different from that of the first embodiment in that a NOR (negative OR) gate 431 is provided instead of the OR gate 430. The configuration of the synchronous operation circuit 500 in the first modified example is different from that of the first embodiment in that inverters 530 and 540 are further provided.

  The NOR gate 431 outputs a negative logical sum of the delayed clock signals CLK_D1 and CLK_D2 to the synchronous operation circuit 500 as the minimum delayed clock signal mCLK. The inverter 530 inverts the minimum delay clock signal mCLK and outputs it to the flip-flop 510. The inverter 540 inverts the minimum delay clock signal mCLK and outputs it to the flip-flop 520.

  As described above, according to the first modification, clock skew can be reduced in the configuration in which the inverter is provided at the clock input terminals of the flip-flops 510 and 520.

[Second Modification]
FIG. 6 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the second modification example of the first embodiment. The configuration of the clock distribution unit 400 in the second modified example is different from that of the first embodiment in that a NOR (negative OR) gate 431 is provided instead of the OR gate 430. The configuration of the synchronous operation circuit 500 in the second modified example is different from that of the first embodiment in that inverters 530 and 540 and a mesh wiring 550 are further provided.

  The configuration of the NOR gate 431 is the same as that of the first modification. Inverters 530 and 540 invert minimum delay clock signal mCLK and output the inverted signal to mesh wiring 550. The mesh wiring 550 distributes the minimum delay clock signal mCLK to a plurality of regions arranged in a lattice shape. In these regions, flip-flops 510 and 520 are arranged.

  As described above, according to the second modification, the clock skew can be reduced in the configuration in which the mesh wiring 550 is connected to the clock input terminals of the flip-flops 510 and 520.

[Third Modification]
FIG. 7 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the third modification example of the first embodiment. In the first embodiment described above, it is assumed that the synchronous operation circuit 500 operates on the rising edge of the clock signal. However, in the third modification, the synchronous operation circuit 500 operates on the falling edge of the clock signal. Assume that it works. Specifically, the configuration of the clock distribution unit 400 in the third modification example is different from that of the first embodiment in that an AND (logical product) gate 432 is provided instead of the OR gate 430. The configuration of the synchronous operation circuit 500 in the third modified example is different from that of the first embodiment in that flip-flops 560 and 570 are provided instead of the flip-flops 510 and 520.

  The AND gate 432 outputs a logical product of the delayed clock signals CLK_D1 and CLK_D2 to the synchronous operation circuit 500 as the minimum delayed clock signal mCLK. The flip-flops 560 and 570 capture and hold data in synchronization with the falling edge of the minimum delay clock signal mCLK.

  FIG. 8 is a timing chart showing an example of the operation of the synchronous operation circuit 500 synchronized with the rising edge of the clock signal in the third modification example of the first embodiment. Consider a case where a falling edge occurs in the clock signal CLK at a certain timing before the value of the input signal D0 is updated from “d2” to “d3”. The clock signal CLK is distributed by the clock distribution circuit 410 and is delayed with respect to the clock signal CLK to cause a falling edge in the delayed clock signal CLK_D1. Further, the clock signal CLK is distributed by the clock distribution circuit 420, and a rising edge is generated in the delayed clock signal CLK_D2. The delay of the delayed clock signal CLK_D1 is greater than the delayed clock signal CLK_D2. The OR gate 430 outputs the logical product of these delayed clock signals as the minimum delayed clock signal mCLK. If a falling edge occurs in any of the delayed clock signals, the value of the logical sum is “0”, so that the falling edge of the delayed clock signal CLK_D2 having the smallest delay falls to the minimum delayed clock signal mCLK. Edges are generated. The flip-flop 560 takes the value of “d2” in synchronization with the falling edge of the minimum delay clock signal mCLK, and outputs the value to the flip-flop 570 as the output signal Q0. The flip-flop 570 takes in the value of “d2” in synchronization with the falling edge of the next minimum delay clock signal mCLK.

  Thus, according to the third modification, the clock skew can be reduced in the configuration in which the synchronous operation circuit 500 operates in synchronization with the falling edge of the clock signal.

[Fourth Modification]
FIG. 9 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the fourth modification example of the first embodiment. In the fourth modified example, it is assumed that the synchronous operation circuit 500 operates on the falling edge as in the third modified example. The configuration of the clock distribution unit 400 in the fourth modification example is different from that of the first embodiment in that a NAND (negative AND) gate 433 is provided instead of the OR gate 430. The configuration of the synchronous operation circuit 500 in the fourth modified example is different from that of the first embodiment in that flip-flops 560 and 570 are provided instead of the flip-flops 510 and 520 and inverters 530 and 540 are further provided.

  The NAND gate 433 outputs a negative logical product of the delayed clock signals CLK_D1 and CLK_D2 to the synchronous operation circuit 500 as the minimum delayed clock signal mCLK. The inverter 530 inverts the minimum delay clock signal mCLK and outputs it to the flip-flop 560. The inverter 540 inverts the minimum delay clock signal mCLK and outputs it to the flip-flop 570. The flip-flops 560 and 570 capture and hold data in synchronization with the falling edge of the minimum delay clock signal mCLK.

  As described above, according to the fourth modification example, in the configuration in which the clock input terminals of the flip-flops 560 and 570 are provided with the inverter, and the synchronous operation circuit 500 operates in synchronization with the falling edge of the clock signal, the clock skew is reduced. Can be reduced.

[Fifth Modification]
FIG. 10 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the fifth modification example of the first embodiment. Also in the fifth modification example, it is assumed that the synchronous operation circuit 500 operates on the falling edge as in the third modification example. The configuration of the clock distribution unit 400 in the fifth modification example is different from that of the first embodiment in that a NAND gate 433 is provided instead of the OR gate 430. The configuration of the synchronous operation circuit 500 in the fifth modified example is different from that of the first embodiment in that flip-flops 560 and 570 are provided instead of the flip-flops 510 and 520. The configuration of the synchronous operation circuit 500 in the fifth modification example is different from that of the first embodiment in that inverters 530 and 540 and a mesh wiring 550 are further provided.

  The configuration of the NAND gate 433 is the same as that of the fourth modification. The configurations of the inverters 530 and 540 and the mesh wiring 550 are the same as in the second modification. The configuration of the flip-flops 560 and 570 is the same as that of the fourth modification.

  As described above, according to the fifth modification, in the configuration in which the clock input terminals of the flip-flops 560 and 570 are connected to the mesh wiring and the synchronous operation circuit 500 operates in synchronization with the falling edge of the clock signal, Can be reduced.

<2. Second Embodiment>
[Configuration example of integrated circuit]
FIG. 11 is a block diagram illustrating a configuration example of the integrated circuit 100 according to the second embodiment. The integrated circuit 100 according to the second embodiment includes a power supply unit 200, a clock generation unit 300, a clock distribution unit 400, a synchronous operation circuit 500, an error measurement unit 600, and a clock distribution circuit control unit 700.

  The power supply unit 200 supplies the power supply voltage VDD to each of the clock generation unit 300, the clock distribution unit 400, the synchronous operation circuit 500, the error measurement unit 600, and the clock distribution circuit control unit 700 via the signal line 209. .

  The clock generator 300 generates a clock signal CLK having a predetermined frequency using a PLL or the like. The clock signal CLK is generated as a signal for instructing the synchronous operation circuit 500 at a predetermined timing. The clock generation unit 300 outputs the generated clock signal CLK to the clock distribution unit 400 via the signal line 309.

  The clock distribution unit 400 distributes the clock signal CLK to the synchronous operation circuit 500. The clock distribution unit 400 generates a minimum delay clock signal mCLK from the clock signal CLK. The clock distribution unit 400 outputs the minimum delay clock signal mCLK to the synchronous operation circuit 500 via the signal line 409. The synchronous operation circuit 500 is a circuit that operates in synchronization with the minimum delay clock signal mCLK.

  The error measurement unit 600 detects a timing error occurring in the synchronous operation circuit 500 and measures the detection frequency. The detection frequency of timing errors is measured, for example, by counting the number of errors within a certain measurement period. The error measurement unit 600 counts the number of timing errors in accordance with the control of the clock distribution circuit control unit 700 and outputs the counted value to the clock distribution circuit control unit 700 via the signal line 609. The error measurement unit 600 is an example of a measurement unit described in the claims.

  The clock distribution circuit control unit 700 controls the clock distribution unit 400 based on the detection frequency of timing errors. Specifically, the clock distribution circuit control unit 700 controls the error measurement unit 600 to start measuring the number of timing errors when the supply voltage VDD from the power supply unit 200 becomes a predetermined voltage or less. Then, the clock distribution circuit control unit 700 generates the enable signals En_M and En_S based on the detected frequency of the timing error. Details of the enable signals En_M and En_S will be described later. The clock distribution circuit control unit 700 outputs enable signals En_M and En_S to the clock distribution unit 400 via signal lines 708 and 709. The clock distribution circuit control unit 700 is an example of a timing signal distribution circuit control unit described in the claims.

[Configuration example of clock distribution unit]
FIG. 12 is a circuit diagram illustrating a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 according to the second embodiment. The clock distribution unit 400 according to the second embodiment includes a main clock distribution circuit 440, a sub clock distribution circuit 450, and OR gates 461 and 462. The synchronous operation circuit 500 according to the second embodiment includes flip-flops 510 and 520.

  The main clock distribution circuit 440 branches the clock signal CLK according to the enable signal En_M, generates a plurality of clock signals, and distributes these signals. Each clock signal branched in the main clock distribution circuit 440 is hereinafter referred to as a “main clock signal”. Here, the main clock distribution circuit 440 includes a plurality of paths, and two of them are paths M_A and M_B. The main clock signal distributed via the path M_A is CLK_M_A, and the main clock signal distributed via the path M_B is CLK_M_B. The main clock distribution circuit 440 is an example of a main timing signal distribution circuit described in the claims.

  The sub clock distribution circuit 450 branches the clock signal CLK according to the enable signal En_S, generates a plurality of clock signals, and distributes these signals. The respective clock signals branched in the sub clock distribution circuit 450 are hereinafter referred to as “sub clock signals”. Here, the main clock distribution circuit 440 includes a plurality of paths, and two of them are defined as paths S_A and S_B. The sub clock signal distributed via the path S_A is CLK_S_A, and the sub clock signal distributed via the path S_A is CLK_S_B. The sub clock distribution circuit 450 is an example of a sub timing signal distribution circuit described in the claims.

  Here, the main clock distribution circuit 440 is always activated by the enable signal En_M in the on state when the synchronous operation circuit 500 is operated. On the other hand, the sub clock distribution circuit 450 is inactivated by the enable signal En_S in the off state in the initial state. The sub clock distribution circuit 450 is activated when the detection frequency of the timing error in the synchronous operation circuit 500 becomes higher than a predetermined value. Here, the enable signal En_S includes En_S_Root, En_S_A, and En_S_B. The path S_A in the sub clock distribution circuit 450 is activated by turning on the enable signals En_S_Root and En_S_A. On the other hand, the path S_B in the sub clock distribution circuit 450 is activated by turning on the enable signals En_S_Root and En_S_B.

  The OR gates 461 and 462 generate a logical sum of their input values. The OR gate 461 includes two input terminals, and the main clock signal CLK_M_A and the sub clock signal CLK_S_A are input to these input terminals. The OR gate 461 outputs the logical sum of these signals to the synchronous operation circuit 500 as the minimum delay clock signal mCLK_A. The OR gate 462 includes two input terminals, and the main clock signal CLK_M_B and the sub clock signal CLK_S_B are input to these input terminals. The OR gate 462 outputs the logical sum of these signals to the synchronous operation circuit 500 as the minimum delay clock signal mCLK_B. In this manner, OR gates 461 and 462 output the logical sum of the main timing signal and the sub-timing signal, respectively, so that the rising edge with the smaller delay among the rising edges of these signals is output. In other words, the signal that is distributed first among the main timing signal and the sub-timing signal is output.

  Each of the OR gates 461 and 462 is an example of a timing signal generation unit described in the claims. The terminals to which the main clock signal is input in the OR gates 461 and 462 are examples of the main input terminal described in the claims. The terminals to which the sub clock signals are input in the OR gates 461 and 462 are examples of the sub input terminals described in the claims.

  The flip-flop 510 incorporates and holds data in synchronization with the minimum delay clock signal mCLK_A. The input signal D_A input to the flip-flop 510 and the latch output signal L_A from the flip-flop 510 are output to the error measurement unit 600 via the signal line 509. The latch output signal L_A is an output signal of the master side latch in the master-slave type flip-flop 510. Further, the minimum delay clock signal mCLK_A is also output to the error measurement unit 600 via the signal line 509. The flip-flop 520 captures and holds data in synchronization with the minimum delay clock signal mCLK_B. The input signal D_B input to the flip-flop 520 and the latch output signal L_B from the flip-flop 510 are output to the error measurement unit 600 via the signal line 509. The latch output signal L_B is an output signal of the master side latch in the master slave side flip-flop 520. Further, the minimum delay clock signal mCLK_B is also output to the error measurement unit 600 via the signal line 509.

  FIG. 13 is a circuit diagram illustrating a configuration example of the flip-flop 510 according to the second embodiment. The flip-flop 510 is a master-slave type latch, and includes a master-side latch 511 and a slave-side latch 512. Note that the configuration of the flip-flop 520 is the same as that of the flip-flop 510.

  The latch 511 holds an input signal in synchronization with the minimum delay clock signal mCLK_A. The latch 511 includes an input terminal Q, an output terminal D, and a gate enable terminal G. The input signal Q_A is input to the input terminal, the minimum delay clock signal mCLK_A is input to the gate enable terminal G, and the output terminal D is connected to the input terminal of the latch 512. The latch 511 outputs the input signal D_A through when the minimum delay clock signal mCLK_A is on. On the other hand, when the minimum delay clock signal mCLK_A is turned off, the latch 511 holds and outputs the input signal D_A at the falling edge. The output of the latch 511 is output to the error measuring unit 600 and the latch 512 as a latch output signal L_A.

  The latch 512 holds the latch output signal L_A in synchronization with the clock signal mCK2_A obtained by inverting the minimum delay clock signal mCLK_A. The configuration of the latch 512 is the same as that of the latch 511. The output of the latch 512 is output as an output signal of the flip-flop 510.

  FIG. 14 is a circuit diagram showing a configuration example of the main clock distribution circuit 440 in the second embodiment. The main clock distribution circuit 440 includes PLLs 441, 443, and 445 and buffers 442, 444, and 446.

  The PLLs 441, 443, and 445 generate a clock signal having the same frequency as the input clock signal. The PLLs 441, 443, and 445 include an input terminal CKI, an output terminal CKO, and an enable terminal EN. The PLLs 441, 443, and 445, for example, output the generated clock signal when an on-state enable signal is input, and stop the output when an off-state enable signal is input. The main clock distribution circuit 440 receives an enable signal En_M including En_M_Root, En_M_A, and En_M_B from the clock distribution circuit control unit 700. En_M_Root, En_M_A, and En_M_B are enable signals for controlling the PLLs 441, 443, and 445, respectively. Here, the signal line 708 includes signal lines 708-1, 708-2, and 708-3, and the enable signal En_M_Root is input to the PLL 441 via the signal line 708-1. The enable signal En_M_A is input to the PLL 443 via the signal line 708-2, and the enable signal En_M_B is input to the PLL 445 via the signal line 708-3.

  The PLL 441 is a circuit installed at a position close to the root of the clock tree, and the clock signal CLK from the clock generation unit 300 is input to the input terminal CKI of the PLL 441. The clock signal output from the PLL 441 is branched into a plurality of clock signals via the buffer 442. Any two of the branched clock signals are input to the input terminals CKI of the PLLs 443 and 445.

  The clock signal CLK output from the PLL 443 is branched into a plurality of clock signals via the buffer 444. One of the branched clock signals is output to the OR gate 461. This signal is the main clock signal CLK_M_A. The clock signal CLK output from the PLL 445 is branched into a plurality of clock signals via the buffer 446. One of the branched clock signals is output to the OR gate 462. This signal is the main clock signal CLK_M_B. A path from the output point of the PLL 441 to the output point of the main clock signal CLK_M_A is defined as a path M_A, and a path from the output point of the PLL 441 to the output point of the main clock signal CLK_M_B is defined as a path M_B.

  FIG. 15 is a circuit diagram showing a configuration example of the sub clock distribution circuit 450 in the second embodiment. The sub clock distribution circuit 450 includes PLLs 451, 453, and 455 and buffers 452, 454, and 456.

  The configurations of the PLLs 451, 453, and 455 are the same as those of the PLL 441. The sub clock distribution circuit 450 receives an enable signal En_S including En_S_Root, En_S_A, and En_S_B from the clock distribution circuit control unit 700. En_S_Root, En_S_A, and En_S_B are enable signals for controlling the PLLs 451, 453, and 455, respectively. Here, the signal line 709 includes signal lines 709-1, 709-2, and 709-3, and the enable signal En_S_Root is input to the PLL 451 via the signal line 709-1. The enable signal En_S_A is input to the PLL 453 via the signal line 709-2, and the enable signal En_S_B is input to the PLL 455 via the signal line 709-3.

  The PLL 451 is a circuit installed at a position close to the root of the clock tree, and the clock signal CLK from the clock generation unit 300 is input to the input terminal CKI of the PLL 451. The clock signal output from the PLL 451 is branched into a plurality of clock signals via the buffer 452. Any two of the branched clock signals are input to the input terminals CKI of the PLLs 453 and 455.

  The clock signal CLK output from the PLL 453 is branched into a plurality of clock signals via the buffer 454. One of the branched clock signals is output to the OR gate 461. This signal is the sub clock signal CLK_S_A. The clock signal CLK output from the PLL 455 is branched into a plurality of clock signals via the buffer 456. One of the branched clock signals is output to the OR gate 462. This signal is the sub clock signal CLK_S_B. A path from the output point of the PLL 451 to the output point of the sub clock signal CLK_S_A is a path S_A, and a path from the output point of the PLL 451 to the output point of the sub clock signal CLK_S_B is a path S_B.

  Here, it is desirable that the main timing signal and the sub timing signal are distributed to the OR gate 461 through the same number of stages. That is, it is desirable that the number of buffer stages in the route M_A and the route S_A is equal. By making the number of buffer stages the same, the variation in the difference in delay time between the main timing signal and the sub-timing signal is reduced. As a result, the variation in the delay of the minimum delay timing signal mCLK is also reduced. Note that the number of buffer stages in each of the paths M_A and S_A may be slightly different as long as the delay times of the main timing signal and the sub-timing signal are approximately the same. The same applies to the routes M_B and S_B.

  Thus, by providing PLL at the root and branch point of the sub clock distribution circuit 450, the integrated circuit 100 can selectively inactivate or activate a plurality of paths. Specifically, when the PLL 451 in the root portion is invalidated, all paths are inactivated. When the PLLs 451 and 453 are enabled, the path S_A is activated and the sub clock signal CLK_S_A is output. When the PLLs 451 and 455 are enabled, the path S_B is activated and the sub clock signal CLK_S_B is output.

[Configuration example of error measurement unit]
FIG. 16 is a circuit diagram illustrating a configuration example of the error measurement unit 600 according to the second embodiment. The error measurement unit 600 includes error detection circuits 610 and 620 and error number counters 630 and 640.

  The error detection circuit 610 detects a timing error that has occurred in the flip-flop 510. The error detection circuit 610 outputs an error detection signal ERR_A indicating the detection result of the timing error to the error number counter 630. The error detection circuit 620 detects a timing error that has occurred in the flip-flop 520. The error detection circuit 620 outputs an error detection signal ERR_B indicating the detection result of the timing error to the error number counter 640. For example, a value “1” is set in the error detection signals ERR_A and ERR_B when a timing error is detected, and a value “0” is set when no timing error is detected.

  The error number counter 630 counts the number of timing errors detected for the flip-flop 510 in synchronization with the minimum delay clock signal mCLK_A. The error number counter 630 receives the enable signal En_CNT_A from the clock distribution circuit control unit 700 via the signal line 609. When the enable signal En_CNT_A is turned on, the error number counter 630 initializes a count value and starts counting timing errors in synchronization with the minimum delay clock signal mCLK_A. The error number counter 630 outputs the count value ERR_CNT_A to the clock distribution circuit control unit 700 via the signal line 609, and initializes the count value when a predetermined measurement period has elapsed.

  The error number counter 640 counts the number of timing errors detected for the flip-flop 520 in synchronization with the minimum delay clock signal mCLK_B. The error number counter 640 receives the enable signal En_CNT_B from the clock distribution circuit control unit 700 via the signal line 609. When the enable signal En_CNT_B is turned on, the error number counter 640 initializes a count value and starts counting timing errors in synchronization with the minimum delay clock signal mCLK_B. The error number counter 640 outputs the count value ERR_CNT_B to the clock distribution circuit control unit 700, and initializes the count value when a predetermined measurement period has elapsed.

  FIG. 17 is a circuit diagram showing a configuration example of the error detection circuits 610 and 620 in the second embodiment in the second embodiment. The error detection circuit 610 includes an inverter 611, a delay unit 612, a latch 614, an XOR (exclusive OR) gate 615 and a latch 616.

  The inverter 611 inverts the minimum delay clock signal mCLK_A. The inverter 611 outputs the inverted minimum delay clock signal mCLK_A to the delay unit 612 and the latch 616 as the enable signal mCK2_A.

  The delay unit 612 includes odd-numbered stages of inverters 613, and those inverters 613 delay the minimum delay clock signal mCLK_A. Here, the number of inverters 613 is determined such that, for example, the delay time in the delay unit 612 is approximately the same as the hold time of the flip-flop 510. The delay unit 612 outputs a signal obtained by delaying the minimum delay clock signal mCLK_A to the latch 614 as the enable signal mCLK_EX_A. Note that the inverter 611 and the delay unit 612 may be provided in the clock distribution unit 400 instead of the error detection circuit 610.

  The latches 614 and 616 transmit or hold data according to the enable signal. The latches 614 and 616 include an input terminal D, an output terminal Q, and a gate enable terminal G, respectively. An enable signal is input to the gate enable terminal G. The latches 614 and 616 pass through the signal input to the input terminal D to the output terminal Q when the enable signal is on. On the other hand, when the enable signal is in the off state, the latches 614 and 616 hold and output the value of the signal input to the input terminal D when the enable signal is in the on state.

  An input signal D_A from the synchronous operation circuit 500 is input to the input terminal D of the latch 614. The output terminal Q of the latch 614 is connected to the input terminal of the XOR gate 615. An enable signal mCK_EX_A is input to the gate enable terminal G of the latch 614.

  The XOR gate 615 outputs an exclusive OR of the signal output from the latch 614 and the latch output signal L_A from the synchronous operation circuit 500 to the latch 616.

  The output terminal of the XOR gate 615 is connected to the input terminal D of the latch 616. The output terminal Q of the latch 616 is connected to the error number counter 630. An enable signal mCK2_A is input to the gate enable terminal G of the latch 616.

  The error detection circuit 620 includes an inverter 621, a delay unit 622, a latch 624, an XOR gate 625, and a latch 626.

  The inverter 621 inverts the minimum delay clock signal mCLK_B. The inverter 621 outputs the inverted minimum delay clock signal mCLK_B to the delay unit 622 and the latch 626 as the enable signal mCK2_B.

  The delay unit 622 includes an odd number of stages of inverters 623 and delays the minimum delay clock signal mCLK_B by the inverters 623. The delay unit 622 outputs a signal obtained by delaying the minimum delay clock signal mCLK_B to the latch 624 as the enable signal mCLK_EX_B.

  The configuration of the latches 624 and 626 is the same as that of the latch 614. An input signal D_B from the synchronous operation circuit 500 is input to the input terminal D of the latch 624. The output terminal Q of the latch 624 is connected to the input terminal of the XOR gate 625. An enable signal mCLK_EX_B is input to the gate enable terminal G of the latch 624.

  The XOR gate 625 outputs an exclusive OR of the signal output from the latch 624 and the latch output signal L_B from the synchronous operation circuit 500 to the latch 626.

  The output terminal of the XOR gate 625 is connected to the input terminal D of the latch 626. The output terminal Q of the latch 626 is connected to the error number counter 640. An enable signal mCK2_B is input to the gate enable terminal G of the latch 626.

  In this configuration, the latch output signal L_A is a value in which the input signal D_A at the falling edge of the minimum delay clock signal mCLK_A is held by the latch 511 in FIG. On the other hand, the latch 614 in FIG. 17 holds the input signal D0 at a timing delayed by the hold time from the falling edge of the minimum delay clock signal mCLK_A. The XOR gate 615 outputs a timing error if the values of these signals do not match. Therefore, an error is detected when the input signal D_A changes between the falling edge of the minimum delay clock signal mCLK_A and the hold time elapses (that is, when a hold violation error occurs).

  Here, consider a case where the input signal D_A changes within a period that goes back the setup time of the latch 511 from the falling edge of the minimum delay clock signal mCLK_A (that is, a setup violation error occurs). In this case, the changed value is not held in the latch 511. As a result, a timing error is detected even when a setup violation error occurs.

  That is, the timing error is detected in the error detection circuit 610 when the input signal D_A changes in the period including the setup time and the hold time at the falling edge of the minimum delay clock signal mCLK_A. The error detection circuit 620 also detects a timing error when the input signal D_B changes in a period including the setup time and the hold time with the falling edge of the minimum delay clock signal mCLK_B as a boundary.

  As the variation in the delay of the main clock signal instructing the timing to the flip-flop is larger, a timing error is more likely to occur in the flip-flop. Therefore, the error measurement unit 600 can measure the variation in the delay of the main clock signal by counting the number of errors in the measurement period (that is, the frequency of occurrence of errors).

[Configuration example of clock distribution circuit controller]
FIG. 18 is a block diagram illustrating a configuration example of the clock distribution circuit control unit 700 according to the second embodiment. The clock distribution circuit control unit 700 includes a main clock distribution circuit control unit 710 and a sub clock distribution circuit control unit 720.

  The main clock distribution circuit control unit 710 controls the main clock distribution circuit 440. The main clock distribution circuit control unit 710 generates and outputs ON enable signals En_M_Root, En_M_A, and En_M_B when the synchronous operation circuit 500 is operated.

  The sub clock distribution circuit control unit 720 controls the sub clock distribution circuit 450. Specifically, the sub clock distribution circuit control unit 720 refers to the power supply voltage VDD from the power supply unit 200 and generates the enable signals En_S_Root, En_S_A, and En_S_B in the off state when the power supply voltage VDD is greater than a predetermined voltage. Output. On the other hand, consider a case where the supply voltage VDD is equal to or lower than a predetermined voltage. In this case, the sub clock distribution circuit control unit 720 turns on the enable signals En_CNT_A and En_CNT_B while keeping the enable signals En_S_Root, En_S_A, and En_S_B in the off state. As a result, timing error counting is started.

  Then, the sub clock distribution circuit control unit 720 receives the count values ERR_CNT_A and ERR_CNT_B from the error measurement unit 600, and controls the sub clock distribution circuit 450 based on the count values. Specifically, the sub clock distribution circuit 450 is instructed to distribute the sub timing signal to the OR gate (461 or 462) connected to the path whose count value is equal to or greater than the predetermined value. The instruction is performed by turning on necessary signals among the enable signals En_S_Root, En_S_A, and En_S_B. Specifically, when the count value ERR_CNT_A becomes equal to or greater than a predetermined value, the sub clock distribution circuit control unit 720 turns on the enable signals En_S_Root and En_S_A. As a result, the path S_A is activated and the sub clock signal is distributed to the OR gate 461. Further, when the count value ERR_CNT_B becomes equal to or greater than a predetermined value, the sub clock distribution circuit control unit 720 turns on the enable signals En_S_Root and En_S_B. As a result, the path S_B is activated and the sub clock signal is distributed to the OR gate 462.

[Operation example of clock distribution circuit controller]
FIG. 19 is a flowchart illustrating an example of the operation of the clock distribution circuit control unit 700 according to the second embodiment. This operation starts when the synchronous operation circuit 500 is operated.

  The clock distribution circuit controller 700 activates the main clock distribution circuit 440 by turning on the enable signal En_M, and deactivates the sub clock distribution circuit 450 by turning off the enable signal En_S (step S901). The clock distribution circuit control unit 700 determines whether or not the supply voltage VDD is equal to or lower than a predetermined voltage (step S902).

  When the supply voltage VDD is not less than or equal to the predetermined voltage (step S902: No), the clock distribution circuit control unit 700 returns to step S901. When the supply voltage VDD is equal to or lower than the predetermined voltage (step S902: Yes), the clock distribution circuit control unit 700 causes the error measurement unit 600 to start counting timing errors in each of the paths M_A and M_B (step S903).

  The clock distribution circuit control unit 700 determines whether any of the count values is greater than or equal to a predetermined value (step S904). If any of the count values is less than the predetermined value (step S904: No), the clock distribution circuit control unit 700 returns to step S902. When any one of the count values is equal to or greater than the predetermined value (step S904: Yes), the clock distribution circuit control unit 700 activates the path (S_A or S_B) of the sub clock distribution circuit 450 whose count value is equal to or greater than the predetermined value. (Step S905). After step S905, the clock distribution circuit control unit 700 ends the operation for controlling the clock distribution unit 400.

  As described above, according to the second embodiment, the main clock distribution circuit 440 branches the clock signal into a plurality of main timing signals and distributes them. On the other hand, the sub clock distribution circuit 450 divides the clock signal into a plurality of sub timing signals and distributes them according to the enable signal. OR gates 461 and 462 output the previously distributed signal of the main timing signal and the sub-timing signal as minimum delay timing signal mCLK, respectively. The synchronous operation circuit 500 operates in synchronization with the minimum delay timing signal mCLK. While the error measurement unit 600 measures the detection frequency of the timing error, the clock distribution circuit control unit 700 sends the clock signal to the sub clock distribution circuit 450 by the enable signal when the detection frequency of the timing error is a predetermined value or more. Direct distribution. As a result, the sub clock signal is distributed by the sub clock distribution circuit 450 when the detection frequency of the timing error exceeds a predetermined value. When the sub clock signal is distributed, the OR gates 461 and 462 each output the signal distributed first, so that the clock skew variation is reduced. Further, since the sub clock distribution circuit 450 is activated only when the detection frequency of timing errors is high, an increase in power consumption is suppressed as compared with a configuration in which the buffer size is increased. Furthermore, even when the values of the clock signals CLK are different, no short-circuit current is generated unlike the mesh wiring, so that an increase in power consumption is suppressed as compared with the mesh wiring.

  The main clock distribution circuit 440 and the sub clock distribution circuit 450 are configured to have two paths, but may have only one path. Three or more routes may be provided.

  Further, the integrated circuit 100 measures the timing error detection frequency. However, the integrated circuit 100 may measure a value other than the timing error detection frequency as long as the value indicates a variation in the delay of the clock signal. For example, the integrated circuit 100 may be configured to measure the delay variation of the clock signal itself.

  The synchronous operation circuit 500 includes one flip-flop for the path A_M, but the circuit configuration of the synchronous operation circuit 500 is not limited to this configuration. For example, two or more flip-flops may be provided for the path A_M. The same applies to the route B_M.

  Further, although the integrated circuit 100 is configured to generate the minimum delay timing signal mCLK using the OR gates 461 and 462, the minimum delay timing signal mCLK may be generated using a logic gate other than the OR gate. . For example, when the synchronous operation circuit 500 operates in synchronization with the falling edge, the integrated circuit 100 may generate the minimum delay timing signal mCLK by an AND gate instead of the OR gate.

[First Modification]
FIG. 20 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the first modification example of the second embodiment. The configuration of the clock distribution unit 400 in the first modification is different from that of the first embodiment in that NOR gates 463 and 464 are provided instead of the OR gates 461 and 462. The configuration of the synchronous operation circuit 500 in the first modified example is different from that of the second embodiment in that inverters 530 and 540 are further provided.

  The NOR gate 463 outputs a negative logical sum of the main clock signal CLK_M_A and the sub clock signal CLK_S_A to the inverter 530 as the minimum delay clock signal mCLK_A. The NOR gate 464 outputs a negative logical sum of the main clock signal CLK_M_B and the sub clock signal CLK_S_B to the inverter 540 as the minimum delay clock signal mCLK_B. The inverter 530 inverts the minimum delay clock signal mCLK_A and outputs the inverted signal to the flip-flop 510. The inverter 540 inverts the minimum delay clock signal mCLK_B and outputs it to the flip-flop 520.

  As described above, according to the first modification, the clock skew variation can be reduced in the configuration in which the inverter is provided at the clock input terminals of the flip-flops 510 and 520.

[Second Modification]
FIG. 21 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the second modification example of the second embodiment. The configuration of the clock distribution unit 400 in the second modified example is different from that of the second embodiment in that NOR gates 463 and 464 are provided instead of the OR gates 461 and 462. The configuration of the synchronous operation circuit 500 in the second modified example is different from that in the second embodiment in that inverters 530 and 540 and a mesh wiring 550 are further provided.

  The configurations of the NOR gates 463 and 464 are the same as in the sixth modification. Inverters 530 and 540 invert minimum delay clock signals mCLK_A and mCLK_B and output them to mesh wiring 550. The mesh wiring 550 distributes the minimum delay clock signal mCLK to a plurality of regions arranged in a lattice shape. In these regions, flip-flops 510 and 520 are arranged.

  As described above, according to the second modification, it is possible to reduce variations in clock skew in the configuration in which the mesh wiring 550 is connected to the clock input terminals of the flip-flops 510 and 520.

[Third Modification]
FIG. 22 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the third modification example of the first embodiment. In the second embodiment described above, it is assumed that the synchronous operation circuit 500 operates on the rising edge of the clock signal. However, in the third modification, the synchronous operation circuit 500 operates on the falling edge. Is assumed. Specifically, the configuration of the clock distribution unit 400 in the third modified example is different from that of the second embodiment in that it includes AND (logical product) gates 465 and 466 instead of the OR gates 461 and 462. The configuration of the synchronous operation circuit 500 in the third modified example is different from that of the second embodiment in that flip-flops 560 and 570 are provided instead of the flip-flops 510 and 520.

  The AND gate 465 outputs a logical product of the main clock signal CLK_M_A and the sub clock signal CLK_S_A to the flip-flop 560 as the minimum delay clock signal mCLK_A. The AND gate 466 outputs a logical product of the main clock signal CLK_M_B and the sub clock signal CLK_S_B to the flip-flop 570 as the minimum delay clock signal mCLK_B. The flip-flops 560 and 570 capture and hold data in synchronization with the falling edges of the minimum delay clock signals mCLK_A and mCLK_B.

  As described above, according to the third modification, the clock skew variation can be reduced in the configuration in which the synchronous operation circuit 500 operates in synchronization with the falling edge of the clock signal.

[Fourth Modification]
FIG. 23 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the fourth modification example of the second embodiment. In the fourth modified example, it is assumed that the synchronous operation circuit 500 operates on the falling edge as in the third modified example. The configuration of the clock distribution unit 400 in the fourth modified example is different from that of the second embodiment in that NAND (negative AND) gates 467 and 468 are provided instead of the OR gates 461 and 462. The configuration of the synchronous operation circuit 500 in the fourth modified example is different from that of the second embodiment in that flip-flops 560 and 570 are provided instead of the flip-flops 510 and 520 and inverters 530 and 540 are further provided.

  The NAND gate 467 outputs a negative logical product of the main clock signal CLK_M_A and the sub clock signal CLK_S_A to the inverter 530 as the minimum delay clock signal mCLK_A. The NAND gate 468 outputs a negative logical product of the main clock signal CLK_M_B and the sub clock signal CLK_S_B to the inverter 540 as the minimum delay clock signal mCLK_B. The inverter 530 inverts the minimum delay clock signal mCLK_A and outputs it to the flip-flop 560. The inverter 540 inverts the minimum delay clock signal mCLK_B and outputs it to the flip-flop 570. The flip-flops 560 and 570 capture and hold data in synchronization with the falling edges of the minimum delay clock signals mCLK_A and mCLK_B.

  As described above, according to the fourth modification example, in the configuration in which the clock input terminals of the flip-flops 510 and 520 are provided with the inverter and the synchronous operation circuit 500 operates in synchronization with the falling edge of the clock signal, Variations can be reduced.

[Fifth Modification]
FIG. 24 is a circuit diagram showing a configuration example of the clock distribution unit 400 and the synchronous operation circuit 500 in the fifth modification example of the second embodiment. Also in the fifth modification example, it is assumed that the synchronous operation circuit 500 operates on the falling edge as in the third modification example. The configuration of the clock distribution unit 400 in the fifth modification example is different from that of the second embodiment in that NAND gates 467 and 468 are provided instead of the OR gates 461 and 462. The configuration of the synchronous operation circuit 500 in the fifth modified example is different from that of the second embodiment in that flip-flops 560 and 570 are provided instead of the flip-flops 510 and 520. The configuration of the synchronous operation circuit 500 in the fifth modification example is different from that of the second embodiment in that inverters 530 and 540 and a mesh wiring 550 are further provided.

  The configurations of NAND gates 467 and 468 are the same as in the fourth modification example of the second embodiment. The configurations of inverters 530 and 540 and mesh wiring 550 are the same as those of the second modification example of the second embodiment. The configuration of flip-flops 560 and 570 is the same as that of the fourth modification example of the second embodiment.

  As described above, according to the fifth modification, in the configuration in which the clock input terminals of the flip-flops 510 and 520 are connected to the mesh wiring, and the synchronous operation circuit 500 operates in synchronization with the falling edge of the clock signal, Can be reduced.

<3. Third Embodiment>
[Configuration example of integrated circuit]
FIG. 25 is a block diagram illustrating a configuration example of the integrated circuit 100 according to the third embodiment. The integrated circuit 100 according to the third embodiment includes a power supply unit 200, a clock generation unit 300, a clock distribution circuit 410, a synchronous operation circuit 500, a combinational logic circuit 580, and an error measurement unit 600.

  The power supply unit 200 supplies power to the clock distribution circuit 410, the synchronous operation circuit 500, and the combinational logic circuit 580. Specifically, the power supply unit 200 steps down the power supply voltage VDD. The stepped down voltage is supplied to the clock distribution circuit 410 via the signal line 207 as the clock distribution circuit drive voltage vCK. The power supply unit 200 supplies a voltage lower than the clock distribution circuit drive voltage vCK to the combinational logic circuit 580 and the synchronous operation circuit 500 as the logic circuit drive voltage vDP via the signal line 208.

  The clock generator 300 generates a clock signal CLK having a predetermined frequency using a PLL or the like. The clock signal CLK is generated as a signal for instructing the synchronous operation circuit 500 and the error measurement unit 600 at a predetermined timing. The clock generation unit 300 outputs the generated clock signal CLK to the clock distribution circuit 410 via the signal line 309.

  The clock distribution circuit 410 distributes the clock signal CLK to each of the circuits in the integrated circuit 100 including the synchronous operation circuit 500. The clock distribution circuit 410 distributes the clock signal CLK to the synchronous operation circuit 500 via the signal line 409 and distributes it to the error measurement unit 600 via the signal line 408. For the error measurement unit 600, the clock signal CLK is distributed to indicate the timing of counting the number of errors. The clock distribution circuit 410 is an example of a timing signal distribution circuit described in the claims.

  The synchronous operation circuit 500 is a circuit that operates in synchronization with the clock signal CLK. The combinational logic circuit 580 executes a predetermined logical operation based on the operation result of the synchronous operation circuit 500. The combinational logic circuit 580 is an example of a logic circuit described in the claims.

  The error measurement unit 600 detects a timing error occurring in the synchronous operation circuit 500 and measures the detection frequency. The detection frequency of timing errors is measured, for example, by counting the number of errors within a certain measurement period. The error measuring unit 600 outputs the timing error count value ERR_CNT to the power supply unit 200 via the signal line 609.

  FIG. 26 is a circuit diagram showing a configuration example of the clock distribution circuit 410 and the synchronous operation circuit 500 according to the third embodiment. The clock distribution circuit 410 includes buffers 411 having a predetermined number of stages, and distributes the clock signal CLK to the synchronous operation circuit 500 through the buffers 411. The synchronous operation circuit 500 includes flip-flops 510 and 520. The flip-flops 510 and 520 capture and hold data in synchronization with the distributed clock signal CLK. The input signal D0 input to the flip-flop 510 and the latch output signal L0 from the flip-flop 510 are output to the error measurement unit 600 via the signal line 509.

  The synchronous operation circuit 500 outputs necessary data in the combinational logic circuit 580 or receives data generated in the combinational logic circuit 580. For example, the flip-flop 510 outputs the held signal to the combinational logic circuit 580 as the output signal Q0. The flip-flop 520 receives and holds the input signal D1 from the combinational logic circuit 580, and outputs the held signal to the combinational logic circuit 580 as the output signal Q1.

  FIG. 27 is a block diagram illustrating a configuration example of the error measurement unit 600 according to the third embodiment. The error measurement unit 600 includes an error detection circuit 610 and an error number counter 631. The configuration of the error detection circuit 610 is the same as the configuration of the error detection circuit 610 in the second embodiment. The error number counter 631 counts the number of errors detected in the error detection circuit 610 within a predetermined measurement period in synchronization with the clock signal CLK. The error number counter 631 outputs the count value ERR_CNT to the power supply unit 200.

  FIG. 28 is a diagram illustrating an implementation example of the clock distribution circuit 410, the synchronous operation circuit 500, and the combinational logic circuit 580 according to the third embodiment. The dotted line in the figure is a wiring for distributing the clock signal CLK. A plurality of signal lines including signal lines 207 and 208 are wired in the integrated circuit 100, and a circuit is connected to these signal lines. However, the clock distribution circuit 410, the synchronous operation circuit 500, and the combinational logic circuit 580 are arranged so that different voltages are supplied thereto. Specifically, the clock distribution circuit 410 is connected to the signal line 207. A circuit is arranged on this signal line 207 so that flip-flops 510 and 520 and logic gate 581 in combinational logic circuit 580 are not connected. On the other hand, flip-flops 510 and 520 and a logic gate 581 are connected to the signal line 208. A circuit is arranged on the signal line 208 so that the clock distribution circuit 410 is not connected thereto. By arranging the circuits in this way, the clock distribution circuit 410 is supplied with the clock distribution circuit drive voltage vCK via the signal line 207, and the synchronous operation circuit 500 and the combinational logic circuit 580 are logically connected via the signal line 208. A circuit drive voltage vDP is supplied.

[Configuration example of power supply unit]
FIG. 29 is a block diagram illustrating a configuration example of the power supply unit 200 according to the third embodiment. The power supply unit 200 includes a clock distribution circuit drive voltage control unit 210 and a logic circuit drive voltage control unit 220. The clock distribution circuit drive voltage controller 210 steps down the power supply voltage VDD and supplies it to the clock distribution circuit 410 as the clock distribution circuit drive voltage vCK. The logic circuit drive voltage controller 220 steps down the clock distribution circuit drive voltage vCK and supplies it to the synchronous operation circuit 500 and the combinational logic circuit 580 as the logic circuit drive voltage vDP. The clock distribution circuit drive voltage control unit 210 is an example of a timing signal distribution circuit drive voltage control unit described in the claims.

  FIG. 30 is a block diagram illustrating a configuration example of the clock distribution circuit drive voltage control unit 210 according to the third embodiment. The clock distribution circuit drive voltage control unit 210 includes a clock distribution circuit drive voltage control circuit 211, a voltage control register 212, and a variable resistor 214. One terminal of the variable resistor 214 is connected to a power supply that supplies a power supply voltage VDD, and the other terminal is connected to the power supply line 207. The clock distribution circuit drive voltage control circuit 211 steps down the power supply voltage VDD by updating the value of the voltage control register 212 and supplies it as the clock distribution circuit drive voltage vCK. When the error count value ERR_CNT is less than the threshold Th, the clock distribution circuit drive voltage control circuit 211 steps down the clock distribution circuit drive voltage vCK to the set value Vsc. On the other hand, when the error count value ERR_CNT is greater than or equal to the threshold Th, the clock distribution circuit drive voltage control circuit 211 boosts the clock distribution circuit drive voltage vCK to the set value Vec. Note that Vec is set to a value higher than Vsc.

  The voltage control register 212 holds a value for controlling the resistivity of the variable resistor 214. The variable resistor 214 is a resistor whose resistance value changes in accordance with a change in the value held in the voltage control register 212. The clock distribution circuit drive voltage vCK supplied changes due to the change in the resistance value of the variable resistor 214.

  FIG. 31 is a diagram illustrating an example of the operation of the clock distribution circuit drive voltage control circuit 211 in the third embodiment. When the error count value ERR_CNT is less than the threshold Th, the clock distribution circuit drive voltage control circuit 211 refers to the value of the voltage control register 212 and acquires the current value of the clock distribution circuit drive voltage vCK. Then, the clock distribution circuit drive voltage control circuit 211 determines whether or not the clock distribution circuit drive voltage vCK is larger than the set value Vsc. If the clock distribution circuit drive voltage vCK is larger than the set value Vsc, the clock distribution circuit drive voltage control circuit 211 steps down the clock distribution circuit drive voltage vCK to the set value Vsc. On the other hand, when the error count value ERR_CNT is equal to or greater than the threshold Th, the clock distribution circuit drive voltage control circuit 211 urgently boosts the clock distribution circuit drive voltage vCK to the set value Vec.

  FIG. 32 is a circuit diagram showing a configuration example of the voltage control register 212 and the variable resistor 214 in the third embodiment. The voltage control register 212 includes n (n is an integer of 1 or more) flip-flops 213. The variable resistor 214 includes n pMOS transistors 215 connected in parallel. The flip-flop 213 holds 1-bit data. The initial value of the data held by each flip-flop 213 is “0”, for example, and the data value is updated by the clock distribution circuit drive voltage control circuit 211. The output terminal of the flip-flop 213 and the gate terminal of the pMOS transistor 215 are connected on a one-to-one basis.

The pMOS transistor 215 allows a current to flow between the source and the drain in accordance with the value of the signal input to the gate terminal. The pMOS transistor 215 includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is connected to the output terminal of the flip-flop 213, the source terminal is connected to the power supply that supplies the power supply voltage VDD, and the drain terminal is connected to the signal line 207. The pMOS transistor 215 is turned on when the holding value of the flip-flop 213 input to the gate terminal is “0”, and a current flows between the source terminal and the drain terminal, and the holding value is “1”. Will be off. Here, the resistance between the gate terminal and the drain terminal in the on state of one pMOS transistor is R ₀ . When the number of pMOS transistors 215 in the on state is m (m is an integer of 1 or more), the combined resistance R of the variable resistor 214 is R ₀ / m. That is, as the value of “0” in the voltage control register 212 increases, the number of pMOS transistors 215 in the on state increases, the combined resistance R decreases, and the clock distribution circuit drive voltage vCK increases. The variable resistor 214 only needs to have a configuration that can control the resistance value, and is not limited to a configuration in which the pMOS transistors 215 are connected in parallel.

  FIG. 33 is a block diagram illustrating a configuration example of the logic circuit drive voltage control unit 220 according to the third embodiment. The logic circuit drive voltage control unit 220 includes a logic circuit drive voltage control circuit 221, a voltage control register 222, and a variable resistor 224. One terminal of the variable resistor 224 is connected to the signal line 207, and the other terminal is connected to the signal line 208. The clock distribution circuit drive voltage control circuit 211 updates the value of the voltage control register 222 to step down the clock distribution circuit drive voltage vCK and supply it as the logic circuit drive voltage vDP. When the error count value ERR_CNT is less than the threshold Th, the logic circuit drive voltage control circuit 221 steps down the logic circuit drive voltage vDP to the set value Vsd. On the other hand, when the error count value ERR_CNT is equal to or greater than the threshold Th, the logic circuit drive voltage control circuit 221 boosts the logic circuit drive voltage vDP to the set value Ved. Ved is set to a value higher than Vsd.

  FIG. 34 is a diagram illustrating an example of the operation of the logic circuit drive voltage control circuit 221 according to the third embodiment. When the error count value ERR_CNT is less than the threshold Th, the logic circuit drive voltage control circuit 221 refers to the value of the voltage control register 222 and acquires the current value of the logic circuit drive voltage vDP. Then, the logic circuit drive voltage control circuit 221 determines whether or not the logic circuit drive voltage vDP is larger than the set value Vsd. If the logic circuit drive voltage vDP is larger than the set value Vsd, the logic circuit drive voltage control circuit 221 steps down the logic circuit drive voltage vDP to the set value Vsd. On the other hand, when the error count value ERR_CNT is greater than or equal to the threshold Th, the logic circuit drive voltage control circuit 221 urgently boosts the logic circuit drive voltage vDP to the set value Ved.

[Operation example of power supply unit]
FIG. 35 is a flowchart illustrating an example of the operation of the clock distribution circuit drive voltage control circuit 211 in the third embodiment. The clock distribution circuit drive voltage control circuit 211 determines whether or not the error count value ERR_CNT is greater than or equal to the threshold value Th (step S911). When the count value ERR_CNT is greater than or equal to the threshold Th (step S911: Yes), the clock distribution circuit drive voltage control circuit 211 urgently boosts the clock distribution circuit drive voltage vCK to the set value Vec (step S912). After step S912, the clock distribution circuit drive voltage control circuit 211 returns to step S911.

  When the count value ERR_CNT is less than the threshold Th (step S911: No), the clock distribution circuit drive voltage control circuit 211 determines whether or not the clock distribution circuit drive voltage vCK is larger than the set value Vsc (step S913). When the clock distribution circuit drive voltage vCK is larger than the set value Vsc (step S913: Yes), the clock distribution circuit drive voltage control circuit 211 steps down the clock distribution circuit drive voltage vCK to the set value Vsc (step S914). When the clock distribution circuit drive voltage vCK is equal to or lower than the set value Vsc (step S913: No), or after step S914, the clock distribution circuit drive voltage control circuit 211 returns to step S911.

  FIG. 36 is a flowchart illustrating an example of the operation of the logic circuit drive voltage control circuit 221 according to the third embodiment. The logic circuit drive voltage control circuit 221 determines whether or not the error count value ERR_CNT is equal to or greater than the threshold value Th (step S921). When the count value ERR_CNT is greater than or equal to the threshold Th (step S921: Yes), the logic circuit drive voltage control circuit 221 urgently boosts the logic circuit drive voltage vDP to the set value Ved (step S922). After step S912, the logic circuit drive voltage control circuit 221 returns to step S921.

When the count value ERR_CNT is less than the threshold Th (step S921: No), the logic circuit drive voltage control circuit 221 determines whether or not the logic circuit drive voltage vDP is greater than the set value Vsd (step S923). When the logic circuit drive voltage vDP is larger than the set value Vsd (step S923: Yes), the logic circuit drive voltage control circuit 221 reduces the logic circuit drive voltage vDP to the set value Vsd (step S924). When the logic circuit drive voltage vDP is equal to or lower than the set value Vsd (step S923: No), or after step S924, the logic circuit drive voltage control circuit 221 returns to step S921.

  FIG. 37 is a graph illustrating a first setting example of the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP in the third embodiment. The vertical axis of the graph is the set value of the clock distribution circuit drive voltage vCK, and the horizontal axis is the set value of the logic circuit drive voltage vDP. In the first setting example, when the logic circuit drive voltage vDP is lower than Vc (for example, 0.7 V), a voltage higher than the logic circuit drive voltage vDP is set as the clock distribution circuit drive voltage vCK. In the interval lower than Vc, the voltage value difference between the logic circuit drive voltage vDP and the clock distribution circuit drive voltage vCK is set to be constant. In the interval equal to or higher than Vc, the voltage values of the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP are set to be the same.

  Note that a voltage other than the set value illustrated in FIG. 37 may be set in the voltage supply unit 200. For example, FIG. 38 is a graph showing a second setting example of the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP. In the second setting example, when the logic circuit driving voltage vDP is lower than Vc1 (for example, 0.7 V), the voltage higher than the logic circuit driving voltage vDP is the clock distribution circuit driving voltage, as in the first setting example. Set to vCK. In a section where the logic circuit drive voltage vDP is equal to or higher than Vc1 and equal to or less than Vc2 (> Vc1), the voltage values of the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP are set to be the same. In a section where the logic circuit drive voltage vDP is higher than Vc2, a voltage lower than the logic circuit drive voltage vDP is set as the clock distribution circuit drive voltage vCK. According to this second setting example, the power consumption can be reduced even when the voltage is sufficiently high.

  For example, FIG. 39 is a graph illustrating a third setting example of the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP. In the third setting example, a constant voltage value (for example, Vc) is set as the clock distribution circuit drive voltage vCK in a section where the logic circuit drive voltage vDP is lower than Vc. According to the third setting example, the integrated circuit 100 can reduce the power consumption while controlling the clock distribution circuit drive voltage vCK so as not to be less than the minimum operating voltage.

  As described above, according to the third embodiment, the power supply unit 200 supplies the logic circuit drive voltage vDP lower than the clock distribution circuit drive voltage vCK to the combinational logic circuit 580 in the low voltage region. As a result, power consumption can be easily reduced as compared with a configuration in which a voltage having the same value is supplied to the clock distribution circuit 410 and the combinational logic circuit 580. As described above, the skew in the clock distribution circuit 410 increases exponentially as the voltage decreases, but the combinational logic circuit 580 has less influence of the skew than the clock distribution circuit 410. For this reason, the minimum operating voltage of the combinational logic circuit 580 may be set lower than that of the clock distribution circuit 410. Therefore, by making the logic circuit drive voltage vDP lower than the clock distribution circuit drive voltage vCK, the power consumption of the entire integrated circuit 100 can be easily reduced.

  Note that the integrated circuit 100 of the third embodiment includes the clock distribution unit 400 of the first embodiment instead of the clock distribution circuit 410 and distributes the minimum delay clock signal mCLK to the synchronous operation circuit 500. Good. This further reduces clock skew. Similarly, the integrated circuit 100 of the third embodiment includes the clock distribution circuit control unit 700 and the clock distribution unit 400 of the second embodiment instead of the clock distribution circuit 410, and synchronizes the minimum delay clock signal mCLK. It may be distributed to the operation circuit 500.

[First Modification]
FIG. 40 is a block diagram illustrating a configuration example of the integrated circuit 100 according to the first modification example of the third embodiment. In the above-described third embodiment, the voltage supply unit 200 supplies the logic circuit drive voltage vDP to the synchronous operation circuit 200. However, other voltages may be supplied to the synchronous operation circuit 200. For example, the voltage supply unit 200 may supply the clock distribution circuit drive voltage vCK to the synchronous operation circuit 500. The power supply unit 200 of the first modification is different from the third embodiment in that the clock distribution circuit drive voltage vCK is supplied to the synchronous operation circuit 500 via the signal line 207.

  According to the first modification, power consumption can be reduced in the configuration in which the clock distribution circuit drive voltage vCK is supplied to the synchronous operation circuit 500.

[Second Modification]
FIG. 41 is a block diagram illustrating a configuration example of the power supply unit 200 in the second modification example of the third embodiment. In the above-described third embodiment, the clock distribution circuit drive voltage control unit 210 and the logic circuit drive voltage control unit 220 are connected in series to the power supply. However, they may be connected in parallel. . The power supply unit 200 of the second modification is different from the third embodiment in that the clock distribution circuit drive voltage control unit 210 and the logic circuit drive voltage control unit 220 are connected in parallel to the power supply. In the second modification, the set value Vsd of the logic circuit drive voltage vDP is set to a value smaller than the set value Vsc of the clock distribution circuit drive voltage vCK.

  According to the second modification, power consumption can be reduced in the configuration in which the clock distribution circuit drive voltage control unit 210 and the logic circuit drive voltage control unit 220 are connected in parallel.

[Third Modification]
FIG. 42 is a block diagram illustrating a configuration example of the integrated circuit 100 according to the third modification example of the third embodiment. The power supply unit 200 may supply the synchronous operation circuit 500 with a voltage different from both the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP. The power supply unit 200 of the third modified example is different from the third embodiment in that the synchronous operation circuit drive voltage vFF is supplied to the synchronous operation circuit 500 via the signal line 206.

  According to the third modification, power consumption can be reduced in the configuration in which the synchronous operation circuit drive voltage vFF different from both vDP and vCK is supplied to the synchronous operation circuit 500.

[Fourth Modification]
FIG. 43 is a block diagram illustrating a configuration example of the power supply unit 200 in the fourth modification example of the third embodiment. The power supply unit 200 of the fourth modified example is different from the third embodiment in that only the clock distribution circuit drive voltage control unit 210 performs emergency boosting. In the fourth modification, the error count value ERR_CNT is input only to the clock distribution circuit drive voltage control unit 210. When the count value ERR_CNT is equal to or greater than the threshold Th, the clock distribution circuit drive voltage control unit 210 performs emergency boosting, while the logic circuit drive voltage control unit 220 does not perform emergency boosting.

  According to the fourth modification, since the logic circuit drive voltage vDP is not urgently boosted, the power consumption during the urgent boost is reduced.

<4. Fourth Embodiment>
[Configuration example of integrated circuit]
FIG. 44 is a block diagram illustrating a configuration example of the integrated circuit 100 according to the fourth embodiment. The integrated circuit 100 according to the fourth embodiment includes a power supply unit 200, a clock generation unit 300, a clock distribution circuit 410, a synchronous operation circuit 500, a combinational logic circuit 580, an error measurement unit 600, and an error compensation control unit 800. .

  The power supply unit 200 supplies power to the clock distribution circuit 410, the synchronous operation circuit 500, and the combinational logic circuit 580. Specifically, the power supply unit 200 supplies a clock distribution circuit drive voltage vCK having a predetermined voltage value to the clock distribution circuit 410 via the signal line 207. The power supply unit 200 supplies the logic circuit drive voltage vDP having a predetermined voltage value to the synchronous operation circuit 500 and the combinational logic circuit 580 via the signal line 208.

  The power supply unit 200 controls the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP according to the analysis result of the error compensation control unit 800. The analysis result includes, for example, a setup violation error, a hold violation error, and a warning of the hold violation error. The power supply unit 200 urgently boosts the clock distribution circuit drive voltage vCK when a setup violation error occurs, and urgently boosts the clock distribution circuit drive voltage vCK and the logic circuit drive voltage vDP when a hold violation error occurs. When the power supply unit 200 receives the warning before the hold violation error occurs, the power supply unit 200 boosts the logic circuit drive voltage vDP to a voltage value lower than the voltage value at the time of emergency boosting.

  The clock generator 300 generates a clock signal CLK having a predetermined frequency using a PLL or the like. The clock signal CLK is generated as a signal for instructing the synchronous operation circuit 500 and the error measurement unit 600 at a predetermined timing. The clock generation unit 300 outputs the generated clock signal CLK to the clock distribution circuit 410 via the signal line 309.

  The clock distribution circuit 410 distributes the clock signal CLK to each of the circuits in the integrated circuit 100 including the synchronous operation circuit 500. The clock distribution circuit 410 distributes the clock signal CLK to the synchronous operation circuit 500 via the signal line 409 and distributes it to the error measurement unit 600 via the signal line 408. For the error measurement unit 600, the clock signal CLK is distributed to indicate the timing of counting the number of errors. The clock distribution circuit 410 is an example of a timing signal distribution circuit described in the claims.

  The synchronous operation circuit 500 is a circuit that operates in synchronization with the clock signal CLK. The combinational logic circuit 580 executes a predetermined logical operation based on the operation result of the synchronous operation circuit 500.

  The error measurement unit 600 generates the error flags ERR1 and ERR2 based on the timing error generated in the synchronous operation circuit 500. The difference between the error flags ERR1 and ERR2 and details of their generation method will be described later. The error measurement unit 600 outputs the error flags ERR1 and ERR2 to the error compensation control unit 800 via the signal line 609.

  The error compensation control unit 800 analyzes timing errors based on the history of the error flags ERR1 and ERR2. The error compensation control unit 800 analyzes, for example, the type of timing error. Types of timing errors include setup violation errors, hold violation errors, and hold violation error warnings. A timing error analysis method will be described later. The error compensation control unit 800 outputs the analysis result to the power supply unit 200 via the signal line 809, and causes the power supply unit 200 to compensate for the error.

  FIG. 45 is a circuit diagram showing a configuration example of the error measurement unit 600, the synchronous operation circuit 500, and the clock distribution circuit 410 in the fourth embodiment. The error measurement unit 600 includes an error detection circuit 650, and the synchronous operation circuit 500 includes a flip-flop 510. Clock distribution circuit 410 includes inverters 471 and 474 and delay units 475 and 477.

  The inverters 471 and 474 invert the input clock signal and output it. The inverter 471 inverts the clock signal CLK from the clock generator 300 and outputs the inverted clock signal CKB to the synchronous operation circuit 500 via the signal line 409. The inverter 474 further inverts the inverted clock signal CKB and outputs it as the clock signal CK2 to the synchronous operation circuit 500 via the signal line 409. The inverter 474 outputs the clock signal CK2 to the error detection circuit 650 via the signal line 408.

  The delay units 475 and 477 are for delaying the clock signal. The delay unit 475 includes an odd number of inverters 476. The delay unit 475 delays the clock signal CK2 by the inverter 476 for a predetermined time, and outputs the delayed clock signal CKB_EX1 to the error detection circuit 650 via the signal line 408. Here, the number of inverters 476 is determined such that, for example, the delay time in the delay unit 475 is approximately equal to the hold time of the flip-flop 510. The delay unit 477 includes an even number of inverters 478. The delay unit 477 further delays the delayed clock signal CKB_EX1 by the inverters 478 and outputs the delayed clock signal CKB_EX2 to the error detection circuit 650 via the signal line 408.

  The flip-flop 510 holds 1-bit data in synchronization with the inverted clock signal CKB. The flip-flop 510 includes latches 511 and 512.

  The latch 511 holds an input signal in synchronization with the inverted clock signal CKB. The latch 511 includes an input terminal Q, an output terminal D, and a gate enable terminal G. The input signal D 0 is input to the input terminal, the inverted clock signal CKB is input to the gate enable terminal G, and the output terminal D is connected to the input terminal of the latch 512. When the inverted clock signal CKB is in the ON state, the latch 511 outputs the input signal D0 as a latch output signal L0 to the error detection circuit 650 and the latch 512. On the other hand, when the inverted clock signal CKB is turned off, the latch 511 holds the input signal D0 at the falling edge, and uses the held signal as the latch output signal L0 to the error detection circuit 650 and the latch 512. Output.

  The configuration of the latches 512, 651, 653, 654 and 656 is the same as that of the latch 511. However, the latch 512 holds the latch output signal L0 and outputs it as the output signal Q0 when the clock signal CK2 is turned off. The latch 651 holds the input signal D0 and outputs it to the input terminal of the XOR gate 652 as the latch output signal L1 when the delayed clock signal CKB_EX1 is turned off. The latch 653 holds the error signal E1 from the XOR gate 652 and outputs it to the error compensation controller 800 as an error flag ERR1 when the clock signal CK2 is turned off. The latch 654 holds the input signal D0 and outputs it to the input terminal of the XOR gate 655 as the latch output signal L2 when the delayed clock signal CKB_EX2 is turned off. The latch 656 holds the error signal E2 from the XOR gate 655 and outputs the error signal ERR2 to the error compensation controller 800 when the clock signal CK2 is turned off.

  XOR gates 652 and 655 generate an exclusive OR of input signals. The XOR gate 652 outputs the exclusive OR of the latch output signals L1 and L0 from the latches 651 and 511 to the latch 653 as the error signal E1. XOR gate 655 outputs the exclusive OR of latch output signals L2 and L0 from latches 654 and 511 to latch 653 as error signal E2.

  The latch 511 is an example of a master latch described in the claims. The latch 651 and the XOR gate 652 are an example of a first error detection unit described in the claims. The latch 654 and the XOR gate 655 are an example of a second error detection unit described in the claims. The latch 651 is an example of a first latch described in the claims. The XOR gate 652 is an example of a first logic gate described in the claims. The latch 654 is an example of a second latch described in the claims. The XOR gate 655 is an example of a second logic gate described in the claims.

  In the configuration illustrated in FIG. 45, as in the second embodiment, the error signal E1 is output when the input signal D0 changes during the period from the monitoring start timing until the setup time and hold time elapse.

  Next, the latch 511 holds the input signal D0 at the falling edge of the inverted clock signal CKB, while the latch 651 holds the input signal D0 at the falling edge of the delayed clock signal CKB_EX2 obtained by further delaying the clock signal CKN_EX1. . Then, the XOR gate 655 detects a timing error if these signals do not match.

  Here, a period from the falling edge of the delayed clock signal CKB_EX1 to the falling edge of the delayed clock signal CKB_EX2 is hereinafter referred to as an “error warning period”. As described above, the XOR gate 655 compares the value of the input signal D0 at the falling edge of the inverted clock signal CKB with the input signal D0 at the falling edge of the delayed clock signal CKB_EX2 (that is, the end point of the error warning period). The result is output. For this reason, XOR gate 655 outputs error signal E2 when the value of input signal D0 changes between the falling edge of inverted clock signal CKB and the elapse of the hold time and error warning period. Even when the value of the input signal D0 changes between the monitoring start timing and the falling edge of the inverted clock signal CKB, the error signal E2 is output to the latch 511 without holding the changed value. .

  That is, the error signal E2 is output when the input signal D0 changes during the period from the monitoring start timing to the setup time, hold time, and error warning period.

  When the inverted clock signal CKB rises after the inverted clock signal CKB falls and the error signals E1 and E2 are output, the latch 511 is released and the input signal D0 and the latch output signal L0 have the same value. turn into. However, since the latches 653 and 656 in the subsequent stage hold the values of the error signals E1 and E2 before the rising of the inverted clock signal CKB, the error signals E1 and E2 before the falling also rise after the inverted clock signal CKB rises. The value is maintained.

  FIG. 46 is a block diagram illustrating a configuration example of the error compensation control unit 800 according to the fourth embodiment. The error compensation control unit 800 includes an error analysis unit 810 and an error flag previous value holding unit 820.

  The error analysis unit 810 analyzes the timing error based on the previous value and the current value of the timing errors ERR1 and ERR2. Specifically, the error analysis unit 810 determines that the timing error is a hold violation error when only the error flag RRR2 is detected last time and the error flags ERR1 and ERR2 are both detected this time. Then, the error analysis unit 810 outputs the hold violation error flag ERR_HOLD in the on state to the power supply unit 200 and updates the held value of the error flag previous value holding unit 820.

  On the other hand, if neither of the error flags ERR1 and ERR2 is detected last time and the error flags ERR1 and ERR2 are detected both this time, the error analysis unit 810 determines that the timing error is a setup violation error. Then, the error analysis unit 810 outputs the setup violation error flag ERR_SET in the on state to the power supply unit 200 and updates the held value of the error flag previous value holding unit 820.

  Further, when neither the error flag ERR1 nor ERR2 is detected last time and only the error flag ERR2 is detected this time, the error analysis unit 810 determines that the input signal D0 has changed during the error warning period. Then, the error analysis unit 810 outputs the hold violation warning flag AL_HOLD in the on state to the power supply unit 200 and updates the held value of the error flag previous value holding unit 820.

  The error flag previous value holding unit 820 holds the previous value ERR_PRE of the error flags ERR1 and ERR2. The error flag previous value holding unit 820 is an example of a history holding unit described in the claims.

  FIG. 47 is a diagram illustrating an example of the operation of the error analysis unit 810 according to the fourth embodiment. Consider a case where both error flags ERR1 and ERR2 are “0”. In this case, the error analysis unit 810 sets all values of the hold violation warning flag AL_HOLD, the hold violation error flag ERR_HOLD, and the setup violation error flag ERR_SET to “0”. Further, the error analysis unit 810 updates the error flag previous value PRE_ERR to “00”.

  When the error flag ERR1 is “0”, the error flag ERR2 is “1”, and the previous value of the error flag is “00”, the error analysis unit 810 sets the hold violation warning flag AL_HOLD to “1”. Further, the error analysis unit 810 sets both the hold violation error flag ERR_HOLD and the setup violation error flag ERR_SET to “0”. Then, the error analysis unit 810 updates the error flag previous value PRE_ERR to “01”.

  When the error flag ERR1 is “0”, the error flag ERR2 is “1”, and the previous value of the error flag is “01” or “11”, the error analysis unit 810 sets all the values of AL_HOLD, ERR_HOLD, and ERR_SET to “ 0 ”. Then, the error analysis unit 810 updates the error flag previous value PRE_ERR to “01”.

  Since the period during which the error flag ERR1 is detected is included in the period during which the error flag ERR2 is detected, only the error flag ERR1 does not become “1”.

  When the error flags ERR1 and ERR2 are both “1” and the previous value of the error flag is “00”, the error analysis unit 810 sets the value of the setup violation error flag ERR_SET to “1”. Further, the error analysis unit 810 sets both the values of the hold violation warning flag AL_HOLD and the hold violation error flag ERR_HOLD to “0”. Then, the error analysis unit 810 updates the error flag previous value PRE_ERR to “11”.

  When the error flags ERR1 and ERR2 are both “1” and the previous value of the error flag is “01”, the error analysis unit 810 sets the value of the hold violation error flag ERR_HOLD to “1”. Also, the error analysis unit 810 sets both the hold violation warning flag AL_HOLD and the setup violation error flag ERR_SET to “0”. Then, the error analysis unit 810 updates the error flag previous value PRE_ERR to “11”.

  Consider the case where the previous value of the error flag is “01” and the current value is “11” in the operation illustrated in FIG. In this case, the update timing of the input signal D0 was within the error warning period last time, but this time there is a high possibility that the error flag ERR1 is detected and deviated from the error warning period. If the difference between the previous time and the current time does not change abruptly, there is a possibility that the input signal D0 has been updated within the period close to the error warning period, that is, the period after the fall of the inverted clock signal CKB. Is expensive. Therefore, in this case, the error analysis unit 810 determines that a hold violation error has occurred.

  On the other hand, when the previous value of the error flag is “00” and the current value is “11”, the input signal D0 is updated within a period far from the error warning period, that is, a period before the falling edge of the inverted clock signal CKB. It is likely that Therefore, in this case, the error analysis unit 810 determines that a setup violation error has occurred.

  FIG. 48 is a diagram illustrating an example of the operation of the power supply unit 200 according to the third embodiment. Consider a case where the values of the hold violation warning flag AL_HOLD, the hold violation error flag ERR_HOLD, and the setup violation error flag ERR_SET are all “0”. In this case, the power supply unit 200 controls the clock distribution circuit drive voltage vCK to the set value Vsc, and controls the logic circuit drive voltage vDP to the set value Vsd. Note that, similarly to the third embodiment, the power supply unit 200 may set the set value Vsd of the logic circuit drive voltage vDP lower than the set value Vsc of the clock distribution circuit drive voltage vCK.

  When only the setup violation error flag ERR_SET is “1”, the power supply unit 200 urgently boosts the clock distribution circuit drive voltage vCK to the set value Vec and urgently boosts the logic circuit drive voltage vDP to the set value Ved.

  When only the hold violation error flag ERR_HOLD is “1”, the power supply unit 200 urgently boosts only the clock distribution circuit drive voltage vCK to the set value Vec.

  When only the hold violation warning flag AL_HOLD is “1”, the power supply unit 200 boosts the clock distribution circuit drive voltage vCK to a set value Vac lower than Vec.

  FIG. 49 is a timing chart showing an example of the operation of the error detection circuit 650 when the error flags ERR1 and ERR2 are both “0” in the fourth embodiment. In this example, it is assumed that the value of the input signal D0 does not change until the setup time, the hold time, and the error warning period elapse from the monitoring start timing.

  When a falling edge occurs in the inverted clock signal CKB in response to the rising of the clock signal CLK, the latch 511 in the previous stage holds the input signal D0 having a value of “d1” at that time and outputs it as the latch output signal L0.

  When a rising edge occurs in the clock signal CK2 in response to the falling of the inverted clock signal CKB, the latch 512 in the subsequent stage outputs the latch output signal L0 from the previous stage as the output signal Q0.

  When the falling edge of the delayed clock signal CKB_EX1 occurs after the falling edge of the inverted clock signal CKB, the latch 651 holds the input signal D0 having a value of “d1” at that time as the latch output signal L1. Output. Since the values of the latch output signals L0 and M1 are both “d1”, the XOR gate 652 outputs the error signal E1 having a value of “0”. The latch 653 holds the error signal E1 and outputs it as an error flag ERR1.

  When the falling edge of the delayed clock signal CKB_EX2 is further delayed with respect to the falling edge of the delayed clock signal CKB_EX1, the latch 654 holds the input signal D0 having the value of “d1” at that time, and the latch output signal Output as L2. Since the values of the latch output signals L0 and L2 are both “d1”, the XOR gate 655 outputs the error signal E2 having a value of “0”. The latch 656 holds the error signal E2 and outputs it as an error flag ERR2.

  Thus, if the value of the input signal D0 does not change from the monitoring start timing until the setup time, hold time, and error warning period elapse, both the error flags ERR1 and ERR2 become “0”.

  FIG. 50 is a timing chart showing an example of the operation of the error detection circuit 650 when only the error flag ERR2 is “0” in the fourth embodiment. In this example, it is assumed that the value of the input signal D0 changes from “d1” to “d2” within the error warning period. The error warning period is a period from the falling edge of the delayed clock signal CKB_EX1 to the falling edge of the delayed clock signal CKB_EX2.

  When a falling edge occurs in the inverted clock signal CKB in response to the rising of the clock signal CLK, the latch 511 in the previous stage holds the input signal D0 having a value of “d1” at that time and outputs it as the latch output signal L0.

  When the falling edge of the delayed clock signal CKB_EX1 is delayed after the falling edge of the inverted clock signal CKB, the latch 651 holds the input signal D0 having the value “d1” at that time as the latch output signal L1. Output. Since the values of the latch output signals L0 and M1 are both “d1”, the XOR gate 652 outputs the error signal E1 having a value of “0”. The latch 653 holds the error signal E1 and outputs it as an error flag ERR1.

  When the delayed clock signal CKB_EX1 is further delayed and a falling edge occurs in the delayed clock signal CKB_EX2, the latch 654 holds the input signal D0 having a value of “d2” at that time and outputs the latch output signal L2 To do. Since the value of the latch output signal L0 is “d1” and the value of the latch output signal L2 is “d2”, the XOR gate 655 outputs the error signal E2 having a value of “1”. The latch 656 holds the error signal E2 and outputs it as an error flag ERR2.

  Thus, when the value of the input signal D0 changes within the error warning period, only the error flag ERR2 becomes “1”.

  FIG. 51 is a timing chart showing an example of the operation of the error detection circuit 650 when the error flags ERR1 and ERR1 are both “1” in the fourth embodiment. In this example, it is assumed that the value of the input signal D0 changes from “d1” to “d2” between the monitoring start timing and the elapse of the setup time and the hold period. The falling edge occurs in the delayed clock signal CKB_EX1 when the hold time has elapsed.

  When a falling edge occurs in the inverted clock signal CKB in response to the rising of the clock signal CLK, the latch 511 in the previous stage holds the input signal D0 having a value of “d1” at that time and outputs it as the latch output signal L0.

  When the falling edge of the delayed clock signal CKB_EX1 occurs after the falling edge of the inverted clock signal CKB, the latch 651 holds the input signal D0 having a value of “d2” at that time as the latch output signal L1. Output. Since the latch output signal L0 is “d1” and the value of the latch output signal L1 is “d2”, the XOR gate 652 outputs the error signal E1 having the value “1”. The latch 653 holds the error signal E1 and outputs it as an error flag ERR1.

  When the delayed clock signal CKB_EX1 is further delayed and a falling edge occurs in the delayed clock signal CKB_EX2, the latch 654 holds the input signal D0 having a value of “d2” at that time and outputs it as a latch output signal L2. To do. Since the value of the latch output signal L0 is “d1” and the value of the latch output signal L2 is “d2”, the XOR gate 655 outputs the error signal E2 having a value of “1”. The latch 656 holds the error signal E2 and outputs it as an error flag ERR2.

  Thus, when the value of the input signal D0 changes between the monitoring start timing and the setup time and hold period, both the error flags ERR1 and ERR1 are “1”.

  FIG. 52 is a diagram illustrating an example of the trap window and data update timing of the error detection circuit 650 according to the fourth embodiment. Here, the trap window is a period during which the error detection circuit 650 detects a timing error.

  The first trap window is a period during which the latch 653 detects the error flag ERR1. This period is a period including a setup time and a hold time at the rising edge of the clock signal CLK.

  The second trap window is a period during which the latch 656 detects the error flag ERR2. This period is a period including a setup time and a hold violation warning margin at the rising edge of the clock signal CLK. The hold violation warning margin is a period obtained by adding an error warning period to the hold time.

  When the input signal D0 is updated outside the range of the second trap window, the error flags ERR1 and ERR2 are both “0”. When the input signal D0 is updated during the error warning period, the update timing is within the second trap window but is not included in the first trap window. Therefore, only the error flag ERR2 is “1”. When the input signal D0 is updated in the first trap window, the error flags ERR1 and ERR2 are both “1”.

  As described above, according to the fourth embodiment, when the input signal D0 changes in the first trap window, the error detection circuit 650 detects the timing error (ERR1). When the input signal D0 changes within the second trap window, the error detection circuit 650 detects a timing error (ERR2). Then, the error analysis unit 810 determines whether the input signal D0 has changed before or after the falling edge of the inverted clock signal CKB based on the history of these timing errors. As a result, the integrated circuit 100 can determine the type of timing error.

  Note that the integrated circuit 100 boosts the voltage when a setup violation error is detected, but frequency control may be further performed. For example, the error detection circuit 650 outputs the setup violation error flag ERR_SET to the clock generation unit 300 instead of the power supply unit 200. The clock generation unit 300 lowers the frequency of the clock signal CLK when the setup violation error flag ERR_SET is “1” than when it is “0”. On the other hand, when a hold violation error is detected, the clock generation unit 300 does not control the frequency, and the power supply unit 200 boosts the voltage. This is because the occurrence rate of the hold violation error is not reduced even if the frequency is lowered. In this case, the clock generation unit 300 is an example of a frequency control unit in the claims. Since the frequency can be changed early compared to the voltage, the integrated circuit 100 can quickly compensate for the error by frequency control.

  When performing the above-described frequency control, the integrated circuit 100 may boost the logic circuit drive voltage vDP in addition to the clock distribution circuit drive voltage vCK when a hold violation error is detected.

  Further, the integrated circuit 100 may include the clock distribution unit 400 of the first embodiment instead of the clock distribution circuit 410 and distribute the minimum delay clock signal mCLK to the synchronous operation circuit 500. This further reduces clock skew. Similarly, the integrated circuit 100 includes the clock distribution circuit control unit 700 and the clock distribution unit 400 of the second embodiment instead of the clock distribution circuit 410, and distributes the minimum delay clock signal mCLK to the synchronous operation circuit 500. Also good.

[First Modification]
FIG. 53 is a block diagram illustrating a configuration example of the integrated circuit 100 according to the first modification example of the fourth embodiment. The clock distribution circuit 410 according to the first modified example is different from the fourth embodiment in that the clock signal CLK is further distributed to the error compensation control unit 800 via the signal line 407. For the error compensation controller 800, the clock signal CLK is distributed to indicate the timing for counting the number of errors.

  FIG. 54 is a block diagram showing an example of the error compensation control unit 800 in the first modification example of the fourth embodiment. The error compensation control unit 800 of the fifteenth modification includes an error analysis unit 811 and an error flag counting unit 830.

  The error flag counter 830 calculates ERR01_CNT and ERR11_CNT. ERR01_CNT is the number of times that only the error flag ERR2 becomes “1” within a predetermined measurement cycle. ERR11_CNT is the number of times that the error flags ERR1 and ERR2 are both “1” within the measurement cycle. The error flag counter 830 outputs these count values to the error analyzer 811 via the signal line 839. The error flag counting unit 830 is an example of a history holding unit described in the claims.

  The error analysis unit 811 analyzes an error based on the count values ERR01_CNT and ERR11_CNT. Specifically, when ERR11_CNT is less than a threshold value (for example, “1”) and ERR01_CNT is larger than ERR11_CNT, the error analysis unit 811 turns on the hold violation warning flag AL_HOLD.

  Further, when ERR01_CNT is equal to or greater than the threshold value and ERR01_CNT is larger than ERR11_CNT, the error analysis unit 811 turns on the hold violation error flag ERR_HOLD. When ERR01_CNT is equal to or less than ERR11_CNT, the error analysis unit 811 turns on the setup violation error flag ERR_SET.

  FIG. 55 is a block diagram illustrating a configuration example of the error flag counting unit 830 in the first modification example of the fourth embodiment. The error flag counter 830 includes AND gates 831 and 832 and error flag counters 833 and 834.

  The AND gates 831 and 832 generate a logical product of the input values. The AND gate 831 outputs a logical product of a value obtained by inverting the error flag ERR1 and the error flag ERR2 to the error flag counter 833. The AND gate 832 outputs the logical product of the error flag ERR1 and the error flag ERR2 to the error flag counter 834.

  The error flag counter 833 counts the number of times that only the value of the error flag ERR2 becomes “1” within a predetermined measurement period. Specifically, the error flag counter 833 increments the count value if the output value of the AND gate 831 is “1” at the timing (for example, rising edge) indicated by the clock signal CLK. The error flag counter 833 outputs the count value to the error analysis unit 811 as ERR01_CNT. Then, the count value is initialized to “0” when a certain clock cycle has elapsed.

  The error flag counter 834 counts the number of times that the values of the error flag ERR1 and the error flag ERR2 are both “1” within a predetermined measurement period. The configuration of the error flag counter 824 is the same as the configuration of the error flag counter 833 except that the output value of the AND gate 832 is monitored. The error flag counter 834 outputs the count value to the error analysis unit 811 as ERR11_CNT.

  FIG. 56 is a diagram illustrating an example of the operation of the error analysis unit 811 in the first modification example of the fourth embodiment. Consider the case where ERR01_CNT = 0 and ERR_CNT = 0. In this case, the error analysis unit 811 sets all values of the hold violation warning flag AL_HOLD, the hold violation error flag ERR_HOLD, and the setup violation error flag ERR_SET to “0”.

  When ERR01_CNT> 0 and ERR11_CNT = 0, the error analysis unit 811 sets the value of the hold violation warning flag AL_HOLD to “1”. Further, the error analysis unit 811 sets both the hold violation error flag ERR_HOLD and the setup violation error flag ERR_SET to “0”.

  When ERR01_CNT> ERR11_CNT and ERR11_CNT> 0, the error analysis unit 811 sets the value of the hold violation error flag ERR_HOLD to “1”. The error analysis unit 811 sets both the hold violation warning flag AL_HOLD and the setup violation error flag ERR_SET to “0”.

  Consider a case where ERR11_CNT ≧ ERR01_CNT and ERR01_CNT> 0, or a case where ERR11_CNT> 0 and ERR01_CNT = 0. In this case, the error analysis unit 811 sets the value of the setup violation error flag ERR_SET to “1”. Further, the error analysis unit 811 sets both the hold violation warning flag AL_HOLD and the hold violation error flag ERR_HOLD to “0”.

  Note that the error analysis unit 811 may detect a hold violation when ERR01_CNT ≧ ERR11_CNT and ERR11_CNT> 0. In this case, the error analysis unit 811 detects a setup violation error when ERR11_CNT> ERR01_CNT and ERR11_CNT> 0.

  FIG. 57 is a diagram showing an example of the trap window and data update timing of the error detection circuit 650 in the first embodiment in the fourth embodiment. Distributions Ds1 to Ds4 are an example of a distribution of update timings of the input signal D0.

  The distribution Ds1 is a distribution that is not entirely included in the first trap window but partially included in the error warning period. In this distribution Ds1, ERR01_CNT> 0 and ERR11_CNT = 0, and the hold violation warning flag AL_HOLD is set to “1”.

  The distribution Ds2 is a distribution in which a peak is included in the error warning period and a part is included in the first trap window. In this distribution Ds2, ERR01_CNT> ERR11_CNT and ERR11_CNT> 0, and the hold violation error flag ERR_HOLD is set to “1”.

  The distribution Ds3 is a distribution in which a peak is included within the setup time in the first trap window. In this distribution Ds3, ERR11_CNT ≧ ERR01_CNT and ERR01_CNT> 0, and the setup violation error flag ERR_SET is set to “1”.

  The distribution Ds4 is a distribution in which a peak is located outside the first trap window and the second trap window and a part thereof is included in the first trap window. In this distribution Ds4, ERR11_CNT> 0 and ERR01_CNT = 0, and the setup violation error flag ERR_SET is set to “1”.

  Thus, according to the first modification, the error analysis unit 811 determines the type of timing error based on ERR01_CNT and ERR11_CNT. In order to analyze the error from the error flag statistics, the error analysis unit 811 can analyze the error more accurately than the fourth embodiment that analyzes from the previous value and the current value of the error flag.

[Second Modification]
FIG. 58 is a circuit diagram showing a configuration example of the error detection circuit 650, the flip-flop 510, and the clock distribution circuit 410 according to the second modification example of the fourth embodiment. The clock distribution circuit 410 according to the second modified example is different from the fourth embodiment in that delay units 472 and 479 are further provided. In the sixteenth modification, the inverter 471 outputs the clock signal CKB_PEX to the error detection circuit 650 and the delay unit 472.

  The delay unit 472 delays the clock signal CKB_PEX. The delay unit 472 includes an even number of inverters 473, delays the clock signal CKB_PEX by these inverters 473, and outputs the delayed clock signal CKB to the flip-flop 510 and the inverter 474. Here, the number of inverters 473 is determined such that, for example, the delay time in the delay unit 472 is longer than the setup time of the flip-flop 510. As a result, in the clock signal CKB_PEX, a falling edge occurs at a timing that goes back the delay time of the delay unit 472 from the falling edge of the clock signal CKB.

  The delay unit 479 further delays the delayed clock signal CKB_EX2. The delay unit 479 includes an even number of inverters 480. The delay unit 479 delays the delayed clock signal CKB_EX2 by these inverters 480 and outputs the delayed clock signal CKB_EX3 to the error detection circuit 650.

  The error detection circuit 650 of the second modification is different from the fourth embodiment in that it further includes latches 657, 659, 670, and 672 and XOR gates 658 and 671.

  The configuration of the latches 657, 659, 670 and 672 is the same as that of the latch 511. However, the latch 657 holds the input signal D0 and outputs it as the latch output signal L3 when the delayed clock signal CKB_EX3 is turned off. The latch 659 holds the error signal from the XOR gate 658 and outputs it to the error compensation controller 800 as an error flag ERR3 when the clock signal CK2 is turned off. The latch 670 holds the input signal D0 and outputs it as the latch output signal L4 when the clock signal CKB_PEX is turned off. The latch 672 holds the error signal from the XOR gate 671 and outputs it to the error compensation controller 800 as an error flag ERR4 when the clock signal CK2 is turned off.

  The XOR gates 658 and 671 output an exclusive OR of the input signals. XOR gate 658 outputs the exclusive OR of latch output signals L3 and L0 from latches 657 and 511 to latch 659 as error signal E3. XOR gate 671 outputs the exclusive OR of latch output signals L1 and L4 from latches 651 and 670 to latch 672 as error signal E4.

  With the above-described configuration, when the input signal D0 changes within a period obtained by adding the delay time of the delay unit 479 after the second trap window, the error signal E3 is detected.

  Further, when the force signal D0 changes within a period from the start point to the time when the delay time of the delay unit 472 is traced back from the start point, the error signal E4 is detected.

  FIG. 59 is a diagram illustrating an example of a trap window in the error detection circuit 650 according to the second modification example of the fourth embodiment. In the error detection circuit 650 of the sixteenth modification, a third trap window and a fourth trap window are added.

  The third trap window is a period during which the latch 659 detects the error flag ERR3. This period is a period in which the delay time of the delay unit 479 is added after the second trap window.

  The fourth trap window is a period during which the latch 672 detects the error flag ERR4. This period is a period from the start point to the end point of the first trap window, starting from the timing when the delay time of the delay unit 472 is traced back from the rising edge of the clock signal CLK.

  Using these error flags, the error compensation controller 800 and the power supply unit 200 can perform error compensation by analyzing errors more accurately.

  For example, if any error flag is “0” last time and only the error flag ERR3 is “1” this time, the power supply unit 200 boosts the clock distribution circuit drive voltage vCK to a set value lower than Vac. To do.

  Also, if any error flag is “0” last time and only the error flag ERR4 is “1” this time, the error compensation control unit 800 issues a warning of setup violation. When only the error flag ERR4 is “1” last time and all the error flags are “1” this time, the error compensation control unit 800 detects a setup violation error.

  Note that a trap window may be further added to the error detection circuit 650 by adding a latch and an inverter. The trap window added to the first trap window is arbitrary. For example, the integrated circuit 100 may add only the fourth trap window to the first trap window, or may add only the second trap window and the third trap window to the first trap window.

  As described above, according to the second modification, the error detection circuit 650 includes three or more trap windows, so that more accurate error analysis can be performed.

  The integrated circuit 100 of the fourth embodiment described above includes the clock distribution unit 400 of the first embodiment instead of the clock distribution circuit 410, and distributes the minimum delay clock signal mCLK to the synchronous operation circuit 500. May be. This further reduces clock skew. Similarly, the integrated circuit 100 of the fourth embodiment includes the clock distribution circuit control unit 700 and the clock distribution unit 400 of the second embodiment instead of the clock distribution circuit 410, and synchronizes the minimum delay clock signal mCLK. It may be distributed to the operation circuit 500.

  The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.

  Further, the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disk), a memory card, a Blu-ray Disc (registered trademark), or the like can be used.

In addition, this technique can also take the following structures.
(1) a main timing signal distribution circuit for branching and distributing a timing signal instructing a predetermined timing into a plurality of main timing signals;
A sub-timing signal distribution circuit for branching and distributing the timing signal into a plurality of sub-timing signals when distribution of the timing signal is instructed;
A minimum delay timing signal output unit that outputs a signal previously distributed as one of the plurality of main timing signals and one of the plurality of sub timing signals as a minimum delay timing signal;
A synchronous operation circuit that operates in synchronization with the minimum delay timing signal;
A measurement unit that measures a value indicating variation in delay of any of the plurality of main timing signals;
An integrated circuit comprising: a timing signal distribution circuit controller that instructs the sub-timing signal distribution circuit to distribute the timing signal when the variation indicated by the measured value is equal to or greater than the predetermined value.
(2) The minimum delay timing signal output unit includes a plurality of timing signal generation units,
Each of the plurality of timing signal generation units includes a main input terminal and a sub input terminal, generates and outputs the minimum delay timing signal from signals input to the main input terminal and the sub input terminal,
The main timing signal distribution circuit distributes the plurality of main timing signals different from each other to the main input terminals of the plurality of timing signal generation units,
The sub-timing signal distribution circuit distributes the plurality of sub-timing signals different from each other to the sub-input terminals of the plurality of timing signal generators according to the timing signal distribution instruction,
The measurement unit measures a value indicating the variation for each of the plurality of main timing signals;
The timing signal distribution circuit control unit instructs distribution of the sub-timing signal to the sub-input terminal of the timing signal generation unit to which the main timing signal whose variation is equal to or greater than the predetermined value is distributed. The integrated circuit according to (1).
(3) The main timing signal distribution circuit and the sub timing signal distribution circuit distribute the main timing signal and the sub timing signal to any one of the plurality of timing signal generation units via a buffer having the same number of stages. The integrated circuit according to (2).
(4) In any one of (1) to (3), the measurement unit measures a value indicating the variation when a voltage supplied to the main timing signal distribution circuit is equal to or lower than a predetermined voltage. An integrated circuit as described.
(5) The measurement unit includes:
An error detector for detecting a timing error in the synchronous operation circuit;
The integrated circuit according to any one of (1) to (4), further including an error detection frequency measurement unit that measures the detection frequency of the timing error as a value indicating the variation.
(6) The minimum delay timing signal output unit outputs a logical sum of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The integrated circuit according to any one of (1) to (5), wherein the synchronous operation circuit operates in synchronization with a rising edge of the minimum delay timing signal.
(7) The minimum delay timing signal output unit outputs a logical sum of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The synchronous operation circuit includes:
An inverter that inverts and outputs the minimum delay timing signal;
The integrated circuit according to any one of (1) to (5), further comprising a flip-flop that operates in synchronization with a rising edge of the inverted minimum delay timing signal.
(8) The minimum delay timing signal output unit outputs a logical product of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The integrated circuit according to any one of (1) to (5), wherein the synchronous operation circuit operates in synchronization with a falling edge of the minimum delay timing signal.
(9) The minimum delay timing signal output unit outputs a logical product of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The synchronous operation circuit includes:
An inverter that inverts and outputs the minimum delay timing signal;
The integrated circuit according to any one of (1) to (5), further including a flip-flop that operates in synchronization with a falling edge of the inverted minimum delay timing signal.
(10) The synchronous operation circuit includes:
Mesh wiring for distributing the minimum delay timing signal to a plurality of regions arranged in a grid pattern; and
The integrated circuit according to any one of (1) to (9), further comprising a flip-flop that operates in synchronization with the minimum delay timing signal distributed to any of the plurality of regions.
(11) The timing signal is a clock signal;
The main timing signal distribution circuit is a clock tree that branches the timing signal into the plurality of main timing signals via a predetermined number of first buffers.
The sub timing signal distribution circuit according to any one of (1) to (10), wherein the sub timing signal distribution circuit is a clock tree that branches the timing signal into the plurality of sub timing signals via a predetermined number of second buffers. Integrated circuit.

DESCRIPTION OF SYMBOLS 100 Integrated circuit 200 Power supply part 210 Clock distribution circuit drive voltage control part 211 Clock distribution circuit drive voltage control circuit 212, 222 Voltage control register 213, 510, 520, 560, 570 Flip-flop 214, 224 Variable resistor 215 pMOS transistor 220 Logic circuit drive voltage control unit 221 Logic circuit drive voltage control circuit 300 Clock generation unit 400 Clock distribution unit 410, 420 Clock distribution circuit 411, 421, 442, 444, 446, 452, 454, 456 Buffers 430, 461, 462 OR ( OR gate) 431, 463, 464 NOR (negative OR) gate 432, 465, 466, 831, 832 AND (logical product) gate 433, 467, 468 NAND (negative logical product) gate 440 Main clock distribution circuit 441, 443, 445, 451, 453, 455 PLL
450 Sub clock distribution circuit 472, 475, 477, 612, 622 Delay unit 500 Synchronous operation circuit 511, 512, 614, 616, 624, 626, 651, 653, 654, 656, 657, 659, 670, 672 Latch 471, 473, 474, 476, 478, 530, 540, 611, 613, 621, 623 Inverter 550 Mesh wiring 580 Combinational logic circuit 600 Error measurement unit 610, 620, 650 Error detection circuit 615, 625, 652, 655, 658, 671 XOR (exclusive OR) gate 630, 631, 640 Error number counter 700 Clock distribution circuit control unit 710 Main clock distribution circuit control unit 720 Sub clock distribution circuit control unit 800 Error compensation control unit 810, 811 Error analysis unit 820 Error flag previous value holding unit 830 the error flag counting section 833, 834 the error flag counter

Claims (11)

A main timing signal distribution circuit that divides and distributes a timing signal indicating a predetermined timing into a plurality of main timing signals;
A sub-timing signal distribution circuit for branching and distributing the timing signal into a plurality of sub-timing signals when distribution of the timing signal is instructed;
A minimum delay timing signal output unit that outputs a signal previously distributed as one of the plurality of main timing signals and one of the plurality of sub timing signals as a minimum delay timing signal;
A synchronous operation circuit that operates in synchronization with the minimum delay timing signal;
A measurement unit that measures a value indicating variation in delay of any of the plurality of main timing signals;
An integrated circuit comprising: a timing signal distribution circuit controller that instructs the sub-timing signal distribution circuit to distribute the timing signal when the variation indicated by the measured value is equal to or greater than the predetermined value. The minimum delay timing signal output unit includes a plurality of timing signal generation units,
Each of the plurality of timing signal generation units includes a main input terminal and a sub input terminal, generates and outputs the minimum delay timing signal from signals input to the main input terminal and the sub input terminal,
The main timing signal distribution circuit distributes the plurality of main timing signals different from each other to the main input terminals of the plurality of timing signal generation units,
The sub-timing signal distribution circuit distributes the plurality of sub-timing signals different from each other to the sub-input terminals of the plurality of timing signal generators according to the timing signal distribution instruction,
The measurement unit measures a value indicating the variation for each of the plurality of main timing signals;
The timing signal distribution circuit control unit instructs distribution of the sub-timing signal to the sub-input terminal of the timing signal generation unit to which the main timing signal whose variation is equal to or greater than the predetermined value is distributed. The integrated circuit according to claim 1. The main timing signal distribution circuit and the sub timing signal distribution circuit distribute the main timing signal and the sub timing signal to any one of the plurality of timing signal generation units via buffers having the same number of stages. 2. The integrated circuit according to 2. The integrated circuit according to claim 1, wherein the measurement unit measures a value indicating the variation when a voltage supplied to the main timing signal distribution circuit becomes a predetermined voltage or less. The measuring unit is
An error detector for detecting a timing error in the synchronous operation circuit;
The integrated circuit according to claim 1, further comprising: an error detection frequency measuring unit that measures the detection frequency of the timing error as a value indicating the variation. The minimum delay timing signal output unit outputs a logical sum of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The integrated circuit according to claim 1, wherein the synchronous operation circuit operates in synchronization with a rising edge of the minimum delay timing signal. The minimum delay timing signal output unit outputs a logical sum of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The synchronous operation circuit includes:
An inverter that inverts and outputs the minimum delay timing signal;
The integrated circuit according to claim 1, further comprising a flip-flop that operates in synchronization with a rising edge of the inverted minimum delay timing signal. The minimum delay timing signal output unit outputs a logical product of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The integrated circuit according to claim 1, wherein the synchronous operation circuit operates in synchronization with a falling edge of the minimum delay timing signal. The minimum delay timing signal output unit outputs a logical product of any of the plurality of main timing signals and any of the plurality of sub timing signals as the minimum delay timing signal,
The synchronous operation circuit includes:
An inverter that inverts and outputs the minimum delay timing signal;
The integrated circuit according to claim 1, further comprising a flip-flop that operates in synchronization with a falling edge of the inverted minimum delay timing signal. The synchronous operation circuit includes:
Mesh wiring for distributing the minimum delay timing signal to a plurality of regions arranged in a grid pattern; and
The integrated circuit according to claim 1, further comprising a flip-flop that operates in synchronization with the minimum delay timing signal distributed to any of the plurality of regions. The timing signal is a clock signal;
The main timing signal distribution circuit is a clock tree that branches the timing signal into the plurality of main timing signals via a predetermined number of first buffers.
2. The integrated circuit according to claim 1, wherein the sub-timing signal distribution circuit is a clock tree that branches the timing signal into the plurality of sub-timing signals via a predetermined number of second buffers.

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