JP2013062279A - Semiconductor light-emitting element array and vehicle lighting fixture - Google Patents

Semiconductor light-emitting element array and vehicle lighting fixture Download PDF

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JP2013062279A
JP2013062279A JP2011197999A JP2011197999A JP2013062279A JP 2013062279 A JP2013062279 A JP 2013062279A JP 2011197999 A JP2011197999 A JP 2011197999A JP 2011197999 A JP2011197999 A JP 2011197999A JP 2013062279 A JP2013062279 A JP 2013062279A
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semiconductor light
light emitting
emitting element
electrode
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JP5781409B2 (en
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Mitsunori Harada
光範 原田
Tatsuma Saito
竜舞 斎藤
Mamoru Miyaji
護 宮地
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Stanley Electric Co Ltd
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Priority to EP12006194.0A priority patent/EP2565927A3/en
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Abstract

PROBLEM TO BE SOLVED: To inhibit an occurrence of an emitted light luminance distribution.SOLUTION: A semiconductor light-emitting element array includes a plurality of semiconductor light-emitting elements formed on a substrate that is longer in a first direction. Each of the plurality of semiconductor light-emitting elements comprises: an electrode layer formed on the substrate; a semiconductor light-emitting layer including a p-type semiconductor layer formed on the electrode layer and electrically connected to the electrode layer, an active layer formed on the p-type semiconductor layer, and an n-type semiconductor layer formed on the active layer; a first wiring layer formed along one side and in parallel with the one side of the semiconductor light-emitting layer; a plurality of second wiring layers extending from the first wiring layer to the semiconductor light-emitting layer and electrically connected with the n-type semiconductor layer on a surface of the semiconductor light-emitting layer; and a phosphor layer formed above the semiconductor light-emitting layer. The semiconductor light-emitting layer has a planar shape which has a base parallel to the first direction and at least one side including a part slanting with respect to a line vertical to the base, in which a width of the semiconductor light-emitting layer in the first direction decreases with distance from the base.

Description

本発明は、半導体発光素子アレイ及び半導体発光素アレイを用いた車両用灯具に関する。   The present invention relates to a semiconductor light emitting element array and a vehicular lamp using the semiconductor light emitting element array.

車両のヘッドランプや照明に用いるためのＬＥＤ素子には大出力が求められているが、単純に素子面積を大きくするだけだと駆動電流が大きくなってしまうということや、均一に電流を流すことが難しくなってしまうことから、複数のＬＥＤ素子に分割し、直列接続したＬＥＤアレイとすることが知られている（例えば、特許文献１参照）。   LED elements for use in vehicle headlamps and lighting are required to have a high output. However, simply increasing the element area will increase the drive current, and allow the current to flow uniformly. Therefore, it is known that the LED array is divided into a plurality of LED elements and connected in series (for example, see Patent Document 1).

車両のヘッドランプ等のアプリケーションでは、横長形状のＬＥＤ素子が求められているが、ＬＥＤ素子の分割数を多くすると、素子間の非発光部の占める割合が増加し好ましくない。そこで、ＬＥＤ素子の分割数を少なくするために、各ＬＥＤ素子の形状は横長になってしまう。   In applications such as vehicle headlamps, horizontally long LED elements are required. However, if the number of LED element divisions is increased, the proportion of non-light emitting portions between the elements increases. Therefore, in order to reduce the number of divided LED elements, the shape of each LED element becomes horizontally long.

図７（Ａ）は、従来のＬＥＤアレイ２００を示す概略平面図であり、図７（Ｂ）は、図７（Ａ）に示すＬＥＤアレイ２００の簡略化した断面図である。   FIG. 7A is a schematic plan view showing a conventional LED array 200, and FIG. 7B is a simplified cross-sectional view of the LED array 200 shown in FIG. 7A.

従来ＬＥＤアレイ２００としては、絶縁性支持基板の上に、４つの窒化物半導体発光素子（ＬＥＤ素子）２０１を基板上に配置し直列接続したものが一般的である。ＧａＮ系白色ＬＥＤ素子を例にとると、サファイア基板上にＬＥＤ構造を形成後、支持基板を貼りあわせ、サファイア基板を剥離し、電極を形成することが行われる。   Conventional LED array 200 is generally one in which four nitride semiconductor light emitting elements (LED elements) 201 are arranged on a substrate and connected in series on an insulating support substrate. Taking a GaN-based white LED element as an example, after an LED structure is formed on a sapphire substrate, a support substrate is bonded, the sapphire substrate is peeled off, and an electrode is formed.

個々のＬＥＤ素子２０１は、ｎ型ＧａＮ層２２１、活性層２２２、ｐ型ＧａＮ層２２３からなるＧａＮ系発光部２０２と、発光部２０２の裏面に形成されたｐ側電極２１２と、発光部２０２の右側短辺に一定間隔を置いて平行に配置される引き出し電極（第１配線層）２１１及び発光部２０２の表面に発光部２０２の長辺と平行に配置され、ｎ型ＧａＮ層２２１と引き出し電極２１１とを接続する引き出し電極（第２配線層）２０８とを有している。左右に隣接するＬＥＤ素子２０１は、右側素子のｐ側電極２１２上に左側素子の引き出し電極２１１が形成されることにより、左側素子のｎ型ＧａＮ層２２１と右側素子のｐ型ＧａＮ層２２３が接続されている。   Each LED element 201 includes a GaN-based light emitting unit 202 including an n-type GaN layer 221, an active layer 222, and a p-type GaN layer 223, a p-side electrode 212 formed on the back surface of the light emitting unit 202, and the light emitting unit 202. An extraction electrode (first wiring layer) 211 arranged in parallel with a certain interval on the right short side and a surface of the light emitting unit 202 arranged in parallel with the long side of the light emitting unit 202, the n-type GaN layer 221 and the extraction electrode 211 and a lead electrode (second wiring layer) 208 that connects to 211. The LED elements 201 adjacent to the left and right are connected to the n-type GaN layer 221 of the left element and the p-type GaN layer 223 of the right element by forming the extraction electrode 211 of the left element on the p-side electrode 212 of the right element. Has been.

蛍光体層２３１は、基板２３０上に実装された複数の発光素子２０１を封止する。例えば、発光素子２０１が青色ＬＥＤ素子であるとき、蛍光体として黄色蛍光体を組み合わせることにより、白色発光させるＬＥＤアレイ２００を作成することができる。この場合、透光性樹脂に予め黄色蛍光体を含有させ、蛍光体を含有させた透光性樹脂（蛍光体含有樹脂）で発光素子２０２を封止する。   The phosphor layer 231 seals the plurality of light emitting elements 201 mounted on the substrate 230. For example, when the light emitting element 201 is a blue LED element, an LED array 200 that emits white light can be created by combining a yellow phosphor as the phosphor. In this case, the light-emitting element 202 is sealed with a light-transmitting resin (phosphor-containing resin) in which a yellow fluorescent material is previously contained in the light-transmitting resin and the fluorescent material is included.

なお、図７（Ａ）の発光部２０２に施したハッチングは発光輝度分布を表し、ハッチングの密度が高くなるに従い輝度が高くなることを表している。   Note that the hatching applied to the light emitting portion 202 in FIG. 7A represents a light emission luminance distribution, which indicates that the luminance increases as the hatching density increases.

特開２００１−１５６３３１号公報JP 2001-156331 A

図７（Ｃ）及び（Ｄ）は、図７（Ａ）に示すＬＥＤアレイ２００の直線ｅｆ間における輝度分布を概略的に表す図である。図７（Ｃ）は、ＬＥＤアレイ２００が蛍光体層２３１を備えない場合の、青色発光素子としての直線ｅｆ間における輝度分布を表し、図７（Ｄ）は、ＬＥＤアレイ２００が蛍光体層２３１を備えた場合の、白色発光素子としての直線ｅｆ間における輝度分布を表す。   7C and 7D are diagrams schematically showing the luminance distribution between the straight lines ef of the LED array 200 shown in FIG. 7A. FIG. 7C illustrates a luminance distribution between the straight lines ef as the blue light emitting elements when the LED array 200 does not include the phosphor layer 231, and FIG. 7D illustrates that the LED array 200 includes the phosphor layer 231. Represents the luminance distribution between the straight lines ef as white light emitting elements.

図７（Ｃ）に示すように、蛍光体層２３１がない青色発光の状態では、従来、輝度分布が素子面内において一様でフラットなものとなっている。しかし、このようなフラットな輝度分布を持つ青色発光素子に蛍光体層２３１を形成して白色化すると、素子面内において縦方向（図中Ｈ方向）の中心部の輝度（最大輝度）が端部の輝度（基準輝度）に比べて約１．２〜１．６７倍になり、図７（Ｄ）に示すような縦方向の中心部が明るく、端部に行くに従い徐々に暗くなるという輝度分布（ランバーシアン配光）が形成されてしまう。このようなＬＥＤアレイ２００を用いてヘッドランプ等を構成すると、照射像に大きな輝度ムラが生じる。   As shown in FIG. 7C, in the blue light emission state without the phosphor layer 231, conventionally, the luminance distribution is uniform and flat in the element plane. However, when the phosphor layer 231 is formed on a blue light emitting element having such a flat luminance distribution to be whitened, the luminance (maximum luminance) at the center in the vertical direction (H direction in the figure) in the element plane is the end. The brightness is about 1.2 to 1.67 times higher than the brightness of the part (reference brightness), the center part in the vertical direction is bright as shown in FIG. Distribution (Lambertian light distribution) is formed. When a headlamp or the like is configured using such an LED array 200, a large luminance unevenness occurs in the irradiated image.

本発明の目的は、発光輝度分布の形成を抑制した半導体発光素子アレイを提供することである。   An object of the present invention is to provide a semiconductor light-emitting element array in which the formation of light emission luminance distribution is suppressed.

また、本発明の他の目的は、照射像の輝度ムラを抑制した車両用灯具を提供することである。   Another object of the present invention is to provide a vehicular lamp that suppresses uneven brightness of an irradiated image.

本発明の一観点によれば、第１の方向に長い基板上に複数の半導体発光素子が形成された半導体発光素子アレイは、前記複数の半導体発光素子のそれぞれが、前記基板上に形成された電極層と、前記電極層上に形成され、前記電極層に電気的に接続されたｐ型半導体層と、前記ｐ型半導体層上に形成された活性層と、前記活性層上に形成されたｎ型半導体層とを有する半導体発光層と、前記半導体発光層の一辺に沿って、該一辺と平行に形成された第１配線層と、前記第１配線層から前記半導体発光層にかけて延在し、前記半導体発光層の表面において、前記ｎ型半導体層と電気的に接続される複数の第２配線層と、前記半導体発光層の上方に形成される蛍光体層とを有し、前記半導体発光層の平面形状が、前記第１の方向に平行な底辺と、該底辺に垂直な線に対して傾斜する部分を含む少なくとも１つの辺を有し、前記半導体発光層の前記第１の方向の幅が前記底辺から離れるに従い減少する形状である。   According to one aspect of the present invention, in a semiconductor light emitting element array in which a plurality of semiconductor light emitting elements are formed on a substrate that is long in the first direction, each of the plurality of semiconductor light emitting elements is formed on the substrate. An electrode layer, a p-type semiconductor layer formed on the electrode layer and electrically connected to the electrode layer, an active layer formed on the p-type semiconductor layer, and formed on the active layer a semiconductor light emitting layer having an n-type semiconductor layer; a first wiring layer formed in parallel with one side of the semiconductor light emitting layer; and extending from the first wiring layer to the semiconductor light emitting layer. And a plurality of second wiring layers electrically connected to the n-type semiconductor layer on the surface of the semiconductor light emitting layer, and a phosphor layer formed above the semiconductor light emitting layer, the semiconductor light emitting A planar shape of the layer is a base parallel to the first direction; At least one of the sides includes a portion inclined relative to a line perpendicular to the bottom, the width of the first direction of the semiconductor light-emitting layer has a shape that decreases with the distance from the bottom.

本発明によれば、発光輝度分布の形成を抑制した半導体発光素子アレイを提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting element array which suppressed formation of light-emitting luminance distribution can be provided.

また、本発明によれば、照射像の輝度ムラを抑制した車両用灯具を提供することができる。   Moreover, according to this invention, the vehicle lamp which suppressed the brightness nonuniformity of an irradiation image can be provided.

本発明の実施例によるＬＥＤアレイ１００及びＬＥＤ素子１０１の概略平面図、回路図及び断面図である。1 is a schematic plan view, a circuit diagram, and a cross-sectional view of an LED array 100 and an LED element 101 according to an embodiment of the present invention. 本発明の実施例によるＬＥＤアレイ１００の発光輝度分布を概略的に表す図である。It is a figure which represents roughly the light emission luminance distribution of the LED array 100 by the Example of this invention. 本発明の実施例によるＬＥＤアレイ１００を組み込んだ車両用灯具（ヘッドランプ）５０の構成を表す概念図である。It is a conceptual diagram showing the structure of the vehicle lamp (headlamp) 50 incorporating the LED array 100 by the Example of this invention. 本発明の実施例によるＬＥＤアレイ１００の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the manufacturing method of the LED array 100 by the Example of this invention. 本発明の実施例によるＬＥＤアレイ１００の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the manufacturing method of the LED array 100 by the Example of this invention. 本発明の実施例によるＬＥＤアレイ１００の他の製造方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the other manufacturing method of the LED array 100 by the Example of this invention. 従来例によるＬＥＤアレイ４００の概略平面図、断面図及び発光輝度分布を表す図である。It is a figure showing the schematic plan view, sectional drawing, and light emission luminance distribution of the LED array 400 by a prior art example.

図１（Ａ）は、本発明の実施例によるＬＥＤアレイ１００の概略平面図であり、図１（Ｂ）は、ＬＥＤアレイ１００の等価回路図である。図１（Ｃ）は、図１（Ａ）の直線ａｂ間のＬＥＤアレイ１００の簡略化した断面図である。なお、図１（Ａ）中発光部２に施したハッチングは発光輝度分布を表し、ハッチングの密度が高くなるに従い輝度が高くなることを表している。   FIG. 1A is a schematic plan view of an LED array 100 according to an embodiment of the present invention, and FIG. 1B is an equivalent circuit diagram of the LED array 100. FIG. 1C is a simplified cross-sectional view of the LED array 100 between the straight lines ab in FIG. Note that the hatching applied to the light emitting portion 2 in FIG. 1A represents a light emission luminance distribution, which indicates that the luminance increases as the hatching density increases.

本発明の実施例によるＬＥＤアレイ１００は、絶縁層７が形成された図中Ｗ方向に長い支持基板３０上に、該Ｗ方向に沿って８つの窒化物半導体発光素子（ＬＥＤ素子）１０１（１０１ａ及び１０１ｂ）を配置し、直列接続したものである。   An LED array 100 according to an embodiment of the present invention includes eight nitride semiconductor light emitting elements (LED elements) 101 (101a) along a W direction on a support substrate 30 that is long in the W direction in the figure in which the insulating layer 7 is formed. And 101b) are arranged and connected in series.

車両のヘッドランプや照明に用いるためのＬＥＤ素子には大出力が求められているが、単純に素子面積を大きくするだけだと駆動電流が大きくなってしまうということや、均一に電流を流すことが難しくなってしまうことから、本実施例では、複数のＬＥＤ素子１０１をアレイ化し、ＬＥＤアレイ１００としている。またそれぞれのＬＥＤ素子１０１に同じ電流値を流すには、直列接続が好ましい。   LED elements for use in vehicle headlamps and lighting are required to have a high output. However, simply increasing the element area will increase the drive current, and allow the current to flow uniformly. In this embodiment, a plurality of LED elements 101 are arrayed to form an LED array 100. Moreover, in order to let the same electric current value flow through each LED element 101, series connection is preferable.

また、車両のヘッドランプに用いる場合には、地表面近傍を照明することが要求され、ＬＥＤアレイ１００は横方向に長い（図中Ｗ方向に長い）形状であることが好ましい。ＬＥＤアレイ１００の寸法は、例えば、幅５ｍｍ以上、高さ１ｍｍ以下に設定される。   Further, when used for a vehicle headlamp, it is required to illuminate the vicinity of the ground surface, and the LED array 100 preferably has a shape that is long in the lateral direction (long in the W direction in the figure). The dimensions of the LED array 100 are set to, for example, a width of 5 mm or more and a height of 1 mm or less.

個々のＬＥＤ素子１０１は、支持基板３０の上記Ｗ方向に沿った辺に平行な底辺を有する三角形状であり、ｎ型ＧａＮ層２１、活性層２２、ｐ型ＧａＮ層２３からなるＧａＮ系発光部（デバイス構造層）２と、発光部２の裏面に形成され該発光部の上下いずれかの前記三角形状の頂点から露出するｐ側電極１２と、ｐ側電極が露出する頂点とは逆側の前記三角形状の底辺と一定間隔を置いて平行に配置される引き出し電極（第１配線層）１１及び発光部２の表面上にＬＥＤアレイ１００の短辺に平行に配置され、ｎ型ＧａＮ層２１と引き出し電極１１とを接続する引き出し電極（第２配線層）８とを有している。   Each LED element 101 has a triangular shape having a base parallel to the side along the W direction of the support substrate 30, and includes a n-type GaN layer 21, an active layer 22, and a p-type GaN layer 23. (Device structure layer) 2, the p-side electrode 12 formed on the back surface of the light-emitting unit 2 and exposed from the apex of the triangular shape either above or below the light-emitting unit, and the apex where the p-side electrode is exposed An extraction electrode (first wiring layer) 11 arranged in parallel with the triangular base at a predetermined interval and a surface of the light emitting unit 2 are arranged in parallel to the short side of the LED array 100, and the n-type GaN layer 21. And a lead electrode (second wiring layer) 8 for connecting the lead electrode 11 and the lead electrode 11.

蛍光体層３１は、基板３０上に実装された複数の発光素子１０１を封止する。例えば、発光素子１０１が青色ＬＥＤ素子であるとき、蛍光体として黄色蛍光体を組み合わせることにより、白色発光させるＬＥＤアレイ１００を作成することができる。この場合、透光性樹脂に予め黄色蛍光体を含有させ、蛍光体を含有させた透光性樹脂（蛍光体含有樹脂）で発光素子１０２を封止する。   The phosphor layer 31 seals the plurality of light emitting elements 101 mounted on the substrate 30. For example, when the light emitting element 101 is a blue LED element, an LED array 100 that emits white light can be created by combining a yellow phosphor as the phosphor. In this case, the light-emitting element 102 is sealed with a light-transmitting resin (phosphor-containing resin) in which a yellow fluorescent material is previously contained in the light-transmitting resin and the fluorescent material is included.

個々のＬＥＤ素子１０１は、それぞれ左右に隣接するＬＥＤ素子１０１と直列に接続されており、ＬＥＤ素子１０１ａの引き出し電極１１は、左側に位置するＬＥＤ素子１０１ｂのｐ側電極１２と電気的に接続され、ＬＥＤ素子１０１ａのｐ側電極１２は右側に位置するＬＥＤ素子１０１ｂの引き出し電極１１と電気的に接続されている。ＬＥＤアレイ１００の端部に位置するＬＥＤ素子１０１ａのｐ側電極１２及びＬＥＤ素子１０１ｂの引き出し電極１１はそれぞれ給電パッド１３に接続されている。   The individual LED elements 101 are connected in series with the LED elements 101 adjacent to the left and right, respectively, and the lead electrode 11 of the LED element 101a is electrically connected to the p-side electrode 12 of the LED element 101b located on the left side. The p-side electrode 12 of the LED element 101a is electrically connected to the lead electrode 11 of the LED element 101b located on the right side. The p-side electrode 12 of the LED element 101a and the lead electrode 11 of the LED element 101b located at the end of the LED array 100 are connected to the power supply pad 13, respectively.

ＬＥＤ素子１０１ａは、ＬＥＤアレイ１００の上長辺側に該長辺に平行に給電側である引き出し電極１１が配置され、そこからｎ型ＧａＮ層２１上にかけて引き出し電極８がＬＥＤアレイ１００の短辺に平行に配置されるため、図中上から下にかけて徐々に注入電流が減少する。発光部２の平面形状が三角形状であるため、下方向に進むにつれ、発光部のＷ方向の幅が減少し、発光部２の三角形状の頂点付近では、輝度が低下する。そのため、上側が明るく、下側が暗くなる発光輝度分布を有する。   In the LED element 101 a, an extraction electrode 11 on the power supply side is arranged on the upper long side of the LED array 100 in parallel with the long side, and the extraction electrode 8 extends from there to the n-type GaN layer 21 so that the short side of the LED array 100. Therefore, the injection current gradually decreases from the top to the bottom in the figure. Since the planar shape of the light emitting unit 2 is triangular, the width of the light emitting unit in the W direction decreases as it progresses downward, and the luminance decreases near the apex of the light emitting unit 2 in the triangular shape. Therefore, it has a light emission luminance distribution in which the upper side is bright and the lower side is dark.

ＬＥＤ素子１０１ｂは、ＬＥＤ素子１０１ａとは逆に、ＬＥＤアレイ１００の下長辺側に該長辺に平行に給電側である引き出し電極１１が配置され、そこからｎ型ＧａＮ層２１上にかけて引き出し電極８がＬＥＤアレイ１００の短辺に平行に配置されるため、図中下から上にかけて徐々に注入電流が減少する。発光部２の平面形状が三角形状であるため、上方向に進むにつれ、発光部のＷ方向の幅が減少し、発光部２の三角形状の頂点付近では、輝度が低下する。そのため、下側が明るく、上側が暗くなる発光輝度分布を有する。   In contrast to the LED element 101 a, the LED element 101 b has a lead electrode 11 on the lower long side of the LED array 100 parallel to the long side, which is on the power supply side, and extends from the lead electrode 11 onto the n-type GaN layer 21. Since 8 is arranged in parallel with the short side of the LED array 100, the injection current gradually decreases from the bottom to the top in the figure. Since the planar shape of the light emitting unit 2 is triangular, the width of the light emitting unit in the W direction decreases as it progresses upward, and the luminance decreases near the apex of the light emitting unit 2 in the triangular shape. Therefore, it has a light emission luminance distribution in which the lower side is bright and the upper side is dark.

すなわち、ＬＥＤ素子１０１ａの発光面には、引き出し電極１１側にピーク（最大輝度部）を持ち、図中下方向（Ｈ方向）に引き出し電極１１から離れるに従い徐々に減少する輝度分布が形成される。ＬＥＤ素子１０１ｂの発光面にもＬＥＤ素子１０１ａと同様の輝度分布が形成されるが、ＬＥＤ素子１０１ｂでは引き出し電極１１が下側の長辺に沿って形成されるため、ＬＥＤ素子１０１ａの発光面とは逆に、下側長辺にピークを持ち、上方向にかけて徐々に減少する輝度分布が形成される。   That is, on the light emitting surface of the LED element 101a, a luminance distribution is formed which has a peak (maximum luminance portion) on the extraction electrode 11 side and gradually decreases in the downward direction (H direction) in the figure as the distance from the extraction electrode 11 increases. . A luminance distribution similar to that of the LED element 101a is formed on the light emitting surface of the LED element 101b. However, since the lead electrode 11 is formed along the lower long side in the LED element 101b, Conversely, a luminance distribution is formed which has a peak on the lower long side and gradually decreases in the upward direction.

なお、ＬＥＤ素子１０１ａとＬＥＤ素子１０１ｂは、ｐ側電極１２、引き出し電極１１、引き出し電極８の配置等の電極パターンが異なり、その他の構造は同一であり、ＬＥＤ素子１０１ａの電極パターンを上下に反転（１８０度回転）したものがＬＥＤ素子１０１ｂである。   The LED element 101a and the LED element 101b have different electrode patterns such as the arrangement of the p-side electrode 12, the extraction electrode 11, and the extraction electrode 8, and the other structures are the same. The electrode pattern of the LED element 101a is inverted up and down. The LED element 101b is (rotated 180 degrees).

本実施例では、発光部２の一方の長辺（図１（Ａ）では下側の長辺）側に引き出し電極（第１配線層）１１を配置し、当該一方の長辺から他方の長辺近傍に向かって延在する引き出し電極（第２配線層）８を有するＬＥＤ素子１０１ａと、他方の長辺（図１（Ａ）では上側の長辺）側に引き出し電極（第１配線層）１１を配置し、当該他方の長辺から上記一方の長辺近傍に向かって延在する引き出し電極（第２配線層）８を有するＬＥＤ素子１０１ｂとをＬＥＤアレイ１００の長辺方向に交互に配列する。   In the present embodiment, an extraction electrode (first wiring layer) 11 is arranged on one long side (lower long side in FIG. 1A) side of the light emitting portion 2, and the one long side to the other long side. An LED element 101a having an extraction electrode (second wiring layer) 8 extending toward the vicinity of the side, and an extraction electrode (first wiring layer) on the other long side (the upper long side in FIG. 1A) LED elements 101b having lead electrodes (second wiring layers) 8 extending from the other long side toward the vicinity of the one long side are alternately arranged in the long side direction of the LED array 100. To do.

図２（Ａ）は、本発明の実施例によるＬＥＤアレイ１００において、蛍光体層３１が形成されていない場合の青色発光輝度分布を表平面図である。図２（Ｂ）は、図２（Ａ）の直線ｃｄ間における蛍光体層３１が形成されていない場合のＬＥＤアレイ１００の発光輝度分布を概略的に表す図である。なお、図２（Ａ）に施したハッチングは発光輝度分布を表し、ハッチングの密度が高くなるに従い輝度が高くなることを表している。   FIG. 2A is a front plan view of the blue light emission luminance distribution when the phosphor layer 31 is not formed in the LED array 100 according to the embodiment of the present invention. FIG. 2B is a diagram schematically showing the light emission luminance distribution of the LED array 100 when the phosphor layer 31 is not formed between the straight lines cd in FIG. Note that the hatching applied to FIG. 2A represents the light emission luminance distribution, and indicates that the luminance increases as the hatching density increases.

図１（Ａ）に示すようにＬＥＤ素子１０１を配列することにより、発光部２の頂点付近の非常に輝度が低い領域は両側に隣接する他のＬＥＤ素子１０１の輝度が高い底辺近傍領域にはさまれることとなる。頂点付近は、輝度が非常に低くなっているものの、Ｗ方向の幅が非常に狭くなっているので、両側に隣接するＬＥＤ素子１０１の底辺近傍の発光が拡散等することにより、ＬＥＤアレイ１００全体としては、当該部分の輝度は低下しない。これに対して、Ｈ方向の中心部では、隣接するＬＥＤ素子１０１のいずれも底辺近傍に比較して低い輝度を有しているので、図２（Ａ）に示すように、蛍光体層３１がない状態の青色発光ＬＥＤアレイ１００全体としては、Ｗ方向の中心部近傍領域では、底辺近傍領域に比較して低い輝度分を有することとなる。   By arranging the LED elements 101 as shown in FIG. 1 (A), a very low brightness area near the apex of the light-emitting portion 2 is in a vicinity of the bottom area where the brightness of the other LED elements 101 adjacent to both sides is high. It will be trapped. Although the brightness in the vicinity of the apex is very low, the width in the W direction is very narrow. Therefore, the light emission near the bottom of the LED element 101 adjacent to both sides is diffused, etc. As a result, the luminance of the portion does not decrease. On the other hand, in the central portion in the H direction, since all of the adjacent LED elements 101 have lower luminance than the vicinity of the bottom side, as shown in FIG. As a whole, the blue light emitting LED array 100 in the absence state has a lower luminance in the region near the center in the W direction than in the region near the bottom.

図２（Ｂ）に示すように、本発明の実施例では、Ｗ方向の中心部近傍領域の輝度（基準輝度）が、底辺近傍領域（最大輝度）の約０．６〜０．８３倍（本実施例では、０．６７倍とする）になるように設定される。すなわち、図７（Ｄ）に示したような、蛍光体層によるランバーシアン配光（中心部が明るく周囲に行くほどなだらかに暗くなる輝度分布）とは、逆のＭ型の輝度分布を意図的に形成する。   As shown in FIG. 2B, in the embodiment of the present invention, the luminance (reference luminance) in the central region in the W direction is about 0.6 to 0.83 times the basic region (maximum luminance) ( In this embodiment, it is set to 0.67). That is, as shown in FIG. 7D, the Lambertian light distribution by the phosphor layer (the luminance distribution in which the central part becomes brighter and becomes darker as it goes to the surroundings) is intentionally an M type luminance distribution opposite to that of the Lambertian light distribution. To form.

蛍光体層３１を形成すると、図７（Ｄ）に示したように、Ｗ方向の中心部近傍領域における輝度が、端部近傍領域における輝度に比較して約１．２〜１．６７倍（本実施例では、１．５倍程度とする）になってしまうので、本実施例のように、蛍光体層３１がない状態の青色発光において、Ｗ方向の中心部近傍領域の輝度（基準輝度）が、底辺近傍領域（最大輝度）の約０．６７倍程度になるように、あえて発光輝度分布をつけることにより、図２（Ｃ）に示すように、蛍光体層３１が形成されて白色発光となった場合における発光輝度分布を平坦化することが可能となる。   When the phosphor layer 31 is formed, as shown in FIG. 7D, the luminance in the vicinity of the central portion in the W direction is about 1.2 to 1.67 times the luminance in the vicinity of the end portion ( In this embodiment, the luminance is approximately 1.5 times). Therefore, in the blue light emission without the phosphor layer 31 as in this embodiment, the luminance in the vicinity of the central portion in the W direction (reference luminance) 2), the phosphor layer 31 is formed as shown in FIG. 2C by deliberately attaching the light emission luminance distribution so that it is about 0.67 times the area near the bottom (maximum luminance). It is possible to flatten the light emission luminance distribution when light is emitted.

なお、本明細書において、三角形状とは、完全な三角形に限らず、設計及び製造上の誤差を含むのはもちろん、それぞれの角が丸められたものや面取りされたものなど、三角形に近似する形状を含む。また、三角形は、図に示すような正三角形に限らず、二等辺三角形や、直角三角形等でもよい。要するに、底辺がＬＥＤアレイ１００の長手方向の辺に平行に配置され、頂点が長手方向の他の辺側に配置される三角形状であれば良い。   In this specification, the triangular shape is not limited to a perfect triangle, and includes errors in design and manufacturing, as well as approximates a triangle such as a rounded or chamfered corner. Includes shape. Further, the triangle is not limited to a regular triangle as shown in the figure, and may be an isosceles triangle, a right triangle, or the like. In short, it is only necessary to have a triangular shape in which the bottom side is arranged in parallel to the side in the longitudinal direction of the LED array 100 and the vertex is arranged on the other side in the longitudinal direction.

なお、本実施例では、引き出し電極１１をＬＥＤ素子１０１の長辺に沿って配置するため、短辺に沿って配置する従来技術に比べて、ＬＥＤ素子１０１間の間隔を狭くすることができる。したがって、ＬＥＤ素子１０１間領域の輝度低下をさらに抑制することができる。   In the present embodiment, since the extraction electrode 11 is disposed along the long side of the LED element 101, the interval between the LED elements 101 can be narrowed as compared with the conventional technique in which the extraction electrode 11 is disposed along the short side. Accordingly, it is possible to further suppress a decrease in luminance in the area between the LED elements 101.

図３は、本発明の実施例によるＬＥＤアレイ１００を組み込んだ車両用灯具（ヘッドランプ）５０の構成を表す概念図である。   FIG. 3 is a conceptual diagram showing the configuration of a vehicular lamp (headlamp) 50 incorporating the LED array 100 according to the embodiment of the present invention.

ヘッドランプ５０は、ＬＥＤアレイ１００からなる光源と、複数の小反射領域に区画されたマルチリフレクタである反射面１０３、シェード１０４及び照射レンズ１０５を含む照射光学系５１とを含んで構成される。   The headlamp 50 includes a light source including the LED array 100 and an irradiation optical system 51 including a reflection surface 103, which is a multi-reflector partitioned into a plurality of small reflection regions, a shade 104, and an irradiation lens 105.

光源（ＬＥＤアレイ）１００は、照射方向（発光面）が上向きとなるように配置され、反射面１０３は、第１焦点が光源１０２近傍に設定され、第２焦点がシェード１０４の上端縁近傍に設定された回転楕円形の反射面であり、光源１０２からの光が入射するように、光源１０２の側方から前方にかけての範囲を覆うように配置されている。   The light source (LED array) 100 is arranged so that the irradiation direction (light emitting surface) faces upward, and the reflecting surface 103 has a first focal point set near the light source 102 and a second focal point near the upper edge of the shade 104. The spheroidal reflection surface is set so as to cover a range from the side of the light source 102 to the front so that light from the light source 102 enters.

反射面１０３は、光源１００の光源像１０６を車両前方に照射し、車両前端部に正対した仮想鉛直スクリーン（照射面）１０７上に、光源像１０６が照射されるように構成されている。   The reflection surface 103 is configured to irradiate a light source image 106 of the light source 100 in front of the vehicle and to irradiate the light source image 106 on a virtual vertical screen (irradiation surface) 107 facing the front end of the vehicle.

シェード１０４は、反射面１０３からの反射光の一部を遮光してヘッドランプに適したカットオフラインを形成するための遮光部材であり、上端縁を照射レンズ１０５の焦点近傍に位置させた状態で照射レンズ１０５と光源１０２の間に配置されている。   The shade 104 is a light-shielding member for shielding a part of the reflected light from the reflective surface 103 to form a cut-off line suitable for a headlamp, with the upper edge positioned in the vicinity of the focal point of the irradiation lens 105. It is disposed between the irradiation lens 105 and the light source 102.

照射レンズ１０５は、車両前方側に配置され、反射面１０３からの反射光を照射面１０７上に照射する。   The irradiation lens 105 is disposed on the front side of the vehicle and irradiates the irradiation surface 107 with the reflected light from the reflection surface 103.

図４及び図５を参照して、本発明の実施例によるＬＥＤアレイ１００の製造方法を説明する。図４及び図５は、図１の直線ａｂ間の概略断面図であるので、図中１つの窒化物半導体発光素子（ＬＥＤ素子）１０１ａのみが表されているが、実際には、複数のＬＥＤ素子１０１ａ及び１０１ｂが交互に配列されて同一基板上に同時に形成される。なお、以下の製造方法は、あくまでも一例であり、これに限られるものではない。   A method for manufacturing the LED array 100 according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5 are schematic cross-sectional views taken along the line ab in FIG. 1, and therefore, only one nitride semiconductor light emitting element (LED element) 101a is shown in the figure. Elements 101a and 101b are alternately arranged and formed simultaneously on the same substrate. The following manufacturing method is merely an example, and the present invention is not limited to this.

まず図４（Ａ）に示すように、サファイアからなる透明基板１を準備し、有機金属化学気相成長（ＭＯＣＶＤ）法を用いて窒化物系半導体からなるデバイス構造層（ＧａＮ系発光部）２を形成する。具体的には、例えば、サファイア基板１をＭＯＣＶＤ装置に投入後、サーマルクリーニングを行い、ＧａＮバッファ層２０を成長した後に、Ｓｉ等をドープした膜厚５μｍ程度のｎ型ＧａＮ層２１、ＩｎＧａＮ量子井戸層を含む多重量子井戸発光層（活性層）２２、Ｍｇ等をドープした膜厚０．５μｍ程度のｐ型ＧａＮ層２３を含むＧａＮ系発光部２を順次成長させる。なお、本願図４及び図５に示す断面図は、説明の便宜上、縮尺を変更している。透明基板１は、ＧａＮのエピタキシャル成長が可能な格子定数を有する単結晶基板であり、後でレーザーリフトオフによる基板剥離を可能にするよう、ＧａＮの吸収端波長である３６２ｎｍの光に対して透明なものから選択される。サファイア以外に、スピネル、ＳｉＣ、ＺｎＯ等を用いても良い。   First, as shown in FIG. 4A, a transparent substrate 1 made of sapphire is prepared, and a device structure layer (GaN-based light emitting portion) 2 made of a nitride semiconductor using a metal organic chemical vapor deposition (MOCVD) method. Form. Specifically, for example, after the sapphire substrate 1 is put into a MOCVD apparatus, thermal cleaning is performed, a GaN buffer layer 20 is grown, an n-type GaN layer 21 having a thickness of about 5 μm doped with Si or the like, and an InGaN quantum well. A GaN-based light emitting portion 2 including a multiple quantum well light emitting layer (active layer) 22 including layers and a p-type GaN layer 23 having a thickness of about 0.5 μm doped with Mg or the like is sequentially grown. Note that the scales of the cross-sectional views shown in FIGS. 4 and 5 are changed for convenience of explanation. The transparent substrate 1 is a single crystal substrate having a lattice constant capable of epitaxial growth of GaN, and is transparent to light having a wavelength of 362 nm which is the absorption edge wavelength of GaN so that the substrate can be peeled off by laser lift-off later. Selected from. In addition to sapphire, spinel, SiC, ZnO, or the like may be used.

次に図４（Ｂ）に示すように、デバイス構造層２表面（ｐ型ＧａＮ層２３表面）に、電子ビーム蒸着法により膜厚２００ｎｍのＡｇ層を形成し、フォトリソグラフィによってパターニングされたｐ電極層（第１電極層）３を形成する。その後、ｐ電極層３の周辺のデバイス構造層２上（ｐ型ＧａＮ層２３上）に、スパッタ法を用いてｐ電極層３と同じ膜厚のＳｉＯ２からなるエッチングストップ層４を形成する。エッチングストップ層４は、図５（Ｂ）を参照して後述するエッチング工程においてエッチストッパーとして機能する。 Next, as shown in FIG. 4B, an Ag layer having a film thickness of 200 nm is formed on the surface of the device structure layer 2 (the surface of the p-type GaN layer 23) by an electron beam evaporation method, and is patterned by photolithography. A layer (first electrode layer) 3 is formed. Thereafter, an etching stop layer 4 made of SiO 2 having the same film thickness as the p electrode layer 3 is formed on the device structure layer 2 (on the p-type GaN layer 23) around the p electrode layer 3 by using a sputtering method. The etching stop layer 4 functions as an etch stopper in an etching process described later with reference to FIG.

次に、ｐ電極層３及びエッチングストップ層４を含む領域に、スパッタ法を用いて膜厚３００ｎｍのＴｉＷからなる拡散防止層５を形成する。拡散防止層５はｐ電極層３に用いた材質の拡散を防止するためのもので、ｐ電極層３にＡｇを含む場合には、Ｔｉ、Ｗ、Ｐｔ、Ｐｄ、Ｍｏ、Ｒｕ、Ｉｒ及びこれらの合金を拡散防止層５として用いることができる。続けて、拡散防止層５上に、スパッタ法等によりＳｉＯ２からなる絶縁層７ａを形成し、その上に、電子ビーム蒸着法を用いて膜厚２００ｎｍのＡｕからなる第１接着層６を形成する。 Next, a diffusion prevention layer 5 made of TiW having a thickness of 300 nm is formed in a region including the p electrode layer 3 and the etching stop layer 4 by sputtering. The diffusion prevention layer 5 is for preventing diffusion of the material used for the p electrode layer 3. When the p electrode layer 3 contains Ag, Ti, W, Pt, Pd, Mo, Ru, Ir, and these Can be used as the diffusion preventing layer 5. Subsequently, an insulating layer 7a made of SiO 2 is formed on the diffusion prevention layer 5 by sputtering or the like, and a first adhesive layer 6 made of Au having a thickness of 200 nm is formed thereon by using an electron beam evaporation method. To do.

なお、ｐ電極層３と拡散防止層５からなるｐ側電極１２の平面形状は、図１（Ａ）に示すように、デバイス構造層２の頂点側からデバイス構造層２外側に一部が突出するように形成される。この突出した領域において、隣接するＬＥＤ素子１０１の引き出し電極１１と電気的に接続される。   The planar shape of the p-side electrode 12 composed of the p-electrode layer 3 and the diffusion prevention layer 5 partially protrudes from the apex side of the device structure layer 2 to the outside of the device structure layer 2 as shown in FIG. To be formed. In the protruding region, the LED 11 is electrically connected to the extraction electrode 11 of the adjacent LED element 101.

次に、図４（Ｃ）に示すように、レジストマスク及び塩素ガスを用いたドライエッチング法を用いることにより、デバイス構造層２を複数の平面形状が三角形状の素子に分割する。分割されたデバイス構造層２の側面は、上方に向かって断面積が減少する形状となる。このとき、各素子間の間隔ｇ（図１（Ｃ））は、１５０μｍ以下、好ましくは３０μｍ程度に設定する。   Next, as shown in FIG. 4C, by using a dry etching method using a resist mask and chlorine gas, the device structure layer 2 is divided into a plurality of triangular elements. The side surface of the divided device structure layer 2 has a shape in which the cross-sectional area decreases upward. At this time, the gap g between the elements (FIG. 1C) is set to 150 μm or less, preferably about 30 μm.

次に、図４（Ｄ）に示すように、Ｓｉからなる支持基板１０を用意し、その上に抵抗加熱蒸着法を用いて膜厚１μｍのＡｕＳｎ（Ｓｎ：２０ｗｔ％）からなる第２接着層９を形成する。支持基板１０は熱膨張係数がサファイア（７．５×１０−６／Ｋ）やＧａＮ（５．６×１０−６／Ｋ）に近く、熱伝導率が高い材料が好ましい。例えば、Ｓｉ、ＡｌＮ、Ｍｏ、Ｗ、ＣｕＷ等を用いることができる。第１接着層６の材質と第２接着層９の材質は、融着接合が可能な、Ａｕ−Ｓｎ、Ａｕ−Ｉｎ、Ｐｄ−Ｉｎ、Ｃｕ−Ｉｎ、Ｃｕ−Ｓｎ、Ａｇ−Ｓｎ、Ａｇ−Ｉｎ、Ｎｉ−Ｓｎ等を含む金属や、拡散接合が可能なＡｕを含む金属を用いることができる。 Next, as shown in FIG. 4D, a support substrate 10 made of Si is prepared, and a second adhesive layer made of AuSn (Sn: 20 wt%) having a thickness of 1 μm is formed thereon using a resistance heating vapor deposition method. 9 is formed. The support substrate 10 is preferably made of a material having a thermal expansion coefficient close to that of sapphire (7.5 × 10 −6 / K) or GaN (5.6 × 10 −6 / K) and having high thermal conductivity. For example, Si, AlN, Mo, W, CuW, or the like can be used. The material of the first adhesive layer 6 and the material of the second adhesive layer 9 are Au-Sn, Au-In, Pd-In, Cu-In, Cu-Sn, Ag-Sn, Ag- that can be fusion bonded. A metal containing In, Ni—Sn, or the like, or a metal containing Au capable of diffusion bonding can be used.

次に、図４（Ｅ）に示すように、第１接着層６と第２接着層９を接触させ、圧力３ＭＰａで加圧した状態で３００℃に加熱して１０分間保持した後、室温まで冷却することにより融着接合を行う。   Next, as shown in FIG. 4 (E), the first adhesive layer 6 and the second adhesive layer 9 are brought into contact with each other, heated to 300 ° C. under a pressure of 3 MPa, held for 10 minutes, and then to room temperature. Fusion bonding is performed by cooling.

その後、ＵＶエキシマレーザの光をサファイア基板１の裏面側から照射し、バッファ層２０を加熱分解することで、図４（Ｆ）に示すように、レーザーリフトオフによるサファイア基板１の剥離を行う。なお、基板１の剥離あるいは除去は、エッチング等の別の手法を用いてもよい。   Thereafter, the UV excimer laser light is irradiated from the back side of the sapphire substrate 1 and the buffer layer 20 is thermally decomposed, whereby the sapphire substrate 1 is peeled off by laser lift-off as shown in FIG. Note that another method such as etching may be used for peeling or removing the substrate 1.

次に、図５（Ａ）に示すように、デバイス構造層２の端部が露出するようにフォトレジストＰＲを形成する。その後、塩素ガスを用いたドライエッチング法により、フォトレジストＰＲから露出したデバイス構造層２の端部をエッチングストップ層４が露出するまでエッチングする。これにより図５（Ｂ）に示すように、デバイス構造層２の側壁は、支持基板１０を下にした場合に上方に向かって断面積が減少するテーパ状となる。   Next, as shown in FIG. 5A, a photoresist PR is formed so that the end portion of the device structure layer 2 is exposed. Thereafter, the edge of the device structure layer 2 exposed from the photoresist PR is etched by dry etching using chlorine gas until the etching stop layer 4 is exposed. As a result, as shown in FIG. 5B, the side wall of the device structure layer 2 has a tapered shape with a cross-sectional area that decreases upward when the support substrate 10 is placed downward.

次に、図５（Ｃ）に示すように、上述した工程で形成した素子の上面全体に、スパッタ法等によりＳｉＯ２からなる保護膜（絶縁膜）７ｂを形成し、その後、デバイス構造層２上に形成された保護膜７ｂの一部を緩衝フッ酸を用いてエッチングして、透明基板１の剥離によって露出したデバイス構造層２の表面（ｎ型ＧａＮ層２１の表面）の一部を露出させる。 Next, as shown in FIG. 5C, a protective film (insulating film) 7b made of SiO 2 is formed on the entire upper surface of the element formed in the above-described process by sputtering or the like, and then the device structure layer 2 A part of the protective film 7b formed thereon is etched using buffered hydrofluoric acid, and a part of the surface of the device structure layer 2 (the surface of the n-type GaN layer 21) exposed by peeling off the transparent substrate 1 is exposed. Let

次に、図５（Ｄ）に示すように、電子ビーム蒸着法により、膜厚１０ｎｍのＴｉ層、膜厚３００ｎｍのＡｌ層、膜厚２μｍのＡｕ層をこの順序で積層し、リフトオフによってパターニングすることにより、デバイス構造層２の底辺に近接した位置に、当該底辺に平行な、例えば、幅４０μｍ程度の引き出し電極（第１配線層）１１と、これと電気的に接続された、ＬＥＤアレイ１００の短辺に平行な、例えば、幅１０μｍ程度の引き出し電極（第２配線層）８を同時に形成する。なお、引き出し電極１１の線幅は２０μｍ以上２００μｍ以下であることが好ましい。また、引き出し電極８の線幅は２０μｍ以下３μｍ以上であることが好ましい。また、引き出し電極１１の線幅は、引き出し電極８の線幅よりも広いことが望ましい。なお、引き出し電極８はＬＥＤアレイ１００の短辺に平行で長辺に垂直に形成されるが、例えば、斜辺に平行にするなど、長辺に平行でなければ必ずしも短辺に平行でなくても良い。   Next, as shown in FIG. 5D, a 10 nm thick Ti layer, a 300 nm thick Al layer, and a 2 μm thick Au layer are stacked in this order by electron beam evaporation and patterned by lift-off. Thus, the LED array 100 electrically connected to the lead electrode (first wiring layer) 11 having a width of about 40 μm, for example, parallel to the bottom side, at a position close to the bottom side of the device structure layer 2. A lead electrode (second wiring layer) 8 having a width of, for example, about 10 μm is formed at the same time. The line width of the extraction electrode 11 is preferably 20 μm or more and 200 μm or less. The line width of the extraction electrode 8 is preferably 20 μm or less and 3 μm or more. The line width of the extraction electrode 11 is desirably wider than the line width of the extraction electrode 8. The lead electrode 8 is formed parallel to the short side of the LED array 100 and perpendicular to the long side. For example, the lead electrode 8 is not necessarily parallel to the short side unless it is parallel to the long side. good.

引き出し電極１１は、隣接した素子ではお互いに異なる長辺に近接して形成される。引き出し電極８は、上述の工程で露出されたデバイス構造層２の表面（ｎ型ＧａＮ層２１の表面）の一部と電気的に接続されている。ｎ側（ｎ型ＧａＮ層２１）に接続する引き出し電極１１及び引き出し電極８は、ｎ型ＧａＮ層２１の表面上に形成されるので、輝度を損なわないように、図１に示すような引き出し電極１１を基部とし、引き出し電極８を櫛の歯とする櫛歯形の平面形状となっている。   The extraction electrode 11 is formed adjacent to different long sides in adjacent elements. The extraction electrode 8 is electrically connected to a part of the surface of the device structure layer 2 (surface of the n-type GaN layer 21) exposed in the above-described process. The extraction electrode 11 and the extraction electrode 8 connected to the n-side (n-type GaN layer 21) are formed on the surface of the n-type GaN layer 21, so that the extraction electrode as shown in FIG. 11 is a comb-shaped planar shape with 11 as a base and the extraction electrode 8 as comb teeth.

引き出し電極１１を形成する位置は、デバイス構造層２から発せられる光の取り出しを妨げないようにするために、デバイス構造層２以外の領域が望ましい。しかしデバイス構造層２から離れすぎると、引き出し電極８での配線抵抗が大きくなるため、デバイス構造層２の長辺と引き出し電極１１の間隔は５０μｍ以内であることがより望ましい。引き出し電極１１は隣接した素子のｐ電極層３と電気的に接続され、複数の素子が直列に接続された発光素子アレイ１００が形成される。なお、一枚の基板から複数のＬＥＤアレイ１００を製造する場合は、スクライブ後ブレイキングして素子分離を行う。   The position where the extraction electrode 11 is formed is desirably a region other than the device structure layer 2 so as not to prevent extraction of light emitted from the device structure layer 2. However, if the distance is too far from the device structure layer 2, the wiring resistance at the extraction electrode 8 increases, and therefore the distance between the long side of the device structure layer 2 and the extraction electrode 11 is more preferably within 50 μm. The extraction electrode 11 is electrically connected to the p-electrode layer 3 of an adjacent element, and a light emitting element array 100 in which a plurality of elements are connected in series is formed. In addition, when manufacturing several LED array 100 from one board | substrate, it breaks after scribe and performs element isolation.

続いて、図５（Ｄ）に示すように、蛍光体層（蛍光体含有樹脂層）３１で、基板３０上に実装された複数のＬＥＤ素子１０１を封止する。ＬＥＤ素子１０１を蛍光体層３１により封止した後に、高温で樹脂硬化させることにより、ＬＥＤアレイ１００を完成させることができる。   Subsequently, as shown in FIG. 5D, a plurality of LED elements 101 mounted on the substrate 30 are sealed with a phosphor layer (phosphor-containing resin layer) 31. After the LED element 101 is sealed with the phosphor layer 31, the LED array 100 can be completed by curing the resin at a high temperature.

蛍光体層３１の厚さは、例えば、２０〜２００μｍに設定され、好ましくは、５０〜１００μｍ程度である。また、蛍光体含有樹脂は、透光性樹脂材料に対して求める色温度になるように蛍光体を測量し、攪拌によって混合することによって作製する。透光性樹脂材料としては、シリコーン、エポキシ及びシリコーンとエポキシが混合されたハイブリッドタイプの樹脂を用いることが好ましい。黄色蛍光体としては、ＹＡＧ（イットリウム・アルミニウム・ガーネット）系蛍光体を用いることが好ましい。なお、蛍光体含有樹脂には、この他、拡散材や増粘材等を混合することも可能である。ＬＥＤ素子１０１を封止する手法としては、印刷、ディスペンスなどが考えられるが、寸法精度の観点より印刷による封止が好ましい。なお、蛍光体層３１の材料や厚さ等の製造条件を変化させても、中心部の輝度が周辺部に比較して１、５倍程度となることに変わりはない。   The thickness of the phosphor layer 31 is set to 20 to 200 μm, for example, and preferably about 50 to 100 μm. In addition, the phosphor-containing resin is prepared by measuring the phosphor so that the color temperature required for the translucent resin material is obtained, and mixing by stirring. As the translucent resin material, it is preferable to use silicone, epoxy, and a hybrid type resin in which silicone and epoxy are mixed. As the yellow phosphor, it is preferable to use a YAG (yttrium, aluminum, garnet) phosphor. In addition to this, the phosphor-containing resin can be mixed with a diffusing material, a thickening material, or the like. As a method for sealing the LED element 101, printing, dispensing, and the like are conceivable, but sealing by printing is preferable from the viewpoint of dimensional accuracy. Note that even if the manufacturing conditions such as the material and thickness of the phosphor layer 31 are changed, the luminance of the central portion is still about 1 to 5 times that of the peripheral portion.

なお、デバイス構造層２は、図６に示すように長辺の一辺のみが下方に向かって外側に広がる斜面となるように加工されていても良い。この場合、図５（Ａ）に示すフォトレジスト形成工程において、デバイス構造層の長辺の一辺にのみ露出されるようにフォトレジストを形成し、図５（Ｂ）に示すエッチング工程では、該デバイス構造層２の長辺の一辺のみを塩素ガスを用いたドライエッチング法を用いることにより、長辺の一辺のみが下方に向かって外側に広がる斜面となる形状に加工する。また、引き出し電極８は、長辺の一辺に形成された斜面に沿って形成される。なお、このとき隣接するＬＥＤ素子１０１では、上下に異なる側の長辺が下方に向かって外側に広がる斜面に加工されているようにする。   In addition, the device structure layer 2 may be processed so that only one side of the long side becomes a slope extending outward as shown in FIG. In this case, in the photoresist forming step shown in FIG. 5A, a photoresist is formed so as to be exposed only on one side of the long side of the device structure layer, and in the etching step shown in FIG. By using a dry etching method using chlorine gas, only one side of the long side of the structural layer 2 is processed into a shape in which only one side of the long side becomes a slope that spreads outward. The extraction electrode 8 is formed along a slope formed on one side of the long side. At this time, in the adjacent LED elements 101, the long sides on the different sides in the vertical direction are processed into slopes extending outwardly downward.

以上、本発明の実施例によれば、発光部２の平面形状を底辺が長方形のＬＥＤアレイ１００の一方の長辺に沿って平行に形成され、頂点が他方の長辺側に配置されるような形状（例えば、三角形状）にすることにより、蛍光体層３１を形成して白色化する前の青色ＬＥＤ素子１０１を複数有する長方形のＬＥＤアレイ１００の輝度分布を、縦方向（短辺方向）の中心部を基準輝度とした場合に、長方形のＬＥＤアレイ１００の長辺に近い側に、基準輝度の１．２〜１．６７倍の輝度を有する最大輝度領域が形成されるようにする。このようにすることにより、蛍光体層３１を形成して白色化した場合に、面内にフラットな白色輝度分布を得ることが可能となる。   As described above, according to the embodiment of the present invention, the planar shape of the light emitting unit 2 is formed in parallel along one long side of the LED array 100 whose base is rectangular and the apex is arranged on the other long side. The luminance distribution of the rectangular LED array 100 having a plurality of blue LED elements 101 before the phosphor layer 31 is formed and whitened is formed in a vertical direction (short side direction). When the central portion of the LED array is set as the reference luminance, a maximum luminance region having a luminance of 1.2 to 1.67 times the reference luminance is formed on the side close to the long side of the rectangular LED array 100. Thus, when the phosphor layer 31 is formed and whitened, a flat white luminance distribution can be obtained in the plane.

また、引き出し電極１１をＬＥＤ素子１０１の長辺に沿って配置するため、ＬＥＤ素子１０１間の間隔ｇを狭くして、ＬＥＤ素子１０１間の輝度低下を抑制することができる。   In addition, since the lead electrode 11 is disposed along the long side of the LED element 101, the gap g between the LED elements 101 can be narrowed to suppress a decrease in luminance between the LED elements 101.

また、発光面の斜辺は、直線に限らず曲線で構成されていても良い。また、直線と曲線の組み合わせでも良く、異なる傾斜角の直線の組み合わせでも良い。少なくとも、ＬＥＤアレイの長辺に対して傾斜を有する部分を有する辺であれば良い。すなわち、発光部２の平面形状は三角形状や三角形に近似する形状に限らず、ホームベース形状のような五角形や一つの頂点を鋭角とした四角形、台形など、ＬＥＤアレイ１００の長辺に平行な底辺と、該底辺に垂直な線に対して傾斜する部分を含む少なくとも１つの辺を有する形状であって、底辺から離れるに従い発光部２の横方向の幅が徐々に減少する形状であればよい。   Further, the hypotenuse of the light emitting surface is not limited to a straight line, but may be a curved line. Further, a combination of straight lines and curves may be used, or a combination of straight lines having different inclination angles may be used. It suffices that the side has at least a portion having an inclination with respect to the long side of the LED array. That is, the planar shape of the light emitting unit 2 is not limited to a triangular shape or a shape approximating a triangular shape, but is parallel to the long side of the LED array 100 such as a pentagon like a home base shape, a quadrangle with a single apex as an acute angle, or a trapezoid. A shape having at least one side including a base and a portion inclined with respect to a line perpendicular to the base may be used as long as the lateral width of the light emitting unit 2 gradually decreases as the distance from the base is increased. .

以上、実施例、及び変形例に沿って本発明を説明したが、本発明はこれらに限定されるものではない。種々の変更、改良、組み合わせ等が可能なことは当業者には自明であろう。   As mentioned above, although this invention was demonstrated along the Example and the modification, this invention is not limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

１…サファイア基板、２…デバイス構造層（ＧａＮ系発光部）、３…ｐ電極層（第１電極層）、４…エッチングストップ層、５…拡散防止層、６…第１接着層、７…絶縁膜、８…引き出し電極（第２ｎ電極層）、９…第２接着層、１０…シリコン（Ｓｉ）支持基板、１１…引き出し電極（第１ｎ電極層）、１２…電極層、２０…バッファ層、２１…ｎ型ＧａＮ層、２２…活性層、２３…ｐ型ＧａＮ層、３１…蛍光体層（波長変換層）、５０…ヘッドランプ、５１…投射光学系、１００…ＬＥＤアレイ、１０１…窒化物半導体発光素子（ＬＥＤ素子）、１０３…反射面、１０４…シェード、１０５…照射レンズ、１０６…光源像、１０７…照射面 DESCRIPTION OF SYMBOLS 1 ... Sapphire substrate, 2 ... Device structure layer (GaN-type light emission part), 3 ... p electrode layer (1st electrode layer), 4 ... Etching stop layer, 5 ... Diffusion prevention layer, 6 ... 1st adhesion layer, 7 ... Insulating film, 8 ... extraction electrode (second n electrode layer), 9 ... second adhesive layer, 10 ... silicon (Si) support substrate, 11 ... extraction electrode (first n electrode layer), 12 ... electrode layer, 20 ... buffer layer 21 ... n-type GaN layer, 22 ... active layer, 23 ... p-type GaN layer, 31 ... phosphor layer (wavelength conversion layer), 50 ... headlamp, 51 ... projection optical system, 100 ... LED array, 101 ... nitriding Solid-state semiconductor light emitting element (LED element), 103 ... reflective surface, 104 ... shade, 105 ... irradiation lens, 106 ... light source image, 107 ... irradiation surface

Claims (5)

第１の方向に長い基板上に複数の半導体発光素子が形成された半導体発光素子アレイであって、
前記複数の半導体発光素子のそれぞれが、
前記基板上に形成された電極層と、
前記電極層上に形成され、前記電極層に電気的に接続されたｐ型半導体層と、前記ｐ型半導体層上に形成された活性層と、前記活性層上に形成されたｎ型半導体層とを有する半導体発光層と、
前記半導体発光層の一辺に沿って、該一辺と平行に形成された第１配線層と、
前記第１配線層から前記半導体発光層にかけて延在し、前記半導体発光層の表面において、前記ｎ型半導体層と電気的に接続される複数の第２配線層と、
前記半導体発光層の上方に形成される蛍光体層とを有し、
前記半導体発光層の平面形状が、前記第１の方向に平行な底辺と、該底辺に垂直な線に対して傾斜する部分を含む少なくとも１つの辺を有し、前記半導体発光層の前記第１の方向の幅が前記底辺から離れるに従い減少する形状である半導体発光素子アレイ。 A semiconductor light emitting element array in which a plurality of semiconductor light emitting elements are formed on a substrate that is long in a first direction,
Each of the plurality of semiconductor light emitting elements is
An electrode layer formed on the substrate;
A p-type semiconductor layer formed on the electrode layer and electrically connected to the electrode layer, an active layer formed on the p-type semiconductor layer, and an n-type semiconductor layer formed on the active layer A semiconductor light emitting layer comprising:
A first wiring layer formed along and parallel to one side of the semiconductor light emitting layer;
A plurality of second wiring layers extending from the first wiring layer to the semiconductor light emitting layer and electrically connected to the n-type semiconductor layer on a surface of the semiconductor light emitting layer;
A phosphor layer formed above the semiconductor light emitting layer,
The planar shape of the semiconductor light emitting layer has at least one side including a bottom side parallel to the first direction and a portion inclined with respect to a line perpendicular to the base side, and the first shape of the semiconductor light emitting layer A semiconductor light-emitting element array having a shape in which the width in the direction decreases with increasing distance from the bottom. 前記形状は三角形である請求項１記載の半導体発光素子アレイ。   The semiconductor light-emitting element array according to claim 1, wherein the shape is a triangle. 隣接する半導体発光素子間においては、前記第１配線層が交互に上下に配置されることを特徴とする請求項１又は２記載の半導体発光素子アレイ。   3. The semiconductor light-emitting element array according to claim 1, wherein the first wiring layers are alternately arranged above and below between adjacent semiconductor light-emitting elements. 前記第１配線層は、一方に隣接する半導体発光素子の前記電極層と電気的に接続され、前記複数の半導体発光素子が直列に接続された請求項１〜３のいずれか１項に記載の半導体発光素子アレイ。   The said 1st wiring layer is electrically connected with the said electrode layer of the semiconductor light-emitting element adjacent to one side, The said some semiconductor light-emitting element was connected in series of any one of Claims 1-3. Semiconductor light emitting element array. 請求項１〜４のいずれか１項に記載の半導体発光素子アレイと、
前記半導体発光素子アレイの照射像が照射面において重なるように照射する光学系と
を有する車両用灯具。 The semiconductor light-emitting element array according to any one of claims 1 to 4,
A vehicular lamp having an optical system for irradiating an irradiation image of the semiconductor light emitting element array so as to overlap on an irradiation surface.
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