JP2013055558A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device that allows the fault detection probability of a circuit generating an error detection code to be further increased.SOLUTION: An information processing device 100 sends data which was input into a communication raw data receiving unit 2 to a check sum generation unit 4 functioning as error detection code generation means, and generates a check sum which is an error detection code by calculation. A verification data generation unit 1 functioning as inspection data generation means generates inspection data on the basis of data input previously if communication raw data has not been present for a period equal to or longer than a preset period, and hands over the inspection data to the check sum generation unit 4.

Description

  The present invention relates to an information processing apparatus including means for generating an error detection code for error detection during data communication or storage.

  As a technique for detecting errors during transmission / reception of digital data, writing / reading of stored data, and error (error), an error detection code that can be calculated from the data itself, such as a checksum, is added to the data, and after reception, writing, or reading There is known a method of comparing the value of an error detection code obtained from subsequent data with an added code.

  A specific example of data transmission / reception is shown in FIG. The communication data 70 is input to the checksum generation circuit 4 (FIG. 8A), the bit values of the data are added, and the lower bit of the sum is added to the communication data 70 as the checksum 71 (FIG. 8B). On the receiving side, the communication data 70 excluding the checksum 71 is taken out (FIG. 8 (c)) and input to the receiving checksum generation circuit 4a to receive the generated checksum 71 ′. Compared with the checksum 71 (FIG. 8D). When the two do not match, it is determined that an error has occurred in the data communication.

  However, if the error detection code generating circuit itself fails and an incorrect error detection code is added, it is erroneously determined that there is an error even though the data itself has no error. Therefore, it is necessary to make a failure determination for a circuit that generates such an error detection code.

  As such a circuit failure determination method, a test pattern is input to an arithmetic unit as described in Patent Document 1, and a fault of the arithmetic circuit is detected by comparing the output value with an expected value for the test pattern. There is a technique.

JP 2006-319055 A

  However, with this method, depending on the test pattern, the output value may coincide with the expected value even when the arithmetic circuit is out of order.

  Therefore, an object of the present invention is to provide an information processing apparatus that can further improve the failure detection probability of a circuit that generates an error detection code.

  In order to solve the above-described problem, an information processing apparatus according to the present invention includes an error detection code generation unit that generates an error detection code by calculation from input data. In the case where there is no input data to the detection means, inspection data generation means for generating inspection data based on data input before that and delivering the inspection data to the error detection code generation means is further provided. It is characterized by having.

  An expected value storage unit that stores an expected value of the error detection code for the input data, and a comparator that compares the stored expected value with the error detection code generated by the error detection code generation unit may be provided.

  The inspection data generation means may adjust the inspection data so that the 0/1 appearance probability of bits in the data delivered to the error detection code generation means approaches 50%.

  According to the present invention, when a blank state in which no data is input to the error detection code generation means continues for a predetermined period or longer, new inspection data is created based on the previous data and error detection is performed. By generating an error detection code by means, various verification data for verifying the error detection code generation means can be acquired. By performing verification using this verification data, a failure of the error detection code generation means can be detected early.

  By storing the expected value of the error detection code and comparing this with the generated error detection code, the failure of the error detection code generation means can be reliably grasped.

  When generating inspection data, by adjusting the 0/1 occurrence probability of the bits in the data passed to the error detection means to approach 50%, it is possible to generate inspection data with high completeness and error detection. The failure of the code generation circuit can be determined early.

It is a block block diagram which shows 1st Embodiment of the information processing apparatus concerning this invention. It is a flowchart which shows the error detection code production | generation process in the apparatus of FIG. It is a table | surface which shows the example of the production | generation data in the process in the apparatus of FIG. It is a modification of the process of FIG. It is a figure which shows the structure of the data sequence sent to a communication data transmission part in the apparatus of FIG. It is a block block diagram which shows 2nd Embodiment of the information processing apparatus concerning this invention. It is a flowchart which shows the error detection code production | generation process in the apparatus of FIG. It is a figure which shows the process at the time of transmission / reception of the produced | generated communication data.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. In order to facilitate the understanding of the description, the same reference numerals are given to the same components in the drawings as much as possible, and duplicate descriptions are omitted.

  FIG. 1 shows a block configuration of a first embodiment of an information processing apparatus 100 according to the present invention. Here, only a transmission unit that transmits separately processed data to another system will be described. This transmission / reception is not limited to transmission / reception to / from another information processing apparatus outside the information processing apparatus, but includes data transmission / reception to / from an external device such as a storage device connected to the information processing apparatus or a built-in device.

  This information processing apparatus 100 generates inspection data, which will be described later, and a verification data generation unit 1 that functions as an inspection data generation unit, a communication raw data reception unit 2 that acquires communication raw data to be transmitted, and communication raw data And a data selection unit 3 for selecting one of the check data, a checksum that is an error detection code from input data, a checksum generation unit 4 that functions as an error detection code generation unit, and a checksum for communication data And a communication data transmission unit 5 for transmission by addition. The verification data generation unit 1 includes data verification means 10 for verifying data and random number generation means 11 for generating random numbers.

  A flow chart of error detection code generation processing in this apparatus is shown in FIG. This process is repeatedly executed at a predetermined timing with the verification data generation unit 1 as the center.

  First, communication raw data is acquired by the communication raw data receiving unit 2 and sent to the data verification means 10 (step S1). It is determined whether or not raw data exists at the time step (step S2). If there is raw data, the process proceeds to step S3. In step S3, the data verification means 10 calculates the appearance rate of 1 in the bits of the raw data for a certain past period (predetermined period). Subsequently, the data selection unit 3 sets 0 indicating the raw data to the flag value for distinguishing whether the data is the raw data or the verification data, and transfers the data to the checksum generation unit 4 (step S4). The checksum generation unit 4 that has received the raw data calculates a checksum value (step S5), passes the raw data and the flag value to the communication data transmission unit 5, and the communication data transmission unit 5 communicates from the received data. Data is generated and data transmission is executed (step S6). The transmission data 7 is obtained by adding a checksum 71 and a flag 72 to the communication data main body 70 as shown in FIG. The receiving side can determine whether the data is raw data or verification data by referring to the flag 72.

  On the other hand, if there is no raw data, the process proceeds to step S7, where the random number generating means 11 is changed based on the appearance rate of 1 in the bit of the raw data in the past fixed period obtained in the previous time step. The data for inspection is generated using the data and sent to the data selection unit 3 and stored in, for example, a buffer in which raw data is stored. At the same time, the data selection unit 3 sets 1 indicating the verification data to the flag value for distinguishing whether the data is the raw data or the verification data, and delivers the data to the checksum generation unit 4 (step S8). The process proceeds to S5. The subsequent processing is the same as when raw data exists.

  The verification data generation process in step S7 will be described below with a specific example. FIG. 3 is a table for explaining data generation. Here, it is assumed that the raw data to be communicated is 4-bit data from bit0 to bit3, and that there is no communication data at t6 and t10 among time steps t1 to t10 (see the table on the upper left).

  The table at the center of each stage shows the appearance rate of 1 for each bit in the communication raw data accumulated from time t1. For example, the cumulative 1 appearance rate of bit 0 at t5 is 60% because 1 appears 3 times out of 5 in the communication data so far. Similarly, the appearance rates of bit2 to bit4 are 0%, 40%, and 80%. This accumulation may be carried out for n time steps immediately before, or may be reset at a cycle of n times. In either case, the influence of the uneven distribution of short-term data can be suppressed by making n sufficiently large.

  If communication data does not exist, the data generated by the verification data generation unit is inserted. When creating the data to be inserted, the value of each bit is generated by a weighted random number. At this time, in this example, weighting is performed so that 0 is generated with a probability corresponding to the appearance rate of 1 in the previous bits. For example, the random number generation means 11 generates a numerical value between 0 and 1 at random, and when it is desired to generate 0 with a probability of 60%, when a random value of 0.6 or less is returned, When a random value exceeding 0 and 0.6 is returned, 1 may be inserted into the bit.

  Specifically, the verification data at the time t6 indicated by the circle 3 is inserted according to the occurrence probability at the time t5 indicated by the circle 2, and the circle 6 according to the one occurrence probability at the time t9 indicated by the circle 5 The verification data at time t10 shown is inserted. As a result, as shown by circles 4 and 7, the rate of 1 appearance at time t10 is close to 50% for all bits compared to before insertion. Thus, by adjusting the appearance probability of 0/1 to approach 50%, the completeness of the verification data is increased, and it is easy to determine the failure of the checksum generation unit 4 early and reliably. .

  In this example, for the inserted data, when the probability of generating 0 is 50% or more, 0 is inserted in each bit, and when it is less than 50%, 1 is inserted in each bit. The opposite value may be inserted into any of the bits. Even if the opposite value is inserted in this way, the cumulative probability of occurrence converges to 50% in the long term.

  Alternatively, as shown in FIG. 4, when the occurrence probability of 1 is 50% or more, 0 is generated with a probability of α%, and when the appearance probability of 1 is less than 50%, (100−α ) 0 is generated with a probability of%. Here, α is set to 51 to 99. If the probability is set with a low probability, the convergence is delayed. If the probability is set with a high probability, the convergence is accelerated. On the other hand, the converged numerical value may be deviated and diverge. Therefore, about 60 is preferable.

  Here, the inspection data is created so that the appearance probability of 1 approaches 50%, but the inspection is performed so that the appearance probability approaches a predetermined probability other than 50% (for example, 40%, 70%, etc.). Data may be created.

  Next, a second embodiment of the information processing apparatus according to the present invention will be described with reference to the block diagram of FIG. The information processing apparatus 101 according to the second embodiment is obtained by adding a checksum verification unit 6 to the information processing apparatus 100 according to the first embodiment. The checksum verification unit 6 includes a comparator 61.

  A specific process of the checksum verification unit 6 will be described with reference to a flowchart of FIG. First, the expected value of the checksum value corresponding to the input data is read from the expected value storage unit 60 (step S11). Next, the checksum value generated by the checksum generator 4 is compared with the expected value by the comparator 61 (step S12). If they match, it is determined that there is no abnormality in the checksum generator 4 (step S13). On the other hand, if they do not match, it is determined that the checksum generator 4 is abnormal. Thus, by performing checksum verification, it is possible to determine an abnormality in the checksum generation unit 4 at an early stage.

  In the above description, the case where the checksum value is used as the error detection code has been described as an example. However, the present invention can also be applied to the case where other error detection codes such as a parity bit, a cyclic code, and a hash function are used.

  DESCRIPTION OF SYMBOLS 1 ... Verification data generation part, 2 ... Communication raw data reception part, 3 ... Data selection part, 4 ... Checksum generation part, 4a ... Checksum generation circuit, 5 ... Communication data transmission part, 6 ... Checksum verification part, 10 ... Data verification means, 11 ... Random number generation means, 60 ... Expected value storage section, 61 ... Comparator, 70 ... Communication data, 70 ... Communication data body, 71 ... Checksum, 72 ... Flag, 100, 101 ... Information processing apparatus .

Claims (3)

In an information processing apparatus including error detection code generation means for generating an error detection code by calculation from input data,
When there is no input data to the error detection code generation means for a period longer than a preset period, test data is generated based on data input before that, and the error detection code generation means An information processing apparatus further comprising inspection data generating means for transferring inspection data. 2. An expected value storage unit for storing an expected value of an error detection code for input data, and a comparator for comparing the stored expected value with the error detection code generated by the error detection code generation means. The information processing apparatus described. The inspection data generation means adjusts the inspection data so that the 0/1 appearance probability of bits in the data delivered to the error detection code generation means approaches 50%. 2. The information processing apparatus according to 2.

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