JP2013055088A - Magnetic resistance element and magnetic storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable magnetic resistance element and a highly reliable magnetic storage device, which can reliably achieve desired multiple values without damages in an etching process by laminating MTJ (Magnetic Tunnel Junction) having an interface magnetization film as a fixed magnetization layer and a free magnetization layer.SOLUTION: A multivalued memory 10A includes: MTJ 10a; MTJ 10b provided above MTJ 10a; and a connection layer 13 provided between MTJ 10a, 10b. MTJ 10a, 10b respectively include: insertion layers 1a, 1b composed of Ta; lower magnetization layers 2a, 2b contacting the insertion layers 1a, 1b on the insertion layers 1a, 1b and each having magnetic anisotropy in a vertical direction with respect to a principal surface; upper magnetization layers 4a, 4b having magnetic anisotropy in the vertical direction with respect to the principal surface; and tunnel barrier layers 3a, 3b respectively provided between the lower magnetization layers 2a, 2b and the upper magnetization layers 4a, 4b. The ones of the lower magnetization layers 2a, 2b and the upper magnetization layers 4a, 4b function as fixed magnetization layers and the other ones function as free magnetization layers.

Description

  The present invention relates to a magnetoresistive element and a magnetic storage device.

  One of the nonvolatile memory elements whose memory is not lost even when the power is turned off is a magnetic random access memory (MRAM). The MRAM can perform a high-speed read / write operation comparable to that of an SRAM, and has advantages such as that power consumption is about 1/10 that of a flash memory and that high integration is possible. That is, the MRAM has almost important attributes as a memory element. Therefore, application as a so-called universal memory having all the functions of SRAM (high-speed operation), DRAM (high integration), and flash memory (non-volatile) is expected.

  2. Description of the Related Art A spin injection tunneling magnetoresistive element (Magnetic Tunnel Junction: MTJ) employs bidirectional writing in which writing is performed by changing the direction of a current flowing through the MTJ. That is, there are two states, a high resistance state (anti-parallel state) and a low resistance state (parallel state), depending on the relative orientation of the free magnetic layer and the fixed magnetic layer provided above and below the tunnel barrier layer. In a spin injection type MRAM, a read operation is performed using this resistance difference.

JP 2010-165790 A

Slonczewski: J. Magn. Magn. Mater. 159 L1 (1996) S. Ikeda et al. Nature Mater., 9, 721 (2010) D. C. Worledge et al., Appl. Phys. Lett., 98, 022501 (2011). T. Ishigaki et al., Symposium on VLSI Technology (2010), pp. 47-48.

  As described above, since the MTJ normally has only two resistance states, a multi-value memory such as a NAND flash memory cannot be configured with only one MTJ. Therefore, it has been proposed to produce an element having three or more resistance states by arranging two MTJs in series and sensing the series resistance (see, for example, Patent Document 1). In particular, it is possible to easily arrange two MTJs in series with the same area as in the case of one MTJ by simply depositing two MTJs vertically.

In order to arrange the STT-MRAM in a multivalued memory structure by arranging two or more MTJs vertically, MTJs having different switching currents (write currents) I _c may be arranged, or MTJs having different areas may be arranged. However, large MTJ write current I _c, or the use of large MTJ area, power consumption increases, and further can not be reduced even if the gate width of the selection transistor. Therefore, there is a problem that it is difficult to integrate the MTJ on a large scale.

The biggest problem in the spin injection type MRAM is to reduce the write current I _c while maintaining the memory retention stability. If the film thickness of the free magnetic layer is reduced or the element area is reduced, the write current I _c is reduced, but the storage retention stability (Δ) is also proportional to the volume of the free layer and thus decreases together.

The MTJ write current density J _c0 is expressed by the following equation (1) (see Non-Patent Document 1).
_{J c0 = αγeM s t (H} ext ± H k - ± H d) / μ B g ··· (1)
Where α is the damping constant, γ is the gyro constant, e is the charge of the electron, M _s is the saturation magnetization of the free magnetic layer, H _ext is the external magnetic field, H _k is the magnetic anisotropy of the free magnetic layer, and H _d is Demagnetizing field in the direction perpendicular to the surface of the free magnetic layer, μ _B is Bohr magneton, and g is spin torque efficiency.

The MTJ retention Δ is expressed by the following equation (2).
Δ = K _u V / k _B T (2)
Here, the volume of K _u is the free magnetic layer anisotropic energy, V is the free magnetic layer, k _B is the Boltzmann constant, T is the absolute temperature.

Since the write current I _c is defined by J _c × the area of the free magnetic layer, and the write current I _c and the retention Δ are both proportional to the volume V of the free magnetic layer, the write current I _c and the retention Δ are traded off from each other. Are in a relationship. That is, if the area of the free magnetic layer is reduced, the write current I _c decreases, but the retention Δ also decreases. In the in-plane MTJ, _Ku is generated almost from the shape magnetic anisotropy, so there is a limit to reducing the area and aspect ratio.

On the other hand, an MTJ having a perpendicular magnetic film that has a large magnetic anisotropy and ensures a large retention Δ even with a small element has been proposed. In the MTJ, K _u is generated from the crystal magnetic anisotropy rather than the shape magnetic anisotropy. In addition, since the demagnetizing field component Hd in the vertical direction in the above formula (1) becomes 0, J _c also becomes small. However, in order to form an alloy-based perpendicular magnetization film mainly composed of an intermetallic compound of noble metal and Co or Fe, it is necessary to form the film while heating the substrate in order to increase the degree of order of the alloy. This is disadvantageous in terms of cost and throughput. The crystal anisotropy and no thicker than a certain physical film thickness of the free magnetic layer since it is difficult to occur, there is a problem that J _c becomes thick free layer increases.

  Therefore, an MTJ in which a perpendicular magnetization film is formed only by a thin CoFeB layer has been proposed (see Non-Patent Document 2). In this MTJ, a tunnel barrier layer made of MgO is sandwiched between a pair of CoFeB layers having a thickness of about 1 nm on a lower electrode in which Ru and Ta are laminated, and a cap layer made of Ta is formed on the upper CoFeB layer. It becomes. In this case, one of the two CoFeB layers is a fixed magnetic layer and the other is a free magnetic layer.

  At present, no attempt has been made to multi-value the MRAM using the MTJ in which the perpendicular magnetization film is formed only by the thin CoFeB layer. In order to achieve this multi-value, it is considered that various ideas are required for Ta under the CoFeB layer, and the present situation has not yet been reached.

  The present invention has been made in view of the above-mentioned problems, and an MTJ having an interface magnetization film as a fixed magnetization layer and a free magnetization layer is laminated to reliably realize an intended multi-value without damage in an etching process. It is an object of the present invention to provide a highly reliable magnetoresistive element and magnetic storage device that can be used.

  One aspect of the magnetoresistive element includes a first memory structure, a second memory structure provided above the first memory structure, and between the first memory structure and the second memory structure. The first memory structure and the second memory structure are each composed of an insertion layer made of Ta, and in contact with the insertion layer on the insertion layer and perpendicular to the main surface. A lower magnetic layer having a magnetic anisotropy, an upper magnetic layer having a magnetic anisotropy perpendicular to the main surface, and a tunnel barrier layer provided between the lower magnetic layer and the upper magnetic layer. One of the lower magnetic layer and the upper magnetic layer is a fixed magnetic layer, and the other is a free magnetic layer.

  One aspect of the magnetic memory device is a magnetic memory device in which a plurality of memory cells each including a magnetoresistive element and a drive transistor are arranged. The magnetoresistive element includes a first memory structure and the first memory. A second memory structure provided above the structure, and a connection layer provided between the first memory structure and the second memory structure, wherein the first memory structure and the second memory structure Each of the memory structures includes an insertion layer made of Ta, a lower magnetization layer in contact with the insertion layer on the insertion layer and having a magnetic anisotropy perpendicular to the main surface, and a magnetic difference perpendicular to the main surface. And a tunnel barrier layer provided between the lower magnetic layer and the upper magnetic layer, and one of the lower magnetic layer and the upper magnetic layer is fixed magnetization. The other layer is a free magnetic layer.

  According to the above aspects, the MTJ having the interface magnetization film as the fixed magnetization layer and the free magnetization layer is laminated, and the desired multi-value can be reliably realized without any damage in the etching process. A magnetoresistive element and a magnetic storage device are realized.

It is a schematic sectional drawing which shows schematic structure of the multilevel memory by 1st Embodiment. 1 is a schematic cross-sectional view showing a schematic configuration of a multi-level memory actually formed in the first embodiment. It is a characteristic view showing the result of measuring the saturation magnetic field in the direction perpendicular to the main surface by VSM (Vibrating Sample Magnetometry) and evaluating the vertical component of CoFeB. FIG. 4 is a characteristic diagram showing a magnetization curve when the thickness of CoFeB is 1 nm in the sample A of FIG. 3. FIG. 4 is a characteristic diagram showing a magnetization curve when the thickness of CoFeB is 1.1 nm in the sample A of FIG. 3. It is a characteristic view showing an MR loop measured by changing the thickness of the lower magnetic layer (CoFeB) of MTJ. It is a characteristic view showing an MR loop measured by changing the thickness of the upper magnetic layer (CoFeB) of MTJ. It is a characteristic view for demonstrating the multi-value storage in the multi-value memory by 1st Embodiment. It is a schematic sectional drawing which shows schematic structure of the multi-value memory by the modification 1 of 1st Embodiment. It is a characteristic view for demonstrating the multi-value storage in the multi-value memory by the modification 1 of 1st Embodiment. It is a schematic sectional drawing which shows schematic structure of the multilevel memory by the modification 2 of 1st Embodiment. It is a characteristic view for demonstrating the multi-value memory | storage in the multi-value memory by the modification 2 of 1st Embodiment. It is a characteristic view for demonstrating the other multi-value storage in the multi-value memory by the modification 2 of 1st Embodiment. It is a top view which shows schematic structure of MRAM by 2nd Embodiment. It is a schematic sectional drawing which shows the manufacturing method of MRAM by 2nd Embodiment to process order. It is a schematic sectional drawing which shows the manufacturing method of the magnetic memory element of MRAM by 2nd Embodiment to process order. FIG. 17 is a schematic cross-sectional view illustrating the method of manufacturing the magnetic memory element of the MRAM according to the second embodiment in the order of steps, following FIG.

  Hereinafter, specific embodiments of the magnetoresistive element and the magnetic memory device will be described in detail with reference to the drawings.

(First embodiment)
In the present embodiment, a structure of a multi-level memory is disclosed.
FIG. 1 is a schematic cross-sectional view showing a schematic configuration of the multilevel memory according to the first embodiment.

The multi-level memory 10A according to the present embodiment is formed on a predetermined lower electrode, for example, a lower electrode 11 made of Ta via a buffer layer 12.
The multi-level memory 10A includes a first MTJ 10a and a second MTJ 10b stacked on the first MTJ 10a via a connection electrode layer 13.

  The buffer layer 12 has a thickness of about 2 nm to 10 nm made of at least one selected from Ru, Pt, Rh, and Pd. In the present embodiment, for example, Ru is about 8 nm thick.

  The connection electrode layer 13 is formed by stacking Ru having a thickness of about 1 nm to 10 nm, Ta having a thickness of 0.2 nm to 1.5 nm, or the above Ru and Ta. In the present embodiment, the connection electrode layer 13 is made of Ru having a thickness of 5 nm, for example. The connection electrode layer 13 electrically connects the first MTJ 10a and the second MTJ 10b, and cuts off the magnetic interaction between the first upper magnetic layer 4a and the second lower magnetic layer 2b. Is.

The first MTJ 10a includes a first insertion layer 1a, a first lower magnetic layer 2a and a first upper magnetic layer 4a sandwiching the first tunnel barrier layer 3a on the first insertion layer 1a, And a first cap layer 5a formed on the first upper magnetic layer 4a.
The second MTJ 10b includes a second insertion layer 1b, a second lower magnetic layer 2b and a second upper magnetic layer 4b sandwiching the second tunnel barrier layer 3b on the second insertion layer 1b, And a second cap layer 5b formed on the second upper magnetic layer 4b.

  In the first MTJ 10a, both the first lower magnetic layer 2a and the first upper magnetic layer 4a have magnetic anisotropy in the direction perpendicular to the main surface. One of the first lower magnetic layer 2a and the first upper magnetic layer 4a is a fixed magnetic layer whose magnetization direction is fixed, and the other is a free magnetic layer whose magnetization direction can be changed. In the present embodiment, as will be described later, the first lower magnetization layer 2a is thinner than the first upper magnetization layer 4a, but the first lower magnetization layer is also coupled with the relationship with the first cap layer 5a. The layer 2a has a larger volume than the first upper magnetic layer 4a. Therefore, the first lower magnetic layer 2a is a fixed magnetic layer, and the first upper magnetic layer 4a is a free magnetic layer.

  In the second MTJ 10b, each of the second lower magnetic layer 2b and the second upper magnetic layer 4b has a magnetic anisotropy in a direction perpendicular to the main surface. One of the second lower magnetic layer 2b and the second upper magnetic layer 4b is a fixed magnetic layer whose magnetization direction is fixed, and the other is a free magnetic layer whose magnetization direction can be changed. In the present embodiment, as will be described later, the second lower magnetization layer 2b is thinner than the second upper magnetization layer 4b, but the second lower magnetization layer is also coupled with the relationship with the second cap layer 5b. The layer 2b has a larger volume than the second upper magnetic layer 4b. Therefore, the second lower magnetic layer 2b is a fixed magnetic layer, and the second upper magnetic layer 4b is a free magnetic layer.

  In the first MTJ 10a, the first insertion layer 1a is made of Ta and has a thickness of about 0.1 nm to 1.1 nm. If the thickness of the first insertion layer 1a is thinner than 0.1 nm, the first lower magnetic layer 2a cannot be made a sufficient perpendicular magnetic film. If the thickness of the first insertion layer 1a is thicker than 1.5 nm, it will be described later. Etching is extremely difficult, and considering the ease of etching, the upper limit of thickness is about 1.1 nm. Therefore, by forming the first insertion layer 1a with a thickness of about 0.1 nm to 1.1 nm, the desired etching can be performed, but the first lower magnetic layer 2a is surely made a perpendicular magnetic film. Can do. In the present embodiment, the first insertion layer 1a has a thickness close to the thinnest, for example, about 0.2 nm, which achieves reliable perpendicular magnetization of the first lower magnetization layer 2a, particularly considering the intended etching. It is formed.

  In the second MTJ 10b, the second insertion layer 1b is made of Ta and has a thickness of about 0.1 nm to 1.1 nm. If the thickness of the second insertion layer 1b is less than 0.1 nm, the second lower magnetic layer 2b cannot be made a sufficient perpendicular magnetic film. Etching is extremely difficult, and considering the ease of etching, the upper limit of thickness is about 1.1 nm. Therefore, by forming the second insertion layer 1b to a thickness of about 0.1 nm to 1.1 nm, the desired etching can be performed, but the second lower magnetization layer 2b is surely made a perpendicular magnetic film. Can do. In the present embodiment, the second insertion layer 1b has a thickness close to the thinnest, for example, about 0.2 nm, for achieving reliable perpendicular magnetization of the second lower magnetic layer 2b, particularly considering the intended etching. It is formed.

  The first lower magnetic layer 2a of the first MTJ 10a and the second lower magnetic layer 2b of the second MTJ 10b are made of CoFeB and have a thickness of about 0.9 nm to 1.1 nm. If the thickness of the first lower magnetic layer 2a and the second lower magnetic layer 2b is less than 0.8 nm, the first lower magnetic layer 2a and the second lower magnetic layer 2b do not become perpendicular magnetic films (referred to as interface perpendicular films), but are thicker than 1.1 nm. There is a possibility of becoming a horizontal magnetization film. Therefore, the thickness of the first lower magnetic layer 2a and the second lower magnetic layer 2b is about 0.8 nm to 1.1 nm, and the thickness is about 0.9 nm to 1.1 nm in consideration of the certainty of interface perpendicular magnetization. Preferably, it is formed, and in this embodiment, it is about 1 nm.

  The first upper magnetic layer 4a of the first MTJ 10a and the second upper magnetic layer 4b of the second MTJ 10b are made of CoFeB, taking into account the reliability of about 1.0 nm to 1.5 nm, and interface perpendicular magnetization. Thus, it is formed to a thickness of about 1.1 nm to 1.5 nm. The thickness ranges of the first upper magnetic layer 4a and the second upper magnetic layer 4b are defined for the same reason as the first lower magnetic layer 2a and the second lower magnetic layer 2b. However, the first upper magnetic layer 4a and the second upper magnetic layer 4b are formed in consideration of the etching of the first insertion layer 1a and the second insertion layer 1b as will be described later. And thicker than the second lower magnetic layer 2b.

  The first tunnel barrier layer 3a of the first MTJ 10a and the second tunnel barrier layer 3b of the second MTJ 10b are made of MgO and have a thickness of about 0.8 nm to 1.1 nm. In the present embodiment, as will be described later, the first tunnel barrier layer 3a is thicker than the second tunnel barrier layer 3b in order to secure a larger difference in resistance value between the first MTJ 10a and the second MTJ 10b. It may be formed. In the present embodiment, when the first tunnel barrier layer 3a and the second tunnel barrier layer 3b have the same thickness, both are formed to have a thickness of about 1.0 nm, for example. On the other hand, when the thicknesses are different, the first tunnel barrier layer 3a is formed with a thickness of about 0.97 nm, for example, and the second tunnel barrier layer 3b is formed with a thickness of about 1.0 nm, for example.

  In the first MTJ 10a, the first cap layer 5a is made of Ta and has a thickness of about 0.5 nm to 1.5 nm. If the thickness of the first cap layer 5a is less than 0.5 nm, there is no effect, and if it is thicker than 1.5 nm, reactive ion etching (RIE) becomes difficult. Therefore, the first cap layer 5a is preferably formed to a thickness of about 0.5 nm to 1.5 nm, and in this embodiment, the thickness is about 1 nm.

  In the second MTJ 10b, the second cap layer 5b is made of Ta and has a thickness of about 0.5 nm to 1.5 nm. If the thickness of the second cap layer 5b is less than 0.5 nm, there is no effect, and if it is thicker than 1.5 nm, RIE becomes difficult. Therefore, the second cap layer 5b is preferably formed to a thickness of about 0.5 nm to 1.5 nm, and in this embodiment, the thickness is about 1 nm.

A shape actually formed for the multi-level memory 10A according to the present embodiment is shown in FIG.
When forming the multi-value memory 10A, the second MTJ 10b to the connection electrode layer 13 and the first MTJ 10a are collectively processed by RIE using CO and NH ₃ or methanol as an etching gas. At this time, an etching residue in RIE occurs. In order to remove this etching residue by over-etching, the multi-level memory 10A is etched so that the side surfaces thereof are forward tapered as shown in FIG.

  The thickness of the first insertion layer 1a and the second insertion layer 1b is considered to be regulated to about 2 nm to 5 nm, for example, if the ease of etching is not taken into consideration. However, in this case, in the batch RIE described above, the etching rate of Ta is so slow that it functions as an etching stopper during the MTJ etching. Therefore, it takes a very long time to etch the first insertion layer 1a and the second insertion layer 1b made of Ta. Therefore, the lower magnetic layer, the upper magnetic layer, and the tunnel barrier layer are exposed to etching for a longer time than necessary and are damaged.

  In the present embodiment, the first insertion layer 1a and the second insertion layer 1b are formed as extremely thin films of about 0.1 nm to 1.1 nm. Therefore, the etching time can be kept short, and the intended batch etching can be performed without damaging the lower magnetic layer, the upper magnetic layer, and the tunnel barrier layer.

  In each MTJ (the first MTJ 10a and the second MTJ 10b) constituting the multi-level memory 10A, the lower magnetic layer and the upper magnetic layer have larger volumes functioning as fixed magnetic layers, and the smaller volumes have free magnetization. Acts as a layer. Normally, when processed by RIE, in this embodiment, the side surface of the multilevel memory 10A is formed in a forward tapered shape, so that the lower magnetic layer has a larger volume than the upper magnetic layer. That is, in the first MTJ 10a, the first lower magnetic layer 2a functions as a fixed magnetic layer, and the first upper magnetic layer 4a functions as a free magnetic layer. In the second MTJ 10b, the second lower magnetic layer 2b functions as a fixed magnetic layer, and the second upper magnetic layer 4b functions as a free magnetic layer.

The buffer layer 12 is used for the following reason.
As described above, an etching residue may adhere to the lower electrode 11 by RIE when forming the multi-level memory 10A. Therefore, when a current is passed through the multi-level memory 10A, the current leaks to the deposit on the lower electrode 11. In particular, the deposits attached to the side walls of the tunnel barrier layers 3a and 3b form, for example, a path that short-circuits the first lower magnetic layer 2a and the second upper magnetic layer 4b, thereby reducing the TMR effect and the STT effect. One of the causes. The buffer layer 12 is provided to avoid this. For example, the buffer layer 12 does not need to be formed if the etching residue at the time of RIE can be sufficiently removed by the over-etching.

In the multilevel memory according to the present embodiment, the technical significance of the Ta insertion layer disposed below the lower magnetic layer and the Ta cap layer disposed on the upper magnetic layer is compared with the comparative example in which no insertion layer is provided. This will be explained based on.
A saturation magnetic field perpendicular to the main surface was measured by VSM (Vibrating Sample Magnetometry) to evaluate the vertical component of CoFeB. The result is shown in FIG.

  As the sample A of the present embodiment, a structure in which Ru (8) / Ta (0.2) / CoFeB (t) / MgO (1) / Ta (5) was stacked in this order on a silicon substrate was used. As a sample B of the comparative example, a structure in which Ru (8) / CoFeB (t) / MgO (1) / Ta (5) was stacked in this order on a silicon substrate was used. Here, the number in parentheses is the film thickness, and the unit is nm. The film thickness t of CoFeB was changed from 0.8 nm to 1.5 nm.

Here, the vertical demagnetizing field H _dz and the saturated magnetic field Hs are the same. The effective demagnetizing field H _d _ _eff is
_{H d _ eff = H dz -H} kz
Therefore, a small Hs perpendicular to the main surface means that the magnetic anisotropy H _{kz in the} perpendicular direction is large. As shown in FIG. 3, the magnetic anisotropy is more vertical in the sample A in which Ta having a thickness of 0.2 nm is inserted between CoFeB and Ru than in the sample B in which only Ru is in contact with CoFeB. It turns out that it is easy.

FIG. 4 is a characteristic diagram showing a magnetization curve when the thickness of CoFeB is 1 nm in the sample A of FIG. FIG. 5 is a characteristic diagram showing a magnetization curve when the thickness of CoFeB is 1.1 nm in the sample A of FIG. 4 and 5, IP represents a saturation magnetic field in a direction parallel to the main surface, and OP represents a case where a saturation magnetic field in the direction perpendicular to the main surface is measured.
Sample B does not show vertical anisotropy, but sample A is excellent in squareness as shown in FIGS. 4 and 5, and it is understood that a vertical film is formed by interface vertical anisotropy.

  In the multilevel memory according to the present embodiment, the proper film thicknesses of the lower magnetic layer and the upper magnetic layer were examined. The experimental results are shown in FIGS. FIG. 6 is a characteristic diagram showing an MR loop measured by changing the thickness of the lower magnetic layer (CoFeB) of the MTJ. FIG. 7 is a characteristic diagram showing an MR loop measured by changing the thickness of the upper magnetic layer (CoFeB) of the MTJ. 6 and 7, (a), (b), (c) are MR loops perpendicular to the main surface of the magnetic layer, and (d), (e), (f) are main surfaces of the magnetic layer. Each of the horizontal MR loops is shown. FIG. 6 shows a case where (a) and (d) are 0.9 nm thick, (b) and (e) are 1.0 nm thick, and (c) and (f) are 1.1 nm thick, respectively. FIG. 7 shows a case where (a) and (d) have a thickness of 1.1 nm, (b) and (e) have a thickness of 1.3 nm, and (c) and (f) have a thickness of 1.5 nm, respectively.

  For the lower magnetized layer, the magnetic anisotropy in the perpendicular direction was exhibited with CoFeB of 0.9 nm to 1.1 nm. As for the upper magnetic layer, the magnetic anisotropy in the perpendicular direction was exhibited with CoFeB of 1.1 nm to 1.5 nm. The thickness of the upper magnetic layer showing the magnetic anisotropy in the vertical direction is thicker than the thickness of the lower magnetic layer showing the magnetic anisotropy in the vertical direction. This is because, in the case of the upper magnetic layer, Ta of the cap layer formed thereon diffuses into CoFeB, and a portion that does not function as a magnetic film (a so-called dead layer) exists on the surface layer.

In the multilevel memory according to the present embodiment, multilevel storage is possible as follows. FIG. 8 is a characteristic diagram for explaining multilevel storage in the multilevel memory according to the first embodiment.
As shown in FIG. 2, the multi-level memory 10A has a side surface formed in a forward tapered shape, so that the first MTJ 10a is larger in size than the second MTJ 10b. Therefore, as shown in FIG. 8A, the switching current I _c1 of the first MTJ (MTJ1) is larger than the switching current I _c2 of the second MTJ (MTJ2). The area resistance (R _A1 ) of the first MTJ is smaller than the area resistance (R _A2 ) of the second MTJ. Therefore, as shown in FIG. 8B, it is possible to take four values (1, 1), (1, 0), (0, 1), (0, 0) as stored values.

Here, in the multilevel memory according to the present embodiment, the first tunnel barrier layer of the first MTJ and the second tunnel barrier layer of the second MTJ may be formed to have different thicknesses.
For example, the first tunnel barrier layer of the first MTJ is formed thicker than the second tunnel barrier layer of the second MTJ. As a result, the difference between the area resistance of the first MTJ and the area resistance of the second MTJ is further increased, and reliable multi-value storage is realized. In addition, when the taper angle of the side surface of the multi-level memory is small and the above difference in sheet resistance cannot be sufficiently secured due to the taper angle, the first tunnel barrier layer should be formed thicker than the second tunnel barrier layer. Thus, the difference in sheet resistance can be compensated.

  As described above, according to the present embodiment, the MTJs 10a and 10b having the interface magnetization film as the fixed magnetization layer and the free magnetization layer are stacked to reliably realize the desired multi-value without damage in the etching process. A multi-value memory 10A with high reliability that can be realized is realized.

(Modification)
Hereinafter, various modifications of the present embodiment will be described. Note that the same components as those of the multi-level memory according to the present embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

-Modification 1-
FIG. 9 is a schematic cross-sectional view showing a schematic configuration of a multilevel memory according to Modification 1 of the first embodiment.
The multi-level memory 10B according to this example is formed on the lower electrode 11 via the buffer layer 12, and the second MTJ 10c and the second MTJ 10c stacked on the first MTJ 10c via the connection electrode layer 13 are formed. MTJ10d. Similarly to the multi-value memory 10A according to the present embodiment, the multi-value memory 10B is also formed by batch etching by RIE so that the side surfaces thereof are forward tapered.

  Similar to the first MTJ 10a in the present embodiment, the first MTJ 10c includes the first insertion layer 1a, the first lower magnetic layer 2a, the first tunnel barrier layer 3a, the first upper magnetic layer 4a, the first MTJ 10a, and the first MTJ 10a. 1 cap layer 5a. However, the first upper magnetic layer 4a is formed to a thickness of about 1 nm, for example. In this example, a so-called material perpendicular magnetization film (with its own thickness or insertion layer) is interposed between the first upper magnetization layer 4a and the first cap layer 5a so as to be in contact with the upper surface of the first upper magnetization layer 4a. Irrespectively, a film exhibiting perpendicular magnetization is hereinafter referred to as this), and a perpendicular magnetization layer 6a is provided.

  Similarly to the second MTJ 10b in the present embodiment, the second MTJ 10d includes the second insertion layer 1b, the second lower magnetic layer 2b, the second tunnel barrier layer 3b, the second upper magnetic layer 4b, Two cap layers 5b are provided. However, the second upper magnetic layer 4b is formed with a thickness of about 1 nm, for example. In this example, a perpendicular magnetic layer 6b which is a material perpendicular magnetic film is provided between the second upper magnetic layer 4b and the second cap layer 5b so as to be in contact with the upper surface of the second upper magnetic layer 4b. ing.

  The perpendicular magnetization layers 6a and 6b are formed of an alloy containing either Co or Fe and either Pt or Pd, or a multilayer system containing either Co or Fe and either Pt or Pd, or Co and Ni. Is a multi-layered perpendicular magnetic film containing about 0.5 nm to 10 nm. Ta or Ru having a thickness of about 0.1 nm to 1 nm between the first upper magnetic layer 4a and the first cap layer 5a and between the second upper magnetic layer 4b and the second cap layer 5b. Alternatively, these laminated films may be inserted.

In the first MTJ 10c, by arranging the perpendicular magnetic layer 6a, the first upper magnetic layer 4a becomes a fixed magnetic layer, and accordingly, the first lower magnetic layer 2a becomes a free magnetic layer (so-called Top-pin). Construction).
In the second MTJ 10d, by arranging the perpendicular magnetic layer 6b, the second upper magnetic layer 4b becomes a fixed magnetic layer, and accordingly, the second lower magnetic layer 2b becomes a free magnetic layer (Top-pin structure). ).

As described above, by defining the fixed magnetization layer and the free magnetization layer, switching from the parallel writing (P) to the anti-parallel writing (AP) becomes easy, and the control of the driving transistor in the memory cell of the MRAM is easy. It becomes.
That is, when the fixed magnetization layer is under the tunnel barrier layer, the anti-parallel write current Ic ₋ is larger than the parallel write current (Ic ₊ ). This is because when a memory cell is operated in combination with a driving transistor (1T-1MTJ), the voltage decreases due to a variable resistance during anti-parallel writing with respect to the MTJ of an anti-parallel writing spin injection type MRAM, and the variable resistance A larger write current was required than during parallel writing, which was not affected. In other words, the anti-parallel writing that requires a large current is required at the lower current driving capability of the driving transistor, and the driving transistor is required to ensure a large writing current even when the current driving capability is low. There was a need to increase the size.
When the magnetization fixed layer is on the tunnel barrier, the RI loop is in the reverse state, and Ic ₊ > Ic ₋ , so that the operation of 1T-1MTJ can be performed easily and reliably.

In the multi-value memory according to this example, multi-value storage can be performed as follows, as in the present embodiment. FIG. 10 is a characteristic diagram for explaining the multi-value storage in the multi-value memory according to the first modification of the first embodiment.
Since the side surface of the multilevel memory 10A is formed in a forward tapered shape, the first MTJ 10c is larger in size than the second MTJ 10d. Therefore, as shown in FIG. 10A, the switching current I _c1 of the first MTJ (MTJ1) is larger than the switching current I _c2 of the second MTJ (MTJ2). The area resistance (R _A1 ) of the first MTJ is smaller than the area resistance (R _A2 ) of the second MTJ. Therefore, as shown in FIG. 10B, four values (1, 1), (1, 0), (0, 1), (0, 0) can be taken as stored values.

  As described above, according to this example, the MTJs 10c and 10d having the interface magnetization film as the fixed magnetization layer and the free magnetization layer are stacked, and the desired multi-value without damage in the etching process can be reliably realized. A highly reliable multi-value memory 10B that can be implemented is realized.

-Modification 2-
FIG. 11 is a schematic cross-sectional view showing a schematic configuration of a multilevel memory according to Modification 2 of the first embodiment.
The multilevel memory 10C according to this example is formed on the lower electrode 11 via the buffer layer 12, and the second MTJ 10c and the second MTJ 10c stacked on the first MTJ 10c via the connection electrode layer 13 are formed. MTJ10b. Similarly to the multi-value memory 10A according to the present embodiment, the multi-value memory 10C is also formed by batch etching by RIE so that the side surfaces thereof are forward tapered.

The first MTJ 10c is the same as the first MTJ 10c in the first modification.
The second MTJ 10b is the same as the second MTJ 10b in the present embodiment, but the second upper magnetic layer 4b is formed with a thickness of about 1 nm, for example.

In the first MTJ 10c, by arranging the perpendicular magnetization layer 6a, the first upper magnetization layer 4a becomes a fixed magnetization layer, and accordingly, the first lower magnetization layer 2a becomes a free magnetization layer (Top-pin structure). ).
In the second MTJ 10b, the second lower magnetic layer 2b becomes a fixed magnetic layer and the second upper magnetic layer 4b becomes a free magnetic layer due to the above-described forward tapered side shape (so-called Bottom-). pin structure).

As described above, by defining the fixed magnetic layer and the free magnetic layer of the first MTJ 10c, switching from parallel writing (P) to anti-parallel writing (AP) is facilitated, and driving in the memory cell of the MRAM is performed. Control of the transistor becomes easy.
In addition, since the first MTJ 10c has a top-pin structure and the second MTJ 10b has a bottom-pin structure, the first lower magnetic layer 2a, which is a free magnetic layer, and the second MTJ 10b are stacked in the stacked structure of the multilevel memory 10C. The upper magnetic layer 4b is separated as much as possible. In the multilevel memory, the difference in the write current I _c between the first MTJ and the second MTJ is largely due to the difference in the area of the free magnetic layer. In this example, the multilevel memory 10C has a tapered side surface shape, and therefore, the area difference between the first lower magnetic layer 2a and the second upper magnetic layer 4b is large in the stacked structure. Therefore, in the multi-level memory 10C, more reliable multi-level processing is possible.

In the multi-value memory according to this example, multi-value storage can be performed as follows, as in the present embodiment. FIG. 12 is a characteristic diagram for explaining multi-value storage in the multi-value memory according to the second modification of the first embodiment.
In the multilevel memory 10C, as shown in FIG. 12A, the first MTJ 10c having the Top-pin structure is shifted to the positive bias side, and the second MTJ 10b having the Bottom-pin structure is shifted to the negative bias side. There is a shift. When both are overlapped, as shown in FIG. 12B, it is possible to take, for example, four values (1, 0), (0, 1), (0, 0) as stored values.

FIG. 13 is a characteristic diagram for explaining another multi-value storage in the multi-value memory according to the second modification of the first embodiment.
As shown in FIG. 13A, a difference is made between the write current Ic and the sheet resistance R _A of the first MTJ 10c and the second MTJ 10b. As a result, as shown in FIG. 13B, the stored values of four or more values (here, (1, 1), (1, 0), (0, 1), (0, 0)) are stored. It is possible.

  As described above, according to this example, the MTJs 10c and 10b having the interface magnetization film as the fixed magnetization layer and the free magnetization layer are stacked, and the desired multi-value without damage in the etching process can be reliably realized. A highly reliable multi-valued memory 10C that can be implemented is realized.

(Second Embodiment)
In the present embodiment, an MRAM including a multilevel memory according to the first embodiment or various modifications is disclosed. The structure of the MRAM will be described together with its manufacturing method. In addition, the same code | symbol is attached | subjected about the structural member etc. which are the same as 1st Embodiment.

  As shown in FIG. 14, the MRAM according to the present embodiment has a plurality of memory cells MC arranged in a matrix. In each memory cell MC arranged in the column direction, the gate electrode 24 is common, and each gate electrode 24 functions as a word line. Thus, instead of making the gate electrode 24 common to each column, a word line for electrically connecting the gate electrode 24 of each memory cell MC to each column may be provided separately. The bit lines 33 are common to the memory cells MC arranged in the row direction. The word line and the bit line 33 are insulated from each other and intersect with each other.

  15 to 17 are schematic views showing the MRAM manufacturing method according to the present embodiment in the order of steps. Here, a case where a memory cell including the multi-level memory 10A shown in the first embodiment is formed is illustrated. The present invention can also be applied to the case where the multilevel memory 10B of the first modification and the multilevel memory 10C of the second modification are formed.

First, as shown in FIG. 15A, a MOS transistor functioning as a drive transistor is formed on the silicon substrate 20 in the memory cell region.
Specifically, the element isolation structure 21 is formed on the surface layer of the silicon substrate 20 by, for example, STI (Shallow Trench Isolation) method to determine the element active region.
Next, an impurity, here boron (B ⁺ ), is ion-implanted into the element active region under conditions of a dose amount of 3.0 × 10 ¹³ / cm ² and an acceleration energy of 300 keV to form the well 22.

  Next, a thin gate insulating film 23 is formed in the element active region by thermal oxidation or the like, a polycrystalline silicon film is deposited on the gate insulating film 23 by a CVD method, and the polycrystalline silicon film and the gate insulating film 23 are formed by lithography and the same. The gate electrode 24 is patterned on the gate insulating film 23 by processing into an electrode shape by subsequent dry etching.

Next, an impurity, here arsenic (As ⁺ ), which is an n-type impurity, is ion-implanted into the active region using the gate electrode 24 as a mask. As a result, impurity diffusion regions 25 functioning as source / drains are formed on both sides of the gate electrode 24 in the element active region.
As the impurity diffusion region 25, after forming a shallow LDD region (extension region), a source / drain may be formed so as to partially overlap this.
Thus, a MOS transistor that functions as a selection transistor in each memory cell is formed.

Subsequently, as shown in FIG. 15B, after forming an interlayer insulating film 26 covering the MOS transistor, contact plugs 27 and 28 electrically connected to the impurity diffusion region 25 of the MOS transistor are formed.
Specifically, for example, silicon oxide is deposited by CVD so as to cover the MOS transistor, and the surface of the silicon oxide is planarized by, for example, chemical mechanical polishing (CMP). Thereby, the interlayer insulating film 26 is formed.

The interlayer insulating film 26 is processed by lithography and subsequent dry etching until a part of the surface of the impurity diffusion region 25 is exposed. As a result, contact holes 26 a and 26 b are formed in the interlayer insulating film 26.
For example, a Ti film and a TiN film are sequentially deposited by sputtering so as to cover the inner wall surfaces of the contact holes 26a and 26b, thereby forming a base film (glue film) (not shown). Then, for example, a W film is deposited so as to fill the contact holes 26a and 26b through the glue film by the CVD method. Thereafter, the W film and the glue film are polished by CMP using the interlayer insulating film 26 as a stopper. Thus, the contact plugs 27 and 28 are formed at the same time so as to fill the contact holes 26a and 26b with W through the glue film.

Subsequently, as shown in FIG. 15C, the wiring 34, the magnetic memory element 30 including the multilevel memory 10A disclosed in the first embodiment, and the like are formed.
A method for manufacturing the magnetic memory element 30 will be described with reference to FIGS. Here, only the magnetic memory element 30 and its peripheral part are shown enlarged.

  A wiring material, for example, an Al alloy is deposited on the interlayer insulating film 26 by a sputtering method or the like, and the Al alloy is processed by lithography and dry etching. Thereby, the wiring 34 electrically connected to the contact plug 27 is formed.

As shown in FIG. 16A, an electrode layer 40, a buffer layer 41, a multi-level memory layer 42, and a hard mask 43 are continuously formed on the interlayer insulating film 26 by, for example, sputtering.
The electrode layer 40 is formed to a thickness of about 20 nm using, for example, Ru as a conductive material.
The buffer layer 41 is formed to a thickness of about 8 nm using, for example, Ru.

For example, the multi-level memory layer 42 has Ta of about 0.2 nm, CoFeB of about 1 nm, MgO of about 0.97 nm, CoFeB of about 1.2 nm, Ta of about 1 nm, Ru of about 5 nm, and Ta of about 0.2 nm. Then, CoFeB is sequentially deposited to about 1 nm, MgO to about 1.0 nm, CoFeB to about 1.2 nm, and Ta to about 1 nm. Thereby, for example, in FIG. 1, the first insertion layer 1a, the first lower magnetic layer 2a, the first tunnel barrier layer 3a, the first upper magnetic layer 4a, the first cap layer 5a, and the connection electrode layer 13 are provided. A multivalued structure in which the second insertion layer 1b, the second lower magnetic layer 2b, the second tunnel barrier layer 3b, the second upper magnetic layer 4b, and the second cap layer 5b are sequentially stacked. A memory layer 42 is formed.
The hard mask 43 is made of, for example, Ta and has a thickness of about 50 nm.

As shown in FIG. 16B, a resist mask 44 is formed.
Specifically, a resist is applied on the hard mask 43, and the resist is processed by lithography. Thereby, a resist mask 44 is formed.

As shown in FIG. 16C, the hard mask 43 is processed.
Specifically, using the resist mask 44, the hard mask 43 is dry etched by reactive ion etching (RIE) using Cl gas, CF ₄ gas or the like as an etching gas. Thereby, the hard mask 43 is processed following the shape of the resist mask 44.
The resist mask 44 is removed by ashing or the like.

As shown in FIG. 16D, the multilevel memory layer 42 and the buffer layer 41 are processed to form the multilevel memory 10A.
Specifically, the multi-value memory layer 42 and the buffer layer 41 are dry-etched by RIE using the hard mask 43 and CO gas + NH ₃ gas or the like as an etching gas. Thereby, the multi-value memory layer 42 and the buffer layer 41 are processed following the shape of the hard mask 43, and the multi-value memory 10 </ b> A via the buffer layer 12 is formed on the electrode layer 40.
The hard mask 43 on the multi-level memory 10A becomes a part of the upper electrode of the multi-level memory 10A.

As shown in FIG. 17A, a resist mask 45 is formed.
Specifically, a resist is applied on the electrode layer 40 so as to cover the multilevel memory 10A and the buffer layer 12, and the resist is processed by lithography. Thereby, a resist mask 45 is formed.

As shown in FIG. 17B, the electrode layer 40 is processed.
Specifically, the electrode layer 40 is dry etched using the resist mask 45. Thereby, the electrode film 41 is processed following the shape of the resist mask 45, and the lower electrode 11 is formed. The lower electrode 11 is electrically connected to the contact plug 28 on its lower surface.
The resist mask 45 is removed by ashing or the like.
As described above, the magnetic memory element 30 including the multi-level memory 10 </ b> A is formed on the lower electrode 11 via the buffer layer 12.

As shown in FIG. 17C, an interlayer insulating film 29 is formed.
Specifically, for example, silicon oxide is deposited by CVD so as to cover the wiring 34 and the magnetic memory element 30 in FIG. 17C, and the surface of the silicon oxide is planarized by CMP, for example. Thereby, an interlayer insulating film 29 is formed.

As shown in FIG. 17D, the via plug 32 is formed.
Specifically, the interlayer insulating film 29 is processed by lithography and subsequent dry etching until a part of the surface of the multilevel memory 10A is exposed. As a result, a via hole 29 a is formed in the interlayer insulating film 29.
For example, a Ti film and a TiN film are sequentially deposited by a sputtering method so as to cover the inner wall surface of the via hole 29a to form a base film (glue film) (not shown). Then, for example, a W film is deposited so as to fill the via hole 29a through the glue film by the CVD method. Thereafter, the W film and the glue film are polished by CMP using the interlayer insulating film 29 as a stopper. As a result, the via plug 32 that fills the via hole 29a with W via the glue film is formed.

  Then, as shown in FIG. 15C, a wiring material, for example, an Al alloy is deposited on the interlayer insulating film 29 by a sputtering method or the like, and the Al alloy is processed by lithography and dry etching. Thereby, the bit line 33 electrically connected to the via plug 32 is formed.

  In this embodiment, the case where a memory cell including the multi-value memory 10A disclosed in the first embodiment is formed is exemplified. However, the multi-value memory 10B disclosed in the first modification or the second modification is disclosed. The present invention can be similarly applied when forming a memory cell including the multilevel memory 10C.

  As described above, according to the present embodiment, the multi-level memory 10A according to the first embodiment is applied to the magnetic memory element 30, and the MRAM is configured so that the interface magnetization film becomes the fixed magnetization layer and the free magnetization. MTJs 10a and 10b included as layers are stacked, and a highly reliable MRAM that can surely realize the desired multi-value without damage in the etching process is realized.

  Hereinafter, various aspects of the magnetoresistive element and the magnetic memory device will be collectively described as additional notes.

(Supplementary note 1) a first memory structure;
A second memory structure provided above the first memory structure;
A connection layer provided between the first memory structure and the second memory structure;
The first memory structure and the second memory structure are respectively
An insertion layer made of Ta;
A lower magnetic layer in contact with the insertion layer on the insertion layer and having a magnetic anisotropy perpendicular to a main surface;
An upper magnetic layer having magnetic anisotropy perpendicular to the main surface;
A tunnel barrier layer provided between the lower magnetic layer and the upper magnetic layer,
One of the lower magnetic layer and the upper magnetic layer is a fixed magnetic layer, and the other is a free magnetic layer.

  (Supplementary note 2) The magnetoresistive element according to supplementary note 1, wherein the insertion layer has a thickness in a range of 0.1 nm to 1.0 nm.

  (Supplementary note 3) The magnetoresistive element according to Supplementary note 1 or 2, wherein the lower magnetic layer has a thickness in a range of 0.8 nm to 1.1 nm.

  (Supplementary Note 4) The first memory structure and the second memory structure each further include a cap layer made of Ta in contact with the upper magnetic layer on the upper magnetic layer. 4. The magnetoresistive element according to any one of items 3.

  (Supplementary note 5) The magnetoresistive element according to supplementary note 4, wherein the upper magnetic layer has a thickness in a range of 1.0 nm to 1.5 nm.

  (Supplementary note 6) Any one of Supplementary notes 1 to 5, wherein the laminated structure has a tapered side surface, and the size of the second memory structure is larger than the size of the first memory structure. 2. The magnetoresistive element according to item 1.

  (Appendix 7) In any one of appendices 1 to 6, the tunnel barrier layer of the first memory structure has a smaller area and a larger area than the tunnel barrier layer of the second memory structure. The magnetoresistive element as described.

(Supplementary Note 8) Each of the first memory structure and the second memory structure has a perpendicular magnetic layer on the upper magnetic layer and in contact with the upper magnetic layer,
The first memory structure and the second memory structure, respectively, wherein the lower magnetic layer is a free magnetic layer, and the upper magnetic layer is a fixed magnetic layer together with the perpendicular magnetic layer, respectively. The magnetoresistive element of any one of -7.

(Supplementary note 9) The first memory structure has a perpendicular magnetic layer on the upper magnetic layer and in contact with the upper magnetic layer,
In the first memory structure, the lower magnetic layer is a free magnetic layer, the upper magnetic layer is a fixed magnetic layer together with the perpendicular magnetic layer, and
8. The magnetoresistive element according to any one of appendices 1 to 7, wherein in the second memory structure, the lower magnetic layer is a fixed magnetic layer, and the upper magnetic layer is a free magnetic layer.

(Supplementary Note 10) A magnetic storage device in which a plurality of memory cells each including a magnetoresistive element and a drive transistor are arranged,
The magnetoresistive element is
A first memory structure;
A second memory structure provided above the first memory structure;
A connection layer provided between the first memory structure and the second memory structure;
The first memory structure and the second memory structure are respectively
An insertion layer made of Ta;
A lower magnetic layer in contact with the insertion layer on the insertion layer and having a magnetic anisotropy perpendicular to a main surface;
An upper magnetic layer having magnetic anisotropy perpendicular to the main surface;
A tunnel barrier layer provided between the lower magnetic layer and the upper magnetic layer,
One of the lower magnetic layer and the upper magnetic layer is a fixed magnetic layer, and the other is a free magnetic layer.

  (Supplementary note 11) The magnetic storage device according to supplementary note 10, wherein the insertion layer has a thickness in a range of 0.1 nm to 1.0 nm.

  (Supplementary note 12) The magnetic storage device according to supplementary note 10 or 11, wherein the lower magnetic layer has a thickness in a range of 0.8 nm to 1.1 nm.

  (Additional remark 13) Each of the first memory structure and the second memory structure further includes a cap layer made of Ta in contact with the upper magnetic layer on the upper magnetic layer. 13. The magnetic storage device according to any one of items 12.

  (Supplementary note 14) The magnetic memory device according to supplementary note 13, wherein the upper magnetic layer has a thickness in a range of 1.0 nm to 1.5 nm.

  (Supplementary Note 15) The supplementary note is characterized in that the magnetoresistive element has a tapered side surface, and has a stacked structure in which the size of the second memory structure is larger than the size of the first memory structure. The magnetic storage device according to any one of 10 to 14.

  (Supplementary note 16) In any one of Supplementary notes 10 to 15, wherein the tunnel barrier layer of the first memory structure has a smaller area and a larger area than the tunnel barrier layer of the second memory structure. The magnetic storage device described.

(Supplementary Note 17) Each of the first memory structure and the second memory structure has a perpendicular magnetic layer in contact with the upper magnetic layer on the upper magnetic layer,
Supplementary note 10 in each of the first memory structure and the second memory structure, wherein the lower magnetic layer is a free magnetic layer, and the upper magnetic layer is a fixed magnetic layer together with the perpendicular magnetic layer. The magnetic storage device according to any one of -16.

(Supplementary Note 18) The first memory structure has a perpendicular magnetic layer on the upper magnetic layer and in contact with the upper magnetic layer,
In the first memory structure, the lower magnetic layer is a free magnetic layer, the upper magnetic layer is a fixed magnetic layer together with the perpendicular magnetic layer, and
17. The magnetic memory device according to any one of appendices 10 to 16, wherein, in the second memory structure, the lower magnetic layer is a fixed magnetic layer, and the upper magnetic layer is a free magnetic layer.

1a 1st insertion layer 2a 1st lower magnetization layer 3a 1st tunnel barrier layer 4a 1st upper magnetization layer 5a 1st cap layer 6a, 6b perpendicular magnetization layer 1b 2nd insertion layer 2b 2nd lower part Magnetized layer 3b Second tunnel barrier layer 4b Second upper magnetized layer 5b Second cap layers 10A, 10B, 10C Multilevel memories 10a, 10c First MTJ
10b, 10d Second MTJ
11 Lower electrode 12 Buffer layer 13 Connection electrode layer 20 Silicon substrate 21 Device isolation structure 22 Well 23 Gate insulating film 24 Gate electrode 25 Impurity diffusion regions 26 and 29 Interlayer insulating films 26a and 26b Contact holes 27 and 28 Contact plugs 29a Via holes 32 Via plug 30 Magnetic memory element 33 Bit line 34 Wiring 40 Electrode layer 42 Multi-level memory layer 43 Hard mask 44, 45 Resist mask

Claims (10)

A first memory structure;
A second memory structure provided above the first memory structure;
A connection layer provided between the first memory structure and the second memory structure;
The first memory structure and the second memory structure are respectively
An insertion layer made of Ta;
A lower magnetic layer in contact with the insertion layer on the insertion layer and having a magnetic anisotropy perpendicular to a main surface;
An upper magnetic layer having magnetic anisotropy perpendicular to the main surface;
A tunnel barrier layer provided between the lower magnetic layer and the upper magnetic layer,
One of the lower magnetic layer and the upper magnetic layer is a fixed magnetic layer, and the other is a free magnetic layer.   2. The magnetoresistive element according to claim 1, wherein the insertion layer has a thickness in a range of 0.1 nm to 1.0 nm.   The magnetoresistive element according to claim 1, wherein the lower magnetic layer has a thickness in a range of 0.8 nm to 1.1 nm.   The first memory structure and the second memory structure each further include a cap layer made of Ta in contact with the upper magnetic layer on the upper magnetic layer. 2. The magnetoresistive element according to item 1.   The magnetoresistive element according to claim 4, wherein the upper magnetic layer has a thickness in a range of 1.0 nm to 1.5 nm.   6. The stacked structure according to claim 1, wherein the stacked structure has a tapered side surface, and the size of the second memory structure is larger than the size of the first memory structure. The magnetoresistive element as described. The first memory structure and the second memory structure each have a perpendicular magnetic layer on the upper magnetic layer and in contact with the upper magnetic layer,
2. The first memory structure and the second memory structure, respectively, wherein the lower magnetic layer is a free magnetic layer, and the upper magnetic layer is a fixed magnetic layer together with the perpendicular magnetic layer. The magnetoresistive element of any one of 1-6. The first memory structure has a perpendicular magnetic layer on the upper magnetic layer and in contact with the upper magnetic layer,
In the first memory structure, the lower magnetic layer is a free magnetic layer, the upper magnetic layer is a fixed magnetic layer together with the perpendicular magnetic layer, and
The magnetoresistive element according to claim 1, wherein in the second memory structure, the lower magnetic layer is a fixed magnetic layer, and the upper magnetic layer is a free magnetic layer. . A magnetic storage device in which a plurality of memory cells each including a magnetoresistive element and a drive transistor are arranged,
The magnetoresistive element is
A first memory structure;
A second memory structure provided above the first memory structure;
A connection layer provided between the first memory structure and the second memory structure;
The first memory structure and the second memory structure are respectively
An insertion layer made of Ta;
A lower magnetic layer in contact with the insertion layer on the insertion layer and having a magnetic anisotropy perpendicular to a main surface;
An upper magnetic layer having magnetic anisotropy perpendicular to the main surface;
A tunnel barrier layer provided between the lower magnetic layer and the upper magnetic layer,
One of the lower magnetic layer and the upper magnetic layer is a fixed magnetic layer, and the other is a free magnetic layer.   The magnetic storage device according to claim 9, wherein the insertion layer has a thickness in a range of 0.1 nm to 1.0 nm.

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