JP2013051495A - Signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing device using a plurality of AD converters to AD-convert the same analog signal which suppresses a reduction in AD conversion precision of the same analog signal due to characteristic variations of the individual AD converters.SOLUTION: A clock generation section 58 generates two clocks different in π[rad] phase, and a target signal supply section 52 supplies either a received signal RS or 0 V to two AD converters 72, 74 of an AD conversion section 68. A correctable data generation section 86 generates readout data RD on the basis of AD conversion results of the received signal RS in the AD conversion section 68. An offset data generation section 76 generates offset data AZ1, AZ2 indicating respective measurement errors of the AD converters 72, 74 on the basis of AD conversion results of the reference voltage in the AD conversion section 68. A correction section 100 executes a corrective process of removing the offset data AZ1, AZ2 from the readout data RD to generate sampling data SD.

Description

  The present invention relates to a signal processing device, and more particularly to a signal processing device that performs AD conversion of the same analog signal by a plurality of AD converters.

  Conventionally, as a method for realizing high-speed AD conversion, a method of sampling the same analog signal by two AD converters is known. As a signal processing apparatus using such a method, for example, as shown in FIG. 9, two AD converters ADC1 and ADC2 are driven by clocks having a phase difference of 180 °, and the respective AD conversion results are converted to ADC1, ADC2, There are some that output alternately in the order of ADC1, ADC2,... (Hereinafter referred to as double speed sampling). In such an apparatus, an output result similar to that obtained by sampling with a clock twice as fast as the clock sampled by the AD converter can be obtained, and the AD result can be obtained at a speed higher than the operation upper limit speed of each AD converter. Conversion can be realized (see Patent Document 1).

JP 2008-32498 A

However, the apparatus is configured on the assumption that the characteristics of the two AD converters, ADC1 and ADC2, are the same.
However, even if the AD converter has the same product number, it has slightly different characteristics for each package, and even if the same analog signal is input, the output result of the AD conversion is not necessarily the same value. Not necessarily.

  For example, when 0V is input to the AD converter, it is ideal that 0 is output as the AD conversion result. In fact, in many cases, a value deviated from 0 is output as the AD conversion result. The Hereinafter, when 0 V is input to the AD converter, an AD conversion result that is actually output with a deviation from 0 that is output in an ideal case is referred to as zero point offset data.

Here, FIG. 10 is a graph illustrating output characteristics (input voltage vs. AD conversion result) of the AD converter under a constant temperature condition.
In FIG. 10, the solid line indicates the output characteristics when the zero point offset data varies on the minus side, and here, the output characteristics of the ADC 1 are illustrated. A broken line indicates the output characteristic when the zero point offset data varies on the plus side, and here, it indicates the output characteristic of the ADC 2.

  The zero point offset data is a value (AD conversion result when the input voltage is 0V) indicated by the graph indicated by the solid line or the dotted line at the intersection with the vertical axis in the figure. Strictly speaking, such zero point offset data also varies depending on the temperature. However, since the temperature fluctuation of the zero point offset data is a slow fluctuation compared with the time required for AD conversion of the waveform, the zero point offset data is described as a constant value here.

  FIG. 11A shows the obtained AD conversion result and the target of AD conversion by performing double-speed sampling of the same analog signal using ADC1 and ADC2 having such characteristics as in the prior art. It is explanatory drawing which overlapped and showed the waveform (original waveform) of the analog signal. In the figure, the AD conversion result of ADC1 is indicated by a white circle, and the AD conversion result of ADC2 is indicated by a black circle.

  As shown in FIG. 11A, due to the influence of the zero point offset data, the ADC 1 AD conversion result is shifted to the minus side of the original waveform shown by the solid line in the figure, that is, the lower side in the figure, and the ADC 2 AD conversion result is , Deviates from the original waveform to the plus side, that is, the upper side in the figure.

FIG. 11B shows a waveform obtained by arranging the AD conversion results of ADC1 and ADC2 in the order of acquisition and connecting them with a straight line (broken line).
As shown in FIG. 11B, it can be seen that the waveform obtained from the AD conversion result generates a downward convex or upward convex pseudo peak that did not exist in the original waveform.

If an operation for obtaining the center of the peak from the waveform shape is performed on such a waveform (see, for example, paragraphs “0080” to “0083” of Patent Document 1), there is a possibility that a correct result cannot be obtained.
In other words, the configuration disclosed in Patent Document 1 is established in an ideal case in which the characteristics of the two AD converters coincide with each other, and deviations between individual characteristics that actually occur are considered. Not.

  The present invention has been made to solve the above-described problem, and in a signal processing apparatus that performs AD conversion of the same analog signal using a plurality of AD converters in order to obtain high resolution, each AD converter is provided. It is an object of the present invention to suppress a decrease in AD conversion accuracy of the same analog signal caused by variations in characteristics of the.

  In the signal processing apparatus according to claim 1, which is an invention made to achieve the above object, the AD conversion means comprises n AD converters. These n AD converters AD-convert the same target signal set in advance according to any one of multi-layer clocks composed of n clocks used for AD conversion sampling. The n clocks are different in phase by 2π / n (n is an integer of 2 or more) at the same frequency.

Here, the target signal supplied from the target signal supply unit to the AD conversion unit is either a predetermined reference voltage or an analog signal to be subjected to AD conversion.
Then, offset data is generated by the offset data generation unit according to the reference voltage conversion result as the conversion result of the AD conversion unit acquired when the target signal is the reference voltage. The offset data is generated for each AD converter and represents a deviation amount of the reference voltage conversion result with respect to the reference AD conversion value associated with the reference voltage.

  For example, when 0V is input to the AD converter, and 0 is ideally output as a result of AD conversion, 0V is referred to as a reference voltage, and 0, which is an ideal output in this case with respect to 0V, is set as a reference AD. This is called a converted value. Actually, characteristics vary among individual AD converters, so even if 0V is input, a value deviated from 0 is output as a reference voltage conversion result. The amount of deviation is offset data.

  Further, in the correction means, the conversion result in the AD conversion means acquired when the target signal is an analog signal is used as an analog signal conversion result, and the AD converter is based on the analog signal conversion result in the AD converter for each AD converter. The data obtained by removing the offset data from the AD converter for each sampling point from the corrected data is output as an AD conversion result.

The reference voltage conversion result and offset data referred to here are data (values), and the analog signal conversion result and AD conversion result are data strings.
In the signal processing device configured as described above, when the offset data is calculated for each AD converter from the result of AD conversion of the reference voltage, and when the offset data is removed from the result of AD conversion of the analog signal, all Instead of using uniform offset data for each conversion value, different offset data is used for each AD converter. Therefore, the influence of AD converter characteristics (offset data) on AD conversion results. Can be removed.

  As a result, the waveform represented by the output results of the plurality of AD converters is a waveform closer to the original analog signal. Therefore, in the signal processing apparatus of the present invention, even when the same analog signal is AD converted by a plurality of AD converters, the accuracy of the AD conversion result is reduced due to variations in characteristics of the individual AD converters. Can be suppressed.

  Here, as described in claim 2, the offset data is preferably an average value of M (M is an integer of 2 or more) reference voltage conversion results. According to the signal processing apparatus configured in this way, random noise is suppressed, and therefore the accuracy of offset data can be improved.

  Furthermore, when the offset data is an average value of M conversion results, the number M of results to be offset data calculation target is set to 2 to the power of k (k is a natural number) as described in claim 3. It is desirable.

  According to the signal processing device configured in this way, the average value can be obtained by shifting the addition value of the M conversion results expressed in binary numbers to the lower bit side by k bits. A configuration for calculating data can be simplified.

  Further, as described in claim 4, when the correction means uses the predetermined period during which the reference voltage is supplied as an offset period and the period during which the analog signal is supplied as an AD conversion period, the AD conversion period It is desirable that the correction process is performed for each period using the offset data obtained in the immediately preceding offset period.

  That is, in the above configuration, offset data is first acquired, and thereafter, correction processing using the offset data is performed on the acquired analog signal conversion result. For example, the reference voltage and the analog are supplied by the target signal supply means in the order of the offset period (OT1), AD conversion period (AT1), offset period (OT2), AD conversion period (AT2), AD conversion period (AT3). When the signal is switched, the analog signal conversion result obtained in the AD conversion period (AT1) is corrected using the offset data obtained in the offset period (OT1). The analog signal conversion results obtained in the AD conversion period (AT2) and the AD conversion period (AT3) are corrected using the offset data obtained in the offset period (OT2).

In the signal processing apparatus configured in this way, correction processing is performed every time an analog signal conversion result is acquired, so that the accuracy of the AD conversion result can be improved.
In particular, the target signal supply means may be configured to switch between the reference voltage and the analog signal so that the offset period and the AD conversion period are alternately repeated. According to this, every time an analog signal conversion result is acquired, correction processing can be performed using the offset data immediately before the analog signal conversion result is acquired. Correction processing can be performed.

Therefore, in the signal processing device configured in this way, even when the offset data fluctuates in a relatively short time, the same effect as the above-described invention can be obtained.
By the way, when noise is superimposed on the target analog signal and only an analog signal having the same level as the noise level can be obtained, signal processing for removing the noise and emphasizing the analog signal is required.

  Therefore, as shown in claim 6, correction is performed using the addition value of W (W is an integer of 2 or more) analog signal conversion results acquired for the same AD converter as integrated data, and the integrated data as corrected data. Processing may be performed.

  That is, for each AD converter, the analog signal conversion results acquired a plurality of times are added for each sampling point. The integrated data generated in this way has a reduced noise and improved S / N compared to the original individual analog signal conversion results. As a result, even if the analog signal is buried in noise, an AD conversion result can be obtained, and the AD conversion accuracy can be improved.

  When the correction process is performed using the integrated data as the data to be corrected, the correction means, as shown in claim 7, each time the AD conversion period is repeated W times, W correction values obtained in the immediately preceding offset period are obtained. The correction processing is performed using data obtained by adding the offset data as addition offset data and using the addition offset data as offset data.

  The signal processing apparatus configured as described above radiates a radar wave within a predetermined angle range and receives and receives a reflected wave from a target of the irradiated radar wave as shown in claim 8. You may comprise so that the radar means which outputs the received signal according to the intensity | strength of a reflected wave may be provided. In this case, the target signal supply means is configured so that the received signal is an analog signal.

It is a block diagram which shows the structure of 1st Embodiment. It is a block diagram which shows the structure of a ranging part. It is a timing diagram which shows the operation timing of each part, such as a 1st adder and a 2nd adder. It is a timing diagram which shows the operation timing of each part, such as FF and DPRAM. It is a timing diagram which shows the operation timing of a correction | amendment part etc. It is a block diagram which shows the structure of 2nd Embodiment. It is explanatory drawing which shows the action | operation of an integrating | accumulating part. It is a timing diagram which shows the operation | movement timing of an integrating | accumulating part. It is explanatory drawing which shows the sampling method of the conventional signal processing apparatus. It is explanatory drawing which shows the zero point offset data of the AD converter in the conventional signal processing apparatus. (A) is explanatory drawing which shows the shift | offset | difference from the ideal waveform of the output of two AD converters in the conventional signal processing apparatus, (b) synthesize | combined the output of the two AD converters in the conventional signal processing apparatus. It is explanatory drawing which shows a waveform.

An embodiment of the present invention will be described with reference to the drawings.
In the following embodiment, mounted on a vehicle, transmits a pulsed laser beam as a radar wave, receives the reflected wave, and measures the time difference from the transmission timing of the laser beam to the reception timing of the reflected wave, An example in which the signal processing device of the present invention is applied to a laser radar device that obtains information (distance, relative speed, etc.) relating to a target reflecting laser light will be described. In the following description, a series of processes for transmitting a laser beam and obtaining a distance from the target reflecting the laser beam from the transmission timing of the laser beam is referred to as a distance measurement process.

[First Embodiment]
<Overall configuration>
FIG. 1 is a block diagram showing the overall configuration of a laser radar device 1 to which the present invention is applied.

  The laser radar device 1 includes a light emitting unit 10 that irradiates laser light toward a region within a predetermined angle range ahead of the vehicle (hereinafter referred to as an irradiation region) according to the transmission timing signal ST, and an object that reflects the laser light. And a light receiving unit 20 that receives reflected light from the mark and converts it into an electrical signal (reception signal RS) corresponding to the received light intensity.

  In addition, the laser radar device 1 generates a transmission timing signal ST to be supplied to the light emitting unit 10 according to the distance measurement start signal SS, and a target that reflects the laser light based on the reception signal RS supplied from the light receiving unit 20 A distance measuring unit 30 for measuring the distance between the distance measuring unit 30 and a distance measurement start signal SS to be supplied to the distance measuring unit 30, and a target existing in the irradiation area is detected from the distance measurement data DD in the distance measuring unit 30. And a signal processing unit 40 for generating information (distance, relative speed, etc.) regarding the target.

<Light emitting part>
The light emitting unit 10 includes a light emitting element 11 including a laser diode (LD) that generates laser light, an LD driving circuit 12 that drives the light emitting element 11 in accordance with a transmission timing signal ST, and a laser light that is irradiated to the irradiation region. A scanner mechanism unit 14 that adjusts the irradiation range of the laser light emitted from the light emitting element 11, a scanner drive circuit 15 that drives the scanner mechanism unit 14 according to the transmission timing signal ST to realize a two-dimensional beam scan, It has.

Each time the transmission timing signal ST is input, the light emitting unit 10 is configured to irradiate the laser light after determining the irradiation direction of the laser light.
<Light receiver>
The light receiving unit 20 generates a light receiving lens 21 that collects the reflected light from the target that reflects the laser light, and an electric signal having a voltage value corresponding to the received light intensity of the reflected light received through the light receiving lens 21. A light receiving element 22 and an amplifier 23 for amplifying an electric signal from the light receiving element 22 are provided. The electric signal amplified by the amplifier 23 is output to the distance measuring unit 30 as a reception signal RS.

<Signal processing unit>
The signal processing unit 40 is composed of a known microcomputer configured with a CPU, a ROM, a RAM, and the like. The signal processing unit 40 outputs a distance measurement start signal SS instructing the start of the distance measurement process.

<Ranging unit>
FIG. 2 is a block diagram illustrating a configuration of the distance measuring unit 30.
The distance measuring unit 30 receives the received signal RS based on the AD conversion output unit 50 that AD converts the received signal RS input from the light receiving unit 20 and the AD conversion result of the received signal RS by the AD conversion output unit 50. And a reception timing calculation unit 120 that calculates a reception timing that is a specific time. In addition, the distance measuring unit 30 includes a distance calculating unit 140 that calculates the distance to the target based on the time difference from the transmission timing to the reception timing with the time when the transmission timing signal ST is output as the transmission timing. .

<AD conversion output unit>
The AD conversion output unit 50 includes a clock generation unit 58 that generates a clock used in the distance measuring unit 30, and a reception signal RS or a reference voltage (an analog voltage of 0 V in this embodiment) as a target signal to be subjected to AD conversion. ) And a target signal supply unit 52 that supplies the selected signal.

  The AD conversion output unit 50 includes an AD conversion unit 68 having two AD converters that perform AD conversion on the target signal supplied from the target signal supply unit 52 according to the clock generated by the clock generation unit 58, and AD conversion. A corrected data generation unit 86 that generates corrected data based on the data AD-converted by the unit 68.

  Further, the AD conversion output unit generates an offset data representing the measurement error for each AD converter in the AD conversion unit 68, and an offset data generation unit 76 based on the offset data generated by the offset data generation unit 76. And a correction unit 100 that corrects the correction data and generates sampling data SD.

<Clock generator>
The clock generation unit 58 includes an AD clock generation unit 62 that generates a first clock CK1 that is a clock for AD conversion having a cycle twice the sampling cycle of the sampling data SD output from the correction unit 100, and a first clock CK1. And a negative logic circuit 64 that generates the second clock CK2 having the same frequency as the first clock CK1 and having a phase different by π [rad] by inverting the clock CK1.

  The clock generation unit 58 includes a logic clock generation unit 66 that generates a logic clock LCK serving as an operation clock for the corrected data generation unit 86, the correction unit 100, the reception timing calculation unit 120, and the distance calculation unit 140. .

The logic clock LCK is set to the same frequency as the first clock CK1 and the second clock CK2.
<Target signal supply unit>
The target signal supply unit 52 selects one of the reception signal RS input from the light receiving unit 20 and the reference voltage according to the switching command signal SC, and outputs the selected signal to the AD conversion unit 68 as the target signal. A portion 56 is provided.

  In addition, when the ranging start signal SS is input, the target signal supply unit 52 generates a switching command signal SC for controlling the signal switching unit 56 so that the target signal is switched according to a preset schedule. The switching control unit that generates the transmission timing signal ST used for the operation of the corrected data generation unit 86, the correction data generation unit, the correction unit 100, and the light emitting unit 10 at the timing of starting AD conversion of the received signal RS as the target signal 54.

  Hereinafter, a period for supplying the reference voltage as the target signal is referred to as an offset period OT, and a period for supplying the reception signal RS as the target signal is referred to as an AD conversion period AT. The offset period OT is set to be longer than the time required to acquire M AD conversion results, and the AD conversion period AT is sufficiently longer than the time required for the laser beam to reciprocate the maximum detection distance of the apparatus 1. (See FIG. 3).

Here, M is set to 2 to the power of k.
The switching control unit 54 is a switching command for controlling the signal switching unit 56 so that the offset period OT and the AD conversion period AT are alternately switched in response to the input of the ranging start signal SS from the signal processing unit 40. The signal SC is output. Hereinafter, a period from when the switching command signal SC is output until the next switching command signal SC is continuously output is referred to as a basic measurement period BT.

  The switching control unit 54 is configured to output the transmission timing signal ST at a timing delayed by an operation delay time WT in the corrected data generation unit 86 described later after the start of the AD conversion period AT.

  The signal switching unit 56 is configured to output a reference voltage when the switching command signal SC is at an active level and to output a reception signal RS when the switching command signal SC is at an inactive level.

<AD converter>
The AD conversion unit 68 includes a first AD converter 72 that repeatedly AD converts the target signal supplied from the signal switching unit 56 in accordance with the first clock CK1, and a second AD converter 74 that repeatedly AD converts in accordance with the second clock CK2. Become.

Here, in each AD converter, each sampled data is represented by a binary number of P bits.
In the following, when the target signal is a reference voltage, the AD conversion result output from the first AD converter 72 is the first reference voltage conversion result Z1 [i], and the AD conversion result output from the second AD converter 74 is the first. This is referred to as 2 reference voltage conversion result Z2 [i], and when the target signal is the received signal RS, the AD conversion result output from the first AD converter 72 is the first AD conversion result D1 [i] and the second AD converter 74. The output AD conversion result is referred to as a second AD conversion result D2 [i].

<Offset data generator>
The offset data generation unit 76 sequentially adds the results AD-converted by the first AD converter 72 in accordance with the first clock CK1, and the AD converter 74 in the second AD converter 74 in accordance with the second clock CK2. The second adder 84 sequentially adds the converted results, and generates the first offset data AZ1 as the offset data of the first AD converter 72, and the second offset data AZ2 as the offset data of the second AD converter 74. Configured to generate.

Here, the first adder 82 and the second adder 84 are configured to operate while the switching command signal SC is at the active level.
That is, while the reference voltage is supplied as the target signal from the target signal supply unit 52, the first adder 82 converts the first reference voltage conversion result Z1 [i] (i = 1, 2,... M) to M. The first addition data S1 (= S1 [M]) is generated by sequential addition, and similarly, the second adder 84 sequentially adds the second reference voltage conversion result Z2 [i] M times to obtain the second. The addition data S2 (= S2 [M]) is generated.

  Here, S1 [i] indicates the elapsed value of the first added data at the time when i first reference voltage conversion results Z1 [1] to Z1 [i] are added. S1 (= S1 [M]) is the value of the first addition data at the time when the M first reference voltage conversion results Z1 [1] to Z1 [M] have been added. ).

  Here, a value that should be associated with the reference voltage and ideally output as an AD conversion value is referred to as a reference AD conversion value. If the reference AD conversion value is 0 when the reference voltage is 0 V, the individual first reference voltage conversion result Z1 [i] and the second reference voltage conversion result Z2 [i] are directly used as the reference AD conversion value. It represents the amount of deviation. These deviation amounts are values unique to each AD converter, and are consistently generated every time AD conversion is performed.

  In addition, the offset data generation unit 76 generates a lower k of the first addition data S1 (= S1 [M]) and the second addition data S2 (= S2 [M]) expressed in P-bit binary numbers, respectively. Data obtained by truncating the bits, that is, (P−k) -bit data in which the (k + 1) -th bit from the lower order side of the first addition data S1 and the second addition data S2 is set to LSB is output to the first adder output A1 ( = A1 [M]) and the second adder output A2 (= A2 [M]).

  Here, A1 [i] indicates the elapsed value of the first adder output at the time when i first reference voltage conversion results Z1 [1] to Z1 [i] are added. A1 (= A1 [M]) is the data value of the first adder output at the time when the M first reference voltage conversion results Z1 [1] to Z1 [M] have been added.

  That is, the first adder output A1 and the second adder output A2 are data obtained by shifting the first addition data S1 and the second addition data S2 by k bits to the lower bit side, that is, 2 to the kth power. The data is rounded down to the nearest whole number.

  Taking the first adder output A1 [M] as an example, the first adder output A1 [M] is expressed by Expression (2).

  As described above, since M is set to 2 to the power of k, the first adder is obtained by shifting the first addition data S1 [M] represented by a P-bit binary number by k bits to the lower bit side. Obtaining the output A1 [M] corresponds to calculating an average value of the M first reference voltage conversion results Z1 [i]. The same applies to the second adder output A2 [M].

  The first adder output A1 [M] and the second adder output A2 [M] calculated in this way are output from the offset data generation unit 76 as the first offset data AZ1 and the second offset data AZ2, respectively. The

  That is, M indicates the number of first AD conversion results D1 [i] and second AD conversion results D2 [i] that are the calculation targets of the first offset data AZ1 and the second offset data AZ2.

  The first AD converter 72 operates at the operating edge (rising edge here) of the first clock CK1, and the second AD converter 74 operates at the operating edge (rising edge here) of the second clock CK2.

FIG. 3 is a timing chart showing the operation timing of each unit such as the first adder and the second adder.
As shown in FIG. 3, when the switching command signal SC is switched from the inactive level (low level) to the active level (high level) (see time t1), the reference to the first AD converter 72 and the second AD converter 74 is set. The supply of the voltage (target signal) is started, and then the first addition data S1 [i] of the first adder 82 and the second addition of the second adder 84 at the first operation edge (rising here) of the clock. Data S2 [i] is reset (see times t2 and t3).

  The first AD converter 72 and the second AD converter 74 start AD conversion at the first operation edge of the clock (see times t2 and t3), and thereafter, for each operation clock, the first reference voltage conversion result Z1 [ i] and the second reference voltage conversion result Z2 [i] are output.

  That is, the first reference voltage conversion result Z1 [i] and the second reference voltage conversion result Z2 [i] are alternately output at timings shifted by half a clock cycle, and the first adder 82 and the second addition Supplied to the vessel 84.

  Since the switching command signal SC is held at the active level for M (= 4) periods of the first clock CK1 and the second clock CK2, and then switched to the inactive level (see time t6), the first AD conversion is performed. The device 72 and the second AD converter 74 perform AD conversion of the reference voltage M times. That is, for each operating edge of the clock, the first reference voltage conversion results Z1 [1] to Z1 [M] and the second reference voltage conversion results Z2 [1] to Z2 [M] are sequentially output.

  The first adder 82 and the second adder 84 reset the first addition data S1 [i] and the second addition data S2 [i] and reset the first reference voltage conversion result Z1 [i at each operating edge of the clock. ”And the second reference voltage conversion result Z2 [i] are sequentially added to update the first addition data S1 [i] and the second addition data S2 [i] (see times t4 and t5).

  The Mth first reference voltage conversion result Z1 [M], the second reference voltage conversion result Z2 [M], and the first addition data S1 [M] reflecting these Z1 [M] and Z2 [M]. The second addition data S2 [M] is output after the switching command signal SC is switched to the inactive level (see times t7 and t8), and thereafter, S1 [M] and S2 [ The value of M] is held.

  The first adder output A1 and the second adder output A2, which are values obtained by removing the lower K bits of the first addition data S1 and the second addition data S2, respectively, until the transmission timing signal ST is output. According to the logic clock LCK, the first offset data AZ1 and the second offset data AZ2 are taken into the correction unit 100 (see time t9).

Note that the switching control unit 54 outputs the transmission timing signal ST after a predetermined time has elapsed after switching the switching command signal SC to the inactive level (see time t10).
<Corrected data generation unit>
Returning to FIG. 2, the corrected data generation unit 86 includes a first flip-flop (FF) 88 that latches the first AD conversion result D1 [i] (i = 1, 2,...) According to the first clock CK1, and the first clock CK1. FF89 which latches the output of FF88 according to clock CK1, FF91 which latches 2nd AD conversion result D2 [i] according to 2nd clock CK2, and FF92 which latches the output of FF91 according to 1st clock CK1 are provided.

  The corrected data generation unit 86 also includes a dual port RAM (DPRAM) 94 that stores the outputs of the FF 89 and the FF 92, a write enable signal WE that permits writing of data to the DPRAM 94, and a write address for writing the data. A write address generation unit 96 that generates AW and a read enable signal RE that permits reading of data from the DPRAM 94 and a read address generation unit 98 that generates a read address AR when reading data are provided.

  The DPRAM 94 simultaneously writes the outputs of the FF 89 and the FF 92, that is, the first AD conversion result D1 [i] and the second AD conversion result D2 [i] at two sampling points that are temporally continuous. The first AD conversion result D1 [i] and the second AD conversion result D2 [i] are read one by one.

  That is, the first AD conversion result D1 [i] and the second AD conversion result D2 [i] are represented by P bits, and the AD conversion unit is configured by n AD converters (n = 2 in the present embodiment). As a matter of fact, data is processed in units of n × P bits on the writing side of the DPRAM 94, and data is processed in units of P bits on the reading side.

  The write data to the DPRAM 94 is when the output of the FF 89 (D1 [i]) is the lower data L [i] and the output of the FF 92 (D2 [i]) is the upper data H [i], and is read from the DPRAM 94. The lower data L [i] (P bit) of the write data and the upper data H [i] (P bit) of the write data are set to be read in this order.

  That is, in the read data RD [k] (k = 1, 2,...), The odd number is composed of the first AD conversion result D1 [(k + 1) / 2], and the even number is the second AD conversion result D2 [k. / 2]. This read data RD [i] corresponds to the above-mentioned corrected data.

  The write address generation unit 96 has passed the detection period Tad, which is the time required for the laser light to reciprocate the maximum detection distance, after the elapse of a predetermined operation delay time WT after the transmission timing signal ST is output. Until this time, the write enable signal WE is output to the DPRAM 94, and during the detection period Tad, Q write addresses AW set in advance are output at each operation timing of the first clock CK1. However, assuming that the cycle of the first clock CK1 is Tcy, the number Q of occurrences of the write address AW is Q = Tad / Tcy. That is, during the detection period Tad, AD conversion is executed for 2Q sampling points, and the AD conversion result is stored in the DPRAM.

  The operation delay time WT here refers to the first first AD conversion result D1 [i] and the second AD conversion result D2 [i] after the transmission timing signal ST is output (the lower data L [ i] and higher-order data H [i]) is the time until it appears at the input end of the DPRAM 94, and is determined by the number of clocks of the first clock CK1.

  The read address generation unit 98 outputs a read enable signal RE to the DPRAM 94 and starts generating the read address AR when a predetermined standby time DT has elapsed since the first data was written in the DPRAM 94. The read address generation unit 98 operates in accordance with the same logic clock LCK as the read clock (CKB) of the DPRAM 94, and generates the read address AR so as to repeat the reading of P-bit data 2 × Q times.

FIG. 4 is a timing chart showing the operation timing of each unit such as the FFs 88, 89, 91, 92, DPRAM 94, and the like. For simplicity, in FIG. 4, it is assumed that Q = 3, M = 4, and k = 2.
Here, the writing of the FFs 88, 89, 92, the write address generation unit 96, and the DPRAM 94 operates at the operation edge (rising edge here) of the first clock CK1. On the other hand, the FF 91 operates at the operation edge (rising edge here) of the second clock CK2, and the reading of the read address generator 98 and the DPRAM 94 operates at the operation edge (rising edge here) of the logic clock LCK.

  When the switching command signal SC is switched to the inactive level and the transmission timing signal ST is output (see time t10), the light emitting unit 10 irradiates the laser beam and supplies the first AD converter 72 and the second AD converter 74 to the laser beam. Supply of the reception signal RS (target signal) is started.

  The transmission timing signal ST is output in synchronization with the operating edge of the first clock CK1, the first AD converter 72 starts operating at the next operating edge (see time t11), and the second AD converter 74 is operated with the first AD. The operation is started at the operation edge of the second clock CK2 delayed by a half clock from the operation start of the converter 72 (see time t12). Thereafter, the first AD conversion result D1 [i] and the second AD conversion result D2 [i] are output for Q (= 3) periods at each operation edge of the operation clock.

The FFs 88 and 91 latch the first AD conversion result D1 [i] and the second AD conversion result D2 [i] for each operation edge and output them to the FFs 89 and 92 (see times t11 and t12).
That is, the first AD conversion result D1 [i] and the second AD conversion result D2 [i] are output to the FFs 89 and 92 at timings shifted by half a clock cycle.

  For each operation clock, the FFs 89 and 92 latch the first AD conversion result D1 [i] and the second AD conversion result D2 [i] output from the FFs 88 and 91 at the operation edge of the first clock CK1 (see time t13). ).

  That is, the first AD conversion result D1 [i] and the second AD conversion result D2 [i] are output to the DPRAM 94 at the same timing (see time t14), and simultaneously to the DPRAM 94 at the next operation edge of the first clock CK1. It is written (see time t15). Thereafter, the writing is repeated a total of Q (= 3) times for each operation edge.

  The read address generation unit 98 is written in the DPRAM 94 at every operation edge of the logic clock LCK after a predetermined standby time DT (see time t16 to time t17) has elapsed since the first data was written in the DPRAM 94. Among the data written in order and simultaneously, the reading is performed 2 × Q (= 6) times in total in the order of the lower data L [1] and the upper data H [1] (see time t17 to time t19). .

<Correction unit>
When the read enable signal RE is switched to the active level (here, high level) after the transmission timing signal ST is output, the correction unit 100 starts reading the read data RD [i], and the read enable signal RE Reading is continued while the active level is maintained.

  When the odd-numbered read data RD [i] is read from the DPRAM 94, the correction unit 100 subtracts this by the first offset data AZ1, and when the even-numbered read data RD [i] is read, the correction unit 100 reads the second read data RD [i]. Subtraction is performed with the offset data AZ2, and these subtraction results are output as sampling data SD [i].

  Specifically, such a correction unit 100 reads out from the DPRAM 94, a selector that selects and outputs either the first offset data AZ1 or the second offset data AZ2 for each operation edge of the logic clock LCK. The read data RD [i] can be configured by a subtracter that subtracts offset data output from the selector.

Here, FIG. 5 is a timing chart showing the operation timing of the correction unit 100 and the like.
The correction unit 100 operates at the operation edge (rising here) of the logic clock LCK.

  When read data RD [i] (i = 1, 2,... 2Q, Q = 3 in FIG. 6 for simplicity) is input (see time t11), the correction unit 100 receives the logic clock LCK. At the first operation edge, the first sampling data SD [1] is obtained by subtracting the first offset data AZ1 from the first read data RD [1], that is, the first AD conversion result D1 [1] (see time t12). Thereafter, the correction unit 100 subtracts the second offset data AZ2 from the second read data RD [2], that is, the second AD conversion result D2 [1], at each operation timing of the logic clock, to obtain the second sampling data. SD [2] (see time t11), the third sampling data SD [3] is obtained by subtracting the first offset data AZ1 from the third read data RD [3], that is, the first AD conversion result D1 [2]. (See time t11)..., And so on, the correction process for subtracting the first offset data AZ1 or the second offset data AZ2 from the read data RD [i] is executed 2 × Q (= 6) times (time t11).

  The correction unit 100 outputs the first sampling data SD [1] until the 2Q (= 6) th sampling data SD [2Q] is output (see time 12 to t13). The sampling data valid signal SDA held in is output.

The sampling data SD [i] and the sampling data valid signal SDA are output every time the basic measurement period BT is repeated.
<Reception Timing Signal Calculation Unit and Distance Calculation Unit>
The reception timing calculation unit 120 receives the reception timing of the reception signal RS based on the sampling data SD [i] input from the correction unit 100 while the sampling data valid signal SDA from the correction unit 100 is held at the active level. Is calculated. Based on the reception timing calculated by the reception timing calculation unit 120 (for example, the timing when the waveform indicated by the sampling data SD [i] peaks), the distance calculation unit 140 calculates the distance to the target and measures the distance. Data DD is generated, and the distance measurement data DD is output to the signal processing unit 40.

Note that the processing executed by the reception timing calculation unit 120 and the distance calculation unit 140 is not a main part of the present invention, but is a well-known process, and a detailed description thereof will be omitted.
<Effect>
As described above, in the AD conversion output unit 50 in the laser radar apparatus 1 of the present embodiment, from the result of AD conversion of the voltage of 0 V (reference voltage), for each of the first AD converter 72 and the second AD converter 74, First offset data AZ1 and second offset data AZ2 are calculated. Then, when removing the offset data from the result of AD conversion of the received signal RS, instead of using uniform offset data for all AD conversion values, the first AD conversion result D1 [i] is not used. The first offset data AZ1 is used, and the second offset data AZ2 is used for the second AD conversion result D2 [i].

As a result, the influence that appears in the AD conversion result due to the different characteristics (offset data) of the first AD converter 72 and the second AD converter 74 is eliminated.
Therefore, in the AD conversion output unit 50 of the laser radar device 1 of the present embodiment, the waveform represented by the output results of two (n = 2) AD converters, the first AD converter 72 and the second AD converter 74, is The waveform is closer to the original received signal RS. Therefore, even when the same received signal RS is AD-converted by two AD converters, it is possible to suppress a decrease in the accuracy of the AD conversion result due to variations in the characteristics of the individual AD converters. As a result, accurate AD conversion can be realized at a speed equal to or higher than the operation upper limit speed of each AD converter.

  In the AD conversion output unit 50 of the present embodiment, the first offset data AZ1 and the second offset data AZ2 are converted into M first reference voltage conversion results Z1 [i] and second reference voltage conversion results Z2 [i]. The average value. According to this, since random noise is suppressed, the accuracy of the first offset data AZ1 and the second offset data AZ2 can be improved.

  Furthermore, in the AD conversion output unit 50 of this embodiment, M is set to 2 to the power of k (k is a natural number). Accordingly, the average value is obtained by shifting the addition value of the M first reference voltage conversion results Z1 [i] and the second reference voltage conversion results Z2 [i] expressed in binary numbers by k bits to the lower bit side. The first offset data AZ1 and the second offset data AZ2 can be obtained. As a result, the configuration for calculating the first offset data AZ1 and the second offset data AZ2 can be simplified.

  Further, the AD conversion output unit 50 of the present embodiment is configured such that the reference voltage and the reception signal RS are switched so that the offset period OT and the AD conversion period AT are alternately repeated.

  According to this, every time the first AD conversion result D1 [i] and the second AD conversion result D2 [i] are acquired, immediately before the first AD conversion result D1 [i] and the second AD conversion result D2 [i] are acquired. Since the correction process can be performed using the first offset data AZ1 and the second offset data AZ2, the correction process is performed using the latest data even when the first offset data AZ1 and the first offset data AZ2 vary. It can be performed.

  Therefore, in the AD conversion output unit 50 of the laser radar device 1 of the present embodiment, even when the first offset data AZ1 and the second offset data AZ2 fluctuate in a relatively short time, the responsiveness following the fluctuation. It is possible to perform a correction process with good quality.

[Correspondence with Invention]
The AD conversion output unit 50 in this embodiment corresponds to a “signal processing device” in the claims, and the target signal supply unit 52 corresponds to “target signal supply means” in the claims. Further, the AD conversion unit 68 corresponds to “AD conversion unit” in the claims, and the offset data generation unit 76 corresponds to “offset data generation unit” in the claims.

Furthermore, the correction unit 100 corresponds to “correction unit” in the claims, and the light emitting unit 10 and the light receiving unit 20 correspond to “radar unit” in the claims.
Further, the first clock CK1 and the second clock CK2 correspond to “multilayer clock” in the claims, and the first AD converter 72 and the second AD converter 74 are “n AD converters” in the claims. And the received signal RS corresponds to an “analog signal” in the claims.

  Furthermore, the first reference voltage conversion result Z1 and the second reference voltage conversion result Z2 correspond to the “reference voltage conversion result” in the claims, and the first offset data AZ1 and the second offset data AZ2 are the claims. Corresponds to “offset data” in FIG. The first AD conversion result D1 and the second AD conversion result D2 correspond to the “analog signal conversion result” in the claims, the read data RD corresponds to “corrected data” in the claims, and the sampling data SD Corresponds to the “AD conversion result” in the claims.

[Second Embodiment]
Next, a second embodiment will be described.
This embodiment is different from the first embodiment in that the AD conversion output unit includes an integration unit.

  In the above-described embodiment, the first offset data AZ1 and the second offset data AZ2 are obtained every time the basic measurement period BT, and the read data RD is corrected by the correction unit. With the integration unit, the correction unit corrects the read data RD once every time the basic measurement period BT is repeated W (W is an integer of 2 or more). ing. Hereinafter, a period in which the basic measurement period BT is repeated W times is referred to as an integrated measurement period IT.

FIG. 6 is a block diagram showing the configuration of the distance measuring unit 31 of the present embodiment. Hereinafter, a description will be given centering on differences from the above embodiment.
<Offset data generator>
In the present embodiment, the first addition data S1 and the second addition data S2 generated by the offset data generation unit 77 are output to the integration unit 110, unlike the above embodiment. Hereinafter, the first addition data S1 output to the integration unit 110 during the j (j = 1, 2,... W) th basic measurement period BT in the integration measurement period IT is referred to as the first addition data S1. [J] and the second addition data S2 is represented as second addition data S2 [j].

<Corrected data generation unit>
In the present embodiment, the read data RD [i] generated by the corrected data generation unit 86 is output to the integration unit 110 unlike the above embodiment. Hereinafter, the read data RD [i] output to the integrating unit 110 during the j-th basic measurement period BT in the integrated measurement period IT is represented as read data RD [i] _j.

<Integration unit>
The integration unit 110 sequentially adds the first addition data S1 [j] input from the offset data generation unit 77 every time the basic measurement period BT is repeated during the integration measurement period IT. 1 accumulated data I1 (= I1W) is generated, and similarly, the second added data S2 [j] is added every time the basic measurement period BT is repeated to generate second accumulated data I2 (= I2W). It is configured.

  Here, I1j indicates the elapsed value of the first integrated data at the time when the first addition data S1 [j] is added during the jth basic measurement period BT. I1W is the first integrated data at the time when the first addition data S1 [j] has been added during the Wth basic measurement period BT, and is represented by Expression (3).

  I2j is the elapsed value of the second accumulated data at the time when the second addition data S2 [j] is added during the jth basic measurement period BT, and is the first value during the Wth basic measurement period BT. The value of the 2 accumulated data I2W is expressed in the same manner as in the equation (3).

  The accumulating unit 110 has data obtained by rounding down the lower k bits of the first accumulated data I1 and the second accumulated data I2 expressed in binary numbers of P bits, that is, the first accumulated data I1W and the second accumulated data. (Pk) -bit data in which the (k + 1) -th bit from the lower side of the integration data I2W is set to LSB is output as first integration offset data B1 and second integration offset data B2. .

  That is, the first integrated offset data B1 and the second integrated offset data B2 are data obtained by dividing the first integrated data I1W and the second integrated data I2W by 2 to the power of k and rounding down the decimal part. Here, as in the above embodiment, M is set to 2 to the power of k.

  Taking the first integrated offset data B1 as an example, the first integrated offset data B1 is expressed by Expression (4).

  That is, the first integrated offset data B1 corresponds to data obtained by sequentially adding the first offset data AZ1 of the above embodiment for a total of W times for each basic measurement period BT. Similarly, the second accumulated offset data B2 corresponds to data obtained by sequentially adding the second offset data AZ2 of the above embodiment for a total of W times for each basic measurement period BT.

  Further, the integration section 110 reads 2Q pieces of read data RD [i] _j (i = 1, 2,... 2Q) read from the DPRAM 94 every time the basic measurement period BT is repeated during the integration measurement period IT. , J = 1, 2,..., W) are added for each sampling point, and the register Ri (i = 1, 2,..., 2Q) is included. The register data Ri [W] stored in the register Ri is sequentially read out as an addition result and output as integrated corrected data IRD [i].

  Here, taking the read data RD [1], which is the first data out of 2Q data of the read data RD [i], as an example, the register data R1 [j] is stored in the jth basic measurement period BT. Sometimes it is the elapsed value of the added value at the time when the read data RD [1] _j is added, and is expressed by equation (5).

  The register data R2 [j] based on the read data RD [2] which is the second data to the register data R2Q [j] based on the read data RD [2Q] which is the second data is similarly expressed. .

That is, the register data Ri [W] corresponds to data obtained by adding the first AD conversion result D1 [i] and the second AD conversion result D2 [i] W times for each sampling point.
FIG. 7 is an explanatory diagram showing the operation of the integrating unit 110. That is, as shown in FIG. 7, the integration unit 110 adds the read data RD [i] _j acquired during the detection period Tad for each sampling point every time the transmission timing signal ST is output. Is repeated (total W times). Although not shown, the accumulating unit 110 acquires the first offset data AZ1 and the second offset data AZ2 every time the switching command signal SC is output, and each time the transmission timing signal ST is output. The process of adding sequentially is repeated (total W times).

Here, FIG. 8 is a timing chart showing the operation timing of the integrating unit 110. FIG. 8 shows a case where W = 3 and Q = 3 for simplicity.
When the first (j = 1) switching command signal SC is switched to the active level, the integrating unit 110 resets the first integrated data I1j, the second integrated data I2j, and the register data R1 [j] to R6 [j]. To do.

  When the switching command signal SC is switched to the inactive level, the first addition data S1 [1] for the first time is output from the first adder 82 of the offset data generation unit 77 at the first operation edge of the first clock CK1 ( At the same time, the second addition data S2 [1] is output at the next operation edge of the second clock CK2 (see time t2).

  Next, when the first transmission timing signal ST is output by the switching control unit 54 (see time t3), the accumulating unit 110 uses the first addition data S1 [1] and the first operation time of the logic clock LCK. The second addition data S2 [1] is set as first integration data I11 and second integration data I21, respectively (see time t4).

  When the first transmission timing signal ST is output, reading of the read data RD [i] _1 from the corrected data generation unit 86 is started at the first operation edge of the logic clock LCK. (See time t4).

  The accumulating unit 110 stores the read data RD [1] _1 in the register R1 at the operation edge of the first logic clock LCK after the reading of the read data RD [i] _1 is started (see time t5). That is, the register data R1 [1] = RD [1] _1. Thereafter, the integrating unit 110 sequentially stores the read data RD [2] _1 to RD [6] _1 as register data R2 [1] to R6 [1] in the registers R2 to R6 for each operation clock (time). t5 to time t6).

  The integration unit 110 outputs the first addition data S1 [2], S1 every time the transmission timing signal ST is output the second time (j = 2) and the third time (j = 3) (see times t7 and t11). [3] and second addition data S2 [2], S2 [3] are sequentially added to generate first integrated data I12, I13 and second integrated data I22, I23 (see times t8, t12).

  In addition, the integration unit 110 outputs the read data RD [1] _2 to 2 every time the transmission timing signal ST is output for the second time (j = 2) and the third time (j = 3) (see times t7 and t11). RD [6] _2 and RD [1] _3 to RD [6] _3 are sequentially added for each sampling point in the registers R1 to R6 (see times t9 to t10 and t13 to t15).

  When the transmission timing signal ST is the third time (j = 3, W = 3), the integrating unit 110 uses the first integrated offset data B1 and the second integrated data based on the first integrated data I13 and the second integrated data I23. Accumulated offset data B2 is output.

  Further, when the transmission timing signal ST is the third time (j = 3, W = 3), the accumulating unit 110 stores the register data R1 [3] to R6 [3] stored in the registers R1 to R6. The data is sequentially read according to the logic clock LCK and output as integrated corrected data IRD [i] (see time t16).

The first integrated offset data B1, the second integrated offset data B2, and the integrated correction data IRD [i] are all output to the correction unit 100.
<Correction unit>
Unlike the above embodiment, the correction unit 100 is configured to operate once every time the transmission timing signal ST is input W times. Further, integrated correction data IRD [i] (i = 1, 2,... 2Q) is input instead of the read data RD [i] of the above embodiment, and the first integrated offset data is replaced with the first offset data AZ1. B1 is input, and second integrated offset data B2 is input instead of the second offset data AZ2.

That is, the correction unit 100 reads the data held in the registers R1 to R6 of the integrating unit 110 as integrated corrected data IRD [i] at a timing of once every W times.
Further, the correction unit 100 determines the read-out integrated correction data IRD [i] from the odd-numbered integrated correction data IRD [(k + 1) / 2] (k = 1, 2,...). 1 integrated offset data B1 is subtracted, and second integrated offset data B2 is subtracted from even-numbered integrated correction data IRD [k / 2] (k = 1, 2,...), And integrated sampling data ISD [i ] Is generated.

Further, the correction unit 100 generates the integrated data valid signal IDA indicating the active level while generating the integrated sampling data ISD [i].
<Effect>
As described above, in the AD conversion output unit 51 of the present embodiment, the first AD conversion result D1 [i] and the second AD conversion result D2 [i] are added W times for each sampling point and integrated corrected data IRD. [I] is generated. As a result, the integrated corrected data IRD [i] generated by adding W times has noise compared to the original first AD conversion result D1 [i] and second AD conversion result D2 [i]. It is suppressed and S / N is improved.

  Therefore, even if the received signal RS is buried in noise, the AD conversion result can be obtained, and as a result, the AD conversion accuracy of the AD conversion output unit 51 can be improved.

[Correspondence with Invention]
The AD conversion output unit 51 in this embodiment corresponds to a “signal processing device” in the claims, and the offset data generation unit 77 corresponds to “offset data generation means” in the claims. Further, the integrated corrected data IRD [i] in the present embodiment corresponds to “integrated data” in the claims, and the first integrated offset data B1 and the second integrated offset data B2 correspond to “added offset data”. .

  The AD conversion output unit 50 in the present embodiment corresponds to a “signal processing device” in the claims, the target signal supply unit 52 corresponds to “target signal supply means” in the claims, and the AD conversion unit 68 includes The correction unit 100 corresponds to the “AD conversion unit” in the claims, the correction unit 100 corresponds to the “correction unit” in the claims, and the light emitting unit 10 and the light receiving unit 20 correspond to the “radar unit” in the claims. To do.

[Other embodiments]
As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects.

  (A) In the above embodiment, the AD conversion output units 50 and 51 each time the transmission timing signal ST is transmitted, that is, every time before the light emitting unit 10 is irradiated with the laser light, the first offset data AZ1 and the second offset data AZ1 Offset data AZ2 was acquired. On the other hand, the AD conversion output unit outputs the first offset data and the first data every time the transmission timing signal ST is transmitted a plurality of times, that is, once every time the laser light is irradiated a plurality of times. Two offset data may be acquired.

  (B) In the above embodiment, the first clock CK1 and the logic clock LCK are generated independently in the clock generation unit 58, but either the first clock CK1 or the second clock CK2 is used as the logic clock LCK. May be.

  (C) In the above embodiment, the first clock CK1, the second clock CK2, and the logic clock LCK are set to the same frequency, but the logic clock LCK has a frequency different from that of the first clock CK1 and the second clock CK2. It may be set.

  However, when the frequency of the first clock CK1 is CK1 and the frequency of the logic clock is LCK and LCK> CK1, the operation in which the DPRAM 94 reads the read data RD [i] according to the logic clock LCK is the write data to the DPRAM 94. It is necessary to set so that it is after the timing at which the lower data L [i] and the upper data H [i] are written.

(D) In the above embodiment, the reference voltage is set to 0V. However, the reference voltage is not limited to 0V and can be set according to the characteristics of each AD converter.
(E) In the above embodiment, the AD conversion unit 68 is composed of two (n = 2) AD converters, but the number of AD converters is not limited to this, and n AD converters are necessary. (N is an integer of 2 or more).

In this case, the following modification may be added to the AD conversion output unit 50 described above.
That is, the clock generation unit generates n clocks having the same frequency and different phases by 2π / n [rad] as multilayer clocks, and each of the n AD converters operates according to one of the multilayer clocks. Configure as follows.

  The offset data generation unit generates offset data for each of the n AD converters when the target signal is a reference voltage, and the corrected data generation unit generates n when the reference voltage is a received signal. The AD conversion results of the individual AD converters are sequentially combined, and a combined waveform corresponding to a waveform sampled at n times the frequency of the operation clock of each AD converter is generated as read data.

Further, the correction unit is configured to generate sampling data by repeating the process of removing offset data of individual AD converters from read data in the order of 1 to n.
It should be noted that the number of AD converters can be set to n as necessary by making the same modification to the AD conversion output unit 51 described above.

  DESCRIPTION OF SYMBOLS 1 ... Laser radar apparatus 10 ... Light emission part 20 ... Light-receiving part 30, 31 ... Distance measuring part 40 ... Signal processing part 50, 51 ... AD conversion output part 52 ... Object Signal supply unit 68... AD conversion unit 72... First AD converter 74... Second AD converter 76 and 77... Offset data generation unit 100... Correction unit AZ1. AZ2 ... second offset data CK1 ... first clock CK2 ... second clock D1 ... first AD conversion result D2 ... second AD conversion result RD ... read data RS ... received signal SD: Sampling data Z1: First reference voltage conversion result Z2: Second reference voltage conversion result

Claims (8)

AD conversion of the same target signal set in advance according to one of the multi-layer clocks consisting of n clocks used for sampling of AD conversion, with different phases by 2π / n (n is an integer of 2 or more) at the same frequency AD conversion means comprising n AD converters,
Target signal supply means for supplying the AD conversion means with either a predetermined reference voltage or an analog signal to be AD converted as the target signal;
A conversion result in the AD conversion means acquired when the target signal is the reference voltage is used as a reference voltage conversion result for each AD converter with respect to a reference AD conversion value associated with the reference voltage. Offset data generating means for generating offset data representing a deviation amount of the reference voltage conversion result in the AD converter;
The conversion result in the AD conversion means acquired when the target signal is the analog signal is taken as an analog signal conversion result, and the analog signal conversion result for each AD converter is based on the analog signal conversion result in the AD converter. Correction means for outputting, as an AD conversion result, correction data for removing the offset data generated by the offset data generation means for the AD converter for each sampling point from the correction data;
A signal processing apparatus comprising:   The signal processing apparatus according to claim 1, wherein the offset data generation unit uses an average value of M (M is an integer of 2 or more) reference voltage conversion results as the offset data. The number M of results for which the offset data is calculated is set to 2 to the power of k (k is a natural number),
The offset data generation unit obtains an average value by shifting an addition value of M reference voltage conversion results expressed in binary numbers by k bits to the lower bit side. Signal processing device.   The correction means sets a predetermined period during which the reference voltage is supplied as an offset period, and sets a predetermined period during which the analog signal is supplied as an AD conversion period, for each AD conversion period. The signal processing apparatus according to claim 1, wherein the correction process is performed using the offset data obtained in the immediately preceding offset period.   The signal processing apparatus according to claim 4, wherein the target signal supply unit switches between the reference voltage and the analog signal so that the offset period and the AD conversion period are alternately repeated. The target signal supply means includes a predetermined fixed period during which the reference voltage is supplied as an offset period, and a predetermined constant period during which the analog signal is supplied as an AD conversion period. Switching between the reference voltage and the analog signal so that the AD conversion period is alternately repeated,
Each time the AD conversion period is repeated W (W is an integer greater than or equal to 2) times, the correction unit calculates the analog signal conversion result obtained for each AD conversion period by the same AD converter for each sampling point. 4. The signal processing apparatus according to claim 1, wherein the correction process is performed using W added data as integration data and the integration data as the data to be corrected. 5.   Each time the AD conversion period is repeated W (W is an integer equal to or greater than 2) times, the correction unit adds, as addition offset data, data obtained by adding the W offset data obtained in the immediately preceding offset period. The signal processing apparatus according to claim 6, wherein the correction processing is performed using the added offset data as the offset data. A radar means for transmitting a radar wave within a predetermined angle range, receiving a reflected wave from a target of the transmitted radar wave, and outputting a received signal corresponding to the intensity of the received reflected wave;
The signal processing apparatus according to claim 1, wherein the target signal supply unit uses the received signal as the analog signal.

Images