JP2013051295A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

Info

Publication number
JP2013051295A
JP2013051295A JP2011188078A JP2011188078A JP2013051295A JP 2013051295 A JP2013051295 A JP 2013051295A JP 2011188078 A JP2011188078 A JP 2011188078A JP 2011188078 A JP2011188078 A JP 2011188078A JP 2013051295 A JP2013051295 A JP 2013051295A
Authority
JP
Japan
Prior art keywords
clip
electrode
lead
semiconductor element
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2011188078A
Other languages
Japanese (ja)
Inventor
Tomoe Fujioka
知恵 藤岡
Daichi Kumano
大地 熊野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2011188078A priority Critical patent/JP2013051295A/en
Publication of JP2013051295A publication Critical patent/JP2013051295A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48484—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) being a plurality of pre-balls disposed side-to-side
    • H01L2224/48485—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) being a plurality of pre-balls disposed side-to-side the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To maintain reliability of a semiconductor device with inhibiting increase in resistance of a clip due to affection of a skin effect.SOLUTION: By providing a through hole 215 and a comb part to increase a surface area of the clip 200, increase in resistance of a clip 200 due to affection of a skin effect can be inhibited. And by providing an opening 216 on a lateral face of the clip 200, an occurrence of air bubbles and voids due to holding of air by an encapsulation resin in the through hole 215 and under the clip 200 can be prevented. As a result, reliability in product quality can be improved.

Description

本発明は、半導体素子とリードがクリップによって接続された構造を有する半導体装置とその製造方法に関するものである。   The present invention relates to a semiconductor device having a structure in which a semiconductor element and a lead are connected by a clip, and a manufacturing method thereof.

携帯電話やノート型ＰＣなどといった移動型通信機器の普及にともない、それらに使用される電池回路用部品等の半導体部品には、低消費電力化などの要求が高まってきている。   With the spread of mobile communication devices such as mobile phones and notebook PCs, there is an increasing demand for lower power consumption in semiconductor components such as battery circuit components used in them.

それらの半導体部品に内蔵される半導体素子自体の内部抵抗を下げる為に、半導体素子を薄くしたりサイズを大きくしていた。さらに素子表面の電極部分に出来るだけ低抵抗で大きな接続材料を接着させて、半導体素子とリードとの接続部の低抵抗化が図られている。   In order to reduce the internal resistance of the semiconductor elements themselves built in these semiconductor components, the semiconductor elements have been made thinner or larger in size. Furthermore, a large connecting material with as low resistance as possible is adhered to the electrode portion on the surface of the element to reduce the resistance of the connecting portion between the semiconductor element and the lead.

また、一方でＰＣなどに使用されるＣＰＵは、消費電力を低減するために低電圧化，高速化・高集積化の為に大電流化、及び高速負荷変動応答の要求が高まってきている。さらにＣＰＵ以外でもシステム全体の消費電力の低減を行うために、電源は低電圧化、多出力化の傾向になっている。そのため、電源系の増加や、機器内での電源装置の占める割合が大きくなってきており、電源装置の小型化の要求も強まってきている。   On the other hand, CPUs used for PCs and the like are increasingly required to have a large current and a high-speed load fluctuation response for low voltage, high speed and high integration in order to reduce power consumption. Furthermore, in order to reduce the power consumption of the entire system other than the CPU, the power supply tends to have a low voltage and multiple outputs. For this reason, the number of power supply systems has increased and the proportion of power supply devices in equipment has increased, and the demand for downsizing of power supply devices has increased.

このような電源装置に関しては、一般に同期整流タイプの降圧型ＤＣ−ＤＣコンバーターが使用されている。ＤＣ−ＤＣコンバーターの小型化には、動作周波数を上げて電源回路に組み込まれているコンデンサやコイルを小型化する方法がある。   In general, a synchronous rectification step-down DC-DC converter is used for such a power supply device. To reduce the size of a DC-DC converter, there is a method of increasing the operating frequency and reducing the size of capacitors and coils incorporated in the power supply circuit.

動作周波数が上がることで、用いられるスイッチング素子の高速スイッチング動作が要求されるが、追従が出来ていないのが現状である。
これは、素子表面の電極とリードとを接続するクリップ等の板状の接続部材における表皮効果が原因となっている。表皮効果では、電流の周波数が上がると導体の実効断面積が減少する。つまり、交流電流が導体を流れると電磁界が発生するが、その大きさは導体の中心部が最も強く、表面部分が弱くなるため、周波数が高くなると電流が主に導体の表面部分を流れるようになる。そのため、電流の流通経路の断面積が減少し、抵抗が増加するため高速スイッチング動作が困難になっていた。 Although the operating frequency is increased, a high-speed switching operation of the switching element to be used is required, but the current situation is that the tracking cannot be performed.
This is due to the skin effect of a plate-like connecting member such as a clip that connects the electrode on the element surface and the lead. In the skin effect, the effective cross-sectional area of the conductor decreases as the current frequency increases. In other words, when an alternating current flows through a conductor, an electromagnetic field is generated, but the magnitude is strongest at the center of the conductor and weakened at the surface, so that the current flows mainly through the surface of the conductor as the frequency increases. become. As a result, the cross-sectional area of the current flow path decreases and the resistance increases, making high-speed switching operation difficult.

表皮効果の影響を低減するために、従来の半導体装置は、半導体素子とリードとを接続するクリップに貫通孔を設けているものがあった（例えば、特許文献１参照）。
以下、図７を用いて従来の半導体装置の構成を説明する。 In order to reduce the influence of the skin effect, some conventional semiconductor devices have a through hole in a clip connecting a semiconductor element and a lead (see, for example, Patent Document 1).
Hereinafter, the configuration of a conventional semiconductor device will be described with reference to FIG.

図７は、従来の半導体装置の構成を示す図である。
図７において、従来の半導体装置では、半導体素子１０６とリード１０７とを接続するクリップ１００には素子接合部１０１とリード接合部１０２との間に延在するビーム部１０９を有しており、これらは一体に形成されている。さらに、クリップ１００には素子接合部１０１からビーム部１０９を含めてリード接合部１０２に至るまで、連続した貫通孔１０５が設けられている構造となっている。クリップ１００に貫通孔１０５が設けられることで、単に板状または帯状のクリップで接続する場合に比べ表面積を増大させることができる。その結果、クリップ１００を流れる電流の周波数が高くなり、表皮効果によって電流が主に導体の表面部分を流れるようになった場合であっても、電流の流通経路の抵抗を低減でき、高速スイッチングが可能となる。 FIG. 7 is a diagram showing a configuration of a conventional semiconductor device.
In FIG. 7, in the conventional semiconductor device, the clip 100 connecting the semiconductor element 106 and the lead 107 has a beam portion 109 extending between the element joint portion 101 and the lead joint portion 102. Are integrally formed. Further, the clip 100 has a structure in which a continuous through hole 105 is provided from the element joint portion 101 to the lead joint portion 102 including the beam portion 109. By providing the through hole 105 in the clip 100, the surface area can be increased as compared with the case of simply connecting with a plate-like or strip-like clip. As a result, the frequency of the current flowing through the clip 100 is increased, and even when the current mainly flows through the surface portion of the conductor due to the skin effect, the resistance of the current flow path can be reduced and high-speed switching can be achieved. It becomes possible.

特開２００９−４４３５号公報JP 2009-4435 A

しかしながら、従来の構成では、特性面における表皮効果の影響に対する抵抗の低減に効果を有するが、反面、素子接合部１０１及びリード接合部１０２の貫通孔１０５の内壁の接合部分などにおいて成形樹脂に気泡や未充填が発生することがあった。つまり、貫通孔１０５がクリップ１００及び半導体素子１０６またはリード１０７に囲まれ、開口部が貫通孔１０５上部及びビーム部１０９方向にしかないため、半導体装置の樹脂封止の際に、樹脂の流通経路が限定され、貫通孔１０５内において樹脂の気泡や未充填部分が生じていた。そのため、従来の半導体装置では、この気泡や未充填に起因する温度サイクル時における接合信頼性の低下や、熱抵抗の劣化とそれに伴う発熱による許容損失の増大などの特性・信頼性面の課題を有していた。   However, the conventional configuration is effective in reducing the resistance to the influence of the skin effect on the characteristic surface, but on the other hand, there is a bubble in the molding resin at the joint portion of the inner wall of the through hole 105 of the element joint portion 101 and the lead joint portion 102. Or unfilled. That is, since the through hole 105 is surrounded by the clip 100 and the semiconductor element 106 or the lead 107, and the opening is only in the upper part of the through hole 105 and the beam part 109, the resin flow path is used for resin sealing of the semiconductor device. It was limited, and resin bubbles and unfilled portions were generated in the through-hole 105. For this reason, conventional semiconductor devices have problems in characteristics and reliability, such as a decrease in bonding reliability during temperature cycles due to bubbles and unfilling, and a decrease in thermal resistance and an increase in allowable loss due to heat generation associated therewith. Had.

本発明は、上述の従来の課題を解決するもので、表皮効果の影響によるクリップの抵抗の増大を抑制しつつ、半導体装置の信頼性を維持することを目的とする。   An object of the present invention is to solve the above-described conventional problems, and to maintain the reliability of a semiconductor device while suppressing an increase in clip resistance due to the skin effect.

上記の目的を達成するために、本発明の半導体装置は、ダイパッド及び１または複数のリードからなるリードフレームと、前記ダイパッドに搭載された半導体素子と、前記リードと電気的に接続されて前記半導体素子が備える電極と、少なくとも１対の前記リードと前記電極とを電気的に接続するクリップと、前記クリップの電極側端部が前記電極から離れる方向に折り曲げられた屈曲部と、前記折り曲げ部の一部を含む前記クリップに形成される１または複数の貫通孔とを有することを特徴とする。   In order to achieve the above object, a semiconductor device of the present invention includes a lead frame including a die pad and one or a plurality of leads, a semiconductor element mounted on the die pad, and the semiconductor electrically connected to the leads. An electrode included in the element; a clip that electrically connects at least one pair of the lead and the electrode; a bent portion in which an electrode side end portion of the clip is bent away from the electrode; and It has one or a plurality of through holes formed in the clip including a part.

また、前記クリップの前記リード側の端部と前記貫通孔との間に形成される前記半導体素子と平行な平坦部をさらに有することが好ましい。
また、本発明の半導体装置は、半導体素子を載置するための第一パッド部を有するドレインリードと、前記第一パッド部に載置され、表面に第一電極及び第二電極を備える半導体素子と、第二パッド部を有するソースリードと、第三パッド部を有するゲートリードと、前記第一電極と前記第二パッド部とを電気的に接続するクリップと、前記クリップのドレインリード側端部が前記第一電極から離れる方向に曲げられた第一屈曲部と、前記第一屈折部の少なくとも一部を含み前記クリップに形成される１または複数の貫通孔と、前記第二電極と前記第三パッド部とを電気的に接続するワイヤと、前記半導体素子，前記ワイヤ及び前記クリップを封止する樹脂成型体とを有することを特徴とする。 Moreover, it is preferable to further have a flat part parallel to the semiconductor element formed between the lead side end of the clip and the through hole.
According to another aspect of the present invention, there is provided a semiconductor device including a drain lead having a first pad portion for placing a semiconductor element, and a first electrode and a second electrode placed on the first pad portion and having a first electrode and a second electrode on the surface. A source lead having a second pad portion, a gate lead having a third pad portion, a clip electrically connecting the first electrode and the second pad portion, and a drain lead side end portion of the clip Is bent in a direction away from the first electrode, one or more through holes formed in the clip including at least a part of the first refracting portion, the second electrode, and the first electrode It has a wire for electrically connecting the three pad portions, and a resin molded body for sealing the semiconductor element, the wire and the clip.

また、前記第一電極及び前記クリップが接合される素子接合部の第二パッド部側端部に前記クリップが前記第一電極から離れる方向に曲げられた第二屈曲部をさらに有することが好ましい。   In addition, it is preferable that the clip further has a second bent portion bent in a direction away from the first electrode at an end portion on the second pad portion side of the element bonding portion to which the first electrode and the clip are bonded.

また、前記クリップ及び前記第二パッド部が接合されるリード接合部と前記第二屈曲部との間に形成される前記半導体素子と平行な前記クリップの平坦部をさらに有し、前記貫通孔が前記第一屈折部の少なくとも一部を含んで前記ドレインリード側端部と前記平坦部との間に形成されることが好ましい。   The clip further includes a flat portion of the clip parallel to the semiconductor element formed between the lead joint portion to which the clip and the second pad portion are joined and the second bent portion, and the through hole It is preferable that it is formed between the drain lead side end portion and the flat portion including at least a part of the first refracting portion.

また、本発明の半導体装置は、半導体素子を載置するための第一パッド部を有するドレインリードと、前記第一パッド部に載置され、表面に第一電極及び第二電極を備える半導体素子と、第二パッド部を有するソースリードと、第三パッド部を有するゲートリードと、前記第一電極と前記第二パッド部とを電気的に接続するクリップと、前記半導体素子及び前記ソースリードから離間される前記クリップの中央部と、前記中央部と接続されて前記第一電極と電気的に接続する１または複数の前記クリップの第一くし部と、前記中央部と接続されて前記第二パッド部と電気的に接続する１または複数の前記クリップの第二くし部と、前記第二電極と前記第三パッド部とを電気的に接続するワイヤと、前記半導体素子，前記ワイヤ及び前記クリップを封止する樹脂成型体とを有することを特徴とする。   According to another aspect of the present invention, there is provided a semiconductor device including a drain lead having a first pad portion for placing a semiconductor element, and a first electrode and a second electrode placed on the first pad portion and having a first electrode and a second electrode on the surface. A source lead having a second pad portion, a gate lead having a third pad portion, a clip electrically connecting the first electrode and the second pad portion, and the semiconductor element and the source lead A central portion of the clip that is spaced apart, a first comb portion of one or more of the clips that is connected to the central portion and electrically connected to the first electrode, and is connected to the central portion and the second A second comb portion of the one or more clips electrically connected to the pad portion, a wire electrically connecting the second electrode and the third pad portion, the semiconductor element, the wire, and the clip; And having a resin molded body for sealing the.

また、前記第一くし部及び前記第二くし部のそれぞれが、前記中央部をはさんで左右に形成され、左右を一対とし、少なくとも前記第一くし部が二対以上設けられても良い。
また、前記中央部に前記半導体素子と平行な平坦部をさらに有することが好ましい。 Further, each of the first comb part and the second comb part may be formed on the left and right sides of the central part, the left and right may be paired, and at least two pairs of the first comb parts may be provided.
Moreover, it is preferable to further have a flat part parallel to the semiconductor element in the central part.

さらに、本発明の半導体装置の製造方法は、前記半導体装置の製造方法であって、前記半導体素子を前記第一パッド部に載置する工程と、前記クリップに形成された前記平坦面を真空吸着して前記クリップを移動させ、前記第一電極及び前記第二パッド部上に前記クリップを載置する工程と、前記第一電極と前記第二パッド部とを前記クリップにて電気的に接続する工程と、前記第二電極と前記第三パッド部とを前記ワイヤにて電気的に接続する工程と、前記半導体素子，前記クリップ及び前記ワイヤを樹脂封止する工程とを有することを特徴とする。   Furthermore, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device, the step of placing the semiconductor element on the first pad portion, and vacuum suction of the flat surface formed on the clip. The clip is moved, and the step of placing the clip on the first electrode and the second pad portion is electrically connected to the first electrode and the second pad portion by the clip. A step of electrically connecting the second electrode and the third pad portion with the wire; and a step of resin-sealing the semiconductor element, the clip, and the wire. .

また、前記樹脂封止する工程において、樹脂を前記ドレインリード側から注入することが好ましい。   In the resin sealing step, it is preferable to inject resin from the drain lead side.

以上のように、板状のクリップとなる接続部材に貫通孔やくし部を設けて表面積を増大されたクリップを配置することで、表皮効果の影響によるクリップの抵抗の増大を抑制するとともに、クリップの側面側に開口部を設けることにより、貫通孔内やクリップ下部における封止樹脂の空気の抱き込みによる気泡や未充填の発生を防止することができるので、製品品質の信頼性を高めることができる。   As described above, by arranging a clip having an increased surface area by providing a through-hole or a comb portion on a connection member that becomes a plate-like clip, an increase in the resistance of the clip due to the influence of the skin effect is suppressed, and By providing an opening on the side surface, it is possible to prevent the generation of bubbles and unfilled air in the through hole and the lower part of the clip due to the entrapment of air in the sealing resin, thereby improving the reliability of product quality. .

本発明の半導体装置の構成を例示する図FIG. 6 illustrates a structure of a semiconductor device of the present invention. 本発明の実施の形態１における半導体装置の内部構造を示す上面図The top view which shows the internal structure of the semiconductor device in Embodiment 1 of this invention 本発明の実施の形態１における半導体装置の内部構造を示す断面図Sectional drawing which shows the internal structure of the semiconductor device in Embodiment 1 of this invention 本発明の実施の形態２における半導体装置の内部構造を示す上面図The top view which shows the internal structure of the semiconductor device in Embodiment 2 of this invention 本発明の実施の形態２における半導体装置の内部構造を示す側面図The side view which shows the internal structure of the semiconductor device in Embodiment 2 of this invention 本発明の半導体装置の製造方法を示すフロー図Flow chart showing a method for manufacturing a semiconductor device of the present invention 従来の半導体装置の構成を示す図The figure which shows the structure of the conventional semiconductor device

本発明の半導体装置は、半導体素子の少なくとも１つの電極をクリップを介してリードに接続するものであり、クリップには、電極側のクリップの端部を折り曲げて折曲部を形成し、電極とクリップとの接続領域及び折曲部の少なくとも一部を含む領域に１つ以上の貫通孔を設けることを特徴とする。さらに、リードとの接続領域と電極との接続領域との間の貫通孔が形成されていない領域に平坦部を設けることがより好ましい。   The semiconductor device of the present invention connects at least one electrode of a semiconductor element to a lead through a clip. The clip is formed by bending an end of the electrode side clip to form a bent portion. One or more through holes are provided in a region including at least a part of a connection region with a clip and a bent portion. Furthermore, it is more preferable to provide a flat portion in a region where a through hole is not formed between the lead connection region and the electrode connection region.

以下、図１を用いて本発明の半導体装置におけるクリップの構成を説明する。
図１は本発明の半導体装置の構成を例示する図であり、図１（ａ）は平面図、図１（ｂ）は図１（ａ）のＸ−Ｘ’断面図であり、樹脂を透視した構成を示している。 Hereinafter, the structure of the clip in the semiconductor device of the present invention will be described with reference to FIG.
1A and 1B are diagrams illustrating the configuration of a semiconductor device according to the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX ′ of FIG. Shows the configuration.

本発明の半導体装置は、図１に示すように、少なくとも１つの電極１０を備える半導体素子１１と、半導体素子１１を搭載するダイパッドとリードとを備えるリードフレーム１２と、電極１０とリードとを電気的に接続するクリップ１３と、半導体素子１１を封止する樹脂１６とから構成される。本発明の半導体装置の特徴は、クリップ１３に１つ以上の貫通孔１４と、半導体素子１１上部のクリップ１３を端部近傍の折り曲げ部１５で折り曲げて形成した屈曲部１０４とを設け、貫通孔１４がクリップ１３と電極１０との接続領域から折り曲げ部１５を超えて屈曲部１０４の一部まで形成されていることである。   As shown in FIG. 1, the semiconductor device of the present invention electrically connects a semiconductor element 11 including at least one electrode 10, a lead frame 12 including a die pad and leads on which the semiconductor element 11 is mounted, and the electrode 10 and leads. The clip 13 is connected to the semiconductor device 11 and the resin 16 is used to seal the semiconductor element 11. A feature of the semiconductor device of the present invention is that the clip 13 is provided with one or more through holes 14 and a bent portion 104 formed by bending the clip 13 on the semiconductor element 11 at a bent portion 15 in the vicinity of the end portion. 14 is formed from the connection region between the clip 13 and the electrode 10 to the bent portion 104 beyond the bent portion 15.

このように、クリップ１３に貫通孔１４を形成することにより、クリップ１３の表面積を増大させて電流流通経路を拡大し、表皮効果を低減して電気抵抗を低減することができる。また、貫通孔１４が形成された領域に折曲部１０４を形成することにより、樹脂成型の際に、折り曲げることによって露出したクリップ１３の折曲部１０４の裏面側からも貫通孔１４内に樹脂が流入するため、貫通孔１４内における樹脂の気泡や未充填を抑制し、半導体装置の信頼性を向上させることができる。   Thus, by forming the through hole 14 in the clip 13, the surface area of the clip 13 can be increased to expand the current flow path, the skin effect can be reduced, and the electrical resistance can be reduced. Further, by forming the bent portion 104 in the region where the through hole 14 is formed, the resin is also introduced into the through hole 14 from the back surface side of the bent portion 104 of the clip 13 exposed by bending at the time of resin molding. Therefore, it is possible to suppress the bubble and unfilling of the resin in the through hole 14 and improve the reliability of the semiconductor device.

さらに、クリップ１３の半導体素子１１との接続領域からリードとの接続領域までの間に平坦部１７を設け、平坦部１７には貫通孔１４を設けない構成としても良い。従来の半導体装置においては、クリップの素子接合部からビーム部及びリード接合部にかけて貫通孔が設けられているため、クリップ上面の平坦面面積が小さく、クリップを半導体素子上に搭載する際に真空吸着といった一般的な手法によるピックアップ動作がうまく行えず、クリップの落下や位置ずれといった加工不良が発生するという製造工程での課題も有していた。これに対して、クリップ１３に貫通孔１４を設けない平坦部１７を形成することにより、クリップ１３を平坦部１７で真空吸着することができ、半導体素子１１へのクリップ１３装着時にクリップ１３の落下や位置ずれを防止し、加工不良を低減させることができる。また、平坦部１７の形成のためにクリップ１３を折り曲げ部１８で曲げ加工して屈曲部２１４する際に、貫通孔１４の形成領域で曲げ加工を行うことにより、樹脂成型の際に、折曲部１０４からだけでなく、この折曲部２１４からも貫通孔１４内に樹脂が流入し、より樹脂の気泡や未充填を抑制することができる。   Further, the flat portion 17 may be provided between the connection region of the clip 13 with the semiconductor element 11 and the connection region with the lead, and the through hole 14 may not be provided in the flat portion 17. In the conventional semiconductor device, since the through hole is provided from the element joint portion of the clip to the beam portion and the lead joint portion, the flat surface area of the upper surface of the clip is small, and vacuum suction is performed when the clip is mounted on the semiconductor element. Such a general pick-up operation cannot be performed well, and there is a problem in the manufacturing process that a processing failure such as dropping or misalignment of the clip occurs. On the other hand, by forming the flat portion 17 in which the through hole 14 is not provided in the clip 13, the clip 13 can be vacuum-sucked by the flat portion 17, and the clip 13 is dropped when the clip 13 is attached to the semiconductor element 11. And misalignment can be prevented, and processing defects can be reduced. Further, when the clip 13 is bent at the bent portion 18 to form the bent portion 214 in order to form the flat portion 17, the bent portion is bent at the formation region of the through hole 14, thereby bending the resin molding. The resin flows into the through-hole 14 not only from the portion 104 but also from the bent portion 214, so that bubbles and unfilling of the resin can be further suppressed.

以上の半導体装置において、複数の電極を有する場合、クリップ１３で接続する電極以外の電極は、ワイヤ等任意のボンディングを行うことができる。また、電極の数も任意であり、少なくともクリップ１３で接続する電極を含めば良い。また、ダイパッドはリードと独立していても良いし、１つのリード上に形成されても良い。   In the above semiconductor device, when a plurality of electrodes are provided, electrodes other than the electrodes connected by the clip 13 can be bonded arbitrarily such as wires. Also, the number of electrodes is arbitrary, and at least the electrodes connected by the clip 13 may be included. Further, the die pad may be independent from the leads, or may be formed on one lead.

以下、ソース端子，ドレイン端子，ゲート端子の３端子から成る電池回路用半導体装置を例に各実施の形態について、図面を参照しながら説明する。
（実施の形態１）
まず、図２，図３を用いて、実施の形態１における半導体装置の構成について説明する。 Hereinafter, each embodiment will be described with reference to the drawings, taking as an example a semiconductor device for a battery circuit comprising three terminals of a source terminal, a drain terminal, and a gate terminal.
(Embodiment 1)
First, the configuration of the semiconductor device in the first embodiment will be described with reference to FIGS.

図２は本発明の実施の形態１における半導体装置の内部構造を示す上面図であり、樹脂を透視して示している。図３は本発明の実施の形態１における半導体装置の内部構造を示す断面図であり、図２のＹ−Ｙ’断面図である。図２、図３において、図１と同じ構成要素については同じ符号を用い、説明を省略する。   FIG. 2 is a top view showing the internal structure of the semiconductor device according to the first embodiment of the present invention, and shows the resin through. FIG. 3 is a cross-sectional view showing the internal structure of the semiconductor device according to the first embodiment of the present invention, and is a Y-Y ′ cross-sectional view of FIG. 2. 2 and 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

図２，図３に示すように、半導体装置はドレインリード２０７とソースリード２０８、ゲートリード２０９、半導体素子１０６、クリップ２００、ワイヤ２０１及びエポキシ系熱可塑性の樹脂成型体２１０により構成されている。各リードはＣｕまたはＣｕを主成分とする合金の素材にＡｇめっきが施されており、それぞれ、半導体素子１０６のドレイン電極と接続する第一パッド部２０２、ソース電極と接続する第二パッド部２０３、ゲート電極と接続する第三パッド部２０４を有している。それぞれのパッド部分からはドレインリード２０７とソースリード２０８及びゲートリード２０９が延在され、樹脂成型体２１０から突出してリード端子を構成している。半導体素子１０６は、ソース、ゲート及びドレインより構成されるＭＯＳ−ＦＥＴタイプが用いられる。また、エポキシ系熱可塑性の樹脂成型体２１０から突出した各リードには外装メッキとしてプリント基板との実装に適したＡｕやＳｎなどのめっきが施されている。   As shown in FIGS. 2 and 3, the semiconductor device includes a drain lead 207, a source lead 208, a gate lead 209, a semiconductor element 106, a clip 200, a wire 201, and an epoxy-based thermoplastic resin molding 210. Each lead is made of Cu or an alloy material containing Cu as a main component, and Ag plating is performed. The first pad portion 202 connected to the drain electrode of the semiconductor element 106 and the second pad portion 203 connected to the source electrode, respectively. And a third pad portion 204 connected to the gate electrode. A drain lead 207, a source lead 208, and a gate lead 209 extend from each pad portion, and project from the resin molding 210 to constitute a lead terminal. The semiconductor element 106 is a MOS-FET type composed of a source, a gate, and a drain. In addition, each lead protruding from the epoxy-based thermoplastic resin molding 210 is plated with Au, Sn, or the like suitable for mounting on a printed circuit board as exterior plating.

半導体素子１０６の表面には、第一電極２０５と該第一電極２０５と絶縁分離された第二電極２０６が形成されている。第一電極２０５は半導体素子の表面の大部分を占めており、第一電極２０５はソース電極、第二電極２０６はゲート電極、半導体素子１０６の裏面側の電極（図示せず）はドレイン電極となっている。   A first electrode 205 and a second electrode 206 insulated from the first electrode 205 are formed on the surface of the semiconductor element 106. The first electrode 205 occupies most of the surface of the semiconductor element, the first electrode 205 is a source electrode, the second electrode 206 is a gate electrode, and an electrode (not shown) on the back side of the semiconductor element 106 is a drain electrode. It has become.

第一パッド部２０２は半導体素子１０６の裏面側の電極と高融点半田やＡｇペーストといった導電性接合剤を介して接合されている。第二パッド部２０３と半導体素子１０６上の第一電極２０５とは、高融点半田やＡｇペーストといった導電性接合剤を介してクリップ２００により電気的に接続されている。第三パッド２０４と第二電極２０６とは、ＡｕやＣｕ等のワイヤ２０１にて電気的に接続されている。   The first pad portion 202 is bonded to the electrode on the back surface side of the semiconductor element 106 via a conductive bonding agent such as high melting point solder or Ag paste. The second pad portion 203 and the first electrode 205 on the semiconductor element 106 are electrically connected by the clip 200 via a conductive bonding agent such as high melting point solder or Ag paste. The third pad 204 and the second electrode 206 are electrically connected by a wire 201 such as Au or Cu.

クリップ２００は、半導体素子１０６の第一電極２０５と接続される素子接合部２１１と、ソースリード２０８の第二パッド部２０３に接合されるリード接合部２１２と、曲げ加工により形成された凸部２１３からなり、Ｃｕ材にて形成されている。また、クリップ２００のドレインリード２０７側端部には、上方へ曲げ加工された屈曲部１０４を有し、該屈曲部１０４から凸部２１３の第一電極２０５側まで、１または複数の貫通孔２１５が設けられている。   The clip 200 includes an element joint portion 211 connected to the first electrode 205 of the semiconductor element 106, a lead joint portion 212 joined to the second pad portion 203 of the source lead 208, and a convex portion 213 formed by bending. It consists of Cu material. Further, the end of the clip 200 on the drain lead 207 side has a bent portion 104 bent upward, and one or a plurality of through holes 215 from the bent portion 104 to the first electrode 205 side of the convex portion 213. Is provided.

クリップ２００の貫通孔２１５はドレイン端子側と凸部２１３側で屈曲され、例えば、成形樹脂に含まれるフィラー径が０．０８ｍｍ〜０．３７ｍｍの場合、高さが、前記半導体素子上面から０．３７ｍｍ以上の貫通孔２１５の開口部２１６を有している。この開口部２１６の値は、成形樹脂に含まれるフィラーの最大径を考慮し、成形樹脂が開口部２１６を阻害されることなく流動できる大きさを下限値とし、上限値はクリップ２００の屈曲部１０４が凸部２１３を超えない範囲とする。   The through-hole 215 of the clip 200 is bent on the drain terminal side and the convex portion 213 side. For example, when the filler diameter contained in the molding resin is 0.08 mm to 0.37 mm, the height is 0. 0 from the upper surface of the semiconductor element. It has an opening 216 of a through hole 215 of 37 mm or more. The value of the opening 216 takes into consideration the maximum diameter of the filler contained in the molding resin, the size at which the molding resin can flow without being obstructed by the opening 216 being the lower limit, and the upper limit is the bent portion of the clip 200 The range 104 does not exceed the convex portion 213.

かかる構成によれば、クリップ２００の凸部２１３の下部に空間が形成され、且つ、クリップ２００の貫通孔２１５がドレインリード２０７側と凸部２１３側で屈曲されることで、半導体素子１０６との素子接合部２１１周辺のクリップ２００が開口されるため、樹脂流動経路が貫通孔２１５上部以外に開口部２１６からも確保され、トランスファーモールドによる樹脂成形時の封止樹脂の流動が阻害されることなく貫通孔２１５の内部まで確実に充填されるので、成形樹脂の空気の抱き込みによる気泡や未充填の発生が抑制される。それにより、気泡や未充填に起因する温度サイクル時における接合信頼性の低下や、熱抵抗の劣化とそれに伴う発熱による許容損失の増大などの特性・信頼性を向上することできる。さらに、凸部２１３の上部に貫通孔２１５を形成せず、全域に平坦面を形成することにより、クリップ２００を半導体素子１０６上に搭載する際の真空吸着によるピックアップ動作を容易に行うことができ、組立搬送中のクリップ２００の落下や搭載時の位置ずれといった加工不良の発生を防ぐことができる。   According to this configuration, a space is formed below the convex portion 213 of the clip 200, and the through hole 215 of the clip 200 is bent on the drain lead 207 side and the convex portion 213 side. Since the clip 200 around the element joint portion 211 is opened, a resin flow path is secured from the opening 216 in addition to the upper portion of the through hole 215, and the flow of the sealing resin at the time of resin molding by transfer molding is not hindered. Since the inside of the through-hole 215 is reliably filled, generation of air bubbles and unfilling due to the inclusion of air in the molding resin is suppressed. As a result, it is possible to improve characteristics / reliability such as a decrease in bonding reliability during a temperature cycle due to bubbles or unfilling, a deterioration in thermal resistance, and an increase in allowable loss due to heat generation associated therewith. Furthermore, by forming the flat surface over the entire area without forming the through hole 215 in the upper portion of the convex portion 213, it is possible to easily perform a pickup operation by vacuum suction when the clip 200 is mounted on the semiconductor element 106. In addition, it is possible to prevent the occurrence of processing defects such as dropping of the clip 200 during assembly and transport and positional deviation during mounting.

また、貫通孔２１５を素子接合部２１１に設けることでクリップ２００の表面積を増大できるので、表皮効果の影響による抵抗の増大を抑制できる。
なお、本実施の形態の図２において、貫通孔２１５の形状を矩形としているが、楕円形状としても良く、クリップ２００の表面積を増大させるための貫通孔であれば、その形状は任意である。
（実施の形態２）
次に、図４，図５を用いて実施の形態２における半導体装置の構造について説明する。 Moreover, since the surface area of the clip 200 can be increased by providing the through-hole 215 in the element joint portion 211, an increase in resistance due to the influence of the skin effect can be suppressed.
In FIG. 2 of the present embodiment, the shape of the through hole 215 is rectangular. However, the shape may be arbitrary as long as it is an elliptical shape and the through hole for increasing the surface area of the clip 200 is used.
(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described with reference to FIGS.

図４は本発明の実施の形態２の半導体装置の内部構造を示す上面図である。図５は本発明の実施の形態２における半導体装置の内部構造を示す側面図であり、図５（ａ）は図４におけるＺ方向から見た半導体装置の内部構造を示す透視側面図、図５（ｂ）は図４におけるＺ’方向から見た半導体装置の内部構造を示す透視側面図である。図４及び図５において、図２および図３と同じ構成要素については同じ符号を用い、説明を省略する。   FIG. 4 is a top view showing the internal structure of the semiconductor device according to the second embodiment of the present invention. 5 is a side view showing the internal structure of the semiconductor device according to the second embodiment of the present invention, and FIG. 5A is a perspective side view showing the internal structure of the semiconductor device as viewed from the Z direction in FIG. FIG. 5B is a transparent side view showing the internal structure of the semiconductor device as viewed from the Z ′ direction in FIG. 4. 4 and 5, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof is omitted.

図４において、クリップ３００はＣｕ材で形成され、半導体素子１０６からソースリード２０８までの略中央部が凸状に形成された凸部１０８を有し、素子接合部３１１及びリード接合部３１２が凸部１０８から左右にくし状に延在され、第一電極２０５及び第二パッド部２０３に高融点半田やＡｇペーストといった導電性接合剤により接合されている。つまり、クリップ３００は、第一電極２０５上から第二パッド部２０３上にかけて半導体素子１０６及びソースリード２０８と間隔を空けて形成された中央部３０１と、中央部３０１から延在されて第一電極２０５と接続する素子接合部３１１を備える第一くし部３０２と、中央部３０１から延在されて第二パッド部２０３と接続するリード接合部３１２を備える第二くし部３０３とから構成される。さらに第一くし部３０２は第一電極２０５との接続を考慮し、左右対称または左右非対称に設けてもよい。   In FIG. 4, the clip 300 is formed of a Cu material, and has a convex portion 108 in which a substantially central portion from the semiconductor element 106 to the source lead 208 is formed in a convex shape, and the element joint portion 311 and the lead joint portion 312 are convex. It extends from the portion 108 to the left and right in a comb shape, and is bonded to the first electrode 205 and the second pad portion 203 by a conductive bonding agent such as high melting point solder or Ag paste. That is, the clip 300 includes a central portion 301 that is spaced from the semiconductor element 106 and the source lead 208 from the first electrode 205 to the second pad portion 203, and extends from the central portion 301 to the first electrode. 205 includes a first comb portion 302 having an element joint portion 311 connected to 205 and a second comb portion 303 having a lead joint portion 312 extending from the central portion 301 and connected to the second pad portion 203. Further, the first comb portion 302 may be provided symmetrically or asymmetrically in consideration of the connection with the first electrode 205.

かかる構成によれば、前記クリップ３００の素子接合部３１１を備える第一くし部３０２がくし型の形状を成しており、表面積を増大できるので、表皮効果の影響による抵抗の増大を抑制できる。さらに、素子接合部３１１とリード接合部３１２を除くクリップ３００が中央部３０１が突出する凸形状を成しており、下部に空間が形成されているため、トランスファーモールドによる樹脂成形時の封止樹脂の流動が阻害されることなく、クリップ３００の下部まで確実に充填されるので、成形樹脂の空気の抱き込みによる気泡や未充填の発生がない。そのため、気泡や未充填に起因する温度サイクル時における接合信頼性の低下や、熱抵抗の劣化とそれに伴う発熱による許容損失の増大などの特性・信頼性を向上することができる。さらに、クリップ３００の中央に設けられた凸部１０８の上面に一様な平坦面を形成することにより、クリップ３００を半導体素子１０６上に搭載する際の真空吸着によるピックアップ動作を容易に行うことができ、クリップ３００の落下や位置ずれといった加工不良の発生を防ぐことができる。   According to this configuration, the first comb portion 302 including the element joint portion 311 of the clip 300 has a comb shape, and the surface area can be increased, so that an increase in resistance due to the influence of the skin effect can be suppressed. Further, since the clip 300 excluding the element joint portion 311 and the lead joint portion 312 has a convex shape from which the central portion 301 protrudes and a space is formed in the lower portion, a sealing resin at the time of resin molding by transfer molding Therefore, the lower portion of the clip 300 is reliably filled without hindering the flow of air, so that there is no generation of air bubbles or unfilled due to the inclusion of the molding resin air. Therefore, it is possible to improve characteristics / reliability such as a decrease in bonding reliability during a temperature cycle due to bubbles or unfilling, a deterioration in thermal resistance, and an increase in allowable loss due to heat generation associated therewith. Further, by forming a uniform flat surface on the upper surface of the convex portion 108 provided at the center of the clip 300, it is possible to easily perform a pickup operation by vacuum suction when the clip 300 is mounted on the semiconductor element 106. It is possible to prevent the occurrence of processing defects such as dropping or misalignment of the clip 300.

上述の実施の形態１及び実施の形態２において、ドレインリード２０７とソースリード２０８及びゲートリード２０９は材質をＣｕまたＣｕを主成分とする合金としたがＦｅやＦｅを主成分とする合金などでも良く、また、めっき皮膜をＡｇめっきとしているが、Ｐｄめっき、Ａｕめっき、でも有効である。   In the first embodiment and the second embodiment described above, the drain lead 207, the source lead 208, and the gate lead 209 are made of Cu or an alloy containing Cu as a main component. Also, although the plating film is Ag plating, Pd plating and Au plating are also effective.

また、クリップの材質としてＣｕ材としたが、必要な導電率や熱伝導率を確保できれば、Ａｌやクラッド材といった材質でも有効である。
次に、図２，図６を用いて本発明の半導体装置の製造方法について説明する。ここでは、実施の形態１の図２を例に説明するが、実施の形態２の図４に係る半導体装置も製造方法は同様である。 Further, although the material of the clip is a Cu material, a material such as Al or a clad material is also effective as long as necessary conductivity and thermal conductivity can be secured.
Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. Here, FIG. 2 of the first embodiment will be described as an example, but the manufacturing method of the semiconductor device according to FIG. 4 of the second embodiment is the same.

図６は本発明の半導体装置の製造方法を示すフロー図である。
図６に示すように、まず、シリコンウエハにパワー系ＭＯＳ−ＦＥＴを形成した後、ダイシング工程にて個片にカットされた半導体素子を作製する（ステップＳ１）。 FIG. 6 is a flowchart showing a method for manufacturing a semiconductor device of the present invention.
As shown in FIG. 6, first, after forming a power MOS-FET on a silicon wafer, a semiconductor element cut into individual pieces in a dicing process is produced (step S1).

次に、ドレインリード２０７の第一パッド部２０２に、半導体素子１０６を高融点半田やＡｇペーストなどの導電性接合剤を用いて搭載接合する（ステップＳ２）。
次に、半導体素子１０６の第二電極２０６と第三パッド２０４をＡｕやＣｕ等のワイヤ２０１により接続する（ステップＳ３）。 Next, the semiconductor element 106 is mounted and bonded to the first pad portion 202 of the drain lead 207 using a conductive bonding agent such as high melting point solder or Ag paste (step S2).
Next, the second electrode 206 and the third pad 204 of the semiconductor element 106 are connected by a wire 201 such as Au or Cu (step S3).

続いて、凸部２１３の上面の平坦面を真空吸着コレットにて吸着し、クリップ２００を半導体素子１０６の第一パッド部２０２とソースリード２０８の第二パッド部２０３に接続させ、高融点半田やＡｇペーストなどの導電性接合剤を用いて接合する（ステップＳ４）。クリップ３００の搭載は凸部２１３上面に設けた比較的広い平坦面により、真空吸着によるピックアップ動作を容易に行うことができ、搬送中のクリップ落下や、搭載後の位置ずれの発生を防止することができる。また、ワイヤボンディングとクリップ接合は、どちらの工程を先に行っても構わないが、クリップ接合剤を硬化する際に溶剤などの揮発により、第二電極２０６と第三パッド部２０４のボンディング面が汚染され、ワイヤボンディング不良が発生する可能性が考えられるので、ワイヤボンディングを先に行うのが好ましい。   Subsequently, the flat surface on the upper surface of the convex portion 213 is adsorbed by a vacuum adsorption collet, and the clip 200 is connected to the first pad portion 202 of the semiconductor element 106 and the second pad portion 203 of the source lead 208, Bonding is performed using a conductive bonding agent such as an Ag paste (step S4). The clip 300 can be mounted on the upper surface of the convex portion 213 with a relatively wide flat surface, so that the pickup operation by vacuum suction can be easily performed, and the clip is not dropped during transport and the position shift after mounting is prevented. Can do. Either wire bonding or clip bonding may be performed first, but when the clip bonding agent is cured, the bonding surfaces of the second electrode 206 and the third pad portion 204 are caused by volatilization of a solvent or the like. Since there is a possibility of contamination and the occurrence of defective wire bonding, wire bonding is preferably performed first.

次に、上記で組み立てられた集合体をトランスファーモールドの金型内に載置し、金型のドレインリード２０７側より封止樹脂を注入し、樹脂成型体２１０を形成する（ステップＳ５）。   Next, the assembly assembled as described above is placed in a transfer mold mold, and a sealing resin is injected from the drain lead 207 side of the mold to form a resin molded body 210 (step S5).

その後、メッキ工程（ステップＳ６）、マーキング工程（ステップＳ７）、検査工程（ステップＳ８）を経て、半導体装置が完成する。
以上のように、本発明の半導体装置の製造方法では、表面積を増大させたクリップを用いて抵抗を低減させながら、クリップの吸着時のクリップの落下を防止すると共に、クリップ搭載を精度よく行えるので加工不良をなくすことができる。また、クリップ２００の形状を考慮し、ドレインリード２０７側から封止樹脂を注入することにより、クリップ２００に設けた貫通孔２１５の屈曲部１０４に形成された開口部２１６及び凸部２１３または１０８（図５（ｂ）参照）の下部の空間を封止樹脂が阻害されることなく流動できるので、空気の抱き込みによる気泡や樹脂の未充填の発生を防止することができ、信頼性の高い半導体装置を提供することが可能となる。 Thereafter, the semiconductor device is completed through a plating process (step S6), a marking process (step S7), and an inspection process (step S8).
As described above, in the method of manufacturing a semiconductor device according to the present invention, the clip can be mounted with high accuracy while preventing the clip from dropping when the clip is attracted while reducing the resistance by using the clip having an increased surface area. Processing defects can be eliminated. Further, in consideration of the shape of the clip 200, by injecting sealing resin from the drain lead 207 side, the opening 216 and the convex portion 213 or 108 (formed in the bent portion 104 of the through hole 215 provided in the clip 200 ( Since the sealing resin can flow without being obstructed in the lower space of FIG. 5B, it is possible to prevent the occurrence of bubbles and unfilled resin due to air inclusion, and a highly reliable semiconductor An apparatus can be provided.

本発明は、表皮効果の影響によるクリップの抵抗の増大を抑制しつつ、半導体装置の信頼性を維持することができ、半導体素子とリードがクリップによって接続された構造を有する半導体装置とその製造方法等に有用である。   The present invention can maintain the reliability of a semiconductor device while suppressing an increase in resistance of the clip due to the effect of the skin effect, and a semiconductor device having a structure in which a semiconductor element and a lead are connected by a clip, and a method for manufacturing the same Etc. are useful.

１０ 電極
１１ 半導体素子
１２ リードフレーム
１３ クリップ
１４ 貫通孔
１５ 折り曲げ部
１６ 樹脂
１７ 平坦部
１８ 折り曲げ部
１００ クリップ
１０１ 素子接合部
１０２ リード接合部
１０４ 屈曲部
１０５ 貫通孔
１０６ 半導体素子
１０７ リード
１０８ 凸部
１０９ ビーム部
２００ クリップ
２０１ ワイヤ
２０２ 第一パッド部
２０３ 第二パッド部
２０４ 第三パッド部
２０５ 第一電極
２０６ 第二電極
２０７ ドレインリード
２０８ ソースリード
２０９ ゲートリード
２１０ 樹脂成型体
２１１ 素子接合部
２１２ リード接合部
２１３ 凸部
２１４ 屈曲部
２１５ 貫通孔
２１６ 開口部
３００ クリップ
３０１ 中央部
３０２ 第一くし部
３０３ 第二くし部
３１１ 素子接合部
３１２ リード接合部 DESCRIPTION OF SYMBOLS 10 Electrode 11 Semiconductor element 12 Lead frame 13 Clip 14 Through-hole 15 Bending part 16 Resin 17 Flat part 18 Bending part 100 Clip 101 Element joint part 102 Lead joint part 104 Bending part 105 Through-hole 106 Semiconductor element 107 Lead 108 Convex part 109 Beam Part 200 Clip 201 Wire 202 First pad part 203 Second pad part 204 Third pad part 205 First electrode 206 Second electrode 207 Drain lead 208 Source lead 209 Gate lead 210 Resin molded body 211 Element joint part 212 Lead joint part 213 Convex part 214 Bent part 215 Through hole 216 Opening part 300 Clip 301 Central part 302 First comb part 303 Second comb part 311 Element joint part 312 Lead joint part

Claims (10)

ダイパッド及び１または複数のリードからなるリードフレームと、
前記ダイパッドに搭載された半導体素子と、
前記リードと電気的に接続されて前記半導体素子が備える電極と、
少なくとも１対の前記リードと前記電極とを電気的に接続するクリップと、
前記クリップの電極側端部が前記電極から離れる方向に折り曲げられた屈曲部と、
前記折り曲げ部の一部を含む前記クリップに形成される１または複数の貫通孔と
を有することを特徴とする半導体装置。 A lead frame comprising a die pad and one or more leads;
A semiconductor element mounted on the die pad;
An electrode electrically connected to the lead and provided in the semiconductor element;
A clip electrically connecting at least one pair of the leads and the electrode;
A bent portion where the electrode side end of the clip is bent in a direction away from the electrode;
One or a plurality of through holes formed in the clip including a part of the bent portion. 前記クリップの前記リード側の端部と前記貫通孔との間に形成される前記半導体素子と平行な平坦部をさらに有することを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, further comprising a flat portion parallel to the semiconductor element formed between the lead-side end portion of the clip and the through hole. 半導体素子を載置するための第一パッド部を有するドレインリードと、
前記第一パッド部に載置され、表面に第一電極及び第二電極を備える半導体素子と、
第二パッド部を有するソースリードと、
第三パッド部を有するゲートリードと、
前記第一電極と前記第二パッド部とを電気的に接続するクリップと、
前記クリップのドレインリード側端部が前記第一電極から離れる方向に曲げられた第一屈曲部と、
前記第一屈折部の少なくとも一部を含み前記クリップに形成される１または複数の貫通孔と、
前記第二電極と前記第三パッド部とを電気的に接続するワイヤと、
前記半導体素子，前記ワイヤ及び前記クリップを封止する樹脂成型体と
を有することを特徴とする半導体装置。 A drain lead having a first pad portion for mounting a semiconductor element;
A semiconductor element mounted on the first pad portion and having a first electrode and a second electrode on the surface;
A source lead having a second pad portion;
A gate lead having a third pad portion;
A clip for electrically connecting the first electrode and the second pad portion;
A first bent portion where the drain lead side end of the clip is bent in a direction away from the first electrode;
One or more through holes formed in the clip including at least a part of the first refracting portion;
A wire for electrically connecting the second electrode and the third pad portion;
A semiconductor device comprising: a resin molded body for sealing the semiconductor element, the wire, and the clip. 前記第一電極及び前記クリップが接合される素子接合部の第二パッド部側端部に前記クリップが前記第一電極から離れる方向に曲げられた第二屈曲部をさらに有することを特徴とする請求項３記載の半導体装置。   The clip further includes a second bent portion that is bent in a direction away from the first electrode at an end of the element bonding portion to which the first electrode and the clip are bonded. Item 4. The semiconductor device according to Item 3. 前記クリップ及び前記第二パッド部が接合されるリード接合部と前記第二屈曲部との間に形成される前記半導体素子と平行な前記クリップの平坦部をさらに有し、前記貫通孔が前記第一屈折部の少なくとも一部を含んで前記ドレインリード側端部と前記平坦部との間に形成されることを特徴とする請求項４記載の半導体装置。   The clip further includes a flat portion of the clip parallel to the semiconductor element formed between the lead joint portion to which the clip and the second pad portion are joined, and the second bent portion, and the through hole has the first hole. 5. The semiconductor device according to claim 4, wherein the semiconductor device is formed between the drain lead side end portion and the flat portion including at least a part of the one refracting portion. 半導体素子を載置するための第一パッド部を有するドレインリードと、
前記第一パッド部に載置され、表面に第一電極及び第二電極を備える半導体素子と、
第二パッド部を有するソースリードと、
第三パッド部を有するゲートリードと、
前記第一電極と前記第二パッド部とを電気的に接続するクリップと、
前記半導体素子及び前記ソースリードから離間される前記クリップの中央部と、
前記中央部と接続されて前記第一電極と電気的に接続する１または複数の前記クリップの第一くし部と、
前記中央部と接続されて前記第二パッド部と電気的に接続する１または複数の前記クリップの第二くし部と、
前記第二電極と前記第三パッド部とを電気的に接続するワイヤと、
前記半導体素子，前記ワイヤ及び前記クリップを封止する樹脂成型体と
を有することを特徴とする半導体装置。 A drain lead having a first pad portion for mounting a semiconductor element;
A semiconductor element mounted on the first pad portion and having a first electrode and a second electrode on the surface;
A source lead having a second pad portion;
A gate lead having a third pad portion;
A clip for electrically connecting the first electrode and the second pad portion;
A central portion of the clip spaced from the semiconductor element and the source lead;
A first comb portion of one or more of the clips connected to the central portion and electrically connected to the first electrode;
A second comb portion of one or more clips connected to the central portion and electrically connected to the second pad portion;
A wire for electrically connecting the second electrode and the third pad portion;
A semiconductor device comprising: a resin molded body for sealing the semiconductor element, the wire, and the clip. 前記第一くし部及び前記第二くし部のそれぞれが、前記中央部をはさんで左右に形成され、左右を一対とし、少なくとも前記第一くし部が二対以上設けられることを特徴とする請求項６記載の半導体装置。   Each of the first comb part and the second comb part is formed on the left and right sides of the central part, the left and right are paired, and at least two first comb parts are provided. Item 7. The semiconductor device according to Item 6. 前記中央部に前記半導体素子と平行な平坦部をさらに有することを特徴とする請求項６または請求項７のいずれかに記載の半導体装置。   The semiconductor device according to claim 6, further comprising a flat portion parallel to the semiconductor element at the central portion. 請求項２または請求項５または請求項８のいずれかに記載の半導体装置の製造方法であって、
前記半導体素子を前記第一パッド部に載置する工程と、
前記クリップに形成された前記平坦面を真空吸着して前記クリップを移動させ、前記第一電極及び前記第二パッド部上に前記クリップを載置する工程と、
前記第一電極と前記第二パッド部とを前記クリップにて電気的に接続する工程と、
前記第二電極と前記第三パッド部とを前記ワイヤにて電気的に接続する工程と、
前記半導体素子，前記クリップ及び前記ワイヤを樹脂封止する工程と
を有することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 2, claim 5, or claim 8,
Placing the semiconductor element on the first pad portion;
Vacuum-adsorbing the flat surface formed on the clip to move the clip, and placing the clip on the first electrode and the second pad part; and
Electrically connecting the first electrode and the second pad portion with the clip;
Electrically connecting the second electrode and the third pad portion with the wire;
And a step of resin-sealing the semiconductor element, the clip, and the wire. 前記樹脂封止する工程において、樹脂を前記ドレインリード側から注入することを特徴とする請求項９記載の半導体装置の製造方法。   10. The method of manufacturing a semiconductor device according to claim 9, wherein in the resin sealing step, resin is injected from the drain lead side.
JP2011188078A 2011-08-31 2011-08-31 Semiconductor device and manufacturing method of the same Withdrawn JP2013051295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011188078A JP2013051295A (en) 2011-08-31 2011-08-31 Semiconductor device and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011188078A JP2013051295A (en) 2011-08-31 2011-08-31 Semiconductor device and manufacturing method of the same

Publications (1)

Publication Number Publication Date
JP2013051295A true JP2013051295A (en) 2013-03-14

Family

ID=48013134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011188078A Withdrawn JP2013051295A (en) 2011-08-31 2011-08-31 Semiconductor device and manufacturing method of the same

Country Status (1)

Country Link
JP (1) JP2013051295A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015178296A1 (en) * 2014-05-20 2015-11-26 三菱電機株式会社 Semiconductor device for electric power
KR101620701B1 (en) * 2013-08-02 2016-05-12 인피니언 테크놀로지스 아게 Segmented bond pads and methods of fabrication thereof
CN107275307A (en) * 2016-03-30 2017-10-20 赛米控电子股份有限公司 Power semiconductor modular
JP2021190504A (en) * 2020-05-27 2021-12-13 株式会社デンソー Semiconductor device and method for manufacturing the same
WO2023021589A1 (en) * 2021-08-18 2023-02-23 三菱電機株式会社 Semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101620701B1 (en) * 2013-08-02 2016-05-12 인피니언 테크놀로지스 아게 Segmented bond pads and methods of fabrication thereof
US9543260B2 (en) 2013-08-02 2017-01-10 Infineon Technologies Ag Segmented bond pads and methods of fabrication thereof
WO2015178296A1 (en) * 2014-05-20 2015-11-26 三菱電機株式会社 Semiconductor device for electric power
CN106104779A (en) * 2014-05-20 2016-11-09 三菱电机株式会社 Power semiconductor apparatus
JPWO2015178296A1 (en) * 2014-05-20 2017-04-20 三菱電機株式会社 Power semiconductor device
CN106104779B (en) * 2014-05-20 2019-05-10 三菱电机株式会社 Power semiconductor apparatus
CN110120375A (en) * 2014-05-20 2019-08-13 三菱电机株式会社 Power semiconductor apparatus
US10658284B2 (en) 2014-05-20 2020-05-19 Mitsubishi Electric Corporation Shaped lead terminals for packaging a semiconductor device for electric power
CN107275307A (en) * 2016-03-30 2017-10-20 赛米控电子股份有限公司 Power semiconductor modular
JP2021190504A (en) * 2020-05-27 2021-12-13 株式会社デンソー Semiconductor device and method for manufacturing the same
JP7347329B2 (en) 2020-05-27 2023-09-20 株式会社デンソー Semiconductor device and its manufacturing method
WO2023021589A1 (en) * 2021-08-18 2023-02-23 三菱電機株式会社 Semiconductor device

Similar Documents

Publication Publication Date Title
JP5272191B2 (en) Semiconductor device and manufacturing method of semiconductor device
US9922905B2 (en) Semiconductor device
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
US9418916B2 (en) Semiconductor device
US9852968B2 (en) Semiconductor device including a sealing region
JP5943795B2 (en) Manufacturing method of semiconductor device
US10727209B2 (en) Semiconductor device and semiconductor element with improved yield
KR101321277B1 (en) Power module package and method for manufacturing the same
KR20170086828A (en) Clip -bonded semiconductor chip package using metal bump and the manufacturing method thereof
JP2017055043A (en) Semiconductor device and electronic device
US20120241934A1 (en) Semiconductor apparatus and method for manufacturing the same
KR101706825B1 (en) Semiconductor Package
JP2013051295A (en) Semiconductor device and manufacturing method of the same
KR20150109284A (en) Semiconductor device and method of manufacturing the same
US10658275B2 (en) Resin-encapsulated semiconductor device
JP2017212349A (en) Semiconductor device and manufacturing method of the same
TWI686917B (en) Semiconductor device and portable apparatus using the same
WO2017071418A1 (en) Semiconductor device and manufacturing method therefor
US9655265B2 (en) Electronic module
US7202105B2 (en) Multi-chip semiconductor connector assembly method
KR20150071336A (en) Power module Package and Manufacturing Method for the same
JP2008294219A (en) Semiconductor device, and manufacturing method thereof
CN211295098U (en) Packaging structure
JP2017183417A (en) Semiconductor device
KR101824725B1 (en) Semiconductor Package

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20141104