JP2013047830A - Display device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent or restrain a (flashing) phenomenon of changing instantaneously the brightness of a screen.SOLUTION: An embodiment has a pixel circuit 3(i, j) including a light emitting diode (OLED), a driving transistor Md and a holding capacitor Cs, and a drive signal generating circuit (horizontal pixel line driving circuit 41) for generating a control signal (electric power source driving pulse DS) for driving the pixel circuit 3(i, j). The horizontal pixel line driving circuit 41 generates the electric power source driving pulse DS having a second level (medium potential Vcc_M) for specifying a period (light emission stop processing period (LM-STOP)) for stopping light emission not inverse-biasing the OLED, a first level (low potential Vcc_L) for specifying a processing period of inverse-biasing the OLED at a level lower than the medium potential Vcc_M, and a third level (high potential Vcc_H) higher than the medium potential Vcc_M and for specifying a light emission permitting period, so as to be supplied to the pixel circuit 3(i, j) pixel circuit.

Description

  A display device comprising: a light emitting diode that emits light when a bias voltage is applied; a drive transistor that controls a drive current thereof; and a storage capacitor that is coupled to a control node of the drive transistor; It relates to electronic equipment.

  An organic electroluminescence element is known as an electro-optic element used in a self-luminous display device. The organic electroluminescence element is generally called an OLED (Organic Light Emitting Diode) and is a kind of light emitting diode.

  In the OLED, a plurality of organic thin films functioning as an organic hole transport layer, an organic light emitting layer, or the like are laminated between a lower electrode and an upper electrode. An OLED is an electro-optic element that utilizes a phenomenon that emits light when an electric field is applied to an organic thin film, and obtains a gradation of color by controlling a current value flowing through the OLED. Therefore, a display device using an OLED as an electro-optical element is provided with a pixel circuit including a driving transistor for controlling the amount of current of the OLED and a capacitor for holding a control voltage of the driving transistor for each pixel.

Various pixel circuits have been proposed, and the main ones are 4 transistors (4T) / 1 capacitor (1C) type, 4T / 2C type, 5T / 1C type, 3T / 1C type, and the like.
All of these prevent image quality degradation caused by variations in characteristics of transistors formed from TFTs (Thin Film Transistors). If the data voltage is constant, the drive current is controlled to be constant within the pixel circuit. This aims to improve the uniformity (brightness uniformity) of the entire screen. In particular, when the OLED is connected to the power source in the pixel circuit, the characteristic variation of the drive transistor that controls the amount of current according to the pixel data of the input video signal directly affects the light emission luminance of the OLED.

The largest variation in characteristics of the drive transistor is variation in threshold voltage. For this reason, it is necessary to correct the gate-source voltage of the drive transistor so that the influence due to the threshold voltage variation of the drive transistor is canceled from the drive current. Hereinafter, this correction is referred to as “threshold voltage correction or threshold correction”.
Furthermore, on the assumption that threshold voltage correction is performed, the influence of a drive capability component (generally referred to as mobility) obtained by subtracting a threshold variation-derived component from the current drive capability of the drive transistor is canceled. When the gate-source voltage is corrected, a higher uniformity can be obtained. Hereinafter, this correction of the driving ability component is referred to as “mobility correction”.
The correction of the threshold voltage and mobility of the driving transistor is described in detail in, for example, Patent Document 1.

JP 2006-215213 A

As described in Patent Document 1, depending on the configuration of the pixel circuit, the light emitting diode (organic EL element) does not emit light when the threshold voltage or mobility is corrected. The above correction may be performed. In this case, when the display screen is switched, a phenomenon occurs in which the brightness of the entire screen changes momentarily. This phenomenon is particularly conspicuous when the screen shines brightly instantaneously, and is hereinafter referred to as “flash phenomenon”.
The present invention relates to a display device and an electronic apparatus that can prevent or suppress a phenomenon in which the brightness of the entire screen instantaneously changes (flash).

A self-luminous display device according to an aspect of the invention (first aspect) includes a light emitting diode, a driving transistor connected to a driving current path of the light emitting diode, and a holding capacitor coupled to a control node of the driving transistor. A pixel circuit and a drive signal generation circuit are included.
The drive signal generation circuit includes a second level that defines a period for stopping light emission without reverse-biasing the light-emitting diode, a first level that reverse-bias the light-emitting diode at a level lower than the second level, and the first level The drive signal having a third level that defines a light emission permission period higher than two levels is generated, and the drive signal is supplied to the pixel circuit.

In addition to the features of the first embodiment, the self-luminous display device according to another embodiment (second embodiment) of the present invention has the following features.
That is, in the self-luminous display device of the second form, the drive transistor and the anode of the light emitting diode are connected, and the cathode potential of the light emitting diode is at a predetermined level between the first level and the second level. The driving signal generation circuit generates the driving signal in which the second level, the first level, and the third level are repeated in a period specific to each level, and the generated driving signal is transmitted to the driving transistor. Among the two nodes through which the operating current flows, the light emitting diode is supplied from the node opposite to the node to which the light emitting diode is connected via the driving transistor.

A driving method of a self-luminous display device according to another embodiment (third embodiment) of the present invention is coupled to a light emitting diode, a driving transistor connected to a driving current path of the light emitting diode, and a control node of the driving transistor. A driving method of a self-luminous display device including a pixel circuit including a holding capacitor that includes the following steps.
(1) a light emission stop processing step for stopping light emission without reverse biasing the light emitting diode;
(2) an initialization step for a certain period of time for reverse-biasing the light emitting diode and initializing the holding voltage of the holding capacitor;
(3) a correction / writing step for correcting the driving transistor and writing a data voltage to the control node;
(4) A step of applying a light-emitting bias for applying a light-emitting bias to the light-emitting diode according to the written data voltage.

By the way, as a result of analyzing the cause of the aforementioned “flash phenomenon”, the present inventors have found that this phenomenon is related to the length of the reverse bias period of the light emitting diode (organic EL element or the like).
Regarding the reverse bias of the organic EL element, the above-mentioned Patent Document 1 describes a control for performing threshold voltage correction in a state where the organic light emitting diode OLED (organic EL element) is reverse biased in a 5T / 1C type pixel circuit. (See the first and second embodiments of Patent Document 1 above, for example, see the description of paragraph [0046] in the first embodiment, etc.). In Patent Document 1, it is not described because only the driving for one pixel is described. However, in an actual organic EL display, the reverse bias of the organic EL element is the screen display period (one field before). It starts from the light emission end point in 1F) and is canceled at the next light emission after a correction period. For this reason, the length (starting point) of the reverse bias depends on the length of the light emission permission period of the organic EL element and sometimes changes.

The characteristics of the organic EL element deteriorate due to changes with time when the amount of flowing current becomes extremely large. This deterioration in characteristics is compensated (corrected) to some extent by the above-described correction of the threshold voltage and mobility. However, since the extreme characteristic deterioration cannot be completely corrected, it is desirable that the characteristic deterioration be small from the beginning. For this reason, when the control for increasing the light emission luminance is performed, the control for increasing the light emission permission period (pulse duty ratio control) may be performed instead of increasing the drive current amount.
In addition, when the environment around the current is bright, in order to increase the overall light emission luminance and make the screen easier to see, control for extending the light emission permission period may be performed in consideration of the correction limit. Furthermore, the luminance is lowered due to the demand for lower power consumption, but at this time, the light emission time may be shortened instead of reducing the drive current amount.

  When the brightness of the screen is changed by increasing or decreasing the average pixel emission brightness, a “flash phenomenon” is observed when the screen is switched, so the flash phenomenon depends on the length of the reverse bias period. How you come out changes. From this point of view, when reverse biasing a light emitting diode (such as an organic EL element), the present inventors change the equivalent capacitance value of the light emitting diode with time, and this affects the correction accuracy. I have the conclusion that the whole screen is changing.

Therefore, in the above-described first to third embodiments of the present invention, when light emission is stopped for the light emitting diode, a second level driving signal for stopping light emission without reverse biasing the light emitting diode is applied, The period during which the light emitting diode is reverse-biased by applying the first level drive signal can be made constant.
By utilizing this fact, when the light emission possible period is changed, the second level (light emission stop process) period can be made variable to absorb the fluctuation of the light emission possible period.
For this reason, even if the reverse bias period is constant, it is easy to change the length of the light emission permission period in which light is actually emitted.

  If the reverse bias application time is constant, the bias voltages of the control nodes of the light emitting diodes are almost the same between pixel circuits to which the same data voltage is input after correction of the threshold voltage and movement. That is, the error component of the bias voltage before light emission to the light emitting diode due to the different reverse bias application time does not occur. Therefore, if the accuracy of correction is further improved and the same data voltage is input, the light emission intensity of the pixel becomes substantially constant.

  According to the display device and the electronic apparatus according to the present invention, since the reverse bias application time can be made constant, if the same data voltage is input, the light emission intensity of the pixel becomes almost constant, and as a result, the so-called flash phenomenon occurs. It can be effectively prevented or suppressed.

It is a block diagram which shows the main structural examples of the organic electroluminescent display in connection with embodiment of this invention. It is a block diagram including the basic composition of the pixel circuit concerning the embodiment of the present invention. It is a figure which shows the graph and formula which show the characteristic of an organic light emitting diode. It is a timing chart which shows the waveform of various signals and voltage in display control concerning the embodiment of the present invention. FIG. 3 is a block diagram of a circuit that generates a ternary power supply driving pulse according to an embodiment of the present invention. FIG. 6 is a waveform diagram for showing first and second pulses P1 and P2 output from the shift register shown in FIG. 5; FIG. 6 is a circuit diagram illustrating a configuration example of a unit illustrated in FIG. 5. It is operation | movement explanatory drawing to the light emission stop period. It is operation | movement explanatory drawing before completion | finish of threshold voltage correction | amendment. It is operation | movement explanatory drawing to the light emission permission period. It is explanatory drawing of a correction effect. It is a timing chart which shows the waveform of the various signals in display control in connection with the comparative example with respect to embodiment of this invention. It is a timing chart which shows the change of the signal waveform and luminescence intensity for explaining the flash phenomenon. It is a timing chart which shows the change of the signal waveform and light emission intensity in the embodiment to which the present invention is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking as an example an organic EL display having a 2T · 1C type pixel circuit.

<Overall configuration>
FIG. 1 shows a main configuration of an organic EL display according to an embodiment of the present invention.
The illustrated organic EL display 1 includes a pixel array 2 in which a plurality of pixel circuits (PXLC) 3 (i, j) are arranged in a matrix, a vertical drive circuit (V scanner) 4 that drives the pixel array 2, and a horizontal And a drive circuit (H selector: HSEL) 5.
A plurality of V scanners 4 are provided depending on the configuration of the pixel circuit 3. Here, the V scanner 4 includes a horizontal pixel line drive circuit (Drive Scan) 41 and a write signal scanning circuit (Write Scan) 42. The V scanner 4 and the H selector 5 are part of a “drive circuit”. The “drive circuit” includes a circuit for supplying a clock signal to the V scanner 4 and the H selector 5, a control circuit (CPU, etc.), and the like. Also includes a circuit (not shown). In particular, the horizontal pixel line driving circuit 41 and a circuit or a control circuit (CPU or the like) that supplies a clock signal for driving the horizontal pixel line driving circuit 41 are referred to as “driving signal generation circuit”.

The code “3 (i, j)” of the pixel circuit shown in FIG. 1 indicates that the pixel circuit has an address i (i = 1, 2) in the vertical direction (vertical direction) and an address j ( j = 1,2,3). These addresses i and j take integers of 1 or more with the maximum values being “n” and “m”, respectively. Here, for simplification of the figure, a case where n = 2 and m = 3 is shown.
This address notation is similarly applied to the elements, signals, signal lines, voltages, and the like of the pixel circuit in the following description and drawings.

Pixel circuits 3 (1,1) and 3 (2,1) are connected to the video signal line DTL (1) in the vertical direction. Similarly, the pixel circuits 3 (1,2) and 3 (2,2) are connected to the video signal line DTL (2) in the vertical direction, and the pixel circuits 3 (1,3) and 3 (2,3) are vertical. Direction video signal line DTL (3). The video signal lines DTL (1) to DTL (3) are driven by the H selector 5.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the write scanning line WSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the write scanning line WSL (2). The write scanning lines WSL (1) and WSL (2) are driven by the horizontal pixel line driving circuit 41.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the power supply scanning line DSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the power supply scanning line DSL (2). The power supply scanning lines DSL (1) and DSL (2) are driven by the write signal scanning circuit.

Any one of the m video signal lines including the video signal lines DTL (1) to DTL (3) will be represented by the symbol “DTL (j)”. Similarly, any one of the n write scan lines including the write scan lines WSL (1) and WSL (2) is represented by reference numeral “WSL (i)”, and the power scan line DSL (1), Any one of the n power supply scanning lines including DSL (2) is represented by a symbol “DSL (i)”.
For the video signal line DTL (j), line-sequential driving in which video signals are discharged all at once in units of display pixel rows (also referred to as display lines), or video is sequentially applied to video signal lines DTL (j) in the same row. Although there is dot sequential driving in which signals are discharged, any driving method may be used in this embodiment.

<Pixel circuit>
FIG. 2 shows a configuration example of the pixel circuit 3 (i, j).
The pixel circuit 3 (i, j) illustrated is a circuit that controls the organic light emitting diode OLED. In addition to the organic light emitting diode OLED, the pixel circuit includes a driving transistor Md and a sampling transistor Ms made of an NMOS type TFT, and one holding capacitor Cs.

  Although the organic light emitting diode OLED is not particularly shown, for example, in the case of a top emission type, an anode electrode is first formed on a TFT structure formed on a substrate made of transparent glass or the like, and a hole transport layer, A light emitting layer, an electron transport layer, an electron injection layer, and the like are sequentially deposited to form a laminate that forms an organic multilayer film, and a cathode electrode made of a transparent electrode material is formed on the laminate. The anode electrode is connected to the positive power source, and the cathode electrode is connected to the negative power source.

  When a bias voltage for obtaining a predetermined electric field is applied between the anode and cathode electrodes of the organic light emitting diode OLED, the organic multilayer film emits light when the injected electrons and holes recombine in the light emitting layer. The organic light emitting diode OLED can emit light in each color of red (R), green (G), and blue (B) by appropriately selecting the organic material constituting the organic multilayer film. For example, color display is possible by arranging the light emission of R, G, B in the pixels of each row. Alternatively, R, G, and B may be distinguished by the color of the filter using an organic material that emits white light. A four-color configuration in which W (white) is added in addition to R, G, and B may be used.

The drive transistor Md functions as current control means for controlling the amount of current flowing through the organic light emitting diode OLED to define display gradation.
The drain of the drive transistor Md is connected to the power supply scanning line DSL (i) that controls the supply of the power supply voltage, and the source is connected to the anode of the organic light emitting diode OLED.

  The sampling transistor Ms is connected between the supply line (video signal line DTL (j)) of the data potential Vsig that determines the pixel gradation and the gate (control node NDc) of the drive transistor Md. One of the source and drain of the sampling transistor Ms is connected to the gate (control node NDc) of the drive transistor Md, and the other is connected to the video signal line DTL (j). A data pulse having a data potential Vsig is supplied to the video signal line DTL (j) from the H selector 5 (see FIG. 1) at a predetermined interval. The sampling transistor Ms samples data at a level to be displayed by the pixel circuit at an appropriate timing in a data potential supply period (data pulse duration time). This is to eliminate the influence on the display image in the transition period where the level is unstable at the front or rear of the data pulse having the desired data potential Vsig to be sampled.

  A holding capacitor Cs is connected between the gate and source of the driving transistor Md (the anode of the organic light emitting diode OLED). The role of the holding capacitor Cs will be clarified in the operation description described later.

In FIG. 2, the horizontal pixel line drive circuit 41 supplies the power drive pulse DS (i) to the drain of the drive transistor Md, and the power supply when the drive transistor Md is corrected or when the organic light emitting diode OLED actually emits light. Done. The waveform of the power supply driving pulse DS (i) will be described later.
Further, the write signal scanning circuit 42 supplies a write drive pulse WS (i) having a relatively short duration to the gate of the sampling transistor Ms to perform sampling control.
The power supply control may be configured such that another transistor is inserted between the drain of the drive transistor Md and the power supply voltage supply line, and the gate is controlled by the horizontal pixel line drive circuit 41 ( (Refer to a modification described later).

  In FIG. 2, the anode of the organic light emitting diode OLED is supplied with the power supply voltage from the positive power supply via the drive transistor Md, and the cathode of the organic light emitting diode OLED is a predetermined voltage line (negative power supply) for supplying the cathode potential Vcath. Line).

  Usually, all transistors in the pixel circuit are formed of TFTs. The thin film semiconductor layer in which the TFT channel is formed is made of a semiconductor material such as polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon). Polysilicon TFTs can have high mobility, but their characteristic variation is large, so they are not suitable for increasing the screen size of a display device. Therefore, in a display device having a large screen, an amorphous silicon TFT is generally used. However, since it is difficult to form a P-channel TFT in an amorphous silicon TFT, it is desirable that all TFTs be an N-channel type like the pixel circuit 3 (i, j) described above.

Here, the pixel circuit 3 (i, j) is an example of a pixel circuit applicable in the present embodiment, that is, a basic configuration example of a two-transistor (2T) / 1-capacitor (1C) type. Therefore, the pixel circuit that can be used in the present embodiment may be a pixel circuit having the above-described pixel circuit 3 (i, j) as a basic configuration and further having a transistor and a capacitor added thereto (see modification examples described later). In some basic configurations, the holding capacitor Cs is connected between the supply line of the power supply voltage and the gate of the drive transistor Md.
Specifically, some pixel circuits other than the 2T • 1C type that can be employed in the present embodiment will be briefly described in modification examples described later. For example, 4T • 1C type, 4T • 2C type, 5T • 1C type It may be a 3T / 1C type.

In the pixel circuit based on the configuration of FIG. 2, when the organic light emitting diode OLED is reverse-biased at the time of threshold voltage correction or mobility correction, the equivalent capacitance value at the time of reverse biasing of the organic light-emitting diode OLED is maintained, as will be described in detail later. Since the value can be sufficiently larger than the value of the capacitor Cs, the anode of the organic light emitting diode OLED is substantially fixed in terms of potential, and the correction accuracy is improved. For this reason, it is desirable to perform correction in a reverse bias state.
The reason why the cathode is connected to a predetermined voltage line capable of controlling the potential without grounding the cathode potential Vcath is to perform reverse bias. In order to reverse bias the organic light emitting diode OLED, for example, the cathode potential Vcath is made smaller than the reference potential (low potential Vcc_L) of the power supply driving pulse DS (i).

<Display control>
The operation at the time of data writing in the circuit of FIG. 2 will be described together with the threshold voltage and mobility correction operation. A series of these operations is called “display control”.
First, the characteristics of the drive transistor to be corrected and the organic light emitting diode OLED will be described.

A holding capacitor Cs is coupled to the control node NDc of the drive transistor Md shown in FIG. The data potential Vsig, which is the effective potential of the data pulse transmitted through the video signal line DTL (j), is sampled by the sampling transistor Ms, and the potential thus obtained is applied to the control node NDc and held by the holding capacitor Cs. When a predetermined potential is applied to the gate of the drive transistor Md, the drain current Ids is determined according to the gate-source voltage Vgs having a value corresponding to the applied potential.
Here, it is assumed that sampling is performed after the source potential Vs of the drive transistor Md is initialized to the reference potential (data reference potential Vo) of the data pulse. The data potential Vsig after sampling, more precisely, the drain current Ids corresponding to the magnitude of the data voltage Vin defined by the potential difference between the data reference potential Vo and the data potential Vsig flows to the drive transistor Md, which is substantially organic light emission. It becomes the drive current Id of the diode OLED.
Therefore, when the source potential Vs of the driving transistor Md is initialized with the data reference potential Vo, the organic light emitting diode OLED emits light with a luminance corresponding to the data potential Vsig.

FIG. 3 shows a graph of the IV characteristic of the organic light emitting diode OLED and a general formula of the drain current Ids of the driving transistor Md (which corresponds to the driving current Id of the OLED).
As is well known, the organic light emitting diode OLED changes its IV characteristic by heat as shown in FIG. At this time, in the pixel circuit of FIG. 2, even if the drive transistor Md tries to pass a constant drain current Ids, the applied voltage of the organic light emitting diode OLED increases as can be seen from the graph shown in FIG. Source potential Vs rises. At this time, since the gate of the driving transistor Md is in a floating state, the gate potential rises together with the source potential so that the substantially constant gate-source voltage Vgs is maintained, and the drain current Ids is kept substantially constant. Acts so as not to change the light emission luminance of the organic light emitting diode OLED.

  However, since the threshold voltage Vth and the mobility μ of the driving transistor Md are different for each pixel circuit, the drain current Ids varies according to the equation of FIG. 3, and the data potential Vsig given in the display screen. Even if the two pixels are the same, the light emission luminance differs between the two pixels.

  In the equation of FIG. 3, the symbol “Ids” represents a current flowing between the drain and the source of the drive transistor Md operating in the saturation region. In the drive transistor Md, “Vth” is the threshold voltage, “μ” is the mobility, “W” is the effective channel width (effective gate width), and “L” is the effective channel length (effective gate length). Respectively. “Cox” represents the sum of the unit gate capacitance of the drive transistor Md, that is, the gate oxide film capacitance per unit area, and the fringing capacitance between the source, drain, and gate.

  The pixel circuit having the N-channel type driving transistor Md has an advantage of high driving capability and simplification of the manufacturing process. However, in order to suppress variations in the threshold voltage Vth and the mobility μ, these correction operations can emit light. Must be done prior to bias setting.

  4A to 4E are timing charts showing waveforms of various signals and voltages in display control. In the display control here, data writing is sequentially performed in units of rows. FIG. 4 shows a case where the pixel circuit 3 (1, j) in the first row is a row (display line) to be written and display control is performed in the field F (1) for the display line in the first row. ing. Note that FIG. 4 shows a part of the control of the field F (0) before that (control of light emission stop).

  FIG. 4A is a waveform diagram of the video signal Ssig. FIG. 4B is a waveform diagram of the write drive pulse WS supplied to the display line to be written. FIG. 4C is a waveform diagram of the power supply driving pulse DS supplied to the display line to be written. FIG. 4E is a waveform diagram of the gate potential Vg of the drive transistor Md (potential of the control node NDc) in one pixel circuit 3 (1, j) belonging to the display line to be written. FIG. 4F is a waveform diagram of the source potential Vs of the drive transistor Md (the anode potential of the organic light emitting diode OLED) in one pixel circuit 3 (1, j) belonging to the display line to be written.

[Definition of period]
As described in the upper part of FIG. 4A, the light emission stop processing period (LM-STOP) of the previous screen follows the light emission permission period (LM0) of the previous screen of one field (or one frame). . The processing of the next screen starts from here, and in the order of time series, the initialization period (INT), the threshold voltage correction period (VTC), the writing & mobility correction period (W & μ), and the light emission permission period as the “correction preparation period” (LM1), the light emission stop processing period (LM-STOP), and each processing period changes.

[Outline of drive pulse]
In FIG. 4, time display is shown at appropriate locations in the waveform diagram by the symbols “T0Ca, T0Cb, T15,..., T19, T1A, T1B, T1Ca, T1Cb”. Time “T0Ca, T0Cb” corresponds to field F (0), and time “T15 to T1Cb” corresponds to field F (1).

  As shown in FIG. 4B, the write drive pulse WS includes a predetermined number of sampling pulses SP1 that are inactive at the “L” level and active at the “H” level for each screen (one field). A write pulse WP is superimposed after the sampling pulse SP1. Thus, the write drive pulse WS is composed of the sampling pulse SP1 and the write pulse WP.

  The video signal Ssig supplied to m (several hundred to several hundreds) video signal lines DTL (j) (see FIGS. 1 and 2) is m video signal lines DTL (j) in line sequential display. Are supplied at the same time. In FIG. 4, only the video signal pulse PP (1) important for the display of the first row is shown. The peak value from the data reference potential Vo of the video signal pulse PP (1) corresponds to the gradation value to be displayed (written) by the display control, that is, the data voltage Vin. This gradation value (= Vin) may be the same for each pixel in the first row (in the case of monochromatic display), but usually changes according to the gradation value of the display pixel row.

  FIG. 4 is mainly for explaining the operation of one pixel in the first row, but the control itself is different except that this display gradation value may be different in other pixels in the same row. This is executed in parallel with the pixel drive control shown in FIG.

The feature of the light emission control in this embodiment is that the potential of the power supply driving pulse DS is controlled to three values.
As shown in FIG. 4C, the power supply drive pulse DS is controlled, and this control is performed by the horizontal pixel line drive circuit 41 shown in FIGS.
The three values taken by the power supply drive pulse DS are a low potential Vcc_L as the “first level”, a high potential Vcc_H as the “third level”, and a predetermined potential between the low potential Vcc_L and the high potential Vcc_H. The medium potential Vcc_M as “two levels”.
The second level (medium potential Vcc_M) is a potential for providing an anode potential that does not reverse bias the organic light emitting diode OLED but does not emit light. The first level (low potential Vcc_L) is a potential for providing a non-light emitting anode potential that reversely biases the organic light emitting diode OLED. The third level (high potential Vcc_H) is a potential for biasing the anode of the organic light emitting diode OLED so as to emit light.
The ternary power supply driving pulse DS is generated by the horizontal pixel line driving circuit 41 shown in FIGS.

[Ternary generation circuit example]
FIG. 5 shows a more detailed block diagram of the horizontal pixel line driving circuit 41 for generating the ternary power supply driving pulse DS.
The horizontal pixel line driving circuit 41 illustrated in FIG. 5 generates two types of synchronization pulses (first pulse P1 and second pulse P2) having different duty ratios, and shifts the shift register 411, the first pulse P1, and the first pulse P1. A DS generation circuit 412 that inputs two pulses P2 and generates a ternary power supply drive pulse DS;

6A and 6B are waveform diagrams corresponding to four fields of the first pulse P1 and the second pulse P2.
The first pulse P1 shown in FIG. 6A takes the “H” level corresponding to the total time of the light emission stop processing period (LM-STOP) and the initialization period (INT), and other periods in one field. Has a waveform having an "L" level.
The second pulse P2 shown in FIG. 6B has a waveform that takes the “L” level during the initialization period (INT) and takes the “H” level during the other period within one field.

The shift register 411 shown in FIG. 5 receives a clock signal from a clock generation circuit (not shown) and generates the first and second pulses P1, P2 for one field shown in FIG. 6 from the clock signal. This circuit shifts two pulses. Alternatively, the shift register 411 may simply shift the first and second pulses P1 and P2 generated by another pulse generation circuit (not shown).
The shift register 411 is provided with n output taps for outputting the first and second pulses P1 and P2 for each pulse, for a total of 2n. This number “n” is the same number as the number of pixel rows n included in the pixel array 2, and the output taps of the first pulse P1 and the output taps of the second pulse P2 are provided in pairs for each pixel row. Yes.

The DS generation circuit 412 includes n units 412U having the same configuration.
The unit 412U has a first input (in1), a second input (in2), and an output (out). From the first pulse P1 input from the first input (in1) and from the second input (in2). This is a circuit that generates a ternary power supply driving pulse DS by synthesizing the waveform of the input second pulse P2 and outputs it from the output (out). Each unit 412U has the same configuration.

FIG. 7 shows a circuit example of one unit 412U. In this example, the first level (low potential Vcc_L) is the first reference potential Vss1, the second level (medium potential Vcc_M) is the second reference potential Vss2, and the third level (high potential Vcc_H) is the power supply potential Vdd.
The unit 412U shown in FIG. 7 includes two NMOS transistors N1 and N2, one PMOS transistor P1, two AND circuits AND1 and AND2 having two inputs, and one inverter INV1.

The transistors P1 and N1 are connected in cascade between the supply line of the power supply potential Vdd and the supply line of the second reference potential Vss2, and the node between the transistors P1 and N1 is connected to the output (out). A transistor N2 is connected between the output (out) and the supply line of the first reference potential Vss1.
The gate of the transistor P1, one input of the AND circuit AND1, and one input of the AND circuit AND2 are connected to the first input (in1). The other input of the AND circuit AND1 is connected to the second input (in2), and the other input of the AND circuit AND2 is connected to the second input (in2) via the inverter INV1.
The output of the AND circuit AND1 is connected to the gate of the transistor N1, and the output of the AND circuit AND2 is connected to the gate of the transistor N2.

The operation of the circuit shown in FIG. 7 will be described with reference to FIG.
As shown in FIGS. 6C and 6D, before the time t0, the first pulse P1 is at “H” level and the second pulse P2 is at “L” level. At this time, since the transistor P1 is off, the output of the AND circuit AND1 is “L” and the transistor N1 is off, and the output of the AND circuit AND2 is “H” and the transistor N2 is on, the output (out) is the first reference. The potential Vss1 is output (FIG. 6B).

  When the period of time t0 to t1 corresponding to the light emission permission period (LM) is reached, the first pulse P1 changes from the “H” level to the “L” level, and the second pulse P2 changes from the “L” level to the “H” level. Transition. Therefore, in FIG. 7, the transistor P1 is turned on, the output of the AND circuit AND2 changes from “H” to “L”, and the transistor N2 is turned off. At this time, although both inputs of the AND circuit AND1 are inverted, the output is maintained at “L”, so that the transistor N1 remains off. Therefore, the output (out) is switched from the output state of the first reference potential Vss1 to the output state of the power supply potential Vdd (FIG. 6B).

  In the interval from time t1 to t2 corresponding to the light emission stop processing period (LM-STOP), the first pulse P1 changes from the “L” level to the “H” level. Therefore, in FIG. 7, the transistor P1 is turned off, and “H” is arranged at the input of the AND circuit AND1, so that the output transitions from “L” to “H”, and the transistor N1 is turned on. At this time, although one input of the AND circuit AND2 is inverted, the other input remains “L”, so the output remains “L” and the transistor N2 remains off. Therefore, the output (out) is switched from the output state of the power supply potential Vdd to the output state of the second reference potential Vss2 (FIG. 6B).

In the period from time t2 to t3 corresponding to the initialization period (INT), the second pulse P2 transitions from the “H” level to the “L” level. For this reason, in FIG. 7, since “H” is arranged at the inputs of the AND circuit AND2, the output transitions from “L” to “H”, and the transistor N2 is turned on. At this time, since the other input of the AND circuit AND2 is inverted from “H” to “L”, the output is also inverted from “H” to “L”, and the transistor N1 is turned off. Since the first pulse P1 maintains the “H” level, the transistor P1 remains off. Therefore, the output (out) is switched from the output state of the second reference potential Vss2 to the output state of the first reference potential Vss1 (FIG. 6B).
As described above, the power supply driving pulse DS having a waveform having a ternary value is generated, and the same ternary waveform is repeated in other fields.

The second row (pixel circuit 3 (2, j)) and the third row (pixel circuit 3 (3, j)) are not particularly shown, but for example, each pulse (write) for one horizontal period. A drive pulse WS and a power supply drive pulse DS are sequentially applied with a delay.
Therefore, during the period when “threshold voltage correction” and “writing & mobility correction” are performed for a certain row, “light emission stop processing” and “initialization” are executed for the previous row. Therefore, seamless processing is executed in units of rows when only “threshold voltage correction” and “writing & mobility correction” are considered. Therefore, a useless period does not occur.

Next, a change in the potential of the source and gate of the driving transistor Md shown in FIGS. 4D and 4E and the operation associated therewith under the above pulse control for each period shown in FIG. 4A. Explained.
Here, the operation explanatory diagram of the pixel circuit 3 (1, j) in the first row shown in FIGS. 8A to 10B, FIG. 2 and the like are referred to as appropriate.

[Front-screen emission permission period (LM0)]
For the pixel circuit 3 (1, j) in the first row, in the light emission permission period (LM0) in the field F (0) (previous screen) before the time T0Ca, as shown in FIG. Is at “L” level, the sampling transistor Ms is off. At this time, as shown in FIG. 4C, the power supply driving pulse DS is in the application state of the high potential Vcc_H.

  As shown in FIG. 8A, the data voltage Vin0 is inputted and held in the gate of the driving transistor Md by the data writing operation of the previous screen. At this time, it is assumed that the organic light emitting diode OLED is in a light emitting state according to the data voltage Vin0. Since the driving transistor Md is set to operate in the saturation region, the driving current Id (= Ids) flowing through the organic light emitting diode OLED is equal to the gate-source voltage Vgs of the driving transistor Md held in the holding capacitor Cs. Accordingly, the value calculated from the above-described equation shown in FIG. 3 is taken.

[Light emission stop processing period (LM-STOP)]
In FIG. 4, the light emission stop process is started at time T0Ca.
At time T0Ca, the horizontal pixel line driving circuit 41 (see FIG. 2) switches the potential of the power supply driving pulse DS from the high potential Vcc_H to the intermediate potential Vcc_M as shown in FIG. 4C. The medium potential Vcc_M is a potential at which light emission is stopped although no reverse bias is applied to the organic light emitting diode OLED. For example, under the assumption that the potential drop due to the drive transistor Md is negligible, the intermediate potential Vcc_M has a lower limit as a potential at which a zero bias is applied to the organic light emitting diode OLED and an upper limit as the light emission threshold voltage of the organic light emitting diode OLED. Potential. Here, the “light emission threshold voltage” does not always coincide with the (current) threshold voltage at which current starts to flow through the organic light emitting diode OLED, and the organic light emitting diode OLED often cannot emit light for a while even when the threshold voltage is exceeded. The “light emission threshold voltage” is a voltage having a value larger than “(current) threshold voltage” and actually starting light emission.

When the potential of the power supply driving pulse DS becomes the middle potential Vcc_M, the potential of the node that has been functioning as the drain until now is suddenly dropped to the middle potential Vcc_M, and the potentials of the source and drain are reversed. A discharge operation is performed in which a node that has been a drain until now is used as a source and a node that has been a source until now is a drain, and the charge of the drain (however, the source potential Vs remains in the notation in the drawing) is extracted.
Therefore, as shown in FIG. 8B, the drain current Ids in the opposite direction to that of the current flows in the driving transistor Md.

When the light emission stop processing period (LM-STOP) starts, as shown in FIG. 4E, the source (drain in actual operation) of the drive transistor Md is rapidly discharged at the time T0Ca as a boundary, and the source potential Vs. Decreases to near the middle potential Vcc_M. Since the gate of the sampling transistor Ms is in a floating state, the gate potential Vg also decreases as the source potential Vs decreases.
At this time, when the intermediate potential Vcc_M is smaller than the sum of the emission threshold voltage Vth_oled. And the cathode potential Vcath of the organic light emitting diode OLED, that is, “Vcc_M <Vth_oled. + Vcath”, the organic light emitting diode OLED is extinguished. However, at this stage, the organic light emitting diode OLED is not reverse-biased.

  The end point (time T0Ca) of the light emission permission period LM0 varies in position on the time axis in a range not exceeding the start point (time T0Cb) of the next field F (1) depending on the length of the light emission time. Therefore, the length of the light emission stop processing period (LM-STOP) also varies depending on the length of the light emission time. However, since the light emission stop processing period (LM-STOP) is not a reverse bias period, the reverse bias period does not vary during this period.

[Initialization period (INT)]
At time T0Cb, the initialization period (INT) of field F (1) starts.
In the initialization period (INT), the horizontal pixel line drive circuit 41 (see FIG. 2) switches the potential of the power supply drive pulse DS from the middle potential Vcc_M to the low potential Vcc_L as shown in FIG. 4C.
When the potential of the power supply driving pulse DS becomes the low potential Vcc_L, the driving transistor Md is again discharged as shown in FIG. For this reason, as shown in FIG. 4E, the source (the drain in actual operation) of the driving transistor Md is further discharged at the time T0Cb boundary, and the source potential Vs drops to near the low potential Vcc_L. Since the gate of the sampling transistor Ms is in a floating state, the gate potential Vg also decreases as the source potential Vs decreases.
At this time, since “Vcc_L <Vth_oled. + Vcath”, the organic light emitting diode OLED is continuously extinguished. The organic light emitting diode OLED is reverse-biased while the source potential Vs is further lowered due to the discharge in the initialization period (INT).

As shown in FIG. 4B, the write signal scanning circuit 42 (see FIG. 2) sets the potential of the write scanning line WSL (1) to the “L” level at time T15 in the middle of the initialization period (INT). Is applied to the gate of the sampling transistor Ms.
By time T15, the potential of the video signal Ssig is switched to the data reference potential Vo. Therefore, the sampling transistor Ms samples the data reference potential Vo of the video signal Ssig, and transmits the sampled data reference potential Vo to the gate of the drive transistor Md.
By this sampling operation, as shown in FIGS. 4D and 4E, the value of the gate potential Vg converges to the data reference potential Vo, and accordingly, the value of the source potential Vs converges to the low potential Vcc_L. .
Here, the data reference potential Vo is a predetermined potential that is lower than the high potential Vcc_H of the power supply driving pulse DS and higher than the low potential Vcc_L.

By this sampling operation, the holding voltage of the holding capacitor Cs is initialized to adjust the initial state of the correction operation.
In the initialization of the holding voltage, the low potential Vcc_L of the power supply driving pulse DS is set so that the gate-source voltage Vgs (= holding voltage) of the driving transistor Md is equal to or higher than the threshold voltage Vth of the driving transistor Md. Specifically, as shown in FIG. 8C, when the gate potential Vg becomes the data reference potential Vo, the source potential Vs becomes the low potential Vcc_L of the power supply driving pulse DS in conjunction with this, so that the holding capacitor Cs The holding voltage decreases to “Vo−Vcc_L”. This holding voltage “Vo−Vcc_L” is the gate-source voltage Vgs itself. If the gate-source voltage Vgs is not larger than the threshold voltage Vth of the drive transistor Md, the threshold voltage correcting operation cannot be performed thereafter. , “Vo−Vcc_L> Vth” is established.

The sampling pulse SP1 shown in FIG. 4B ends at time T17 when a sufficient time has elapsed from time T15, and the sampling transistor Ms is turned off.
Processing for the field F (1) is started at the previous time T16.

[Threshold correction period (VTC)]
At time T16, as shown in FIG. 4B, the first sampling pulse SP1 rises, and the sampling transistor Ms is turned on. In this state, at time T16, the potential of the power supply driving pulse DS is switched from the low potential Vcc_L to the high potential Vcc_H, and the threshold correction period (VTC) starts.

Since the on-state sampling transistor Ms is sampling the data reference potential Vo immediately before the start of the threshold correction period (VTC) (time T16), as shown in FIG. The gate potential Vg of Md is electrically fixed at a constant data reference potential Vo.
In this state, when the potential of the power supply driving pulse DS changes from the low potential Vcc_L to the high potential Vcc_H at time T16, the power supply voltage Vdd corresponding to the maximum amplitude value of the power supply driving pulse DS is generated between the source and drain of the driving transistor Md. Applied. Therefore, the drive transistor Md is turned on and the drain current Ids flows.

The source of the driving transistor Md is charged by the drain current Ids, and the source potential Vs rises as shown in FIG. 4E. Therefore, between the gate and source of the driving transistor Md that has previously taken the value of “Vo−Vcc_L”. The voltage Vgs (holding voltage of the holding capacitor Cs) gradually decreases (see FIG. 9A).
When the rate of decrease of the gate-source voltage Vgs is fast, as shown in FIG. 4E, the increase of the source potential Vs is saturated within the threshold correction period (VTC). This saturation occurs because the drive transistor Md is cut off by the rise of the source potential. Therefore, the gate-source voltage Vgs (holding voltage of the holding capacitor Cs) converges to a value substantially equal to the threshold voltage Vth of the driving transistor Md.

9A, the drain current Ids flowing through the driving transistor Md charges the one electrode of the holding capacitor Cs, and charges the capacitance Coled. Of the organic light emitting diode OLED. At this time, assuming that the capacitance Coled. Of the organic light emitting diode OLED is sufficiently larger than the holding capacitor Cs, most of the drain current Ids is used for charging the holding capacitor Cs. In this case, the convergence point of the gate-source voltage Vgs is the threshold value. The value is almost equal to the voltage Vth.
In order to guarantee the accurate threshold voltage correction, the correction operation is started in a state where the organic light emitting diode OLED is reversely biased in advance with the intention of sufficiently increasing the capacitance Coled.

As shown in FIG. 4B, the threshold correction period (VTC) ends at time T19, but at the previous time T17, the write drive pulse WS is deactivated and the sampling pulse SP1 ends. As a result, as shown in FIG. 9B, the sampling transistor Ms is turned off, and the gate of the drive transistor Md is in a floating state. At this time, the gate potential Vg maintains the data reference potential Vo.
Sampling pulse SP1 ends at time T17, and it is necessary to apply video signal pulse PP (1) at time T18 up to time T19, that is, to change the potential of video signal Ssig to data potential Vsig. This is because the data potential Vsig becomes a stable predetermined level at the time of data sampling at time T19, and the data potential Vsig needs to be stabilized in order to correctly write the data voltage Vin. Therefore, the length of time T18 to T19 is set to a time sufficient for stabilizing the data potential.

[Effect of threshold voltage correction]
If the gate-source voltage of the driving transistor is increased by “Vin”, the gate-source voltage is “Vin + Vth”. Further, a driving transistor having a large threshold voltage Vth and a driving transistor having a small threshold voltage Vth are considered.
The former driving transistor having a larger threshold voltage Vth has a larger gate-source voltage by the amount of the larger threshold voltage Vth, and conversely, the driving transistor having a smaller threshold voltage Vth has a smaller threshold voltage Vth, resulting in a smaller gate-source voltage. Therefore, regarding the threshold voltage Vth, the variation can be canceled by the threshold voltage correction operation, and the same drain current Ids can be caused to flow to the drive transistor at the same data voltage Vin.

  In the threshold voltage correction period (VTC), the drain current Ids is exclusively consumed when flowing into one electrode side of the holding capacitor Cs, that is, one electrode side of the capacitance Coled. Of the organic light emitting diode OLED. It is necessary to prevent the OLED from turning on. When the voltage between the terminals of the organic light emitting diode OLED is expressed as “Voled.”, The light emission threshold voltage is expressed as “Vth_oled.”, And the cathode potential is expressed as “Vcath”, the condition for maintaining the organic light emitting diode OLED in the off state is “Voled. . ≦ Vcath + Vth_oled. ”Is always true.

  Here, when the cathode potential Vcath of the organic light emitting diode OLED is constant at the low potential Vcc_L (for example, the ground voltage GND), this equation can always be established when the light emission threshold voltage Vth_oled. Is very large. However, the light emission threshold voltage Vth_oled. Is determined by the manufacturing conditions of the organic light emitting diode OLED, and the light emission threshold voltage Vth_oled. Cannot be increased too much for efficient light emission at a low voltage. Therefore, in the present embodiment, until the threshold voltage correction period (VTC) ends, the organic light emitting diode OLED is reverse-biased by setting the cathode potential Vcath to be higher than the low potential Vcc_L.

  Due to the reverse bias, the cathode potential Vcath remains constant throughout the period shown in FIG. However, a constant potential of the cathode potential Vcath is set to a value at which the reverse bias is released by the threshold voltage correction. Accordingly, the reverse bias is released after the time T19 when the source potential Vs becomes higher than that at the time of threshold voltage correction, and in this state, processing for mobility correction and light emission is performed, and then the organic light emitting diode OLED is again performed in the light emission stop processing. Becomes a reverse bias state.

[Writing & mobility correction period (W & μ)]
From time T19, the writing & mobility correction period (W & μ) starts. The state at this time is the same as in FIG. 9B, in which the sampling transistor Ms is off and the drive transistor Md is cut off. The gate of the driving transistor Md is held at the data reference potential Vo, the source potential Vs is “Vo−Vth”, and the gate-source voltage Vgs (the holding voltage of the holding capacitor Cs) is “Vth”.

As shown in FIG. 4B, the write pulse WP is supplied to the gate of the sampling transistor Ms at time T19 during application of the video signal pulse PP (1). Then, as shown in FIG. 10A, the sampling transistor Ms is turned on, and the difference between the data potential Vsig (= Vin + Vo) of the video signal line DTL (j) and the gate potential Vg (= Vo), that is, data The voltage Vin is input to the gate of the drive transistor Md. As a result, the gate potential Vg becomes “Vo + Vin”.
When the gate potential Vg rises by the data voltage Vin, the source potential Vs also rises in conjunction with this. At this time, the data voltage Vin is not directly transmitted to the source potential Vs, but the source potential Vs rises by a change ΔVs of the ratio corresponding to the capacitive coupling ratio g, that is, “g * Vin”. This is shown in the following formula (1).

[Equation 1]
ΔVs = Vin (= Vsig−Vo) × Cs / (Cs + Coled.) (1)
Here, the capacitance value of the holding capacitor Cs is indicated by the same symbol “Cs”. The symbol “Coled.” Is an equivalent capacitance value of the organic light emitting diode OLED.
From the above, the source potential Vs after the change is “Vo−Vth + g * Vin” unless mobility correction is taken into consideration. As a result, the gate-source voltage Vgs of the drive transistor Md becomes “(1−g) Vin + Vth”.

Here, the variation due to the mobility μ will be described.
Although the error due to the mobility μ is actually included every time the drain current Ids is flowed in the threshold voltage correction performed earlier, the error component due to the mobility μ is not strictly discussed because the variation in the threshold voltage Vth is large. It was. At this time, the reason why the description is simply expressed as “up” or “down” without using the capacitive coupling ratio g is to avoid the complexity caused by explaining the variation in mobility. is there.
On the other hand, as already described, after the threshold voltage correction is strictly performed, the threshold voltage Vth is held in the holding capacitor Cs at that time. The drain current Ids does not vary depending on the magnitude of Vth. For this reason, if the drive transistor Md after the threshold voltage correction is conducted, if the value of the holding voltage (gate-source voltage Vgs) of the holding capacitor Cs varies due to the drive current Id during the conduction, the amount of fluctuation ΔV (which can be positive or negative) is a variation of the mobility μ of the driving transistor Md, more precisely, in addition to the mobility in a pure sense, which is a physical property parameter of the semiconductor material, This reflects the overall variation in factors that affect the current driving force in the structure or manufacturing process.

  Returning to the description of the operation based on the above, in FIG. 10A, when the sampling transistor Ms is turned on and the data voltage Vin is added to the gate potential Vg, the driving transistor Md is connected to the data voltage Vin. A drain current Ids having a magnitude corresponding to (gradation value) is attempted to flow between the source and the drain. At this time, the drain current Ids varies depending on the mobility μ, and as a result, the source potential Vs becomes “Vo−Vth + g * Vin + ΔV” obtained by adding the variation ΔV due to the mobility μ to “Vo−Vth + g * Vin”. .

At this time, in order to prevent the organic light emitting diode OLED from emitting light, the cathode potential Vcath corresponding to the data voltage Vin, the capacitive coupling ratio g, or the like is satisfied so that “Vs (= Vo−Vth + g * Vin + ΔV) <Vth_oled. + Vcath” is satisfied. It may be set in advance.
If this setting is performed in advance, the organic light emitting diode OLED is reverse-biased and does not emit light because it is in a high impedance state, and exhibits simple capacitance characteristics rather than diode characteristics.

  At this time, as long as the expression “Vs (= Vo−Vth + g * Vin + ΔV) <Vth_oled. + Vcath” is satisfied, the source potential Vs exceeds the sum of the emission threshold voltage Vth_oled. Of the organic light emitting diode OLED and the cathode potential Vcath. Therefore, the drain current Ids (drive current Id) is the capacitance value of the holding capacitor Cs (denoted by the same symbol Cs) and the capacitance value of the equivalent capacitance at the time of reverse bias of the organic light emitting diode OLED (denoted by the same symbol Coled. As the parasitic capacitance). Is used to charge the capacity “C = Cs + Coled.”. As a result, the source potential Vs of the drive transistor Md increases. At this time, since the threshold voltage correction operation of the drive transistor Md is completed, the drain current Ids that the drive transistor Md flows reflects the mobility μ.

4 (D) and 4 (E), the gate-source voltage Vgs held in the holding capacitor Cs is set to the source potential Vs as indicated by the expression “(1−g) Vin + Vth−ΔV”. Since the added fluctuation amount ΔV is subtracted from the gate-source voltage Vgs (= (1−g) Vin + Vth) after the threshold voltage correction, the fluctuation amount ΔV is held in the holding capacitor Cs so that negative feedback is applied. . Therefore, hereinafter, the fluctuation amount ΔV is also referred to as “negative feedback amount”.
This negative feedback amount ΔV can be expressed by the equation: ΔV = t * Ids / (Coled. + Cs + Cgs) in a state where the organic light emitting diode OLED is reverse-biased. From this equation, it can be seen that the fluctuation amount ΔV is a parameter that changes in proportion to the fluctuation of the drain current Ids.

From the negative feedback amount ΔV, the negative feedback amount ΔV added to the source potential Vs is the magnitude of the drain current Ids (this magnitude is positively correlated with the magnitude of the data voltage Vin, that is, the gradation value). 4), it depends on the time during which the drain current Ids flows, that is, the time (t) from the time T19 required for mobility correction to the time T1A shown in FIG. That is, the larger the gradation value and the longer the time (t), the larger the negative feedback amount ΔV.
Therefore, the mobility correction time (t) is not necessarily constant, and on the contrary, it may be preferable to adjust it according to the drain current Ids (gradation value). For example, when the drain current Ids is close to white display and the drain current Ids is large, the mobility correction time (t) is shortened. Conversely, when the drain current Ids is close to black display and becomes small, the mobility correction time (t) is lengthened. It is good to set to. This automatic adjustment of the mobility correction time according to the gradation value can be realized by providing the function in advance in the write signal scanning circuit 42 shown in FIG.

[Light emission permission period (LM1)]
When the writing & mobility correction period (W & μ) ends at time T1A, the light emission permission period (LM1) starts.
Since the write pulse WP ends at time T1A, the sampling transistor Ms is turned off, and the gate of the drive transistor Md is in an electrically floating state.

  By the way, in the writing & mobility correction period (W & μ) before the light emission permission period (LM1), the drive transistor Md tries to flow the drain current Ids according to the data voltage Vin, but it is not always possible to actually flow it. . The reason is that since the sampling transistor Ms is turned on, the gate potential Vg of the driving transistor Md is fixed to “Vo + Vin”, and the gate-source voltage Vgs (= “(1−g) Vin + Vth−ΔV”) decreases from there. This is because the source potential Vs tends to converge to the potential (“Vo−Vth + g * Vin + ΔV”). Therefore, no matter how long the mobility correction time (t) is increased, the source potential Vs cannot be a potential exceeding the convergence point. In the mobility correction, the difference in mobility μ is monitored and corrected based on the difference in speed until convergence. For this reason, even when the data voltage Vin for white display with the maximum luminance is input, the time (t) for mobility correction is determined to the extent that the convergence is not achieved.

When the light emission permission period (LM1) starts and the gate of the drive transistor Md becomes floating, the source potential Vs can be further increased. Therefore, the drive transistor Md operates so as to flow the drive current Id corresponding to the input data voltage Vin.
As a result, the source potential Vs (the anode potential of the organic light emitting diode OLED) rises, and as shown in FIG. 10B, the drain current Ids starts to flow as the driving current Id to the organic light emitting diode OLED. Actually starts to emit light. After a while from the start of light emission, the drive transistor Md is saturated with the drain current Ids corresponding to the input data voltage Vin, and when the drain current Ids (= Id) becomes constant, the organic light emitting diode OLED becomes the data voltage Vin. The light emission state with the corresponding brightness is obtained.

The rise in the anode potential of the organic light emitting diode OLED is nothing but the rise in the source potential Vs of the driving transistor Md from the start of the light emission permission period (LM1) until the luminance becomes constant, “ΔVoled.” In the sense of an increase amount of the anode voltage Voled. The source potential Vs of the drive transistor Md is “Vo−Vth + g * Vin + ΔV + ΔVoled.” (See FIG. 4E).
On the other hand, since the gate potential Vg is in a floating state, as shown in FIG. 4D, the gate potential Vg rises by the same amount as the increase amount ΔVoled. In conjunction with the source potential Vs, and the drain current Ids is saturated. Accordingly, when the source potential Vs is saturated, the gate potential Vg is also saturated.
As a result, for the gate-source voltage Vgs (holding voltage of the holding capacitor Cs), the mobility correction value (“(1−g) Vin + Vth−ΔV”) is maintained even during the light emission permission period (LM1).

In the light emission permission period (LM1), since the drive transistor Md operates as a constant current source, the IV characteristic of the organic light emitting diode OLED changes with time, and the source potential Vs of the drive transistor Md changes accordingly. Sometimes.
However, the holding voltage of the holding capacitor Cs is maintained at “(1−g) Vin + Vth−ΔV” regardless of whether the IV characteristic of the organic light emitting diode OLED changes with time. Since the holding voltage of the holding capacitor Cs includes a component (+ Vth) for correcting the threshold voltage Vth of the driving transistor Md and a component (−ΔV) for correcting the variation due to the mobility μ, the threshold voltage Vth and the movement Even if the degree μ varies between different pixels, the drain current Ids of the drive transistor Md, that is, the drive current Id of the organic light emitting diode OLED is kept constant.

Specifically, as the threshold voltage Vth increases, the drive transistor Md decreases the source potential Vs by the threshold voltage correction component (+ Vth) of the holding voltage so that the drain current Ids (drive current Id) flows more. Increase drain-to-drain voltage. Therefore, the drain current Ids is constant even if the threshold voltage Vth varies.
In addition, when the mobility μ is small and the fluctuation amount ΔV is small, the driving transistor Md has a relatively small decrease amount of the holding voltage due to the mobility correction component (−ΔV) of the holding voltage of the holding capacitor Cs. Therefore, a large source-drain voltage is ensured, and as a result, the drain current Ids (driving current Id) flows more. Therefore, the drain current Ids is constant even when the mobility μ varies.

FIG. 11 shows an initial state where threshold voltage and mobility are not corrected ((A)), a state where only threshold voltage correction is performed ((B)), and a state where threshold voltage and mobility are corrected ((C )) Schematically shows a change in the relationship between the magnitude of the data potential Vsig and the drain current Ids (input / output characteristics of the drive transistor Md).
From FIG. 11, it can be seen that the characteristic curves of the pixel A and the pixel B, which are greatly deviated from each other, first approach each other by the threshold voltage correction, and then approach to the extent that they can be regarded as almost the same when the mobility correction is performed.

  From the above, even if the threshold voltage Vth and mobility μ of the drive transistor Md vary between pixels, and even if the characteristics of the drive transistor Md change over time, the organic light emitting diode OLED can be used as long as the data voltage Vin remains the same. The light emission brightness is also kept constant.

  Next, the effect of making the power supply drive pulse DS three-valued and making the reverse bias period constant in this embodiment will be described using a comparative example in which the power supply drive pulse DS is binary-controlled.

<Comparative example>
12A to 12E are timing charts showing waveforms of various signals and voltages in the light emission control of the comparative example. In FIG. 12, pulses, time (timing), potential changes and the like overlapping those in FIG. 4 are all denoted by the same reference numerals. Therefore, as far as the same reference numerals are concerned, the description so far applies also to the comparative example. Hereinafter, only differences between the control in FIG. 12 and the control in FIG. 4 will be described.

  As apparent from comparison of FIG. 12 with FIG. 4, in the control shown in FIG. 12, the power supply driving pulse DS in the control shown in FIG. 4 is ternary control, whereas in the control shown in FIG. Takes two values, a high potential Vcc_H and a low potential Vcc_L. The potential of the power supply driving pulse DS takes the low potential Vcc_L during the light emission stop processing period (LM-STOP) (time T0C to time T16) of the field F (0), and takes the high potential Vcc_H in other periods.

The light emission stop processing period (LM-STOP) in the control of FIG. 12 is different from the light emission stop processing period (LM-STOP) in the control of FIG. 4, and the write drive pulse WS is activated at a high level at time T0D. Therefore, this is a processing period that also serves as an initialization period (INT) in the control of FIG.
Therefore, the correction preparation (initialization) performed immediately before the threshold correction period (VTC) process is performed during the light emission stop period (LM-STOP).

  However, the length of the light emission stop period (LM-STOP) may be changed depending on the specifications of the system (equipment) in which the organic EL display 1 is mounted. A so-called “flash phenomenon” occurs.

FIG. 13 is a diagram for explaining the cause of the flash phenomenon.
FIG. 13A shows the waveform of the power supply driving pulse DS shown in FIG. 12C for about one field (1F) over four fields (4F).
In FIG. 4 described above, the threshold correction period (VTC) and the writing & mobility correction period (W & μ) are slightly shorter than the light emission permission periods (LM0, LM1). For this reason, in FIG. 13A, the threshold correction period (VTC) and the writing & mobility correction period (W & μ) are not shown, and the light emission permission period (LM) starts from the beginning of the 1F period. Here, the light emission permission period (LM) is a period in which the potential of the power supply driving pulse DS takes the high potential Vcc_H, and the subsequent period of the low potential Vcc_L corresponds to the light emission stop processing period (LM-STOP) shown in FIG. .

FIG. 13B schematically shows the light emission intensity L that changes at the timing synchronized with FIG. Here, a case where pixel rows having the same data voltage Vin are continuously displayed for a period of 4F is shown.
As shown in FIG. 13A, the light emission stop period (LM-STOP) is relatively short in the first 2F period, while the light emission stop period (LM-STOP) is relatively long in the subsequent 2F period. ing. In this system (equipment) in which the organic EL display 1 is mounted, this control is performed when, for example, the CPU or the like (not shown) in the device is darkened in response to the device being moved from the outdoor to the indoor. In some cases, the brightness of the display is lowered as a whole to improve the visibility. Similar processing may be performed by shifting to the low power consumption mode. On the other hand, there is a case where the CPU or the like performs control to keep the drive current constant for the purpose of extending the life of the organic light emitting diode OLED. For example, when the data voltage Vin is large, the drive current is kept constant to prevent the drive current from increasing excessively, and the light emission luminance corresponding to the data voltage Vin is ensured by extending the light emission permission period (LM). In the opposite case, that is, as shown in the drawing, a predetermined emission luminance may be obtained in response to a decrease in the data voltage Vin by shortening the emission permission period (LM) while keeping the drive current constant at a large value.

In the organic light emitting diode OLED, it takes time until the value of the capacitance Coled. Shown in FIG. This time is longer than the 1F period, and the capacitance value changes slowly, so that the value of the capacitance Coled. Increases as the reverse bias period increases. For this reason, from the above equation (1), the larger the value of the capacitance Coled., The smaller the change ΔVs of the source potential Vs, and the gate-source voltage Vgs of the drive transistor Md is input with the same data voltage Vin. It will be larger than the other fields in time. When the gate-source voltage Vgs increases between the fields, as shown in FIG. 13B, the light emission intensity L increases by “ΔL” from the display of the next field, and the entire display surface becomes bright instantly. “Flash phenomenon” occurs.
On the contrary, when the initialization period (INT) is suddenly shortened, the reverse bias period is shortened, and the gate-source voltage Vgs is suddenly decreased for the opposite reason, so that the light emission intensity L is reduced and displayed. A phenomenon that the screen darkens in an instant (a type of flash phenomenon) occurs.

14A and 14B are diagrams showing the waveform diagram of the power supply driving pulse DS and the light emission intensity L corresponding to FIGS. 13A and 13B.
In order to prevent the flash phenomenon, in the display control shown in FIGS. 14A and 4C according to the present embodiment, the length is defined by the low potential Vcc_L of the power supply driving pulse DS, and the length is required by the system. The light emission stop processing period (LM-STOP) that also serves as initialization that may fluctuate is fixed in time. Instead, a medium potential Vcc_M having a level at which a reverse bias is not applied to the organic light emitting diode OLED is provided as the potential of the power supply driving pulse DS. The application time of the medium potential Vcc_M is controlled in length so as to absorb the time variation of the light emission permission period.
Therefore, the reverse bias period that affects the light emission intensity L is always constant, and the flash phenomenon described above is effectively prevented. Specifically, as shown in FIG. 14B, the increase ΔL of the emission intensity L generated in FIG. 13B does not occur in the field after the light emission time is shortened.

  A modification in this embodiment will be described.

<Modification 1>
The pixel circuit is not limited to that shown in FIG.
In the pixel circuit of FIG. 2, the data reference potential Vo is given by sampling the video signal Ssig, but the data reference potential Vo can also be given to the source and gate of the drive transistor Md via another transistor.
In the pixel circuit of FIG. 2, the capacitor is only the holding capacitor Cs. However, another holding capacitor may be provided between the drain and the gate of the driving transistor Md, for example.

<Modification 2>
A driving method in which the pixel circuit controls light emission and non-light emission of the organic light emitting diode OLED includes a method in which the transistors in the pixel circuit are controlled by a scanning line, and a method in which a power supply voltage supply line is AC driven by a driving circuit (power supply AC Drive method).
The pixel circuit of FIG. 2 is an example of the latter power source AC driving method, but in this method, the cathode side of the organic light emitting diode OLED may be AC driven to control whether a driving current flows or not.
On the other hand, in the former method of controlling the light emission control by the scanning line, another transistor is inserted between the drain side of the driving transistor Md or between the source and the organic light emitting diode OLED, and the gate thereof is scanned for power supply driving control. Drive with lines.

<Modification 3>
In the display control shown in FIG. 4, the threshold correction period (VTC) is performed by one correction. However, even if the threshold correction is performed by a plurality of consecutive processes (meaning that initialization is not sandwiched), Good.
In addition, during the light emission permission period, control such as temporarily stopping the light emission while keeping the gate of the drive transistor Md floating may be arbitrarily performed.

  According to the embodiment of the present invention, even if the light emission permission period is changed for each field, the bias fluctuation of the organic light emitting diode that occurred during the non-light emission permission period (light emission stop period) due to the length of the reverse bias application period. If the same data voltage is input without being influenced by the above, the luminance of each field becomes the same, so that a so-called flash phenomenon can be effectively prevented.

  DESCRIPTION OF SYMBOLS 1 ... Organic EL display, 2 ... Pixel array, 3 ... Pixel circuit, 4 ... V scanner, 5 ... H selector, 41 ... Horizontal pixel line drive circuit, 42 ... Write signal scanning circuit, OLED ... Organic light emitting diode, Md ... Drive Transistor, Ms ... Sampling transistor, Cs ... Holding capacitor, NDc ... Control node, DSL ... Power supply scan line, DS ... Power supply drive pulse, DTL ... Video signal line, WSL ... Write scan line, WS ... Write drive pulse, Vsig , Vin ... data potential, Vo ... data reference potential, Vcc_H ... high potential, Vcc_M ... medium potential, Vcc_L ... low potential

Claims (12)

Including a plurality of pixel circuits and a drive circuit;
Each of the plurality of pixel circuits is
A light emitting diode;
A drive transistor for controlling a current flowing from a power supply line to the light emitting diode;
A storage capacitor coupled to a control node of the drive transistor;
A sampling transistor that controls sampling of a signal from a signal line to the storage capacitor;
Including at least
The drive circuit is
After stopping the light emission of the light emitting diode by setting the anode electrode of the light emitting diode to an intermediate potential higher than the potential of the cathode electrode of the light emitting diode,
The anode electrode of the light emitting diode is lower than the intermediate potential, and a potential equal to or lower than the potential of the cathode electrode of the light emitting diode,
A signal voltage corresponding to a video signal is applied to one end of the storage capacitor from the signal line through the sampling transistor, and a current supplied from a power supply line is supplied to the storage capacitor through a drive transistor. From
By turning off the sampling transistor and setting the anode electrode of the light emitting diode to a potential at which the light emitting diode can emit light, a current corresponding to the voltage held in the storage capacitor is supplied to the light emitting diode. To drive,
Display device. The drive circuit is
The holding capacitor is configured to apply the signal voltage from the signal line to the one end of the holding capacitor via the sampling transistor and to cause a current supplied from a power supply line to flow to the holding capacitor via the driving transistor. Driving to maintain a voltage corresponding to both the driving capability of the driving transistor and the signal voltage;
The display device according to claim 1. The pixel circuit further includes a transistor that applies an initialization voltage to the storage capacitor.
The display device according to claim 1 or 2. The pixel circuit further includes a light emission control transistor connected between the driving transistor and the power supply line or between the transistor and a light emitting diode.
The display device according to any one of claims 1 to 3. The light emitting diode is an organic light emitting device,
The display device according to any one of claims 1 to 4. A display panel having a drive circuit and a plurality of pixel circuits;
A control circuit for controlling the drive circuit;
Including
Each of the plurality of pixel circuits is
A light emitting diode;
A drive transistor for controlling a current flowing from a power supply line to the light emitting diode;
A storage capacitor coupled to a control node of the drive transistor;
A sampling transistor that controls sampling of a signal from a signal line to the storage capacitor;
Including at least
The drive circuit is
After performing a first drive to stop the light emission of the light emitting diode by setting the anode electrode of the light emitting diode to an intermediate potential higher than the potential of the cathode electrode of the light emitting diode,
Performing a second drive for setting the anode electrode of the light emitting diode to a potential lower than the intermediate potential and equal to or less than the potential of the cathode electrode of the light emitting diode;
A signal voltage corresponding to a video signal is applied to one end of the storage capacitor from the signal line through the sampling transistor, and a current supplied from a power supply line is supplied to the storage capacitor through a drive transistor. From
By turning off the sampling transistor and setting the anode electrode of the light emitting diode to a potential at which the light emitting diode can emit light,
Driving to perform a light emitting operation of supplying a current corresponding to the voltage held in the holding capacitor to the light emitting diode;
Electronics. The drive circuit is
The driving operation is repeated with one frame or one field period as a cycle,
The period of the light emitting operation and the period of the first drive are variable according to the control of the drive circuit.
The electronic device according to claim 6. The drive circuit controls the period of the light emitting operation and the period of the first drive according to the brightness of the surrounding environment.
The electronic device according to claim 7. The drive circuit is
By applying a signal voltage from the signal line to the one end of the storage capacitor via the sampling transistor, and by causing a current supplied from a power supply line to flow to the storage capacitor via the drive transistor, the storage capacitor Driving to maintain a voltage corresponding to both the driving capability of the driving transistor and the signal voltage;
The electronic device according to any one of claims 6 to 8. The pixel circuit further includes a transistor that applies an initialization voltage to the storage capacitor.
The electronic device according to any one of claims 6 to 9. The pixel circuit further includes a light emission control transistor connected between the driving transistor and the power supply line or between the transistor and a light emitting diode.
The electronic device according to any one of claims 6 to 10. The light emitting diode is an organic light emitting device,
The electronic device according to claim 6.

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