JP2013045807A - Nonvolatile semiconductor storage device manufacturing method and nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor device manufacturing method which optimizes a shape of a cavity between gate electrodes of a memory cell transistor to achieve high performance and high reliability.SOLUTION: A nonvolatile semiconductor storage device manufacturing method of an embodiment comprises: forming on a semiconductor substrate, a plurality of memory cell gate electrodes each including a lamination structure of a first gate insulation film, a first floating gate electrode, a first inter-gate insulation film, a first control gate electrode, a first gate mask insulation film; forming a protection film on a side wall of the memory cell gate electrode and removing a part of the protection film so as to expose a part of a side wall of the first control gate electrode; forming a metal film and reacting the metal film with the control gate electrode by a heat treatment to form a first metal semiconductor compound layer; and embedding between the memory cell gate electrodes to form an interlayer insulation film having cavities inside such that each of top edges of the cavities is located at a distance from the semiconductor substrate further than a top face of the first control gate electrode.

Description

  Embodiments described herein relate generally to a method for manufacturing a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device.

  Nonvolatile semiconductor memory devices using semiconductor elements such as EEPROM, AND flash memory, NOR flash memory, NAND flash memory, etc. have been widely known. Among them, the NAND flash memory is advantageous for high integration because each memory cell shares a source / drain diffusion layer.

  As the NAND flash memory is highly integrated, it is required to reduce the resistance of the gate electrode of the memory cell transistor and improve the coupling ratio in order to maintain or improve the memory performance. As a means for realizing low resistance, there is silicidation of the gate electrode. As a means for improving the coupling ratio, there is a method of providing a gap (air gap) in the insulating film between the gate electrodes.

JP 2008-21768 A

  The problem to be solved by the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device that optimizes the shape of the gap between the gate electrodes of the memory cell transistor and realizes high performance and high reliability. There is to do.

  A method for manufacturing a nonvolatile semiconductor memory device according to an embodiment includes a first gate insulating film, a first floating gate electrode, a first inter-gate insulating film, a first control gate electrode, a first gate, A plurality of memory cell gate electrodes having a stacked structure of gate mask insulating films, a protective film is formed on a side wall of the memory cell gate electrode, and a part of the protective film is formed on the first control gate electrode. A part of the side wall is removed so as to be exposed, a metal film is formed on the first gate mask insulating film and on the side wall of the first control gate electrode, and the metal film and the first control gate are formed. The electrode is reacted by heat treatment to form a first metal semiconductor compound layer, the metal film and the first control gate electrode are reacted to form a first metal semiconductor compound layer, An interlayer insulating film having a gap between the memory cell gate electrodes and having a gap inside, wherein the upper end of the gap is located at a position farther from the semiconductor substrate than the upper surface of the first control gate electrode Form.

1 is a schematic cross-sectional view of a nonvolatile semiconductor memory device according to an embodiment. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device in the embodiment. FIG. It is a schematic cross section which shows the modification of the manufacturing method of the non-volatile semiconductor memory device of embodiment. It is a figure which shows the effect | action of the manufacturing method of the non-volatile semiconductor memory device of embodiment.

  In the method of manufacturing the nonvolatile semiconductor memory device of this embodiment, a first gate insulating film, a first floating gate electrode, a first inter-gate insulating film, a first control gate electrode, A plurality of memory cell gate electrodes having a laminated structure of one gate mask insulating film is formed. A peripheral gate having a laminated structure of a second gate insulating film, a second floating gate electrode, a second inter-gate insulating film, a second control gate electrode, and a second gate mask insulating film on the semiconductor substrate An electrode is formed. Then, a protective film is formed on the side wall portion of the memory cell gate electrode, and a part of the protective film is removed so that a part of the side wall portion of the first control gate electrode is exposed. Then, a metal film is formed on the first gate mask insulating film and on the side wall of the first control gate electrode, and the metal film and the first control gate electrode are reacted by heat treatment to cause the first metal semiconductor compound film Then, an interlayer insulating film having a gap between the memory cell gate electrodes is formed. The gap of the interlayer insulating film has an upper end at a position farther from the semiconductor substrate than the upper surface of the first control gate electrode. Note that the nonvolatile semiconductor memory device of this embodiment is a NAND flash memory.

  According to the method for manufacturing the nonvolatile semiconductor memory device of the embodiment, the electric field concentration inside the interlayer insulating film is suppressed by setting the upper end of the gap of the interlayer insulating film to a position higher than the upper surface of the control gate electrode. Therefore, a memory cell transistor having high reliability is realized. Further, since the size of the gap (air gap) in the interlayer insulating film between the gate electrodes is increased, the coupling ratio of the gate electrode of the memory cell transistor is improved, and a high-performance memory transistor is realized.

  FIG. 1 is a schematic cross-sectional view of the nonvolatile semiconductor memory device according to the embodiment. 1A is a cross-sectional view of the memory cell transistor in the channel length direction, and FIG. 1B is a cross-sectional view of the peripheral transistor in the channel length direction.

  In this specification, the peripheral transistor is a general term for transistors other than the memory cell transistor. For example, the concept includes a selection gate transistor disposed adjacent to the memory cell transistor.

  Further, in this specification, the gate electrode of the memory cell transistor is referred to as a memory cell gate electrode, and the gate electrode of the peripheral transistor is referred to as a peripheral gate electrode. The line width of the peripheral gate electrode is larger than the line width of the memory cell gate electrode.

  As shown in FIG. 1, the non-volatile semiconductor memory device is formed using a p-type silicon semiconductor substrate 10, for example. The impurity of the semiconductor substrate 10 is, for example, boron (B).

  As shown in FIG. 1A, in the memory cell array portion, a first gate insulating film 12, a first floating gate electrode 14, a first inter-gate insulating film 16, a first control are formed on a semiconductor substrate 10. A plurality of memory cell gate electrodes MG having a stacked structure of the gate electrode 18 and the first gate mask insulating film 20 are formed.

  The first gate insulating film 12 is, for example, a silicon oxide film. The first floating gate electrode 14 is, for example, a polycrystalline silicon film doped with phosphorus (P). The first inter-gate insulating film 16 is, for example, an ONO (Oxide-Nitride-Oxide) film. The first control gate electrode 18 has a laminated structure of, for example, a polycrystalline silicon layer 18a and a silicide layer 18b. The silicide layer 18b is, for example, a nickel silicide (NiSi) layer or a cobalt silicide (CoSi) layer. The first gate mask insulating film 20 is, for example, a silicon nitride film.

  Further, as shown in FIG. 1B, in the peripheral portion, on the semiconductor substrate 10, the second gate insulating film 22, the second floating gate electrode 24, the second inter-gate insulating film 26, the second A peripheral gate electrode PG having a laminated structure of the control gate electrode 28 and the second gate mask insulating film 30 is formed.

  A portion of the second inter-gate insulating film 26 is removed to provide a conductive portion, so that the second floating gate electrode 24 and the second control gate electrode 28 are in physical contact and electrically Is also conducting.

  An opening 32 reaching the upper surface of the second control gate electrode 28 is provided in the second gate mask insulating film 30.

  The second gate insulating film 22 is, for example, a silicon oxide film. The second floating gate electrode 24 is, for example, a polycrystalline silicon film doped with phosphorus (P). The second inter-gate insulating film 26 is, for example, an ONO (Oxide-Nitride-Oxide) film. The second control gate electrode 28 has a laminated structure of, for example, a polycrystalline silicon layer 18a and a silicide layer 18b. The silicide layer 18b is, for example, a nickel silicide (NiSi) layer or a cobalt silicide (CoSi) layer. The second gate mask insulating film 30 is, for example, a silicon nitride film.

  A protective film 34 is provided on the side walls of the memory cell gate electrode MG and the peripheral gate electrode PG. The protective film 34 is, for example, a silicon oxide film.

Then, an interlayer insulating film 38 having a gap 36 embedded therein and provided between the memory cell gate electrodes MG is provided. The gap 36 has an upper end at a position farther from the semiconductor substrate 10 than the upper surface of the first control gate electrode 18. That is, in FIG. 1A, the distance h ₁ between the semiconductor substrate 10 and the upper end of the gap 36 is larger than the distance h ₂ between the semiconductor substrate 10 and the upper surface of the first control gate electrode 18. That is, h ₁ > h ₂ .

  The interlayer insulating film 38 is, for example, a silicon oxide film. The interlayer insulating film 38 is also provided on the peripheral gate electrode PG.

  Although not shown in FIG. 1, for example, a multilayer wiring layer including a plurality of wiring layers and contacts is formed on the interlayer insulating film 38.

Adjacent when the distance h ₁ between the semiconductor substrate 10 and the upper end of the gap 36 is not more than the distance h ₂ between the semiconductor substrate 10 and the upper surface of the first control gate electrode 18, that is, when h ₁ ≦ h _2. At least at the uppermost portion between the first control gate electrodes 18, an interlayer insulating film 38 is present between the electrodes without interruption. For this reason, the electric field concentrates on the upper surface corner of the first control gate electrode 18. Therefore, there is a concern that the interlayer insulating film 38 may break down or leakage current between adjacent gate electrodes may increase. That is, the characteristics of the memory cell transistor are deteriorated, and the memory cell may malfunction.

  According to the embodiment, the air gap 36 exists between the adjacent first control gate electrodes 18. Therefore, the electric field between the adjacent control gate electrodes 18 is relaxed, the dielectric breakdown of the interlayer insulating film 38 is less likely to occur, and the leakage current between the adjacent gate electrodes is also suppressed.

Further, since the size of the gap 36 between the adjacent first control gate electrodes 18 is larger than that when h ₁ ≦ h ₂ , the first control gate electrodes 18 or the first control gate electrodes 18 are adjacent to each other. The capacity between the gate electrode 18 and the semiconductor substrate 10 is reduced, and the coupling ratio of the gate electrode is also improved. Therefore, for example, the write characteristics of the memory cell are improved.

  Further, as in the case where the second gate mask insulating film 30 is a silicon nitride film and the interlayer insulating film 38 is a silicon oxide film, the dielectric constant of the second gate mask insulating film 30 is greater than the dielectric constant of the interlayer insulating film 38. If it is higher, the wiring capacity of the peripheral gate electrode is suppressed by providing the opening 32 in the second gate mask insulating film 30. Therefore, there is an advantage that the peripheral transistor is increased in speed.

  Next, a method for manufacturing the nonvolatile semiconductor memory device according to the embodiment will be described with reference to the drawings. 2 to 10 are schematic cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment. 2A to 10A are cross-sectional views of the memory cell transistor in the channel length direction, and FIGS. 2B to 10B are cross-sectional views of the peripheral transistors in the channel length direction.

  First, as shown in FIG. 2, a first gate insulating film 12, a first floating gate electrode 14, a first inter-gate insulating film 16, a first gate insulating film 16 are formed on a p-type silicon semiconductor substrate 10 by a known method. A plurality of memory cell gate electrodes MG having a stacked structure of one control gate electrode 18 and first gate mask insulating film 20 are formed. In this state, the first control gate electrode 18 is formed only of the polycrystalline silicon layer 18a.

The first gate insulating film 12 is, for example, a silicon oxide film formed by thermal oxidation. The first floating gate electrode 14 is, for example, a polycrystalline silicon film doped with phosphorus (P) formed by LPCVD (Low Pressure Chemical Vapor Deposition). The first inter-gate insulating film 16 is, for example, an ONO (Oxide-Nitride-Oxide) film. The polycrystalline silicon layer 18a is a polycrystalline silicon film doped with phosphorus (P) formed by LPCVD, for example. The first gate mask insulating film 20 is, for example, a silicon nitride film. As a material of the first gate mask insulating film 20, for example, a silicon oxide film, alumina (Al ₂ O ₃ ), titania (TiO ₂ ), or the like can be used.

  Simultaneously with the memory cell gate electrode MG, the second gate insulating film 22, the second floating gate electrode 24, the second inter-gate insulating film 26, the second control gate electrode 28, the second gate insulating film 22 are formed on the semiconductor substrate 10. A peripheral gate electrode PG having a laminated structure of the gate mask insulating film 30 is formed. However, before the formation of the polycrystalline silicon layer 28a of the second control gate electrode 28, a part of the second inter-gate insulating film 26 is removed.

  As the material of each layer of the peripheral gate electrode PG, the same material as that of the memory cell gate electrode MG can be applied.

  Next, as shown in FIG. 3, a protective film 34 is formed on the memory cell gate electrode MG and the peripheral gate electrode PG. The protective film 34 is a silicon oxide film deposited by, for example, the LPCVD method, the ALD (Atomic Layer Deposition) method, or the like.

  Next, as shown in FIG. 4, for example, a resist film 40 is applied and resist etch back is performed by RIE (Reactive Ion Etching). By this etching, the resist film 40 is etched so as to partially remain between the memory cell gate electrodes MG and between the peripheral gate electrodes PG. Subsequently, the protective film 34 is etched by the RIE method. By this etching, a part of the protective film 34 is removed so that a part of the side walls of the first control gate electrode 18a and the second control gate electrode 28a is exposed.

  At this time, the upper end of the protective film 34 on the side wall portion of the memory cell gate electrode MG is above the first inter-gate insulating film 16 and the second inter-gate insulating film 26, that is, the first inter-gate insulating film 16 and The process is controlled so that the second inter-gate insulating film 26 is positioned away from the semiconductor substrate 10. This is to prevent the first floating gate electrode 14 and the second floating gate electrode 24 from reacting with the metal film when forming the metal semiconductor compound later.

  The resist film 40 prevents the protective film 34 and the gate insulating film 12 at the bottom between the memory cell gate electrodes MG from being etched when the protective film 34 is etched.

  Next, as shown in FIG. 5, the resist film 40 is removed by, for example, ashing.

  Next, as shown in FIG. 6, a resist mask 42 in which a part of the peripheral gate electrode PG on the second gate mask insulating film 30 is opened is formed by lithography.

  Next, as shown in FIG. 7, an opening 32 is formed by RIE so that the upper surface of the polycrystalline silicon layer 28a of the second control gate electrode 28 is exposed. Thereafter, the resist mask 42 is removed by, for example, ashing.

  Next, as shown in FIG. 8, a metal film 44 is formed on the memory cell gate electrode MG and the peripheral gate electrode PG. At this time, the metal film 44 is formed on the first gate mask insulating film 20 and on the side wall portion of the first control gate electrode 18a. The metal film 44 is also formed on the upper surface of the second control gate electrode 28a.

  The metal film 44 is, for example, a nickel (Ni) film or a cobalt (Co) film formed by a PVD (Physical Vapor Deposition) method. The metal film 44 can also be formed by, for example, a plating method.

  Next, as shown in FIG. 9, the metal film 44 and the polycrystalline silicon layer 18a of the first control gate electrode 18 are reacted by heat treatment to form a first metal semiconductor compound layer (silicide layer) 18b. Here, for example, when the metal film 44 is nickel, the first metal semiconductor compound layer 18b is a nickel silicide (NiSi) layer.

  By this heat treatment, the metal film 44 and the polycrystalline silicon layer 28a of the second control gate electrode 28 also react to form a second metal semiconductor compound layer (silicide layer) 28b.

  Next, as shown in FIG. 10, the unreacted metal film 44 is peeled off by, for example, wet etching. Thus, in the embodiment, a so-called salicide (self-aligned silicide) process is applied.

  Thereafter, an interlayer insulating film 38 is formed which is embedded between the memory cell gate electrodes MG and has a gap 36 therein. At this time, the gap 36 is formed such that the upper end of the gap 36 is positioned farther from the semiconductor substrate 10 than the upper surface of the first control gate electrode 18.

The interlayer insulating film 38 is, for example, a silicon oxide film formed by a plasma CVD (Chemical Vapor Deposition) method, such as a Plasma-TEOS (Tetraethyl orthosilicate) film or a Plasma-SiH ₄ film. As the step coverage of the interlayer insulating film 38 is worse, the gap 36 is more easily formed and its size is increased.

  The nonvolatile semiconductor memory device shown in FIG. 1 is formed by the above manufacturing method. Thereafter, multilayer wiring and the like are formed on the interlayer insulating film 38 by a known process to complete the nonvolatile semiconductor memory device.

  According to the manufacturing method of the embodiment, while using a so-called salicide process, the upper surface of the first control gate electrode 18 of the memory cell gate electrode MG is covered with the first gate mask insulating film 20, It is possible to form the interlayer insulating film 38 filling the space between the memory cell gate electrodes MG. Therefore, it is possible to form the interlayer insulating film 38 in which the upper end of the gap 36 is located at a position farther from the semiconductor substrate 10 than the upper surface of the first control gate electrode 18.

  However, the line width of the peripheral gate electrode PG is larger than the line width of the memory cell gate electrode MG. Therefore, in the peripheral gate electrode PG, there is a possibility that sufficient metal is not supplied for silicidation only from the metal film 44 in contact with the side wall portion. In the embodiment, the opening 32 is provided in the second gate mask insulating film before the metal film 44 is formed. By supplying the metal also from the opening 32, it is possible to realize sufficient silicidation in the peripheral gate electrode PG.

  Further, the degree of silicidation of the peripheral gate electrode PG can be controlled by adjusting the size of the opening 32 provided in the second gate mask insulating film. For example, when the gate electrode is formed by a salicide process, the sheet resistance after silicidation may vary depending on the line width of the gate electrode. According to the embodiment, for example, the line width dependency of the sheet resistance of the gate electrode can be improved by adjusting the size of the opening 32 according to the line width of the peripheral gate electrode.

  Alternatively, an optimum resistance value can be given to each gate electrode. For example, a low-resistance gate electrode can be formed by widening the opening 32 of the gate electrode where the resistance is to be lowered. In addition, a gate electrode having a high resistance can be realized by narrowing or eliminating the opening 32 of the gate electrode where the resistance is to be increased.

  FIG. 11 is a schematic cross-sectional view showing a modification of the method for manufacturing the nonvolatile semiconductor memory device of the embodiment. 11A is a cross-sectional view of the memory cell transistor in the channel length direction, and FIG. 11B is a cross-sectional view of the peripheral transistor in the channel length direction.

  FIG. 11 is a cross-sectional view immediately after the silicide layers 18b and 28b are formed by the heat treatment. As shown in FIG. 11A, in the memory cell gate electrode MG, the polycrystalline silicon layer 18a of the first control gate electrode 18 is completely reacted with the metal film 44 by the heat treatment to become the silicide layer 18b. This is a so-called FUSI (Fully Silicided) structure. On the other hand, in the peripheral gate electrode PG, a part of the unreacted polycrystalline silicon layer 28a remains.

  FIG. 12 is a diagram illustrating an operation of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment. FIG. 12 is a cross-sectional view immediately after the silicide layers 18b and 28b are formed by the heat treatment. 12A is a cross-sectional view of the memory cell transistor in the channel length direction, and FIG. 12B is a cross-sectional view of the peripheral transistor in the channel length direction.

  When the FUSI structure as shown in FIG. 11 is formed, a relatively long heat treatment is applied in order to completely silicide the polycrystalline silicon layer. In the memory cell gate electrode MG, since there is the first inter-gate insulating film 16, the first floating gate electrode 14 is not silicided.

  On the other hand, as shown in FIG. 12B, the peripheral gate electrode PG has a conductive portion provided by removing a part of the second inter-gate insulating film 26. When the heat treatment is performed for a long time, silicidation proceeds to the second floating gate electrode 24 through the conductive portion, and in some cases, the second gate insulating film 22 may be reached as shown in FIG. is there. In such a case, there is a concern that the breakdown breakdown voltage of the second gate insulating film 22 is deteriorated or leakage current is increased.

  According to the embodiment, even in the case of forming the FUSI structure, the silicide layer 28b is made to be the second gate insulating film 22 by adjusting the size of the opening 32 provided in the second gate mask insulating film. It is possible to suppress excessive silicidation that can be reached.

  As described above, according to the nonvolatile semiconductor memory device and the manufacturing method of the embodiment, electric field concentration inside the interlayer insulating film is suppressed by setting the upper end of the gap of the interlayer insulating film to a position higher than the upper surface of the control gate electrode. . Therefore, a memory cell transistor having high reliability is realized. In addition, since the size of the gap in the interlayer insulating film between the gate electrodes is increased, the coupling ratio of the gate electrode of the memory cell transistor is improved and a high-performance memory transistor is realized. Therefore, a nonvolatile semiconductor memory device having high performance and high reliability is realized.

  Further, by making it possible to control the degree of silicidation of the peripheral gate electrode, it is possible to give an optimum resistance value to each gate electrode pattern. In addition, it is possible to suppress deterioration of reliability such as deterioration of gate insulating film characteristics of the peripheral gate electrode. Therefore, also from this viewpoint, a nonvolatile semiconductor memory device having high performance and high reliability is realized.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. Further, in the description of the embodiments, the description of the non-volatile semiconductor memory device manufacturing method, the non-volatile semiconductor memory device, and the like that are not directly necessary for the description of the present invention is omitted. Elements related to a method for manufacturing a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device, and the like can be appropriately selected and used.

  In addition, all methods for manufacturing a nonvolatile semiconductor memory device and nonvolatile semiconductor memory devices that include the elements of the present invention and whose design can be changed as appropriate by those skilled in the art are included in the scope of the present invention. The scope of the present invention is defined by the appended claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 1st gate insulating film 14 1st floating gate electrode 16 1st inter-gate insulating film 18 1st control gate electrode 18a Polycrystalline silicon layer 18b Silicide layer (1st metal semiconductor compound layer)
20 first gate mask insulating film 22 second gate insulating film 24 second floating gate electrode 26 second intergate insulating film 28 second control gate electrode 28a polycrystalline silicon layer 28b silicide layer (second metal Semiconductor compound layer)
30 Second gate mask insulating film 32 Opening 34 Protective film 36 Void 38 Interlayer insulating film 44 Metal film

Claims (6)

A laminated structure of a first gate insulating film, a first floating gate electrode, a first inter-gate insulating film, a first control gate electrode of a polycrystalline silicon layer, and a first gate mask insulating film on a semiconductor substrate. Forming a plurality of memory cell gate electrodes,
A peripheral gate electrode having a laminated structure of a second gate insulating film, a second floating gate electrode, a second inter-gate insulating film, a second control gate electrode, and a second gate mask insulating film on the semiconductor substrate Form the
Forming a protective film on the side walls of the memory cell gate electrode and the peripheral gate electrode;
Removing a part of the protective film so that a part of a side wall portion of the first control gate electrode and the second control gate electrode is exposed;
An opening is provided in the second gate mask insulating film so that the upper surface of the second control gate electrode is exposed,
A nickel (Ni) film on the first gate mask insulating film, on the side wall of the first control gate electrode, on the upper surface of the second control gate electrode, and on the side wall of the second control gate electrode Alternatively, a metal film that is a cobalt (Co) film is formed,
Reacting the metal film and the first control gate electrode by a heat treatment to form a first metal semiconductor compound layer using the first control gate electrode as a metal semiconductor compound film completely;
Reacting the metal film and the second control gate electrode by the heat treatment to form a second metal semiconductor compound layer;
An interlayer insulating film having a gap between the memory cell gate electrodes and having a gap therein, the interlayer insulating film having an upper end of the gap located at a position farther from the semiconductor substrate than the upper surface of the first control gate electrode A method for manufacturing a nonvolatile semiconductor memory device. A plurality of memory cells having a stacked structure of a first gate insulating film, a first floating gate electrode, a first inter-gate insulating film, a first control gate electrode, and a first gate mask insulating film on a semiconductor substrate Forming a gate electrode,
Forming a protective film on the side wall of the memory cell gate electrode;
Removing a part of the protective film so that a part of the side wall of the first control gate electrode is exposed;
Forming a metal film on the first gate mask insulating film and on the side wall of the first control gate electrode;
Reacting the metal film and the first control gate electrode by heat treatment to form a first metal semiconductor compound layer;
An interlayer insulating film having a gap between the memory cell gate electrodes and having a gap therein, the interlayer insulating film having an upper end of the gap located at a position farther from the semiconductor substrate than the upper surface of the first control gate electrode A method for manufacturing a nonvolatile semiconductor memory device. A peripheral gate electrode having a laminated structure of a second gate insulating film, a second floating gate electrode, a second inter-gate insulating film, a second control gate electrode, and a second gate mask insulating film on the semiconductor substrate Form the
Before forming the metal film, an opening is provided in the second gate mask insulating film so that the upper surface of the second control gate electrode is exposed.
Forming the metal film on the upper surface of the second control gate electrode;
3. The method of manufacturing a nonvolatile semiconductor memory device according to claim 2, wherein the heat treatment causes the metal film and the second control gate electrode to react to form a second metal semiconductor compound layer.   4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 2, wherein the first control gate electrode is completely made into a metal semiconductor compound film by the heat treatment.   5. The device according to claim 2, wherein the first control gate electrode is a polycrystalline silicon layer, and the metal film is a nickel (Ni) film or a cobalt (Co) film. A method for manufacturing a nonvolatile semiconductor memory device. A semiconductor substrate;
A first gate insulating film, a first floating gate electrode, a first inter-gate insulating film, a first control gate electrode made of a metal semiconductor compound, and a first gate mask formed on the semiconductor substrate. A plurality of memory cell gate electrodes having a laminated structure of insulating films;
A second gate insulating film, a second floating gate electrode, a second inter-gate insulating film, a second control gate electrode made of at least a part of a metal semiconductor compound, and the second control film formed on the semiconductor substrate; A peripheral gate electrode having a laminated structure of a second gate mask insulating film provided with an opening reaching the upper surface of the gate electrode;
An interlayer insulating film embedded between the memory cell gate electrodes and having a gap inside, wherein the upper end of the gap is located at a position farther from the semiconductor substrate than the upper surface of the first control gate electrode A non-volatile semiconductor memory device comprising:

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