JP2013042211A - Am detection circuit and am detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To demodulate a detection signal while reducing the throughput without compromising the accuracy of the detection signal.SOLUTION: An AM detection circuit (120) comprises: a first zero-cross detection unit (122); a second zero-cross detection unit (123); and a holding unit (127). Based on a reception signal subjected to amplitude modulation (AM), a complex IF signal of LowIF system is generated. The first zero-cross detection unit (122) detects the zero-cross point of an IF_I signal representing the real part of the complex IF signal. The second zero-cross detection unit (123) detects the zero-cross point of an IF_Q signal representing the imaginary part of the complex IF signal. The holding unit (127) holds the absolute value of amplitude of the IF_Q signal when the first zero-cross detection unit detected the zero-cross point of an IF_I signal, and the absolute value of amplitude of the IF_I signal when the second zero-cross detection unit detected the zero-cross point of the IF_Q signal.

Description

  The present invention relates to an amplitude modulation (AM) signal detection circuit and a detection method.

  In recent years, in AM (Amplitude Modulation) / FM (Frequency Modulation) tuner systems, so-called silicon tuners in which components such as a coil and a diode are mounted on a semiconductor chip are becoming common, and the price is being reduced. In order to meet the demand for further price reduction, it is desired to reduce the cost by narrowing down to the minimum necessary functions and reducing the circuit scale and the calculation amount.

  In a silicon tuner in which an RF (Radio Frequency) circuit is mounted by a CMOS process or the like, a complex signal that is decomposed into complex numbers is used as an IF (Intermediate Frequency) signal. As the intermediate frequency, a frequency called ZeroIF or LowIF that uses a lower frequency than the conventional IF signal is used. In ZeroIF, the IF signal to be converted is an IF signal when the frequency (for example, 455 kHz) of the IF signal generally known in the superheterodyne method is 0 Hz. In Low IF, the IF signal is an IF signal having a frequency lower than the frequency of the IF signal generally known in the superheterodyne system. In both cases of ZeroIF and LowIF, the complex signal is a signal expressed as a real part of a complex number (hereinafter referred to as an I signal) and a signal expressed as an imaginary part of a complex number (hereinafter referred to as a Q signal). There is a 90 degree phase difference between them. In general, in AM demodulation (detection) processing, an AM detection signal is obtained by obtaining the magnitude of a vector represented by polar coordinates of an I signal and a Q signal.

  Japanese Patent Application Laid-Open No. 09-284054 discloses a digital AM demodulator having an improved PSN (Phase Shift Networks) absolute value detection method. Even if the absolute value added signal does not satisfy the sampling condition, a high-quality demodulated signal can be obtained with a small distortion. In the envelope detection method, the circuit scale on mounting increases due to the square root processing required for demodulation. This technique is a method for obtaining a demodulated signal without using the square root processing.

  FIG. 1 is a block diagram showing a configuration of a radio receiver according to the demodulation method. The radio receiver includes an AD converter 902, a phase shift circuit 903, phase shift absolute value signal generation units 920-1 to 920-n, an adder circuit 904, a multiplier circuit 905, a high-pass filter 906, a D / D A converter 907 is provided. Each of the phase shift absolute value signal generation units 920-1 to 920-n includes multiplication circuits 912 and 913, an addition circuit 914, and an absolute value conversion circuit 915. Further, phase coefficient generators 910 and 911 for supplying coefficients to the multiplier circuits 912 and 913 and a correction coefficient generator 916 for supplying coefficients to the multiplier circuit 905 are provided. The phase shift circuit 903, the multiplication circuits 912 and 913, and the addition circuit 914 form a PSN matrix 909. The input signal in is converted into a digital signal by the AD converter 902 and supplied to the phase shift circuit 903. The phase shift circuit 903 separates the IF signal into a complex I signal and a Q signal. The multiplying circuits 912 and 913 independently multiply each system of the I signal and the Q signal in order to give a desired phase difference between the I signal and the Q signal. The adder circuit 914 adds both multiplication results. The absolute value conversion circuit 915 obtains an absolute value from the addition result. The adder circuit 904 adds the absolute value conversion results of the respective systems. The multiplication circuit 905 corrects the addition result. The high pass filter 906 removes a DC component from the corrected signal. The D / A converter 907 converts the AM detection signal obtained by removing the DC component into an analog signal out.

  As described above, while the square root processing is unnecessary, the n sets of phase-shift absolute value signal generation units 920 include multiplication circuits 912 and 913, an addition circuit 914, and an absolute value conversion circuit 915, respectively. That is, a multiplication circuit that performs independent multiplication for each of the I and Q systems, an addition circuit that adds each multiplication result, and an absolute value conversion circuit that obtains an absolute value are set as a set of elements, and AM detection is performed by the n elements. Get a signal. When n is 2, four multiplication circuits, two addition circuits, two absolute value conversion circuits, and one correction multiplication circuit are required. Further, the accuracy of the detection signal obtained by the conventional technique has a trade-off relationship with n (the number of phase shift absolute value signal generation units 920), that is, the circuit scale. Therefore, in order to increase the accuracy of the detection signal, a circuit scale that is equal to or larger than the implementation by the envelope detection method is required, and the circuit scale cannot be reduced.

  Japanese Patent Laid-Open No. 2010-178220 discloses a tuning circuit that converts a radio wave received by an antenna into an intermediate frequency and outputs it, and a demodulator that demodulates the intermediate frequency signal from the tuning circuit and outputs a demodulated signal A radio receiver comprising a circuit is disclosed. This radio receiver has a PLL circuit that generates an in-phase component signal and a quadrature component signal from an intermediate frequency in a demodulation circuit. The PLL circuit is provided with a frequency counter capable of detecting a frequency shift from the reference intermediate frequency of the intermediate frequency during interference by the jamming station. A signal indicating the frequency shift detected by the frequency counter is input to an oscillator provided in the PLL circuit. The oscillation frequency of the oscillator is corrected based on a signal indicating a frequency shift. This technology extracts interference and non-interference component signals when receiving radio waves in the adjacent station interference state, and prevents or avoids interference by adjacent stations to prevent deterioration of the sound quality of the demodulated signal. is there.

Japanese Patent Laid-Open No. 09-284054 JP 2010-178220 A

  The present invention provides an AM detection circuit and an AM detection method that perform demodulation by reducing the amount of processing without impairing the accuracy of the detection signal.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the “DETAILED DESCRIPTION”. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In an aspect of the present invention, the AM detection circuit (120) includes a first zero cross detection unit (122), a second zero cross detection unit (123), and a holding unit (127). A low IF complex IF signal is generated based on the amplitude-modulated (AM) received signal. The first zero cross detector (122) detects a zero cross point of the IF_I signal indicating the real part of the complex IF signal. The second zero cross detector (123) detects a zero cross point of the IF_Q signal indicating the imaginary part of the complex IF signal. The holding unit (127) includes an absolute value of the amplitude of the IF_Q signal when the first zero cross detection unit detects the zero cross point of the IF_I signal, and an IF_I signal when the second zero cross detection unit detects the zero cross point of the IF_Q signal. Holds the absolute value of the amplitude. In this way, by obtaining an AM detection signal equivalent to multiplication, addition, and square root calculation, it is possible to reduce the number of arithmetic circuits or processes without impairing the accuracy of the detection signal.

  In another aspect of the present invention, an AM detection method receives an amplitude-modulated (AM) received signal to generate a Low IF complex intermediate frequency signal, and IF_I indicating a real part of the complex intermediate frequency signal. Detecting a zero cross point in the signal and the IF_Q signal indicating the imaginary part, holding an absolute value of the amplitude of the IF_Q signal when the zero cross point is detected in the IF_I signal, and detecting a zero cross point in the IF_Q signal Holding the absolute value of the amplitude of the IF_I signal.

  ADVANTAGE OF THE INVENTION According to this invention, the AM detection circuit and AM detection method which reduce and demodulate a processing amount, without impairing the precision of a detection signal can be provided.

FIG. 1 is a diagram showing the configuration of a digital AM demodulator disclosed in Japanese Patent Laid-Open No. 09-284054. FIG. 2 is a block diagram showing the configuration of the AM signal receiver according to the embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of the detection circuit according to the embodiment of the present invention. FIG. 4 is a diagram illustrating a waveform of a complex IF signal when there is no AM modulation. FIG. 5 is a polar coordinate display of the complex IF signal without AM modulation. FIG. 6 is a diagram illustrating a waveform of a complex IF signal in the case of AM modulation. FIG. 7 is a diagram in which the complex IF signal with AM modulation is displayed in polar coordinates. FIG. 8 is a timing chart showing the operation of the detection circuit according to the embodiment of the present invention. FIG. 9 is a state transition diagram of AM detection processing according to the embodiment of the invention.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a block diagram showing a configuration of the LowIF AM signal receiver 100 according to the embodiment of the present invention. The AM signal receiver 100 includes a high frequency amplifier 102, a frequency conversion unit 110, a detection circuit 120, and a low frequency amplifier 130. The high frequency amplifier 102 is a low noise amplifier, and selects and amplifies an input signal. The frequency converter 110 includes a local oscillator 112 and mixers 114 and 116, and is a circuit that converts the received signal amplified by the high-frequency amplifier 102 into a constant low frequency. This low frequency is called the intermediate frequency. The low frequency amplifier 130 amplifies the detected signal so that a speaker or the like can be driven.

  As shown in FIG. 3, the detection circuit 120 includes a zero cross detection (I) unit 122, a zero cross detection (Q) unit 123, a selection signal generation unit 124, a selection unit (MUX) 125, and an absolute value conversion unit. (ABS) 126, holding unit (HOLD) 127, logical sum unit 128, and high-pass filter (HPF) 129. The zero cross detection (I) unit 122 detects a zero point passing point (zero cross) of the signal IF_I and generates a signal ZX_I indicating the detection timing. The zero cross detection (Q) unit 123 detects a zero point passing point of the signal IF_Q and generates a signal ZX_Q indicating the detection timing. The selection signal generation unit 124 generates a selection signal SEL that indicates selection logic used in the selection unit 125. The selection unit 125 selects and outputs a signal propagated to the subsequent stage from the signal IF_I and the signal IF_Q. The absolute value converter 126 performs absolute value conversion on the input signal IFM to generate an absolute value IF signal IFA. The holding unit 127 holds the value of the absolute value IF signal IFA output from the absolute value conversion unit 126. The logical sum unit 128 generates a holding timing signal EN used by the holding unit 127. The high pass filter 9 removes a DC (direct current) component of the input signal and outputs an AM detection signal DTC.

  The zero cross detection (I) unit 122 receives the signal IF_I and outputs the detection signal ZX_I to the selection signal generation unit 124 and the logical sum unit 128. The zero cross detection (Q) unit 123 receives the signal IF_Q, and outputs a detection signal ZX_Q to the selection signal generation unit 124 and the logical sum unit 128. The selection signal generation unit 124 receives the signal ZX_I from the zero cross detection (I) unit 122 and the signal ZX_Q from the zero cross detection (Q) unit 123, and outputs the selection signal SEL to the selection unit 125. The selection unit 125 receives the signal IF_I, the signal IF_Q, and the selection signal SEL, and outputs a signal IFM to the absolute value conversion unit 126. The absolute value conversion unit 126 receives the signal IFM from the selection unit 125 and outputs the signal IFA after the absolute value conversion to the holding unit 127. The logical sum unit 128 receives the signal ZX_I from the zero cross detection (I) unit 122 and the signal ZX_Q from the zero cross detection (Q) unit 123, and outputs a holding timing signal EN indicating the timing of holding the value to the holding unit 127. The holding unit 127 receives the signal IFA from the absolute value conversion unit 126 and the holding timing signal EN from the logical sum unit 128, and outputs a signal VCT to the high pass filter 129. The high-pass filter (HPF) 129 receives the holding signal VCT from the holding unit 127, removes a DC (direct current) component of the holding signal, and outputs an AM detection signal DTC.

  4 and 5 are diagrams illustrating waveforms of complex IF signals (signal IF_I and signal IF_Q) in the case of no AM modulation (modulation degree 0%).

  In FIG. 4, the complex IF signals shown as signal IF_I and signal IF_Q are plotted with the amplitude on the vertical axis and the time on the horizontal axis. The signal IF_I and the signal IF_Q are signals having the same frequency and have a phase difference of 90 degrees therebetween.

  In FIG. 5, the same signals as in FIG. 4 are plotted in polar coordinates. In FIG. 5, the horizontal axis represents the amplitude of the signal IF_I, and the vertical axis represents the amplitude of the signal IF_Q.

  The state at time A1 shown in FIG. 4 is shown at position A2 in the polar coordinates of FIG. Similarly, the states at times B1, C1, and D1 shown in FIG. 4 are shown at positions B2, C2, and D2 in FIG. 5 polar coordinates. One period of the IF signal corresponds to one rotation in polar coordinates.

  Further, since the signal IF_I and the signal IF_Q are signals having the same frequency and always have a phase difference of 90 degrees, the position on the polar coordinate is shown to move at a constant angular velocity in FIG. That is, the transition time from the polar coordinate position A2 to the polar coordinate position B2, from the polar coordinate position B2 to the polar coordinate position C2, from the polar coordinate position C2 to the polar coordinate position D2, and from the polar coordinate position D2 to the polar coordinate position A2 is always constant.

  Next, FIG. 6 and FIG. 7 are diagrams showing waveforms of complex IF signals (signal IF_I, signal IF_Q) in the case of AM modulation (modulation degree> 0%) according to the present invention.

  In FIG. 6, the complex IF signals indicated as the signal IF_I and the signal IF_Q are plotted with the amplitude on the vertical axis and the time on the horizontal axis. As with the signal shown in FIG. 4, the signal IF_I and the signal IF_Q are signals having the same frequency and have a phase difference of 90 degrees therebetween.

  In FIG. 7, the same signals as in FIG. 6 are plotted in polar coordinates. In FIG. 7, the horizontal axis represents the amplitude of the signal IF_I, and the vertical axis represents the amplitude of the signal IF_Q. The waveforms shown by dotted lines in FIGS. 6 and 7 are complex IF signals without AM modulation (modulation degree 0%) (see FIGS. 4 and 5) and with AM modulation (modulation degree> 0%). The IF signal is indicated by a solid line.

  As shown in FIG. 6, the AM-modulated signal has a constant frequency, and a change due to the modulation appears only in the amplitude direction. Therefore, as shown in FIG. 7, the transition of the position of the polar coordinates indicated by the signal IF_I and the signal IF_Q becomes a constant angular velocity. In FIG. 7, the AM detection signal corresponds to the vector size V.

  FIG. 8 is a timing chart showing the operation of the detection circuit 120 according to the present embodiment. The signal IF_I and the signal IF_Q shown here are the same as the complex IF signal with AM modulation described with reference to FIGS.

  The timing A shown in FIG. 8 corresponds to the time A1 shown in FIG. 6 and the polar coordinate position A2 shown in FIG. The signal IF_I passes through the 0 point (FIG. 8A), and the zero cross detection unit 122 sets the zero cross detection signal ZX_I to High for one clock (FIG. 8C). At this time, the selection signal SEL is at the low level (FIG. 8 (e)), the selection unit 125 outputs the signal IFM indicating the level of the signal IF_Q to the absolute value conversion unit 126, and the absolute value conversion unit 126 outputs the absolute value thereof. The converted signal IFA is output to the holding unit 127. The holding unit 127 holds the amplitude value after the absolute value conversion in response to the holding timing signal EN (FIG. 8 (f)) (FIG. 8 (g)). The value held is the absolute value of the amplitude of the signal IF_Q (FIG. 8B) and is equal to the magnitude of the vector on the polar coordinates. From the signal VCT output from the holding unit 127, the DC component is removed by the high-pass filter 129, and the AM modulation component is extracted (FIG. 8 (h)). After the holding unit 127 holds the amplitude value, the selection signal generation unit 124 switches the selection signal SEL to the high level so as to select the signal IF_I (FIG. 8 (e)).

  Timing B shown in FIG. 8 corresponds to time B1 shown in FIG. 6 and polar coordinate position B2 shown in FIG. The signal IF_Q passes through the 0 point (FIG. 8B), and the zero cross detection unit 123 sets the zero cross detection signal ZX_Q to High for one clock (FIG. 8D). At this time, the selection signal SEL is at a high level (FIG. 8 (e)), the selection unit 125 outputs a signal IFM indicating the level of the signal IF_I to the absolute value conversion unit 126, and the absolute value conversion unit 126 has its absolute value. The converted signal IFA is output to the holding unit 127. The holding unit 127 holds the amplitude values (VECT (a), VECT (b)...) After the absolute value conversion in response to the holding timing signal EN (FIG. 8 (f)) (FIG. 8 (g)). . The value held is the absolute value of the amplitude of the signal IF_I (FIG. 8A) and is equal to the magnitude of the vector on the polar coordinates. From the signal VCT output from the holding unit 127, the DC component is removed by the high-pass filter 129, and the AM modulation component is extracted (FIG. 8 (h)). After the holding unit 127 holds the amplitude value, the selection signal generation unit 124 switches the selection signal SEL to the low level so as to select the signal IF_Q (FIG. 8E). Similarly, at timing C and timing D, the holding unit 127 holds the vector magnitude at each timing, and a signal DTC indicating an AM modulation component is output from the high-pass filter 129 (FIG. 8 (h)).

  Thereafter, the operations at timings A to D are repeated. Since the signals IF_I and I_F_Q are signals having a constant frequency, zero cross points appear at regular intervals, and the magnitudes of vectors indicated by the signals IF_I and IF_Q can be obtained accurately and continuously at a constant sampling time. It is done. The high-pass filter 129 removes a DC component from the obtained signal VCT indicating the magnitude of the vector and outputs an AM detection signal DTC.

  FIG. 9 is a state transition diagram of the AM detection processing of the present invention.

(A) When the AM detection process detects a zero cross point in the signal IF_I, the AM detection process transits from the event waiting state S1 to the IF_Q signal holding state S2 (T1).
(B) In the IF_Q signal holding state S2, the AM detection process holds the absolute value of the signal IF_Q in the variable AMDET. Thereafter, the state transitions to the event waiting state S1 (T2).
(C) When the AM detection process detects a zero cross point in the signal IF_Q, the AM detection process transitions from the event waiting state S1 to the IF_I signal holding state S3 (T3).
(D) In the IF_I signal holding state S3, the AM detection process holds the absolute value of the signal IF_I in the variable AMDET. After that, the state transits to the event waiting state S1 (T4).
(E) Except for the IF_Q signal holding state S2 and the IF_I signal holding state S1, the state is an event waiting state S1, and waits for an IF_I zero-cross detection or IF_Q zero-cross detection event (T4).

  FIGS. 6 and 7 are diagrams showing the complex IF signal operation in the case of AM modulation according to the present invention, and the mechanism will be described with reference to FIGS.

In FIG. 7, the magnitude of the vector obtained at each of the polar coordinate position A2, the polar coordinate position B2, the polar coordinate position C2, and the polar coordinate position D2 is obtained by Expression (1) and is equal to the vector magnitude.
(Vector size) = √ (I ² × Q ² ) (1)

For example, since the polar coordinate position A2 in FIG. 7 is the zero cross position of the IF_I signal, that is, I = 0, the magnitude of the vector is expressed by Expression (2).
√ (0 ² + Q ² ) = √Q ² = Q (2)

  As described above, according to the AM detector of the present invention, the zero-cross detection circuits 122 and 123, the selection signal generation circuit 124, the selection circuit 125, the absolute value conversion unit 126, and the holding unit of each system of the complex IF signal I and Q signals. By including 127 and the logical sum unit 128, it is possible to obtain an AM detection signal with the same accuracy as the square root processing. That is, complicated arithmetic processing such as multiplication and addition or time-consuming arithmetic processing is unnecessary, and the circuit can be simplified. The IF signal is preferably a quantized digital signal. The AD converter may be provided either before or after the frequency conversion unit 110. When an AD converter is provided in the previous stage of the frequency conversion unit 110, the frequency conversion unit 110 also performs digital signal processing.

In the present invention, since the LowIF frequency is low, the time resolution is studied. The upper limit of the frequency band to be extracted as AM detection is the unit of 10 kHz (9 kHz in the case of North America in Japan and Europe) of the interval between broadcast stations. On the other hand, an intermediate frequency generally used as LowIF is about several tens kHz to several hundreds kHz. In the configuration according to the present invention, since the zero cross point appears every 90 degrees phase of the IF signal, the number of samples obtained from the IF signal is four times the IF signal frequency. For example, even when the intermediate frequency f _IF = 10 kHz, the sampling frequency is 40 kHz, so that a sufficient number of samples can be obtained for AM detection processing. Therefore, the time resolution is sufficient even at a low frequency LowIF.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 100 AM signal receiver 102 High frequency amplifier 110 Frequency conversion part 112 Local oscillator 114, 116 Mixer 120 Detection circuit 122, 123 Zero cross detection part 124 Selection signal generation part 125 Selection part (MUX)
126 Absolute value converter (ABS)
127 Holding part (HOLD)
128 OR part 129 High pass filter (HPF)
130 Low frequency amplifier 902 AD converter 903 Phase shift circuit 904 Addition circuit 905 Multiplication circuit 906 High pass filter 907 D / A converter 909 PSN matrix 910, 911 Phase coefficient generator 912, 913 Multiplication circuit 914 Addition circuit 915 Absolute value conversion circuit 916 Correction coefficient generators 920-1 to 920-n Phase-shift absolute value signal generator

Claims (7)

A first zero cross detection unit that detects a zero cross point of an IF_I signal indicating a real part of a complex IF signal of a Low IF method generated based on an amplitude-modulated (AM) received signal;
A second zero cross detection unit for detecting a zero cross point of the IF_Q signal indicating an imaginary part of the complex IF signal;
The absolute value of the amplitude of the IF_Q signal when the first zero cross detection unit detects the zero cross point of the IF_I signal, and the IF_I signal when the second zero cross detection unit detects the zero cross point of the IF_Q signal. An AM detection circuit comprising: a holding unit that holds the absolute value of the amplitude. The holding unit outputs an absolute value of an amplitude of a signal held in synchronization with a timing of detecting a zero cross point of the IF_Q signal and a zero cross point of the IF_I signal;
An AM detection circuit further comprising a high-pass filter for removing a DC component of a signal output from the holding unit. A selection unit that inputs the IF_I signal and the IF_Q signal, and switches and outputs one of the signals in response to detection of the zero-cross point;
An absolute value conversion unit that calculates an absolute value of a signal output from the selection unit, and
The selection unit switches to output the IF_I signal when the zero cross point of the IF_I signal is detected, and switches to output the IF_Q signal when the zero cross point of the IF_Q signal is detected. AM detection circuit. The IF_I signal and the IF_Q signal are digital signals,
4. The detection of a zero cross point of the IF_I signal and the IF_Q signal and the calculation and holding of absolute values of the amplitudes of the IF_I signal and the IF_Q signal are digital signal processing. 5. AM detection circuit. An AM signal receiver comprising the AM detection circuit according to claim 1. Receiving an amplitude-modulated (AM) received signal to generate a Low IF complex intermediate frequency signal;
Detecting a zero cross point in an IF_I signal indicating a real part of the complex intermediate frequency signal and an IF_Q signal indicating an imaginary part;
Holding an absolute value of the amplitude of the IF_Q signal when a zero cross point is detected in the IF_I signal;
Holding an absolute value of the amplitude of the IF_I signal when a zero cross point is detected in the IF_Q signal;
An AM detection method comprising: Outputting absolute values of amplitudes of the held IF_I signal and IF_Q signal in synchronization with a timing at which a zero cross point is detected in the IF_I signal and the IF_Q signal;
The AM detection method according to claim 6, further comprising: removing and outputting a DC component of the signal output in synchronization.

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