JP2013041366A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of promptly restoring a processing unit from an idle state.SOLUTION: A data processor including plural processing units restores a processing unit put into an idle state by execution of a specific command, using an interrupt, restoration processing for responding to rewrite of a control bit rewritable by the processing units to a predetermined value, and restoration processing for responding to task scheduling of the processing unit in the idle state. Therefore, another processing unit can perform rewrite of the control bit or task scheduling, except when restoration from the idle state needs required processing by interrupt processing. When rewrite of the control bit or task scheduling can be performed, interrupt processing accompanying null processing is not required.

Description

  The present invention relates to low power consumption control of a data processing apparatus having a plurality of processing units, and relates to a technique that is effective when applied to, for example, a microcomputer that performs data processing by object type multiprocessing (SMP).

  Some microcomputers have a low power consumption mode such as a sleep mode. For example, when the central processing unit (CPU) executes a sleep command, the CPU shifts to a sleep state in which the supply of the synchronous clock signal to the CPU is stopped and the execution of a new command is paused. Patent Documents 1 and 2 describe such a low power consumption mode, and an interrupt to the CPU is used to return from the low power consumption mode to a state where a new instruction can be executed. For example, when there is an interrupt request from the outside, when the interrupt controller gives an interrupt signal to the CPU, the clock control circuit restarts the supply of the synchronous clock to the CPU, thereby enabling the CPU to process the interrupt request.

Japanese Patent Application No. 4-87043 JP 2002-163032 A

  The present inventor has studied a low power consumption mode in multiprocessing in which processing is distributed to a plurality of processing units. A processing unit is a circuit module that includes at least a central processing unit (CPU) that executes instructions.

  In order to return the processing unit from the hibernation state to the operable state, some return processing is required. In the case of a microcomputer having only one processing unit (hereinafter also referred to as a single-core microcomputer), the system cannot be operated if the processing unit is paused. Therefore, the processing unit is paused by using an external interrupt or system reset. Must be restored from.

  On the other hand, in the case of a microcomputer having a plurality of processing units (hereinafter also simply referred to as a multi-core microcomputer), the operation as a multi-core system can be continued as long as all the processing units are not in a dormant state. It is also possible to restore by an interrupt request from another processing unit in operation. For example, some processing units are temporarily suspended for the purpose of power saving, and when the processing load increases, such as when the number of executable tasks exceeds a certain number, the suspended processing units are restored. In a multi-core microcomputer in which some processing units are suspended while such a system operation is maintained, high-speed processing is required for halting the processing units and returning from the suspension. In particular, in the case where only a return by an external interrupt or a reset can be used as a recovery method, similarly to a single core microcomputer, a high-speed recovery operation cannot be realized. In the return operation by interrupt, the processing unit performs interrupt processing in response to the interrupt signal, and even if it is only necessary to restart the supply of the synchronous clock signal to the processing unit, the empty processing interrupt processing is executed. In other words, time is spent on processing that is substantially meaningless, and it takes time to recover. Patent Documents 1 and 2 do not focus on the circumstances of return from sleep in such a multi-core microcomputer.

  An object of the present invention is to provide a data processing apparatus capable of returning a processing unit from a hibernation state at high speed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, in a data processing apparatus having a plurality of processing units, in addition to using an interrupt to return a suspended processing unit to an operable state by executing a specific instruction, a control bit that can be rewritten by the processing unit A return process in response to rewriting to a predetermined value is used, and a return process in response to a memory access to a predetermined address for task scheduling for a processing unit in a dormant state is used.

  As a result, except for the case where required processing is required by interruption processing to return from the hibernation state, rewriting of control bits by another processing unit or memory access for task scheduling may be performed. If memory access is performed for rewriting control bits or task scheduling, it is not necessary to perform interrupt processing with empty processing.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the processing unit can be returned from the hibernation state at high speed.

FIG. 1 is a block diagram illustrating a multi-core microcomputer according to the first embodiment of the invention. FIG. 2 is a format diagram illustrating a register format of one control register area in the control register. FIG. 3 is an explanatory diagram illustrating a transition control mode between the active state and the hibernate state in the multi-core microcomputer of FIG. FIG. 4 is an explanatory diagram illustrating the relationship between task variables and task control fields for managing task processing. FIG. 5 is a flowchart showing an example of task scheduling and task dispatch processing. FIG. 6 is a flowchart exemplifying an outline of a dispatcher process for distributing and managing a process flow by a task under the management of the OS. FIG. 7 is a flowchart showing an example of the power saving process. FIG. 8 is a flowchart illustrating an operation of canceling the hibernation state of the processing unit through an interrupt. FIG. 9 is a flowchart exemplifying an operation for canceling the sleep state of the processing unit by operating the wakeup bit WUPx. FIG. 10 is a block diagram illustrating a multi-core microcomputer according to the second embodiment of the invention. FIG. 11 is an explanatory diagram illustrating a transition control mode between the active state and the hibernation state in the multi-core microcomputer of FIG. FIG. 12 is a flowchart illustrating an example of an operation for canceling the sleep state of the processing unit by a write operation on a predetermined schedule task variable. FIG. 13 is an explanatory diagram illustrating a usage form of a multi-core microcomputer provided with four processing units. FIG. 14 is an explanatory diagram illustrating a state in which the load is reduced in the system of FIG.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Release instruction execution in response to control bit rewriting>
A data processing apparatus (1) according to a representative embodiment of the present invention responds to execution of a plurality of processing units (11, 12) for executing instructions and specific instructions (sleep instructions) by the processing units. Then, control for halting execution of a new instruction by the processing unit is performed, and a control bit (WPUx) provided corresponding to the processing unit is rewritten to a predetermined value or an interrupt is generated for the processing unit (INT1, INTn). And a control circuit (22) for performing control to cancel the instruction execution suspension in response to (). A control register (30) rewritable by the processing unit has the control bit.

  As a result, the control bit may be rewritten by another processing unit, except for the case where required processing by interrupt processing is required to return from the sleep state. If the control bit is rewritten, it is not necessary to perform an interrupt process involving an empty process. Therefore, the processing unit can be returned from the hibernation state at high speed. Furthermore, it becomes possible to use the pause of the processing unit simply and frequently, and it becomes easy to increase the contribution to power saving.

[2] <Stop of new instruction execution in response to execution of sleep instruction>
In the data processing device according to item 1, the control for stopping the instruction execution is control for stopping the supply of the synchronous clock signals (CLK1, CLKn) to the central processing unit included in the processing unit. The control for canceling the execution suspension of the instruction is control for restarting the supply of the synchronous clock signal to the central processing unit.

  As a result, the stop and restart of instruction execution are controlled by supplying and stopping the synchronous clock signal, so that the internal state of the processing unit can be maintained and the control of pause and restart can be easily realized.

[3] <Light sleep mode>
In the data processing device according to item 2, the control to pause the instruction execution is to supply a synchronous clock signal to the internal memory of the corresponding processing unit when the mode bit (LTSLPx) held by the control register is the first value. In this control, the supply of the synchronous clock signal to the central processing unit is stopped while maintaining, and the supply of the synchronous clock signal to the central processing unit and the internal memory is stopped when the mode bit is a second value. The control for canceling the suspension of execution of the instruction restarts the supply of the synchronous clock signal to the corresponding central processing unit in response to the rewriting of the control bit to the predetermined value when the mode bit is the first value, When the mode bit is a second value, the control bit is resumed in response to the rewriting of the control bit to a predetermined value to resume the supply of the synchronous clock signal to the corresponding central processing unit and the internal memory.

  According to this, it is possible to select the power saving level of the processing unit in the hibernation state and the length of time required until the processing unit is completely restored according to the state of the mode bit.

[4] <Task dispatch processing>
In the data processing device according to any one of Items 1 to 3, the processing unit determines whether or not scheduling of a task to be processed is performed, and when it is scheduled, transitions to execution of the task, When it is not scheduled, a process (S2) for executing the specific instruction is performed.

  According to this, when there is no task to be executed, the processing unit is always in a dormant state, and power saving can be promoted.

[5] <Task activation process>
In the data processing device according to item 4, the processing unit performs a task scheduling for another processing unit in which instruction execution is suspended, and then rewrites a control bit of the control register to a predetermined value (first task activation process) S43) is performed.

  According to this, when returning from the hibernation state by rewriting the control bit, it is possible to guarantee a state in which there is always a task to be returned and executed, and it is possible to prevent the occurrence of a situation where the processing unit is returned to waste. can do.

[6] <Release instruction execution suspension by interrupt and task activation>
The data processing apparatus according to item 4 includes an interrupt controller (21) that outputs an interrupt signal to the processing unit in response to an interrupt request. The processing unit performs a second task activation process for outputting an interrupt request for the other processing unit to the interrupt controller after scheduling a task for the other processing unit in which instruction execution is suspended. The interrupt controller outputs an interrupt signal to another processing unit in response to the interrupt request by the second task activation process (S41).

  According to this, when returning from the hibernation state by an interrupt, it is possible to guarantee a state in which there is always a task to be returned and executed, and it is possible to prevent the occurrence of a situation where the processing unit returns to waste. it can.

[7] <Release instruction execution in response to task scheduling>
A data processing apparatus (1A) according to another embodiment of the present invention includes a plurality of processing units (11, 12) that execute instructions and control data for scheduling tasks processed by the processing units. In response to execution of a specific instruction (extended sleep instruction) by the memory (2) to be stored and execution of the processing unit, a task to be processed by the processing unit is performed while performing control to pause execution of a new instruction by the processing unit And a control circuit (22A) for controlling to cancel the execution suspension of the instruction in response to the task control data of the memory being stored at a predetermined address of the memory or an interrupt to the processing unit is issued .

  Thus, task scheduling by another processing unit may be performed except for the case where required processing by interrupt processing is required to return from the sleep state. If the memory storing operation of control data for task scheduling is performed, it is not necessary to perform an interrupt process accompanied by an empty process. Therefore, the processing unit can be returned from the hibernation state at high speed. Furthermore, it becomes possible to use the pause of the processing unit simply and frequently, and it becomes easy to increase the contribution to power saving.

[8] <Specific instruction specifies a predetermined address>
In the data processing device according to item 7, the specific instruction specifies the predetermined address.

  According to this, a predetermined address which is one of the conditions for canceling the hibernation state can also be specified by the specific instruction, and the return from the hibernation state set by the specific instruction execution can also be specified by the instruction description. It becomes possible to respond flexibly.

[9] <Stop of new instruction execution in response to execution of extended sleep instruction>
In the data processing device according to item 7, the control for stopping the instruction execution is control for stopping the supply of the synchronous clock signals (CLK1, CLKn) to the central processing unit included in the processing unit. The control for canceling the execution suspension of the instruction is control for restarting the supply of the synchronous clock signal to the central processing unit.

  As a result, the stop and restart of instruction execution are controlled by supplying and stopping the synchronous clock signal, so that the internal state of the processing unit can be maintained and the control of pause and restart can be easily realized.

[10] <Light sleep mode>
In the data processing device according to item 9, the control for halting the execution of the instruction is performed when the mode bit (LTSLPx) held in the control register (30A) is a first value when the synchronous clock signal to the internal memory of the corresponding processing unit is set. The control is to stop the supply of the synchronous clock signal to the central processing unit while maintaining the supply, and to stop the supply of the synchronous clock signal to the central processing unit and the internal memory when the mode bit is a second value. . When the mode bit is a first value, the control for releasing the execution suspension of the instruction restarts the supply of the synchronous clock signal to the corresponding central processing unit in response to the storage of the task control data, and the mode bit Is a control for resuming the supply of the synchronous clock signal to the corresponding central processing unit and the internal memory in response to the storage of the task control data when is a second value.

  According to this, depending on the state of the mode bit, the power saving of the processing unit in the hibernation state and the length of time required until the processing unit is completely restored can be selected.

[11] <Task dispatch processing>
In the data processing device according to any one of Items 7 to 10, the processing unit determines whether or not scheduling of a task to be processed by itself is performed, and when it is scheduled, transitions to execution of the task, When it is not scheduled, a process (S2) for executing the specific instruction is performed.

  According to this, when there is no task to be executed, the processing unit is always in a dormant state, and power saving can be promoted.

[12] <Task activation process>
In the data processing device according to item 11, the processing unit performs a task scheduling for another processing unit in which instruction execution is suspended, and then writes the task control data in the memory. First task activation processing (S46) I do.

  According to this, when returning from the hibernation state by rewriting the control bit, it is possible to guarantee a state in which there is always a task to be returned and executed, and it is possible to prevent the occurrence of a situation where the processing unit is returned to waste. can do.

[13] <Release instruction execution suspension by interrupt and task activation>
The data processing device according to item 11 further includes an interrupt controller (21A) that outputs an interrupt signal to the processing unit in response to an interrupt request. The processing unit performs a second task activation process for outputting an interrupt request for the other processing unit to the interrupt controller after scheduling a task for the other processing unit in which instruction execution is suspended. The interrupt controller outputs an interrupt signal to another processing unit in response to an interrupt request by the second task activation process.

  According to this, when returning from the hibernation state by an interrupt, it is possible to guarantee a state in which there is always a task to be returned and executed, and it is possible to prevent the occurrence of a situation where the processing unit returns to waste. it can.

[14] <Release instruction execution in response to control bit rewriting>
A data processing device (1) according to yet another embodiment of the present invention comprises a plurality of processing units (11, 12) for executing instructions and a clock control circuit (22) for supplying a synchronous clock signal to the processing units. And a control register (30) rewritable by the processing unit. The clock control circuit stops supplying a synchronous clock signal to the processing unit in response to execution of a specific instruction by the processing unit, and stops writing a predetermined value or supplying a synchronous clock signal to the control register. The supply stop of the synchronous clock signal is released in response to the occurrence of an interrupt to the processing unit.

  As a result, the control bit may be rewritten by another processing unit, except for the case where a required process by an interrupt process is required to return from the sleep state. If the control bit is rewritten, it is not necessary to perform an interrupt process involving an empty process. Therefore, the processing unit can be returned from the hibernation state at high speed. Furthermore, it becomes possible to use the pause of the processing unit simply and frequently, and it becomes easy to increase the contribution to power saving.

[15] <Release instruction execution in response to task scheduling>
A data processing apparatus (1A) according to still another embodiment of the present invention includes a plurality of processing units (11, 12) for executing instructions and control data for scheduling tasks processed by the processing units. And a clock control circuit (22A) for supplying a synchronous clock signal to the processing unit. The instruction set of the processing unit includes a low power consumption control instruction (extended sleep instruction). The low power consumption control instruction stops the supply of a synchronous clock signal to the processing unit that executed the instruction, and another processing unit schedules the new task to be processed by the processing unit in the memory, or the processing This is an instruction for causing the clock control circuit to release the supply stop of the synchronous clock signal after waiting for an interrupt to be issued to the unit.

  Thus, task scheduling by another processing unit may be performed except for the case where required processing by interrupt processing is required to return from the sleep state. If the memory storing operation of control data for task scheduling is performed, it is not necessary to perform an interrupt process accompanied by an empty process. Therefore, the processing unit can be returned from the hibernation state at high speed. Furthermore, it becomes possible to use the pause of the processing unit simply and frequently, and it becomes easy to increase the contribution to power saving.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 illustrates a multi-core microcomputer according to the first embodiment of the present invention. The multi-core microcomputer 1 shown in FIG. 1 is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique.

  The multi-core microcomputer (MCU) 1 includes a plurality of processing units (PRCS (# 1), PRCS (#n)) 11 and 12 connected to an internal bus 13. Each of the processing units 11 and 12 has at least a CPU for executing instructions, and further includes a floating point arithmetic unit, a memory management unit, and a cache memory. Although not particularly limited, the plurality of processing units 11 and 12 execute application programs under the management of an OS (operating system) that implements SMP.

  The internal bus 13 is interfaced to the peripheral bus 16 via a bus bridge (BBRDG) 14. An interrupt controller (INTC) 21, a clock control circuit (CPCNT) 22, a bus state controller (LBCNT) 23, an SDRAM controller (SDRAMCNT) 25, an input / output port (IOP) 24, and the like are connected to the peripheral bus 26.

  The interrupt controller 21 performs interrupt priority level and interrupt mask control for interrupt requests given from inside and outside the multi-core microcomputer 1 to control acceptance of interrupt requests. When receiving an interrupt request, the interrupt controller 21 provides an interrupt signal corresponding to the interrupt request to one of the processing units 11 and 12. Interrupt signals INT1 and INTn are assigned to the processing units (PRCS (# 1), PRCS (#n)) 11 and 12, respectively. The processing unit to which the interrupt signal is given, for example, completes the execution of an instruction in the middle of execution, performs necessary processing such as saving, and then branches to a processing routine corresponding to the interrupt factor.

  The clock control circuit 22 generates a synchronous clock signal used inside the multi-core microcomputer 1 based on an oscillator (not shown) or a system clock signal supplied from outside. For example, the processing unit 11 is supplied with a synchronous clock signal CLK1, and the processing unit 12 is supplied with a synchronous clock signal CLKn. The clock control circuit 22 has a control register (STBCR) 30 for low power consumption control, although not particularly limited.

  For example, the ROM 3 and the SRAM 2 are connected to the bus state controller 23 via the external bus 4. The ROM 3 holds programs and parameter data. The SRAM 2 is used as a work area for the processing units 11 and 12. An SDRAM 5 such as DDR3 is connected to the SDRAM controller 25. The SDRAM 5 is used for a large capacity data primary storage area.

  The multi-core microcomputer 1 has a low power consumption mode of the processing unit. For example, when the CPU executes a sleep command, the CPU enters the sleep state in which the supply of the synchronous clock signal to the CPU is stopped and the execution of a new command is paused. This hibernation state is the low power consumption mode. There are three types of methods for canceling the low power consumption mode: reset, interrupt request, or rewriting of the control register 30.

  FIG. 2 illustrates a register format of one control register area in the control register 30.

  The control register 30 has a storage area (control register area) corresponding to each of the processing units 11 and 12. Each control register area has a write sleep bit LTSLPx, a sleep indication bit SLEEPx, a wakeup bit WUPx, and the like, as illustrated in FIG. x is a suffix meaning the corresponding processing unit. For example, x = 1 corresponds to the processing unit (PRCS (# 1)) 11 and x = n corresponds to the processing unit (PRCS (#n)) 12.

  The light sleep bit LTSLPx is a mode bit indicating whether the sleep mode or the light sleep mode is changed when the sleep command is executed, and the value “0” indicates that the corresponding processing unit changes to the sleep mode. 1 ″ indicates that the corresponding processing unit shifts to the light sleep mode. The sleep mode is an operation in which the processing unit is suspended by stopping the supply of the operation clock signal to the entire corresponding processing unit, that is, the CPU, the floating point arithmetic unit, the memory management unit, and the cache memory. Mode. In the light sleep mode, the supply of the operation clock signal to the CPU of the corresponding processing unit is stopped, and the supply of the operation clock signal to the other floating point arithmetic units, the memory management unit, and the cache memory is maintained. This is an operation mode in which the processing unit is suspended. The write sleep bit LTSLPx is a control bit that can be read and written by the processing units 11 and 12 according to a user mode, that is, an application program.

  The sleep display bit SLEEPx indicates whether the corresponding processing unit is set in the sleep mode or the light sleep mode and is in a dormant state, or is released from the dormant state and is in an operable state (active state). A value “0” indicates an active state, and a value “1” indicates a dormant state. In the user mode, only the read operation is arbitrarily enabled for the sleep indication bit SLEEPx. For the write operation, the corresponding bit is set to “1” in response to the execution of the sleep instruction via a predetermined hardware logic, It is cleared to the value “0” in response to the release of the hibernation state.

  The wake-up bit WUPx is a control bit for canceling the corresponding processing unit from the hibernation state and returning it to the active state. The value “1” instructs to return the corresponding processing unit from the hibernation state to the active state. Writing the value “0” is ignored. Although not particularly limited, the wakeup bit WUPx is cleared to the value “0” in conjunction with the corresponding sleep indication bit SLEEPx being set to the value “1” in response to the execution of the sleep command.

  FIG. 3 shows a transition control mode between the active state and the hibernation state in the multi-core microcomputer 1. Here, a case where the processing unit (PRCS (#n)) 12 is put into a dormant state is exemplified. When the processing unit 12 executes the sleep command, the clock control circuit 22 is requested to stop the synchronous clock signal CLKn, whereby the supply of the clock signal CLKn to the processing unit 12 is stopped. The stop range of the synchronous clock signal CLKn in the processing unit 12 is determined by the value of the write sleep bit LTSLPx (x = n).

  In order for the processing unit 12 in the dormant state to resume task processing, an external interrupt request to the processing unit 12 is generated, an internal interrupt request to the processing unit 12 is generated by the processing unit 11 in the active state, or the processing unit 12 causes the processing unit 12 to It waits for the wakeup bit WUPx (x = n) corresponding to to be rewritten to the value “1”. As a result, the clock control circuit 22 resumes the supply of the synchronous clock signal CLKn. When rewriting the wakeup bit WUPx of the processing unit 12 to the value “1”, first, the processing unit 11 schedules a task to be processed by the processing unit 12 in the SRAM 2 when the sleep state is canceled. Similarly, when requesting an interrupt to the processing unit 12 in the dormant state, first, the processing unit 11 schedules a task to be processed by the processing unit 12 in the SRAM 2 when the dormant state is canceled.

  FIG. 4 illustrates the relationship between task variables and task control fields for managing task processing. In the task control field, a task control block TCBLKm used for storing task control data used for processing of each task is assigned to TCFLD. In the figure, task control blocks TCBLK1, TCBLK2, and TCBLK3 are assigned to tasks TSK1, TSK2, and TSK3. There are an execution variable (ctxtsk) representing a task being executed as a task variable and a schedule task variable (schedtsk) representing a scheduled task. In each variable, the head address of the control block TCBLKm of the corresponding task is written. Normally, the values of the execution variable (ctxtsk) and the scheduled task variable (schedtsk) are matched. Task scheduling is performed, for example, by writing the start address of a control block related to a new task in a schedule task variable (schedtsk) corresponding to a required processing unit. The scheduled task variable (schedtsk) is rewritten when, for example, a task having a higher priority than the currently executing task becomes executable. When the OS does not match the execution variable (ctxtsk) and the scheduled task variable (schedtsk), it writes the scheduled task variable (schedtsk) value to the execution variable (ctxtsk) so that it matches. Switch).

  FIG. 5 shows a processing example of task scheduling and task dispatch. When there is no task to be executed, both the execution variable (ctxtsk variable) and the scheduled task variable (schedtsk variable) have the value “0”. The value “0” is similarly obtained when the processing units 11 and 12 are in a rest state. When a task TSKi in a new executable state is generated from this state, the start address of the task control block corresponding to the task TSKi, for example, “0x80001080” is written in the schedule task variable (schedtsk variable). As a result, the value of the corresponding execution variable (ctxtsk variable) and the value of the scheduled task variable (schedtsk variable) do not match, so that the value "0x80001080" is written to the corresponding execution variable (ctxtsk variable) Dispatch occurs and task TSKi is being executed.

  FIG. 6 illustrates a schematic flowchart of a dispatcher process that distributes and manages a process flow by a task under the management of the OS. In the dispatcher process, task context evacuation (S1), kernel idle loop process (S2), and task context return process (S3) are performed in accordance with the end of the task process to control the return to the task process. In the kernel idle loop process (S2), it is determined whether or not a task to be processed next is scheduled (S21). If it is not scheduled, a power saving process is performed (S22). The process proceeds to context return processing (S3).

  In the power saving process (S22), the corresponding CPU executes a sleep command, and the processing unit is put into a sleep state as described above.

  FIG. 7 shows an example of the power saving process. Here, a case where the value “1” is set in the corresponding write sleep bit LTSLPx (S30) is taken as an example. Thereafter, the interrupt is canceled (S31), the interrupt is prohibited after returning from the sleep (S32) (S33), and the process is terminated. When the light sleep mode is used as a dormant state, the synchronous clock signal of the cache memory or the like is maintained, so that cache coherency is maintained. That is, in the light sleep mode, processing such as cache write-back before the suspension is unnecessary, and cache misses can be reduced even after returning from the suspension state. Thereby, it is possible to speed up both the transition of the processing unit to the hibernation state and the transition from the hibernation state to the active state.

  FIG. 8 illustrates an operation for canceling the sleep state of the processing unit via an interrupt. As one method for returning the processing unit that has transitioned to the hibernation state by executing the sleep instruction in the kernel idle loop process S2 of FIG. 6 to another processing unit, There is a way to request an interrupt. Here, it is assumed that the processing unit (PRCS (#n)) 12 is in a dormant state on the kernel idle loop (S2) by saving the task context in the dispatcher process. At this time, when the data processing load of the multi-core microcomputer 1 increases and it is intended to cancel the hibernation state of the processing unit 12, the other processing units 11 perform task activation processing (S40) for that purpose. In the task activation process, first, scheduling of a task to be processed by the processing unit 12 after returning is performed to the SRAM 2 (S41), and then the processing unit 11 sends an interrupt request to the interrupt processing unit 12 to the interrupt controller 21. Issue (S42).

  In response to an interrupt request to the processing unit 12 that has been paused, the interrupt controller 12 outputs the interrupt signal INTn to the processing unit 12 and restarts the supply of the synchronous clock signal CLKn to the processing unit 12 to the clock control circuit 22. As a result, the processing unit 12 that has transitioned to the active state executes interrupt processing in response to the interrupt signal INTn (S50). In interrupt processing (S50), interrupt entry processing (S51) such as saving and interrupt handler address fetching, interrupt handler processing according to the interrupt handler description program (S52), and exit from the interrupt handler such as return Processing (S53) is performed. Here, it is sufficient that the processing unit 12 is released from the hibernation state. Therefore, if the processing by the interrupt handler has no substantial processing (empty processing), the purpose of the interrupt is sufficiently achieved. After the interrupt exit process (S53), the task context is restored (S3), the task process is restored, and the task scheduled in step S41 is performed.

  As is clear from the processing procedure of FIG. 8, when the processing unit is released from the sleep state using an interrupt, if the interrupt handler is an empty process, a series of processes that call it once and then return to the original routine. However, the processing becomes substantially wasteful, and wasteful time is consumed until the processing unit is released from the hibernation state, which is contrary to the efficiency of data processing. If there is a process to be executed by the interrupt handler in advance by the start of the task process, the process is not wasted time and is allowed for data processing.

  FIG. 9 illustrates an operation of canceling the sleep state of the processing unit by operating the wakeup bit WUPx. Another method for returning the processing unit that has transitioned to the sleep state by executing the sleep instruction in the kernel idle loop process S2 of FIG. 6 is that the other processing units correspond to the processing unit in the sleep state. This is a method of rewriting the wakeup bit WUPx of the control register 30 to the value “1”. As in FIG. 8, it is assumed that the processing unit (PRCS (#n)) 12 is in a dormant state on the kernel idle loop (S2) by saving the task context in the dispatcher process. At this time, when the data processing load of the multi-core microcomputer 1 increases and it is going to cancel the hibernation state of the processing unit 12, the other processing units 11 perform task activation processing (S43) for that purpose. In the task activation process, first, scheduling of a task to be processed by the processing unit 12 after returning is performed to the SRAM 2 (S44), and then the processing unit 11 wakes up the control register 30 for the processing unit 12 in the dormant state. WUPx is rewritten to the value “1” (S45).

  In response to this rewriting, the clock control circuit 22 resumes the supply of the synchronous clock signal CLKn to the processing unit 12. As a result, the processing unit 12 transitioned to the active state immediately returns the task context (S3), returns to the task processing, and starts the processing of the task scheduled in step S44.

  When the processing unit is released from the sleep state by rewriting the wakeup bit WUPx, no interrupt processing is required, and no wasteful time is spent in the empty processing described with reference to FIG. Therefore, when there is no processing to be executed in advance by the interrupt processing before the task processing is resumed, the hibernation state cancellation method by rewriting the wakeup bit WUPx can be used to contribute to improvement of data processing efficiency. .

  Furthermore, since the return time to the task is fast, even if the processing unit is frequently paused and the low power consumption is measured, the influence on the system performance can be reduced.

  In addition, one interrupt request signal between CPUs used in the kernel for canceling sleep can be made available, and this can be distributed to other interrupt factors and used.

<< Embodiment 2 >>
FIG. 10 illustrates a multi-core microcomputer according to the second embodiment of the present invention. The multi-core microcomputer 1A shown in the figure is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique.

  The multi-core microcomputer (MCU) 1 </ b> A has a plurality of processing units (PRCS (# 1), PRCS (#n)) 11, 12 connected to the internal bus 13. Each of the processing units 11 and 12 has at least a CPU for executing instructions, and further includes a floating point arithmetic unit, a memory management unit, and a cache memory. Although not particularly limited, the plurality of processing units 11 and 12 execute application programs under the management of an OS (operating system) that implements SMP.

  The internal bus 13 is interfaced to the peripheral bus 16 via a bus bridge (BBRDG) 14. An interrupt controller (INTC) 21, a clock control circuit (CPCNT) 22A, a bus state controller (LBCNT) 23A, an SDRAM controller (SDRAMCNT) 25, an input / output port (IOP) 24, and the like are connected to the peripheral bus 26.

  The interrupt controller 21A performs interrupt priority level and interrupt mask control for interrupt requests given from inside and outside the multi-core microcomputer, and controls acceptance of interrupt requests. When receiving an interrupt request, the interrupt controller provides an interrupt signal corresponding to the interrupt request to at least one of the processing units 11 and 12. Interrupt signals INT1 and INTn are assigned to the processing units (PRCS (# 1), PRCS (#n)) 11 and 12, respectively. The processing unit to which the interrupt signal is given, for example, completes the execution of an instruction in the middle of execution, performs necessary processing such as saving, and then branches to a processing routine corresponding to the interrupt factor. The interrupt controller has two modes, a fixed distribution mode and an automatic distribution mode. In the fixed distribution mode, a CPU that masks and processes a corresponding interrupt request by setting an interrupt mask register for each processing unit. Is fixedly used. This mode is applied to a case where one factor is processed by one CPU, and is used, for example, in a system in which the CPU has a fixed role such as an AMP method. On the other hand, the automatic distribution mode distributes an interrupt request to the CPUs to be distributed at the same time, and masks the interrupt request of each CPU when one of the CPUs accepts the interrupt request. When the CPU to be processed is fixed as in the fixed distribution mode, if the CPU is in the interrupt disabled state, an interrupt is waited until the interrupt prohibition is canceled. If an interrupt can be accepted by any one of the CPUs, the interrupt can be processed without waiting.

  The clock control circuit 22A generates a synchronous clock signal used inside the multi-core microcomputer based on an oscillator (not shown) or a system clock signal supplied from outside. For example, the processing unit 11 is supplied with a synchronous clock signal CLK1, and the processing unit 12 is supplied with a synchronous clock signal CLKn. Although not particularly limited, the clock control circuit 22 includes a control register (STBCR) 30A for low power consumption control. The control register 30A is different from the control register of FIG. 1 in that it does not have the wake-up bit WUPx.

  For example, the ROM 3 and the SRAM 2 are connected to the bus state controller 23A via the external bus 4, for example. The ROM 3 holds programs and parameter data. The SRAM 2 is used as a work area for the processing units 11 and 12. An SDRAM 5 such as DDR3 is connected to the SDRAM controller 25. The SDRAM 5 is used for a large capacity data primary storage area.

  The multi-core microcomputer 1A has a low power consumption mode of the processing unit. For example, when the CPU executes a sleep command, the CPU enters the sleep state in which the supply of the synchronous clock signal to the CPU is stopped and the execution of a new command is paused. This hibernation state is the low power consumption mode. There are three types of methods for canceling the low power consumption mode: reset, interrupt request, or rewriting a predetermined scheduled task variable.

  The cancellation of the dormant state by rewriting the scheduled task variable will be described. The bus state controller 23A determines based on the access address to the SRAM whether or not a new task to be processed is scheduled because the processing unit in the dormant state becomes active, and notifies the clock control circuit 22A of the determination result. To do.

  For example, the address mapping information of the SRAM 2 in which the schedule task variable (schedtsk) is mapped for each of the processing units 11 and 12 is given to the bus state controller 23A, and the sleep state bit SLEEPx of the control register 30 is referred to, and the sleep state is It is determined whether or not the start address of the task control field is newly written in the schedule task variable corresponding to the processing unit. When the clock control circuit 22A receives the determination result DST and detects that a new task has been scheduled, the clock control circuit 22A performs control to resume the supply of the synchronous clock signal to the inactive processing unit. In this case, it is necessary for the processing unit that controls the cancellation of the hibernation state to separately execute a store instruction for rewriting the schedule task variable.

  Furthermore, as a method for efficiently canceling the hibernation state, the mapping address of the schedule task variable (schedtsk) for which writing should be detected may be specified on the sleep instruction. Such a sleep command is also simply referred to as an extended sleep command. If the extended sleep instruction is used, the bus state controller 23A does not need to hold the mapping information or refer to the sleep display bit SLEEPx of the control register 30. The bus state controller 23A holds the address information specified by the extended sleep instruction, monitors writing to the held address, and outputs this as the determination result DST when the writing is detected.

  FIG. 11 shows a transition control mode between the active state and the hibernate state in the multi-core microcomputer 1A. Here, a case where the processing unit (#n) 12 is put into a dormant state is exemplified. When the processing unit 12 executes the sleep command, the clock control circuit 22A is requested to stop the synchronous clock signal CLKn, and thereby the supply of the clock signal CLKn to the processing unit 12 is stopped. The stop range of the synchronous clock signal CLKn in the processing unit 12 is determined by the value of the write sleep bit LTSLPx.

  In order to transition the processing unit 12 in the dormant state to the active state, an external interrupt request for the processing unit 12 is generated, an internal interrupt request for the processing unit 12 is generated by the processing unit 11 in the active state, or the processing unit 12 is processed by the processing unit 11. Wait for the new task to be scheduled. As a result, the clock control circuit 22A resumes the supply of the synchronous clock signal CLKn.

  For example, it is assumed that the extended sleep instruction is included in the instruction set of the processing unit 12. At this time, if the processing unit 12 executes the extended sleep instruction to shift to the sleep state, the address information specified by the instruction is set in the bus state controller 23A, and the bus state controller 23A specifies the instruction. Monitor writes to specified addresses. The address information is the first mapping address of the schedule task variable (schedtsk) of the processing unit 12. When the processing unit 11 in the active state writes to the scheduled task variable (schedtsk) and schedules the task when attempting to resume the task processing by the processing unit 12 that has been suspended, the bus state controller 23A detects this. Thus, the clock control circuit 22A restarts the output of the clock signal CLKn.

  When the extended sleep instruction is executed, if an interrupt request is issued to the inactive processing unit 12 before writing to the scheduled task variable (schedtsk) occurs, the interrupt controller 21A sends the clock signal CLKn to the clock control circuit 22A. The output is resumed, whereby the processing unit 12 becomes active, and interrupt processing defined by the interrupt handler corresponding to the interrupt request is performed.

  Although not particularly limited, the relationship between the task variable for managing task processing and the task control field is the same as described with reference to FIG.

  FIG. 12 illustrates an operation of canceling the sleep state of the processing unit by a write operation with respect to a predetermined schedule task variable. As described with reference to FIG. 6, by executing the sleep wakeup instruction in the kernel idle loop process (S2), one method for returning the processing unit 12 that has transitioned to the sleep state to the active state is the other processing unit. 11 is a method of performing task scheduling for the processing unit 12 in the dormant state. It is assumed that the processing unit PRCS (#n) 12 has saved the task context in the dispatcher process and has been put into a sleep state on the kernel idle loop (S2). At this time, when the data processing load of the multi-core microcomputer 1A increases and the processing unit 12 is to be released from the hibernation state, the other processing units 11 perform task activation processing (S46). In the task activation process, scheduling of a task to be processed by the processing unit 12 after returning is performed on the SRAM 2 (S47). That is, the writing to the first mapping address of the schedule task variable (schedtsk) of the processing unit 12 is performed. When the sleep state is set by execution of the extended sleep instruction, the write address is an address specified by the extended sleep instruction. When the bus state controller 23A detects this access, the clock control circuit 22A The output of the synchronous clock signal CLKn is resumed. As a result, the processing unit 12 transitioned to the active state immediately returns the task context (S3), returns to the task processing, and starts the processing of the task scheduled in step S47.

  In order to cancel the hibernation state by the interrupt request, the same process as described in FIG. 8 may be performed.

  As indicated by the address specified by the extended sleep instruction, the dormant processing unit automatically transitions to the active state due to the new task scheduling performed for the dormant processing unit by writing to the predetermined address. Therefore, no interrupt processing is required to release the hibernation state, and no wasteful time is consumed in the above-described empty processing. Therefore, if there is no processing to be executed in advance by interrupt processing before resuming task processing, a hibernation release method linked to task scheduling by writing to a predetermined address specified by an extended sleep instruction or the like should be adopted. Therefore, it is possible to contribute to improvement of data processing efficiency as in the first embodiment. In particular, when transitioning to the hibernation state using the extended sleep instruction, if the task scheduling is performed on a predetermined schedule task variable by another processing unit, the hibernation state is immediately released without adding any operation thereafter. be able to.

<< Embodiment 3 >>
A usage example of the multi-core microcomputer 1 (1A) will be described.

  FIG. 13 illustrates a usage form of a multi-core microcomputer having four processing units. Here, illustrations other than the processing unit are omitted, but actually, other configurations described with reference to FIGS. 1 and 10 are also provided. The multi-core microcomputer of FIG. 13 has four processing units PRCS (# 1), PRCS (# 2), PRCS (# 3), and PRCS (# 4), and is applied to, for example, a mobile phone system. Here, tasks that are constantly activated for incoming call monitoring and battery monitoring, and tasks for a game application, a moving image reproduction application, a moving image decoder, a browser, and a mail application are operating. The processing performance of each processing unit is set to LD = 100. The value of the number y of LD = y in () of each task means that the load is applied to the corresponding processing unit, and processing performance is required by that number.

  FIG. 14 illustrates a state where the load in the system of FIG. 13 is reduced. For example, when the mail, the video playback application, and the video playback decoder are terminated from the state shown in FIG. In this case, since the processing performance of the two processing units is sufficient, the remaining two processing units can be put into a dormant state by consolidating the tasks in operation into the two processing units.

  As described above, power saving can be realized by dynamically reducing the number of processing units to be operated according to the load of the entire system. When the load increases again, the dormant processing unit may be returned to the active state. Even if the processing unit is frequently suspended or returned to the active state according to the load state of the entire system, the wakeup bit WUPx described with reference to FIG. 1 or the task scheduling for the predetermined address described with reference to FIG. By adopting the recovery technology linked to the system, power saving can be realized without degrading the data processing performance.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the present invention is one of multi-processing that distributes processing to a plurality of processing units, that is, SMP, that is, a plurality of processing units use the same memory space, and can share information respectively. The present invention is not limited to multiprocessors that allow units to perform the same processing as others to improve processing capability. The present invention can also be applied to a multiprocessor that performs asymmetric multiprocessing (AMP) in which a predetermined function is assigned to each processing unit in advance.

  The suspension control of the processing unit is not limited to the output control of the synchronous clock signal by the CPG, but may be performed by the switch control of the clock gate arranged in the clock path.

  Further, in the above description, the processing unit is in a sleep state when the synchronization clock signal is stopped, and the circuit power supply is maintained in the sleep state, and the internal state of the processing unit is maintained in the state immediately before the sleep in the sleep state. It is assumed that if the supply of the synchronous clock signal is resumed, the processing can be resumed from the previous state. The present invention is not limited to this, and can also be applied to a case where some kind of save processing is required to maintain the internal state necessary for resumption. In that case, it is necessary to restore the saved information in order to resume the processing from the hibernation state.

  The number of processing units, the circuits provided in the processing units other than the CPU, the types of circuit modules provided in the multi-core microcomputer, and the like can be changed as appropriate.

1, 1A Multi-core microcomputer (MCU)
2 SRAM
3 ROM
11,12 processing units (PRCS # 1, PRCS # n)
21,21A Interrupt controller (INTC)
22,22A Clock control circuit (CPCNT)
CLK1, CLKn Synchronous clock signal 23, 23A Bus state controller (LBCNT)
25 SDRAM controller (SDRAMCNT)
INT1, INTn Interrupt signal 30, 30A Control register (STBCR)
LTSLPx Write sleep bit SLEEPx Sleep indication bit WUPx Wakeup bit TCFLD Task control field TSK1, TSK2, TSK3 Task TCBLK1, TCBLK2, TCBLK3 Task control block PRCS # 1, PRCS # 2, PRCS # 3, PRCS # 4 Processing unit

Claims (15)

A plurality of processing units for executing instructions;
In response to execution of a specific instruction by the processing unit, the control unit performs control to pause execution of a new instruction by the processing unit, and rewrites a control bit provided corresponding to the processing unit to a predetermined value or the processing unit. A control circuit that performs control to cancel execution suspension of an instruction in response to occurrence of an interrupt to
A data processing device, wherein a control register rewritable by the processing unit has the control bit. The control for pausing the instruction execution is a control for stopping the supply of the synchronous clock signal to the central processing unit of the processing unit,
The data processing apparatus according to claim 1, wherein the control for canceling execution of the instruction is control for restarting supply of a synchronous clock signal to the central processing unit. When the mode bit held by the control register is a first value, the control for halting the execution of the instruction is performed by maintaining the supply of the synchronous clock signal to the internal memory of the corresponding processing unit while maintaining the synchronous clock to the central processing unit. Control to stop the supply of a signal and stop the supply of a synchronous clock signal to the central processing unit and the internal memory when the mode bit is a second value,
The control for canceling the suspension of execution of the instruction restarts the supply of the synchronous clock signal to the corresponding central processing unit in response to the rewriting of the control bit to the predetermined value when the mode bit is the first value, The control for resuming the supply of a synchronous clock signal to the corresponding central processing unit and the internal memory in response to rewriting of the control bit to a predetermined value when the mode bit is a second value. Data processing equipment.   The processing unit determines whether or not a task to be processed is scheduled, transitions to execution of the task when it is scheduled, and executes the specific instruction when it is not scheduled The data processing system according to claim 1, wherein idle loop processing is performed.   5. The data according to claim 4, wherein the processing unit performs a first task activation process for rewriting a control bit of the control register to a predetermined value after scheduling a task for another processing unit in which instruction execution is suspended. Processing system. An interrupt controller that outputs an interrupt signal to the processing unit in response to an interrupt request;
The processing unit performs a second task activation process of outputting an interrupt request for the other processing unit to the interrupt controller after scheduling a task for the other processing unit in which instruction execution is suspended,
5. The data processing system according to claim 4, wherein the interrupt controller outputs an interrupt signal to another processing unit in response to an interrupt request by the second task activation process. A plurality of processing units for executing instructions;
A memory for storing control data for scheduling tasks to be processed by the processing unit;
In response to execution of a specific instruction by the processing unit, control is performed to pause execution of a new instruction by the processing unit, and task control data of a task processed by the processing unit is stored at a predetermined address in the memory. Or a control circuit that performs control to release the execution suspension of the instruction in response to the interrupt being issued to the processing unit.   The data processing apparatus according to claim 7, wherein the specific instruction specifies the predetermined address. The control for pausing the instruction execution is a control for stopping the supply of the synchronous clock signal to the central processing unit of the processing unit,
The data processing apparatus according to claim 7, wherein the control for canceling execution of the instruction is control for restarting supply of a synchronous clock signal to the central processing unit. When the mode bit held by the control register is the first value, the control for pausing the instruction execution is performed by maintaining the supply of the synchronous clock signal to the internal memory of the corresponding processing unit while maintaining the synchronous clock signal to the central processing unit. The supply of the synchronous clock signal to the central processing unit and the internal memory when the mode bit is a second value,
When the mode bit is a first value, the control for releasing the execution suspension of the instruction restarts the supply of the synchronous clock signal to the corresponding central processing unit in response to the storage of the task control data, and the mode bit 10. The data processing device according to claim 9, wherein when the second value is a control, the supply of the synchronous clock signal to the corresponding central processing unit and the internal memory is resumed in response to the storage of the task control data.   The processing unit determines whether or not a task to be processed is scheduled, transitions to execution of the task when it is scheduled, and executes the specific instruction when it is not scheduled The data processing system according to claim 7, wherein idle loop processing is performed.   12. The data processing system according to claim 11, wherein the processing unit performs a first task activation process for writing the task control data to the memory after scheduling a task for another processing unit in which instruction execution is suspended. . An interrupt controller that outputs an interrupt signal to the processing unit in response to an interrupt request;
The processing unit performs a second task activation process of outputting an interrupt request for the other processing unit to the interrupt controller after scheduling a task for the other processing unit in which instruction execution is suspended,
12. The data processing system according to claim 11, wherein the interrupt controller outputs an interrupt signal to another processing unit in response to an interrupt request by the second task activation process. A plurality of processing units for executing instructions;
A clock control circuit for supplying a synchronous clock signal to the processing unit;
A control register rewritable by the processing unit,
The clock control circuit stops supplying a synchronous clock signal to the processing unit in response to execution of a specific instruction by the processing unit, and stops writing a predetermined value or supplying a synchronous clock signal to the control register. A data processing device that cancels the supply stop of the synchronous clock signal in response to the occurrence of an interrupt to the processing unit. A plurality of processing units for executing instructions;
A memory for storing control data for scheduling tasks to be processed by the processing unit;
A clock control circuit for supplying a synchronous clock signal to the processing unit,
The instruction set of the processing unit includes a low power consumption control instruction,
The low power consumption control instruction stops the supply of the synchronous clock signal to the processing unit that executed the instruction, and another processing unit schedules a new task to be processed by the processing unit in the memory or the processing. A data processing apparatus, which is an instruction that waits for an interrupt to be issued to a unit and causes the clock control circuit to cancel the supply of the synchronous clock signal

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