JP2013038107A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves an operation speed with inhibiting increase in element area.SOLUTION: A semiconductor device disclosed in the present specification comprises a plurality of field effect transistors 10a, 10b including body regions 11a, 11b, gate electrodes 13a, 13b arranged via gate insulation layers 12a, 12b and a pair of source/drain regions 14a, 14b, 14c arranged to sandwich the body regions 11a, 11b. In the plurality of transistors 10a, 10b, the body regions 11a, 11b are electrically connected and only the gate electrode 13a of one transistor 10a among the plurality of transistors 10a, 10b is electrically connected with the body region of one transistor among the plurality of transistors 10a, 10b.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, semiconductor devices such as transistors have been used.

  The performance of a transistor is improved by increasing its operation speed. For example, in order to increase the operation speed, a field effect transistor having a dynamic threshold voltage in which a voltage having the same potential as that of a gate electrode is directly applied to a body region between a pair of source / drain regions has been proposed.

  1A is a plan view showing a semiconductor device according to a conventional example, FIG. 1B is a cross-sectional view taken along line A1-A1 in FIG. 1A, and FIG. 1C is FIG. 2 is a cross-sectional view taken along line A2-A2.

  The semiconductor device 101 includes a substrate 102 and a transistor 110 disposed in an element region defined by the element isolation layer 103 on the substrate 102. The substrate 102 is formed with a well 104 and a well 105 into which impurities are implanted. The transistor 110 is disposed on the well 104.

  The transistor 110 includes a body region 111, a gate electrode 113 disposed on the body region 111 via a gate insulating layer 112, and a pair of source / drain regions 114a and 114b disposed with the body region 111 interposed therebetween. Have. A side wall 115 is disposed on the side surface of the gate electrode 113.

  In the transistor 110, the gate electrode 113 is electrically connected to the well tap 116 through a shared contact 117 that is a conductor. The well tap 116 is electrically connected to the body region 111 and the well 104. Therefore, in the transistor 110, the gate electrode 113 and the body region 111 are short-circuited via the shared contact 117 and the well tap 116, so that a voltage having the same potential as that of the gate electrode 113 is directly applied to the body region 111. .

  Next, operation of the transistor 110 is described.

  When the transistor 110 is turned on, a high potential voltage is applied to the gate electrode 113, and the same potential voltage is also applied to the body region 111. Therefore, the threshold voltage is reduced when the transistor 110 is turned off due to the forward bias drop. It changes to a lower value than the one. Accordingly, the time required for the transistor 110 to change from the off state to the on state is shortened.

  On the other hand, when the transistor 110 is turned off, the voltage applied to the gate electrode 113 becomes a low potential, so the voltage applied to the body region 111 also becomes a low potential. Return to previous value. Accordingly, the transistor 110 has no change in the leakage current when it is off.

JP-A-2005-260607 JP 2007-19811 A

  In a logic circuit or the like, a plurality of transistors may be connected in series. However, when the transistors having the structure shown in FIG. 1 are connected in series, the problem described below occurs.

  2A is a plan view in the case where two transistors are arranged in series in the semiconductor device illustrated in FIG. 1, and FIG. 2B is a cross-sectional view taken along line B1-B1 in FIG. 2 (C) is a cross-sectional view taken along line B2-B2 of FIG. 2 (A).

  The semiconductor device 201 includes a substrate 102 and two transistors 110 a and 110 b disposed in an element region defined by the element isolation layer 103 on the substrate 102. In the two adjacent transistors 110a and 110b, the source / drain regions between the adjacent transistors are integrally formed and have a common source / drain region 114b.

  Each of the two transistors 110a and 110b has a structure similar to that of the transistor illustrated in FIG.

  The gate electrode 113a of the transistor 110a is short-circuited to the body region 111a through the shared contact 117a and the well tap 116a. Similarly, the gate electrode 113b of the transistor 110b is short-circuited to the body region 111b through the shared contact 117b and the well tap 116b.

  The body region 111 a and the body region 111 b are electrically connected via the well 104. Therefore, the gate electrode 113a and the gate electrode 113b are short-circuited through the body region 111a, the body region 111b, the well 104, and the like.

  If the gate electrode 113a and the gate electrode 113b are short-circuited, the two transistors 110a and 110b cannot be operated independently. Therefore, in order to operate the two transistors 110a and 110b independently, it is necessary to insulate the gate electrode 113a and the gate electrode 113b.

  In order to insulate the gate electrode 113a and the gate electrode 113b from each other, for example, two transistors 110a and 110b are arranged with an element isolation layer interposed therebetween so that the body region between adjacent transistors is not short-circuited. Let Then, the source / drain regions between adjacent transistors can be electrically connected using wiring. In this way, a short circuit of the body region between adjacent transistors can be prevented.

  However, when such a structure is used, there may be a problem that an element area in which the two transistors 110a and 110b are arranged increases.

  An object of the present specification is to provide a semiconductor device in which an operation speed is improved while an increase in element area is suppressed.

  It is another object of the present specification to provide a method for manufacturing a semiconductor device in which an operation speed is improved while suppressing an increase in element area.

  According to one embodiment of a semiconductor device disclosed in this specification, a body region, a gate electrode disposed on the body region via a gate insulating layer, and a pair of source / A plurality of field effect transistors each having a drain region, wherein the plurality of transistors have the body regions electrically connected to each other, and only the gate electrode of one of the plurality of transistors is It is electrically connected to the body region of any one of the plurality of transistors.

  Further, according to one embodiment of a method for manufacturing a semiconductor device disclosed in this specification, a body region, a gate electrode disposed on the body region via a gate insulating layer, and the body region are disposed. A plurality of the transistors are formed so as to electrically connect the body regions to each other, and the plurality of the transistors are formed. Only the gate electrode of one of the transistors is electrically connected to the body region of any one of the plurality of transistors.

  According to one embodiment of the semiconductor device disclosed in this specification, the operation speed is improved while suppressing an increase in element area.

  Further, according to one embodiment of a method for manufacturing a semiconductor device disclosed in this specification, a semiconductor device in which an operation speed is improved while an increase in element area is suppressed can be obtained.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

(A) is a top view which shows the semiconductor device by a prior art example, (B) is A1-A1 sectional view taken on the line of (A), (C) is A2-A2 sectional view taken on the line of (A). . (A) is a plan view when two transistors are arranged in series in the semiconductor device shown in FIG. 1, (B) is a sectional view taken along line B1-B1 in (A), and (C) is (A). It is B2-B2 sectional view taken on the line. (A) is a top view which shows 1st Embodiment of the semiconductor device disclosed to this specification, (B) is C1-C1 sectional view taken on the line of (A), (C) is C2 of (A). FIG. 6 is a cross-sectional view taken along line C2-C, (D) is a cross-sectional view taken along line C3-C3 in FIG. FIG. 4 is a circuit diagram of the semiconductor device shown in FIG. 3. (A) is a top view which shows the modification 1 of 1st Embodiment of the semiconductor device disclosed to this specification, (B) is D1-D1 sectional view taken on the line of (A), (C) is ( It is D2-D2 sectional view taken on the line of A). (A) is a top view which shows the modification 2 of 1st Embodiment of the semiconductor device disclosed to this specification, (B) is the E1-E1 sectional view taken on the line of (A), (C) is ( It is E2-E2 sectional view taken on the line of A). FIG. 7 is a circuit diagram of the semiconductor device shown in FIG. 6. (A) is a top view which shows 2nd Embodiment of the semiconductor device disclosed to this specification, (B) is F1-F1 sectional view taken on the line of (A), (C) is F2 of (A). FIG. 4 is a cross-sectional view taken along line F2-F, FIG. 4D is a cross-sectional view taken along line F3-F3 in FIG. 3A, and FIG. (A) is a top view which shows the modification of 2nd Embodiment of the semiconductor device disclosed to this specification, (B) is G1-G1 sectional view taken on the line of (A), (C) is (A 2 is a cross-sectional view taken along line G2-G2. (A) is a top view which shows 3rd Embodiment of the semiconductor device disclosed to this specification, (B) is H1-H1 sectional view taken on the line of (A), (C) is H2 of (A). FIG. 4 is a cross-sectional view taken along line -H2, and (D) is a cross-sectional view taken along line H3-H3 in FIG. (A) is a top view which shows the modification of 3rd Embodiment of the semiconductor device disclosed to this specification, (B) is the I1-I1 sectional view taken on the line of (A). 10 is a flowchart illustrating a method for manufacturing a semiconductor device disclosed in this specification. (A) is a top view which shows other embodiment of the semiconductor device disclosed to this specification, (B) is J1-J1 sectional view taken on the line of (A), (C) is J2 of (A). FIG. 4 is a cross-sectional view taken along line J2-(D) is a cross-sectional view taken along line J3-J3 in (A), and FIG.

  Hereinafter, a preferred first embodiment of a semiconductor device disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  3A is a plan view illustrating a first embodiment of the semiconductor device disclosed in this specification, and FIG. 3B is a cross-sectional view taken along line C1-C1 in FIG. 3A. 3C is a cross-sectional view taken along line C2-C2 in FIG. 3A, FIG. 3D is a cross-sectional view taken along line C3-C3 in FIG. 3A, and FIG. 3E is FIG. FIG. 4 is a cross-sectional view taken along line C4-C4. FIG. 4 is a circuit diagram of the semiconductor device shown in FIG.

  The semiconductor device 1 according to the present embodiment includes a substrate 2 and two field effect transistors 10a and 10b disposed in an element region defined by an element isolation layer 3 on the substrate 2. The transistors 10a and 10b are n-type MOS transistors. On the substrate 2, a well 4 having p-type conductivity and a well 5 having n-type conductivity are formed. As the substrate 2, for example, a bulk silicon wafer can be used. The well 4 is disposed in the element region defined by the element isolation layer 3. The two transistors 10 a and 10 b are arranged on the well 4.

  The transistor 10a includes a body region 11a having p-type conductivity and a gate electrode 13a disposed on the body region 11a with a gate insulating layer 12a interposed therebetween. A side wall 15a is disposed on the side surface of the gate electrode 13a. Body region 11 a is in electrical contact with well 4.

  The body region 11a is a portion including a channel region located under the gate insulating layer 12a. The body region 11a can be formed, for example, by implanting a p-type impurity for threshold adjustment into the well 4.

  The transistor 10a includes a pair of n-type conductive source / drain regions 14a and 14b arranged with the body region 11a interposed therebetween.

  The above description regarding the transistor 10a is also applied to the transistor 10b as appropriate.

  In the two adjacent transistors 10a and 10b, the source / drain regions between the adjacent transistors are integrally formed and have a common source / drain region 14b.

  The transistor 10 a has a well tap 16 that is in electrical contact with the body region 11 a and the well 4. The well tap 16 is disposed on one end side in the longitudinal direction of the gate electrode 13a. The well tap 16 has p-type conductivity, and the impurity concentration of the well tap 16 is preferably higher than that of the well 4 in order to take out the potentials of the body region 11a and the well 4 without loss.

  Further, the transistor 10 a has a shared contact 17 that is in electrical contact with the gate electrode 13 a and the well tap 16. The shared contact 17 is disposed adjacent to one end in the longitudinal direction of the gate electrode 13a and covers the end of the gate electrode 13a. The shared contact 17 is a contact electrically connected to an upper layer wiring (not shown), and is shared by the gate electrode 13 a and the well tap 16.

  In the transistor 10a, the gate electrode 13a is electrically connected to the well tap 16 through the shared contact 17 which is a conductor. That is, in the transistor 10a, since the gate electrode 13a and the body region 11a are short-circuited via the shared contact 17 and the well tap 16, a voltage having the same potential as that of the gate electrode 13a is directly applied to the body region 11a. . Note that the voltage applied to the body region 11a may be slightly lower than the potential of the gate electrode 13a due to the influence of parasitic resistance, but this is not an essential problem.

  The body region 11b of the transistor 10b is electrically connected to the body region 11a of the transistor 10a through the well 4. Accordingly, a voltage having the same potential as that of the gate electrode 13a of the transistor 10a is directly applied to the body region 11b of the transistor 10b. Note that the voltage applied to the body region 11b may be slightly lower than the potential of the gate electrode 13a due to the influence of parasitic resistance, but this is not an essential problem.

  Next, the operation of the transistors 10a and 10b will be described.

  When the transistor 10a is turned on, a high-potential voltage is applied to the gate electrode 13a, and the same-potential voltage is also applied to the body region 11a. It changes to a lower value than the one. Accordingly, the time required for the transistor 10a to change from the off state to the on state is shortened.

  On the other hand, when the transistor 10a is turned off, the voltage applied to the gate electrode 13a has a low potential, so the voltage applied to the body region 11a also has a low potential. Return to previous value. Therefore, in the transistor 10a, there is no change in the drain-source leakage current when the transistor 10a is off.

  Here, when the transistor 10a is turned on when the transistor 10a is turned on, a voltage having the same potential as that of the gate electrode 13a is applied to the body region 11b of the transistor 10b. As a result, the threshold voltage changes to a value lower than that when the transistor 10b is off. Accordingly, the time required for the transistor 10b to change from the off state to the on state is shortened.

  Similarly, when the transistor 10a changes from the off state to the on state, and when the transistor 10b changes from the off state to the on state, the time required for the transistor 10b to change from the off state to the on state is shortened. Is done.

  Thus, although the well tap and the shared contact as in the transistor 10a are not arranged in the transistor 10b, the switching time is shortened similarly to the transistor 10a.

  According to the semiconductor device 1 of the present embodiment described above, the operation speed of the transistors 10a and 10b can be improved. Here, since the well tap and the shared contact are not arranged in the transistor 10b, the operation speed of the transistor 10b can be improved while suppressing an increase in the element area.

  In the semiconductor device 1 according to the present embodiment described above, the gate electrode 13a and the body region 11a are connected via the shared contact 17, and the well tap 16 and the source / drain regions 14a and 14b are separated from each other by the T-shaped gate electrode 13a. It is done by. However, the embodiment of connection and separation is not limited to this, and other forms may be used.

  Next, Modification Example 1 and Modification Example 2 of the semiconductor device of the first embodiment described above will be described below with reference to the drawings.

  FIG. 5A is a plan view showing Modification Example 1 of the first embodiment of the semiconductor device disclosed in this specification, and FIG. 5B is a cross-sectional view taken along line D1-D1 in FIG. FIG. 5C is a cross-sectional view taken along line D2-D2 of FIG.

  The semiconductor device 1 according to the first modification has two element regions R1 and R2. Each of the two element regions R1 and R2 is defined by being electrically separated by an element isolation layer 3 formed on the substrate 2.

  In the element region R1, two transistors 10a and 10b are arranged as in the semiconductor device of the first embodiment described above.

  In the element region R2, a transistor 10c that is an n-type MOS transistor is arranged. The transistor 10c is disposed on the well 6 having p-type conductivity. The transistor 10c has a structure similar to that of the transistor 10b.

  Since the well 4 in the element region R1 is electrically connected to the well 6 of the adjacent element region R2, the body region 11a of the transistor 10a in the element region R1 and the transistor 10c in the element region R2 The body region 11c is not electrically connected.

  Therefore, even if a voltage is applied to the gate electrode 13a of the transistor 10a disposed in the element region R1, no voltage is applied to the body region 11c of the transistor 10c disposed in the element region R2.

  In this way, by not extending the well 4 of the element region R1 to the adjacent element region R2, the application of voltage to the gate electrode 13a of the transistor 10a is prevented from affecting the transistor 10c.

  FIG. 6A is a plan view showing a modified example 2 of the first embodiment of the semiconductor device disclosed in this specification, and FIG. 6B is a cross-sectional view taken along line E1-E1 in FIG. 6A. 6C is a cross-sectional view taken along line E2-E2 of FIG. FIG. 7 is a circuit diagram of the semiconductor device shown in FIG.

  The semiconductor device 1 according to the modified example 2 is different from the first embodiment described above in that three transistors 10a, 10b, and 10d are arranged in an element region defined by the element isolation layer 3 on the substrate 2. Is different.

  The three transistors 10a, 10b, and 10d are electrically connected in series.

  The transistor 10d has a structure similar to that of the transistor 10b. In the two adjacent transistors 10b and 10s, the source / drain regions between the adjacent transistors are integrally formed and have a common source / drain region 14c.

  The body region 11d of the transistor 10d is electrically connected to the body region 11a of the transistor 10a through the well 4. Therefore, a voltage having the same potential as that of the gate electrode 13a of the transistor 10a is directly applied to the body region 11d of the transistor 10d.

  Accordingly, the operation speed of the transistor 10d is improved similarly to the transistor 10b.

  In Modification 2 described above, three transistors are arranged in one element region, but the number of transistors arranged in one element region may be four or more.

  Next, second and third embodiments of the semiconductor device will be described below with reference to FIGS. Regarding points that are not particularly described in the second and third embodiments, the description in detail regarding the first embodiment is applied as appropriate.

  The semiconductor device 20 of the present embodiment includes a substrate 2a and two transistors 20a and 20b disposed in an element region defined by the element isolation layer 3a on the substrate 2a. The transistors 20a and 20b are n-type MOS transistors. A well 7 having p-type conductivity is formed on the substrate 2a. As the substrate 2a, for example, an SOI (Silicon on Insulator) wafer can be used. In this case, the element isolation layer 3a can be formed using an electrical insulating layer on the SOI substrate. The well 7 is disposed in the element region defined by the element isolation layer 3a. The two transistors 20 a and 20 b are arranged on the well 7.

  The transistor 20a includes a body region 21a having p-type conductivity, and a gate electrode 23a disposed on the body region 21a via a gate insulating layer 22a. Side walls 25a are disposed on the side surfaces of the gate electrode 23a. Body region 21 a is in electrical contact with well 7.

  The body region 21a is a portion including a channel region located under the gate insulating layer 22a. The body region 21a can be formed, for example, by injecting a p-type impurity for threshold adjustment into the well 7.

  The transistor 20a includes a pair of n-type conductive source / drain regions 24a and 24b arranged with the body region 21a interposed therebetween.

  The above description of the transistor 20a is applied as appropriate to the transistor 20b.

  In the two adjacent transistors 20a and 20b, the source / drain regions between the adjacent transistors are integrally formed and have a common source / drain region 24b.

  The transistor 20 a has a well tap 26 that is in electrical contact with the body region 21 a and the well 7. The well tap 26 has p-type conductivity, and the impurity concentration of the well tap 26 is preferably higher than that of the well 7 in order to take out the potentials of the body region 21a and the well 7 without loss.

  As shown in FIGS. 8A and 8E, the well tap 26 is also in electrical contact with the body region 21b of the transistor 20b.

  As shown in FIG. 8B, the transistor 20 a includes a shared contact 27 that is in electrical contact with the gate electrode 23 a and the well tap 26. The shared contact 27 is a contact that is electrically connected to an upper layer wiring (not shown), and is shared by the gate electrode 23 a and the well tap 26.

  In the transistor 20a, the gate electrode 23a is electrically connected to the well tap 26 through a shared contact 27 that is a conductor. Accordingly, in the transistor 20a, the gate electrode 23a and the body region 21a are short-circuited via the shared contact 27 and the well tap 26, and thus a voltage having the same potential as that of the gate electrode 23a is directly applied to the body region 21a.

  The body region 21b of the transistor 20b is electrically connected to the gate electrode 23a of the transistor 20a through the well tap 26 and the shared contact 27. In this way, a voltage having the same potential as that of the gate electrode 23a of the transistor 20a is directly applied to the body region 21b of the transistor 20b.

  According to the semiconductor device 20 of the present embodiment described above, the same effects as those of the first embodiment can be obtained.

  In the present embodiment, since the element isolation layer 3a, which is an electrical insulating layer, is disposed under the well 7, since the stray capacitance and the leakage current are reduced, the switching speed is further improved and the power consumption is reduced. To do.

  Next, a modified example of the semiconductor device of the second embodiment described above will be described below with reference to the drawings.

  FIG. 9A is a plan view showing a modification of the second embodiment of the semiconductor device disclosed in this specification, and FIG. 9B is a cross-sectional view taken along line G1-G1 in FIG. FIG. 9C is a cross-sectional view taken along line G2-G2 in FIG.

  The semiconductor device 20 of this modification is different from the above-described second embodiment in the structure of electrical connection between the gate electrode 23a of the transistor 20a and the body region 21b of the transistor 20b.

  In this modification, the body region 21b of the transistor 7b is disposed on the well 7b as shown in FIG. 9B. The transistor 7b has a body region 21b and a well tap 26b that is in electrical contact with the well 7b.

  The transistor 7a has a structure similar to that of the transistor 7b. In this modification, the well tap 26a of the transistor 7a is not electrically connected to the well tap 26b of the transistor 7b. Further, the well 7a of the transistor 20a is not electrically connected to the well 7b of the transistor 20b.

  A contact 28 is disposed on the well tap 26b of the transistor 20b. The contact 28 and the shared contact 27 of the transistor 20 a are electrically connected through a wiring 29. That is, the body regions 21 a and 21 b of the two transistors 20 a and 20 b are electrically connected via the wiring 29. The contact 28, the shared contact 27, and the wiring 29 are embedded in an insulating layer (not shown).

  Accordingly, the body region 21b of the transistor 20b is electrically connected to the gate electrode 23a of the transistor 20a through the well tap 26b, the contact 28, the wiring 29, and the shared contact 27. In this way, a voltage having the same potential as that of the gate electrode 23a of the transistor 20a is directly applied to the body region 21b of the transistor 20b.

  10A is a plan view illustrating a third embodiment of the semiconductor device disclosed in this specification, and FIG. 10B is a cross-sectional view taken along the line H1-H1 in FIG. 10A. 10C is a cross-sectional view taken along line H2-H2 in FIG. 10A, and FIG. 10D is a cross-sectional view taken along line H3-H3 in FIG.

  The semiconductor device 30 of this embodiment is a NAND circuit. The semiconductor device 30 includes two transistors 30a and 30b that are electrically connected in series, and two transistors 30c and 30d that are electrically connected in parallel. Have

  First, the two transistors 30a and 30b will be described below.

  The transistor 30a has the same structure as the transistor 10a of the first embodiment described above. That is, in the transistor 30a, the gate electrode 33a is electrically connected to the body region 31a via the shared contact 37a and the well tap 36a.

  The transistor 30b has the same structure as the transistor 10b of the first embodiment described above. That is, since the body region 31b of the transistor 30b is electrically connected to the body region 31a of the transistor 30a via the well 4, the body region 31b has the same potential as the gate electrode 33a of the transistor 30a. A voltage is applied directly.

  A contact 38a is disposed on the source / drain region 34a of the transistor 30a. A contact 38b is disposed on the source / drain region 34c of the transistor 30b. A wiring 39b is connected to the contact 39b.

  Thus, the transistor 30a and the transistor 30b are electrically connected in series.

  Next, the two transistors 30c and 30d will be described below.

  The transistor 30c has a structure similar to that of the transistor 30a except that the conductivity is different. The transistor 30d has a structure similar to that of the transistor 30b except that the conductivity is different.

  As illustrated in FIG. 10D, the transistor 30c includes a body region 31c having n-type conductivity and a gate electrode 33c disposed over the body region 31c with a gate insulating layer 32c interposed therebetween. The gate electrode 33c is formed integrally with the gate electrode 33a. The gate insulating layer 32c is formed integrally with the gate insulating layer 32a. A side wall 35c is disposed on the side surface of the gate electrode 33c. The side wall 35c is formed integrally with the side wall 35a. The body region 31c is in electrical contact with the well 8 having n-type conductivity. The well 8 is disposed on the well 9 having p-type conductivity.

  The body region 31c is a portion including a channel region located under the gate insulating layer 32c. The body region 31c can be formed, for example, by implanting an n-type impurity for threshold adjustment into the well 8.

  The transistor 30c includes a pair of p-type source / drain regions 34d and 34e disposed with the body region 31c interposed therebetween.

  The above description regarding the transistor 30c also applies as appropriate to the transistor 30d.

  In the two adjacent transistors 30c and 30d, the source / drain regions between the adjacent transistors are integrally formed and have a common source / drain region 34e.

  The transistor 30 c includes a body region 31 c and a well tap 36 b that is in electrical contact with the well 8. The well tap 36b has n-type conductivity, and the impurity concentration of the well tap 36b is preferably higher than that of the well 8 in order to take out the potentials of the body region 31c and the well 8 without loss.

  The transistor 30c includes a shared contact 37b that is in electrical contact with the gate electrode 33c and the well tap 36b. The shared contact 37b is a contact electrically connected to an upper layer wiring (not shown), and is shared by the gate electrode 33c and the well tap 36b.

  In the transistor 30c, the gate electrode 33c is electrically connected to the well tap 36b through the shared contact 37b which is a conductor. Therefore, in the transistor 30c, the gate electrode 33c and the body region 31c are short-circuited via the shared contact 37b and the well tap 36b, and therefore, a voltage having the same potential as that of the gate electrode 33c is directly applied to the body region 31c.

  The body region 31d of the transistor 30d is electrically connected to the body region 31c of the transistor 30c through the well 8. Therefore, a voltage having the same potential as that of the gate electrode 33c of the transistor 30c is directly applied to the body region 31d of the transistor 30d.

  A contact 38c is disposed on the source / drain region 34d of the transistor 30c. A contact 38e is disposed on the source / drain region 34f of the transistor 30d. The contact 38c and the contact 38e are electrically connected by a wiring 39a. The wiring 39a electrically connects the contact 38c and the contact 38e with the contact 34a.

  A contact 38d is disposed on the source / drain region 34e common to the two transistors 30c and 30d. A wiring 39c is connected to the contact 38d. The contacts 38a, 38b, 38c, 38d, and 38e, the shared contacts 37a and 37b, and the wirings 39a and 39b are embedded in an insulating layer (not shown).

  Thus, the transistor 30c and the transistor 30d are electrically connected in parallel.

  In the NAND circuit, the transistor 10a switches from the off state to the on state. Further, when the transistor 10a is in the on state, the transistor 10b switches from the off state to the on state. Furthermore, the transistor 10b may change from the off state to the on state at the same time as the transistor 10a changes from the off state to the on state.

  In such a case, in the semiconductor device 30, the switching time of the transistor 10a and the transistor 10b is shortened, so that the response is high.

  Similarly, in the NAND circuit, the transistor 30c is switched from the off state to the on state. Further, when the transistor 30c is in the on state, the transistor 30d is switched from the off state to the on state. Further, the transistor 30d may change from the off state to the on state at the same time as the transistor 30c changes from the off state to the on state.

  In such a case, in the semiconductor device 30, since the switching time of the transistors 30c and 30d is shortened, the responsiveness is high.

  According to the semiconductor device 30 of the present embodiment described above, the operation speed of the two transistors 30a and 30b connected in series and the two transistors 30c and 30d connected in parallel can be improved. Here, in the semiconductor device 30, since the transistor 30b and the transistor 30d are not provided with well taps or shared contacts, the operation speed of the transistor 30b and the transistor 30d is improved while suppressing an increase in the element area.

  In the present embodiment described above, two n-type transistors are connected in series, and two p-type transistors are connected in parallel. Similarly, a NOR circuit can be formed by connecting two p-type transistors in series and connecting two n-type transistors in parallel.

  Next, a modified example of the semiconductor device of the third embodiment described above will be described below with reference to the drawings.

  FIG. 11A is a plan view showing a modification of the third embodiment of the semiconductor device disclosed in this specification, and FIG. 11B is a cross-sectional view taken along the line I1-I1 of FIG.

  The semiconductor device 30 of this modification is different from the above-described third embodiment in that the p-type transistor 30c does not have a shared contact.

  In this modification, the body region 31c of the transistor 30c and the portion of the well 4 located under the body region 31a of the transistor 30a are in contact with the well 8a having n-type conductivity.

  Although not shown, similarly, the body region 31d of the transistor 30d and the portion of the well 4 located below the body region 31b of the transistor 30b are also in contact with the well 8a.

  A well tap 36c for extracting the potential of the well 8a is disposed so as to be insulated from the transistor 30c by the element isolation layer 3. The position of the well tap 36c is not particularly limited as long as the potential of the well 8a can be taken out. Therefore, the well tap 36c is not necessarily arranged at the position shown in FIG.

  According to this modified example described above, the element area can be reduced by removing the shared contact from the transistor 30c. In the NAND logic operation, when the two transistors 30a and 30b connected in series are turned from the off state to the on state at the same time, the circuit length is longer than that of the parallel connection, so that the switching time becomes longer. Therefore, the logical operation speed can be greatly improved by improving the switching speed of the two transistors 30a and 30b connected in series. In this modified example, although the switching speed of the two transistors 30c and 30d connected in parallel is slower than that of the third embodiment described above, there is no change in improving the NAND logic operation speed.

  Next, a preferred embodiment of a method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to FIG.

  First, as shown in step S10, an element region is formed on a substrate.

  Next, as shown in step S12, a plurality of transistors are formed in the element region so as to electrically connect the body regions, and only the gate electrode of one of the plurality of transistors is formed. And electrically connected to the body region of any one of the plurality of transistors. In this case, when forming a plurality of transistors, it is preferable that a common source / drain region between adjacent transistors is integrally formed in two adjacent transistors.

  Next, as shown in step S14, a contact is formed on the gate electrode or source / drain region of the transistor.

  And as shown to step S16, the wiring connected with a contact is formed.

  In each step of the semiconductor device manufacturing method described above, a known element technology can be applied.

  In the present invention, the semiconductor device and the method for manufacturing the semiconductor device described above can be changed as appropriate without departing from the spirit of the present invention. In addition, the configuration requirements of one embodiment can be applied to other embodiments as appropriate.

  For example, in the semiconductor device described above, the gate electrode of one of the plurality of transistors is electrically connected to the body region of the one transistor. However, the gate electrode of one of the plurality of transistors may be electrically connected to the body region of any one of the plurality of transistors. For example, in FIG. 3, the gate electrode 13a of the transistor 10a may be electrically connected only to the body region 11b of the transistor 10b.

  Further, in the semiconductor device described above, the source / drain regions between adjacent transistors are integrally formed in adjacent transistors, but the source / drain regions between adjacent transistors are integrally formed in adjacent transistors. It may not be formed. Hereinafter, this embodiment will be described with reference to the drawings.

  13A is a plan view illustrating another embodiment of a semiconductor device disclosed in this specification, and FIG. 13B is a cross-sectional view taken along line J1-J1 in FIG. 13C is a cross-sectional view taken along line J2-J2 in FIG. 13A, FIG. 13D is a cross-sectional view taken along line J3-J3 in FIG. 13A, and FIG. FIG. 4 is a sectional view taken along line J4-J4.

  The semiconductor device 1 includes a substrate 2 and two transistors 10 a and 10 b disposed in an element region defined by the element isolation layer 3 on the substrate 2. The transistors 10a and 10b are n-type MOS transistors.

  The transistor 10a includes a pair of n-type conductive source / drain regions 14a and 14b arranged with the body region 11a interposed therebetween. The transistor 10b includes a pair of n-type conductive source / drain regions 14f and 14g arranged with the body region 11b interposed therebetween.

  The source / drain region 14b of the transistor 10a and the source / drain region 14f of the transistor 10b are electrically insulated by the element isolation layer 3.

  The transistor 10a has a shared contact 17 that electrically connects the gate electrode 13a and the well tap 16a. The gate electrode 13a is electrically connected to the body region 11a through the shared contact 17 and the well tap 16a.

  Body region 11a of transistor 10b is electrically connected to well tap 16a. Therefore, the body region 11a of the transistor 10b is electrically connected to the gate electrode 13a of the transistor 10a via the well tap 16a and the shared contact 17.

  In this way, a voltage having the same potential as that of the gate electrode 13a of the transistor 10a is directly applied to the body region 11b of the transistor 10b.

  In the semiconductor device 1 shown in FIG. 13, the source / drain regions between adjacent transistors 10a and 10b are not integrally formed, but the operation speed of the transistors 10a and 10b is improved.

  All examples and conditional words mentioned herein are intended to assist the reader in deepening their understanding of the inventions and concepts contributed by the inventors. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

  Regarding the above-described embodiments, the following additional notes are disclosed.

(Appendix 1)
The body region,
A gate electrode disposed on the body region via a gate insulating layer;
A pair of source / drain regions disposed across the body region;
A plurality of field effect transistors having
In the plurality of transistors, the body regions are electrically connected to each other,
A semiconductor device in which only the gate electrode of one of the plurality of transistors is electrically connected to the body region of any one of the plurality of transistors.

(Appendix 2)
The semiconductor device according to appendix 1, wherein the gate electrode of the one transistor is electrically connected to the body region of the one transistor.

(Appendix 3)
The body regions of the plurality of transistors are electrically connected to wells, and the body regions of the plurality of transistors are electrically connected to each other through the wells. Semiconductor device.

(Appendix 5)
The plurality of transistors are arranged in one element region having the well,
The semiconductor device according to attachment 3, wherein the well is not electrically connected to another well included in another adjacent element region.

(Appendix 4)
The semiconductor device according to appendix 1 or 2, wherein the body regions of the plurality of transistors are electrically connected by wiring.

(Appendix 6)
The semiconductor device according to any one of appendices 1 to 4, wherein the plurality of transistors are formed by integrally forming the source / drain regions between adjacent transistors.

(Appendix 7)
The semiconductor device according to claim 1, wherein the plurality of transistors are connected in series.

(Appendix 8)
The semiconductor device according to claim 1, wherein the plurality of transistors are connected in parallel.

(Appendix 9)
A method of manufacturing a field effect transistor having a body region, a gate electrode disposed on the body region via a gate insulating layer, and a pair of source / drain regions disposed with the body region interposed therebetween. And
A plurality of the transistors are formed so as to electrically connect the body regions, and only the gate electrode of one of the plurality of transistors is electrically connected to the body region of the one transistor. Manufacturing method of a semiconductor device to be connected to each other.

1a, 20, 30 Semiconductor device 2, 2a Substrate 3, 3a Element isolation layer 4 Well 5 Well 6 Well 7, 7a, 7b Well 8 Well 9 Well 10a, 10b, 10c, 10d Transistor 11a, 11b, 11c, 11d Body region 12a, 12b, 12c, 12d Gate insulating film 13a, 13b, 13c, 13d Gate electrode 14a, 14b, 14c, 14d, 14e, 14f Source / drain region 15a, 15b, 15c, 15d Side wall 16, 16a Well tap 17 Shared contact 20a, 20b Transistors 21a, 21b Body regions 22a, 22b Gate insulation films 23a, 23b Gate electrodes 24a, 24b, 24c Source / drain regions 25a, 25b Side walls 26, 26a, 26b Well taps 27 Shared Contact 28 Contact 29 Wiring 30a, 30b, 30c, 30d Transistor 31a, 31b, 31c, 31d Body region 32a, 32b, 32c, 32d Gate insulating film 33a, 33b, 33c, 33d Gate electrode 34a, 34b, 34c, 34d, 34e , 34f Source / drain region 35a, 35b, 35c, 35d Side wall 36a, 36b, 36c Well tap 37a, 37b Shared contact 38a, 38b, 38c, 38d, 38e Contact 39a, 39b, 39c Wiring R1 First element region R2 Second Element area

Claims (4)

The body region,
A gate electrode disposed on the body region via a gate insulating layer;
A pair of source / drain regions disposed across the body region;
A plurality of field effect transistors having
In the plurality of transistors, the body regions are electrically connected to each other,
A semiconductor device in which only the gate electrode of one of the plurality of transistors is electrically connected to the body region of any one of the plurality of transistors.   2. The semiconductor according to claim 1, wherein each of the body regions of the plurality of transistors is electrically connected to a well, and the body regions of the plurality of transistors are electrically connected to each other through the well. apparatus. The plurality of transistors are arranged in one element region having the well,
The semiconductor device according to claim 2, wherein the well is not electrically connected to another well included in another adjacent element region.   The semiconductor device according to claim 1, wherein the body regions of the plurality of transistors are electrically connected by wiring.

Images