JP2013037737A - Neuron cmos circuit and electronic circuit provided with neuron cmos circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a neuron CMOS circuit for achieving advanced threshold control by suppressing the influence of capacitance between a floating gate and a substrate, and to provide an electronic circuit provided with such a neuron CMOS circuit.SOLUTION: According to one embodiment of this invention, the neuron CMOS circuit is provided, having a PMOSFET and an NMOSFET formed on a substrate, constituting a CMOS circuit and having a common floating gate and a plurality of input gates. Capacitance between the common floating gate and the substrate is almost equal to capacitance between one input gate electrode of the plurality of input gates and the common floating gate.

Description

The present invention relates to a neuron CMOS circuit in which a plurality of gates are arranged on a floating gate. In particular, the present invention relates to a neuron CMOS circuit that suppresses variation in threshold value due to the influence of the capacitance between the floating gate and the substrate. The present invention also relates to an electronic circuit including a neuron CMOS circuit.

Computers that are generally used are configured by Neumann electronic circuits that execute instructions one by one in accordance with a predetermined program. Neumann electronic circuits can perform very high-speed operations for simple numerical calculations. On the other hand, in order to realize complicated arithmetic processing, research on a neurocomputer that mimics the function of a nerve cell has been advanced, and a MOS semiconductor element (neuron MOSFET) that mimics the structure of a neuron has been reported (Patent Document) 1).

A neuron MOSFET is a MOSFET having two or more input gate electrodes that are capacitively coupled to a floating gate electrode, and a value obtained by linearly adding a voltage applied to each of the input gate electrodes with a predetermined weight is greater than a predetermined threshold value. This is a MOS circuit configured so that the source and drain regions are electrically connected only when the size becomes large. Further, the drains of a p-channel neuron MOSFET (hereinafter referred to as P-νMOS) and an n-channel neuron MOSFET (hereinafter referred to as N-νMOS) are connected to each other, and the floating gates of P-νMOS and N-νMOS are used as a common gate. A neuron CMOS circuit having more than one input gate electrode has been reported (Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 3-6679 International Publication Number WO96 / 30855

Since the neuron CMOS circuit is provided with a plurality of input gate electrodes, a coupling capacitance is formed between the floating gate and each input gate electrode. In addition, as described above, the source and drain regions are electrically connected only when a value obtained by applying a predetermined weight to the voltage applied to each of the input gate electrodes and linearly adding the value exceeds a predetermined threshold value. Therefore, in the neuron CMOS circuit, a high degree of threshold value control is required. However, there is a problem that the threshold value seen from the input gate varies due to the influence of the capacitance between the floating gate and the substrate.

An object of the present invention is to provide a neuron CMOS circuit that suppresses the influence of a capacitance between a floating gate and a substrate and realizes a high threshold control. It is another object of the present invention to provide an electronic circuit including such a neuron CMOS circuit.

According to an embodiment of the present invention, a CMOS circuit is formed on a substrate, and includes a PMOSFET and an NMOSFET having a common floating gate and a plurality of input gates, and is disposed between the common floating gate and the substrate. A neuron CMOS circuit having a capacitance approximately equal to a capacitance between one input gate electrode of the plurality of input gates and the common floating gate is provided.

The plurality of input gate electrodes may each have a predetermined capacitance with the common floating gate, and an output voltage may be output in accordance with a voltage input to each of the plurality of input gate electrodes.

A power supply voltage may be applied to the source of the PMOSFET and the one input gate electrode.

According to an embodiment of the present invention, a substrate, an n-well formed in the substrate, a first p-type diffusion region formed in the n-well, and a first n formed in the substrate. A type diffusion region, a floating gate disposed on the first p-type diffusion region and the first n-type diffusion region, and a plurality of input gate electrodes disposed on the floating gate. A neuron CMOS circuit is provided in which a capacitance between the floating gate and the substrate is substantially equal to a capacitance between one input gate electrode of the plurality of input gates and the floating gate.

A first wiring layer connected to the first p-type diffusion region and the one input gate electrode to apply a power supply voltage; a second wiring layer connected to the first n-type diffusion region and grounded; A wiring layer and a third wiring layer that is connected to the first p-type diffusion region and the first n-type diffusion region and outputs an output voltage may further be provided.

According to one embodiment of the present invention, the substrate, the n-well and the p-well formed in the substrate, the first p-type diffusion region formed in the n-well, and the p-well are formed. A first n-type diffusion region; a floating gate disposed on the first p-type diffusion region and the first n-type diffusion region; and a plurality of input gate electrodes disposed on the floating gate A neuron CMOS circuit comprising:

The substrate may be a substrate not containing impurities, a substrate having a low impurity concentration, or an insulating substrate.

A second n-type diffusion region formed in the n-well and a second p-type diffusion region formed in the p-well may be further provided.

According to an embodiment of the present invention, a substrate, an n-well formed in the substrate, a first p-type diffusion region formed in the n-well, and a first n formed in the substrate. A type diffusion region, a floating gate disposed on the first p-type diffusion region and the first n-type diffusion region, and a plurality of input gate electrodes disposed on the floating gate. A neuron CMOS circuit is provided in which the n-well is arranged so as to overlap with an area half of the floating gate.

The semiconductor device may further include a second n-type diffusion region formed in the n-well and a second p-type diffusion region formed in the substrate.

A first wiring layer connected to the first p-type diffusion region and applying a power supply voltage; a second wiring layer connected to the first n-type diffusion region and grounded; and the first p-type diffusion region A third wiring layer connected to the type diffusion region and the first n-type diffusion region and outputting an output voltage may further be provided.

Each of the plurality of input gate electrodes may have a predetermined capacitance, and an output voltage may be output according to a voltage input to each of the plurality of input gate electrodes.

According to an embodiment of the present invention, an electronic circuit including any one of the above neuron CMOS circuits is provided.

According to the present invention, there is provided a neuron CMOS circuit that suppresses threshold fluctuation due to the influence of the capacitance between the floating gate and the substrate and realizes advanced threshold control. The invention also provides an electronic circuit comprising such a neuron CMOS circuit.

(A) is a circuit diagram of a conventional neuron CMOS circuit 900, and (b) is a circuit diagram of an equivalent circuit 990 of the neuron CMOS circuit 900. (A) is a circuit diagram of a neuron CMOS circuit 100 according to an embodiment of the present invention, and (b) is a circuit diagram of an equivalent circuit 190 of the neuron CMOS circuit 100. It is a figure which shows an example of the layout of the neuron CMOS circuit 100 which concerns on one Embodiment of this invention. It is a figure which shows an example of the layout of the neuron CMOS circuit 200 which concerns on one Embodiment of this invention. 2 is a circuit diagram of an equivalent circuit 290 of a neuron CMOS circuit 200 according to an embodiment of the present invention. FIG. It is a figure which shows an example of the layout of the neuron CMOS circuit 300 which concerns on one Embodiment of this invention. 3 is a circuit diagram of an equivalent circuit 390 of the neuron CMOS circuit 300 according to an embodiment of the present invention. FIG. 1 is a circuit diagram of an n-bit flash AD converter 500 according to an embodiment of the present invention. FIG. 2 shows a neuron CMOS circuit νCMOS _{i according} to an embodiment of the present invention and its equivalent circuit. 2 shows a neuron CMOS circuit νCMOS _{j according} to an embodiment of the present invention and its equivalent circuit.

Hereinafter, a neuron CMOS circuit according to the present invention will be described in detail with reference to the drawings. However, the neuron CMOS circuit of the present invention can be implemented in many different modes, and is not construed as being limited to the description of the embodiments and examples shown below. Note that in the drawings referred to in this embodiment mode and examples, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

The present inventor has found that advanced control of the threshold value of the neuron CMOS circuit can be realized by suppressing the influence of the capacitance between the floating gate and the substrate. That is, the present invention realizes advanced control of the threshold value of the neuron CMOS circuit by providing the neuron CMOS circuit with a mechanism for suppressing the fluctuation of the threshold value due to the influence of the capacitance between the floating gate and the substrate. Note that the neuron CMOS circuit according to the present invention is a circuit having n (n is an integer of 2 or more) input gate electrodes in a floating gate. An example in which the input voltage V _INA and the input voltage V _INB are respectively applied from two input gate electrodes will be described.

(Embodiment 1)
FIG. 1A is a circuit diagram of a conventional neuron CMOS circuit 900, and FIG. 1B is a circuit diagram of an equivalent circuit 990 of the neuron CMOS circuit 900. Here, a neuron CMOS circuit 900 provided with two input gate electrodes will be described as an example. C ₁ and C ₂ are capacitances for determining the threshold value of the neuron CMOS circuit 900, and are capacitances between the input gate electrode and the floating gate. An input voltage V _INA and an input voltage V _INB are applied from the input gate electrodes, respectively. Φ is a voltage of the floating gate with respect to the substrate potential, and the capacitance between the floating gate and the substrate is C ₀ . The source of the p-channel neuron MOSFET (hereinafter referred to as PMOS) of the neuron CMOS circuit 900 is applied with the power supply voltage V _DD , and the source of the n-channel MOSFET (hereinafter referred to as NMOS) is grounded. Further, the PMOS and NMOS drains of the neuron CMOS circuit 900 output the output voltage V _OY .

At this time, the voltage Φ of the floating gate of the neuron CMOS circuit 900 is expressed by the following equation (1).

Neuron CMOS circuit 900 outputs power supply voltage V _DD as output voltage V _OY when voltage Φ <threshold voltage V _TH . When voltage Φ ≧ threshold voltage V _TH , the ground voltage (generally 0 V) is output as the output voltage V _OY .

Here, in the neuron CMOS circuit 900, the floating gate-substrate capacitance C ₀ is generated in proportion to the area of the floating gate. As the number of input gate electrodes provided in the floating gate increases, the area of the floating gate also increases, and as a result, the capacitance C ₀ cannot be ignored. For this reason, the threshold value of the neuron CMOS circuit varies under the influence of the capacitance C ₀ . Therefore, a mechanism for suppressing fluctuation due to the influence of the capacitance between the floating gate and the substrate is required.

2A is a circuit diagram of the neuron CMOS circuit 100 according to one embodiment of the present invention, and FIG. 2B is a circuit diagram of an equivalent circuit 190 of the neuron CMOS circuit 100. Neuron CMOS circuit 100, the floating gate - a third input gate electrode having a capacitance equal C ₃ and substrate capacitance C ₀ is provided to the floating gate, the power supply voltage V _DD is applied to the input gate electrode. The other configuration is the same as that of the neuron CMOS circuit 900. The neuron CMOS circuit 100 according to the present embodiment cancels the influence of the capacitance C ₀ by providing the floating gate with a capacitance C ₃ equal to the floating gate-substrate capacitance C _0, and increases the threshold level of the neuron CMOS circuit 100. Can be realized. In the present embodiment, the floating gate - and the capacitance C ₃ between the capacitance C ₀ between the substrates third input gate electrode and the floating gate are equal, indicates that the value of the theoretical equivalent, actual circuit Means that the capacities are approximately equal within an allowable range in the circuit manufacturing process.

Floating gate - by providing the substrate capacitance C ₀ is equal capacitance C _3, floating gate - to be able to cancel the effect of substrate capacitance C _0, it will be described with reference to equations. The voltage Φ of the floating gate of the neuron CMOS circuit 100 is expressed by the following equation (2).

Assuming that the threshold for the floating gate voltage of the neuron CMOS circuit 100 is ½ of the power supply voltage V _DD , the output of the neuron CMOS circuit 100 is as shown in Expression (3).

Substituting C ₀ = C ₃ into equation (3) and rearranging results in equation (4).

From equation (4), it can be seen that the neuron CMOS circuit 100 is not affected by the floating gate-substrate capacitance C ₀ .

FIG. 3 is a diagram illustrating an example of the layout of the neuron CMOS circuit 100. In the neuron CMOS circuit 100, an n-type diffusion region 111 and a p-type diffusion region 113 are formed on a region of the substrate (not shown) where the n-well 101 is formed, and the n-type diffusion region 115 and the p-type diffusion are formed on the substrate. Region 117 is formed. A floating gate 121 is disposed above the p-type diffusion region 113 and the n-type diffusion region 115 via a first insulating layer (not shown). The floating gate 121 is drawn from the region where the p-type diffusion region 113 and the n-type diffusion region 115 are formed, and the input gate electrodes 131, 133, and 135 are disposed through a second insulating layer (not shown). . A third insulating layer (not shown) is formed above the floating gate 121 and the input gate electrodes 131, 133, and 135, and wiring layers 141, 143, 151, 153, and 155 are formed thereon. The Here, the wiring layer 151 is a wiring for applying the power supply voltage V _DD to the neuron CMOS circuit 100, and the wiring layer 153 is a wiring for grounding. The wiring layer 155 is a wiring for outputting the output voltage V _OY of the neuron CMOS circuit 100.

The wiring layer 151 is connected to the n-type diffusion region 111, the p-type diffusion region 113, and the input gate electrode 135 through a contact hole 161. The wiring layer 153 is connected to the n-type diffusion region 115 and the p-type diffusion region 117 through a contact hole 161. The input gate electrode 131 and the wiring layer 141, and the input gate electrode 133 and the wiring layer 143 are connected by a contact hole 161. A wiring layer 155 is disposed in a region of the p-type diffusion region 113 opposite to the region where the wiring layer 151 is disposed with respect to the floating gate 121, and is connected to the p-type diffusion region 113 through a contact hole 161. In addition, a wiring layer 155 is arranged in a region of the n-type diffusion region 115 opposite to the region where the wiring layer 153 is arranged with respect to the floating gate 121, and is connected to the n-type diffusion region 115 through the contact hole 161. .

Neuron CMOS circuit 100, by adjusting the thickness and the area of the input gate electrodes 131 and 133 and 135, capacitor C _1, C ₂ and C ₃ between the input gate electrodes 131, 133 and 135 and the floating gate 121 Can be designed to a desired capacity. As described above, the capacitance C ₃ is designed to be equal to the floating gate-substrate capacitance C ₀ . In the present embodiment, the floating gate to the extent permitted in the manufacturing process of the circuit - to approximately equal the capacity C ₃ between the capacitance C ₀ between the substrates third input gate electrode and the floating gate.

Note that a known material used for manufacturing a semiconductor device can be used for the neuron CMOS circuit 100 according to the present embodiment. A known semiconductor device manufacturing method can be applied to the manufacture of the neuron CMOS circuit 100. Therefore, detailed description of materials and manufacturing methods used for the neuron CMOS circuit 100 is omitted.

As described above, in the neuron CMOS circuit 100 according to the present embodiment, the third input gate electrode having the capacitance C ₃ equal to the floating gate-substrate capacitance C ₀ is arranged in the floating gate, and the third input gate electrode By applying the power supply voltage V _DD to the capacitor, the threshold value fluctuation due to the influence of the capacitance between the floating gate and the substrate is suppressed, and there is an excellent effect that the advanced control of the threshold value of the neuron CMOS circuit 100 can be realized. In the present embodiment, the example in which the input voltage V _INA and the input voltage V _INB are applied from the two input gate electrodes has been described, but the present invention is not limited to this, and the input gate electrode The number can be set arbitrarily.

(Embodiment 2)
In the first embodiment, a third input gate electrode having a capacitance C ₃ equal to the floating gate-substrate capacitance C ₀ is arranged on the floating gate in order to suppress the threshold fluctuation due to the influence of the floating gate-substrate capacitance. In the neuron CMOS circuit 200 according to the present embodiment, a substrate not containing impurities, a substrate having a low impurity concentration, or an insulating substrate is used, and a region where impurities are not diffused as much as possible, specifically, a MOSFET is configured. By disposing the floating gate on the region where impurities are not diffused, except for the part necessary for this, the capacitance between the floating gate and the substrate is negligibly small compared to the capacitance between the input gate and the floating gate. The neuron CMO suppresses the influence of the capacitance between the floating gate and the substrate It will be described circuit.

FIG. 4 is a diagram showing an example of the layout of the neuron CMOS circuit 200 according to an embodiment of the present invention. FIG. 5 is a circuit diagram of an equivalent circuit 290 of the neuron CMOS circuit 200. The neuron CMOS circuit 200 is applicable when a substrate that does not contain impurities, a substrate with a low impurity concentration, or an insulating substrate is used. In the neuron CMOS circuit 200, the same reference numerals are given to the same configurations as those of the neuron CMOS circuit 100.

In the neuron CMOS circuit 200, the floating gate 121 is arranged on a region where impurities are not diffused except for a portion necessary for constituting the MOSFET, that is, so as not to overlap the n well 101 and the p well 203. As a result, the capacitance between the floating gate and the substrate is made negligibly small compared to the capacitance between the input gate and the floating gate. This is why the floating gate-substrate capacitance C ₀ is omitted in the equivalent circuit 290 of the neuron CMOS circuit 200.

In the neuron CMOS circuit 200, an n-type diffusion region 111 and a p-type diffusion region 113 are formed on a region of the substrate (not shown) where the n-well 101 is formed, and on the region where the p-well 203 is formed. An n-type diffusion region 115 and a p-type diffusion region 117 are formed. A floating gate 121 is disposed above the p-type diffusion region 113 and the n-type diffusion region 115 via a first insulating layer (not shown). At this time, the floating gate 121 is arranged so as not to overlap with the n-well 101 and the p-well 203 except for a portion necessary for constituting the MOSFET. The floating gate 121 is drawn from the region where the p-type diffusion region 113 and the n-type diffusion region 115 are formed, and the input gate electrodes 231 and 233 are arranged through a second insulating layer (not shown). A third insulating layer (not shown) is formed above the floating gate 121 and the input gate electrodes 231 and 233, and wiring layers 141, 143, 151, 153, and 155 are formed thereon. Here, the wiring layer 151 is a wiring for applying the power supply voltage V _DD to the neuron CMOS circuit 200, and the wiring layer 153 is a wiring for grounding. The wiring layer 155 is a wiring for outputting the output voltage V _OY of the neuron CMOS circuit 200.

The wiring layer 151 is connected to the n-type diffusion region 111 and the p-type diffusion region 113 through a contact hole 161. The wiring layer 153 is connected to the n-type diffusion region 115 and the p-type diffusion region 117 through a contact hole 161. The input gate electrode 231 and the wiring layer 141, and the input gate electrode 233 and the wiring layer 143 are connected to each other through a contact hole 161. A wiring layer 155 is disposed in a region of the p-type diffusion region 113 opposite to the region where the wiring layer 151 is disposed with respect to the floating gate 121, and is connected to the p-type diffusion region 113 through a contact hole 161. In addition, a wiring layer 155 is arranged in a region of the n-type diffusion region 115 opposite to the region where the wiring layer 153 is arranged with respect to the floating gate 121, and is connected to the n-type diffusion region 115 through the contact hole 161. .

The neuron CMOS circuit 200 can design the capacitances C ₁ and C ₂ between the input gate electrodes 231 and 233 and the floating gate 121 to a desired capacitance by adjusting the areas of the input gate electrodes 231 and 233. .

In the neuron CMOS circuit 200 according to the present embodiment, a known material used for manufacturing a semiconductor device can be used as long as the substrate does not contain impurities, a substrate with low impurity concentration, or an insulating substrate. As the substrate having a low impurity concentration, for example, a p-type silicon substrate having a substrate concentration of 10 ¹⁵ atoms / cm ³ or less can be used. A known semiconductor device manufacturing method can be applied to the manufacture of the neuron CMOS circuit 200. Therefore, detailed description of materials and manufacturing methods used for the neuron CMOS circuit 200 is omitted.

As described above, the neuron CMOS circuit 200 according to the present embodiment uses a substrate that does not contain impurities, a substrate having a low impurity concentration, or an insulating substrate, and constitutes a region where impurities are not diffused as much as possible, specifically, a MOSFET. By designing the floating gate to be disposed on a region where impurities are not diffused, except for the necessary portion, the threshold value variation due to the influence of the capacitance between the floating gate and the substrate can be reduced with only two input gate electrodes. This provides an excellent effect of suppressing and realizing advanced control of the threshold value of the neuron CMOS circuit 200. In the present embodiment, the example in which the input voltage V _INA and the input voltage V _INB are applied from the two input gate electrodes has been described, but the present invention is not limited to this, and the input gate electrode The number can be set arbitrarily.

(Embodiment 3)
In the second embodiment, two input gate electrodes are formed by using a substrate that does not contain impurities, a substrate having a low impurity concentration, or an insulating substrate, and by designing a floating gate to be disposed over a region where impurities are not diffused as much as possible. In the neuron CMOS circuit 300 according to the present embodiment, half the area of the floating gate is designed to overlap with the n well. Thus, a neuron CMOS circuit in which the influence of the capacitance between the floating gate and the substrate is suppressed will be described.

FIG. 6 is a diagram showing an example of the layout of the neuron CMOS circuit 300 according to the embodiment of the present invention. FIG. 7 is a circuit diagram of an equivalent circuit 390 of the neuron CMOS circuit 300. In FIG. 7, a capacitor _CD is a floating gate-power source capacitor. In the neuron CMOS circuit 300, the same reference numerals are given to the same configurations as those of the neuron CMOS circuit 100 and the neuron CMOS circuit 200.

The neuron CMOS circuit 300 forms an n-well 301 on a substrate (not shown) so as to overlap with the half area of the floating gate 121. An n-type diffusion region 311 and a p-type diffusion region 113 are formed on the region where the n-well 301 is formed, and an n-type diffusion region 115 and a p-type diffusion region 317 are formed on the substrate. A floating gate 121 is disposed above the p-type diffusion region 113 and the n-type diffusion region 115 via a first insulating layer (not shown). The floating gate 121 is drawn from the region where the p-type diffusion region 113 and the n-type diffusion region 115 are formed, and the input gate electrodes 231 and 233 are arranged through a second insulating layer (not shown). A third insulating layer (not shown) is formed above the floating gate 121 and the input gate electrodes 231 and 233, and wiring layers 141, 143, 151, 153, and 155 are formed thereon. Here, the wiring layer 151 is a wiring for applying the power supply voltage V _DD to the neuron CMOS circuit 300, and the wiring layer 153 is a wiring for grounding. The wiring layer 155 is a wiring for outputting the output voltage V _OY of the neuron CMOS circuit 300.

The wiring layer 151 is connected to the n-type diffusion region 311 and the p-type diffusion region 113 through a contact hole 161. Further, the wiring layer 153 is connected to the n-type diffusion region 115 and the p-type diffusion region 317 through a contact hole 161. The input gate electrode 231 and the wiring layer 141, and the input gate electrode 233 and the wiring layer 143 are connected to each other through a contact hole 161. A wiring layer 155 is disposed in a region of the p-type diffusion region 113 opposite to the region where the wiring layer 151 is disposed with respect to the floating gate 121, and is connected to the p-type diffusion region 113 through a contact hole 161. In addition, a wiring layer 155 is arranged in a region of the n-type diffusion region 115 opposite to the region where the wiring layer 153 is arranged with respect to the floating gate 121, and is connected to the n-type diffusion region 115 through the contact hole 161. .

The neuron CMOS circuit 300 can design the capacitances C ₁ and C ₂ between the input gate electrodes 231 and 233 and the floating gate 121 to a desired capacitance by adjusting the areas of the input gate electrodes 231 and 233. .

In neurons CMOS circuit 300, by providing the n-well 301 so as to overlap with half of the area of the floating gate 121, the floating gate - substrate capacitance C ₀ and the floating gate - and the power supply capacitance C _D is equal, The fluctuation of the threshold voltage of the neuron CMOS circuit due to the influence of the capacitance of the floating gate 121 on the substrate and the power supply can be suppressed.

This will be explained using mathematical expressions. The voltage Φ of the floating gate of the neuron CMOS circuit 300 is expressed by the following equation (5).

Assuming that the threshold value for the floating gate voltage of the neuron MOS circuit 300 is ½ of the power supply voltage V _DD , the output of the neuron MOS circuit 300 is given by equation (6).

Substituting C ₀ = C _D into equation (6) and rearranging results in equation (7).

From the equation (7), it can be seen that the neuron CMOS circuit 300 according to the present embodiment is not affected by the floating gate-substrate capacitance C ₀ .

Note that a known material used for manufacturing a semiconductor device can be used for the neuron CMOS circuit 300 according to the present embodiment. In addition, a known semiconductor device manufacturing method can be applied to manufacture the neuron CMOS circuit 300. Therefore, detailed description of materials and manufacturing methods used for the neuron CMOS circuit 300 is omitted.

As described above, in the neuron CMOS circuit 300 according to the present embodiment, the n-well is disposed so as to overlap with the area of the half of the floating gate, so that the influence of the capacitance between the floating gate and the substrate can be achieved with only two input gate electrodes. As a result, it is possible to suppress the fluctuation of the threshold value due to the above and to realize an advanced control of the threshold value of the neuron CMOS circuit 300. In the present embodiment, the example using the p substrate has been described. However, even when the n substrate is used, the same effect can be obtained by designing the half area of the floating gate to overlap the p well. Can be obtained. Further, in the present embodiment, an example in which the input voltage V _INA and the input voltage V _INB are applied from two input gate electrodes has been described, but the present invention is not limited to this, and the input gate electrode The number can be set arbitrarily.

As an example of an electronic circuit using the neuron CMOS circuit according to the present invention described above, an n-bit flash AD converter using a circuit equivalent to the neuron CMOS circuit 100 according to an embodiment of the present invention will be described below.

(N-bit flash AD converter)
The n-bit flash AD converter 500 according to this embodiment includes a quantization output unit 530 and an encoding unit 550. FIG. 8 is a circuit diagram of an n-bit flash AD converter 500 according to an embodiment of the present invention. In FIG. 8, N _i (i = 1 to 2 ⁿ⁻¹ −1), N _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1), N _IN1 and N _IN2 are CMOS circuits, and νCMOS _i (i = 1). ˜2 ⁿ⁻¹ −1) and νCMOS _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1) are neuron CMOS circuits. The n-bit flash AD converter 500 includes νCMOS _i (i = 1 to 2 ⁿ⁻¹ −1) and νCMOS _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1), that is, 2 ⁿ −2 pieces. A neuron CMOS circuit and one CMOS circuit N _IN1 are connected to a terminal for inputting an analog input voltage V _IN, and a waveform shaping CMOS circuit is connected in series to each neuron CMOS circuit, and the CMOS circuit N _A CMOS circuit N _IN2 is connected in series to _IN1 .

C _{i, 1} , C _{i, 2} , C _{i, 3} (i = 1 to 2 ⁿ⁻¹ −1) and C _{j, 1} , C _{j, 2} , C _{j, 3} ( j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1) is a coupling capacitance between each input terminal of the neuron CMOS circuit and the floating gate. In the n-bit flash AD converter 500, the capacitance C _i, of the neuron CMOS circuit νCMOS _i (i = 1 to 2 ⁿ⁻¹ −1) and νCMOS _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1) _{. A} power supply voltage V _DD is applied to the gate having ₁ (i = 1 to 2 ⁿ⁻¹ −1) and C _{j, 1} (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1), and the capacitance C _{i, 2} The analog input voltage V _IN is applied to the gate having (i = 1 to 2 ⁿ⁻¹ −1) and C _{j, 2} (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1). The power supply voltage V _DD is applied to the gate having the capacitance C _{i, 3} (i = 1 to 2 ⁿ⁻¹ −1) of νCMOS _i (i = 1 to 2 ⁿ⁻¹ −1), and νCMOS _j (j = gate having ^{2 n-1 + 1~2 n -1} ) capacity C _j, ³ of ^{(j = 2 n-1 +} 1~2 n -1) is grounded. Analog input voltage V _IN is also applied to the CMOS circuit N _IN1 connected in series to the CMOS circuit N _IN2.

The n-bit flash AD converter 500 further includes an encoding unit 550. A circuit for obtaining the AD conversion output V _Oi (i = 1 to n−1) in the case of n bits can be designed by Expression (8).

As described in the above embodiment, the capacitors C _{i, 1} and C _{j, 1} are capacitors for preventing the threshold of the neuron CMOS circuit from fluctuating due to the influence of the capacitance between the floating gate and the substrate. This is the capacitance between the electrode and the floating gate. Therefore, the capacitances C _{i, 1} and C _{j, 1} are the floating gate-substrate capacitances C _{i, 0} (not shown), C _{j, 0} (see FIG. (Not shown). In an actual circuit, this means that the capacitances are approximately equal within a range allowed in the circuit manufacturing process.

また、全てのＣＭＯＳ回路の閾値は電源電圧V_DDの１／２、全てのニューロンＣＭＯＳ回路のフローティングゲートの電圧に対する閾値は電源電圧V_DDの１／２とする。 C _{i, 2} , C _{i, 3} , C _{j, 2} , C _{j, 3} are capacitances for determining the threshold value of the neuron CMOS circuit, and the relations of the following equations (11) to (14) are given respectively. Fulfill. _Cu is a basic capacitance that is optimally set in the design of the semiconductor.

Further, threshold values of all the CMOS circuits 1/2 of the power supply voltage V _DD, the threshold for the floating gate voltage of all neurons CMOS circuit is a half of the power supply voltage V _DD.

9 is a circuit of the i-th (i = 1 to 2 ⁿ⁻¹ −1) neuron CMOS circuit νCMOS _i from the top of FIG. 8 and its equivalent circuit, and FIG. 10 is the j-th (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1) neuron CMOS circuit νCMOS _j and its equivalent circuit. 9 and 10, C _{i, 0} and C _{j, 0} are floating gate-substrate capacitances, and Φ _i and Φ _j are floating gate voltages based on the substrate potential. The voltages Φ _i and Φ _j of the floating gate are as shown in the following expressions (15) and (16).

Neuron CMOS circuit is a device that outputs 0V, the power supply voltage V _DD in the case of less than V _DD / 2 when the voltage of the floating gate is 1/2 or more of the power supply voltage V _DD. The voltage obtained by inverting the output of the neuron CMOS circuit νCMOS _i (i = 1 to 2 ⁿ⁻¹ −1) by the circuit N _i (i = 1 to 2 ⁿ⁻¹ −1) is the quantized output voltage V _i (i = 1). ˜2 ⁿ⁻¹ −1), and the output of the neuron CMOS circuit νCMOS _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1) is the CMOS circuit N _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1). ) Is the quantized output voltage V _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1). Therefore, the quantized output voltages V _i (i = 1 to 2 ⁿ −1) and V _j (j = 2 ⁿ⁻¹ +1 to 2 ⁿ −1) are expressed by the equations (17) and (18). .

When Expression (9), Expression (11), and Expression (12) are substituted into Expression (17) and rearranged, Expression (19) is obtained. Further, when Expression (10), Expression (13), and Expression (14) are substituted into Expression (18) and rearranged, Expression (20) is obtained.

As described above, the n-bit flash AD converter 500 according to the present embodiment uses a neuron CMOS circuit having a smaller circuit size and lower power consumption than a comparator as an element for comparing voltages, and therefore, a conventional flash type. A flash AD converter that consumes less power than an AD converter can be realized.

In this embodiment, an example using a circuit equivalent to the neuron CMOS circuit 100 has been described. However, the n-bit flash AD converter 500 according to this embodiment includes the neuron CMOS circuit 200 or the neuron CMOS circuit 300. It can also be used. In this embodiment, an n-bit flash AD converter has been described as an example. However, the neuron CMOS circuit according to the present invention can be applied to various electronic circuits.

100: neuron CMOS circuit, 101: n-well, 111: n-type diffusion region, 113: p-type diffusion region, 115: n-type diffusion region, 117: p-type diffusion region, 121: floating gate, 131: input gate electrode, 133: input gate electrode, 135: input gate electrode, 141: wiring layer, 143: wiring layer, 151: wiring layer, 153: wiring layer, 155: wiring layer, 190: equivalent circuit of neuron CMOS circuit 100, 200: neuron CMOS circuit, 203: p-well, 231: input gate electrode, 233: input gate electrode, 290: equivalent circuit of neuron CMOS circuit 200, 300: neuron CMOS circuit, 301: n-well, 311: n-type diffusion region, 317: p-type diffusion region, 390: equivalent circuit of neuron CMOS circuit 300, 500: n Tsu Preparative flash type AD converter, 530: quantized output unit, 550: Encoding unit

Claims (13)

Formed on a substrate, constituting a CMOS circuit, having a common floating gate and a plurality of input gates and a PMOSFET and an NMOSFET;
A neuron CMOS circuit wherein a capacitance between the common floating gate and the substrate is substantially equal to a capacitance between one input gate electrode of the plurality of input gates and the common floating gate. . The plurality of input gate electrodes each have a predetermined capacitance with the common floating gate,
2. The neuron CMOS circuit according to claim 1, wherein an output voltage is output in accordance with a voltage input to each of the plurality of input gate electrodes. 3. The neuron CMOS circuit according to claim 1, wherein a power supply voltage is applied to a source of the PMOSFET and the one input gate electrode. A substrate,
An n-well formed on the substrate;
A first p-type diffusion region formed in the n-well;
A first n-type diffusion region formed in the substrate;
A floating gate disposed over the first p-type diffusion region and the first n-type diffusion region;
A plurality of input gate electrodes disposed on the floating gate, and
A neuron CMOS circuit, wherein a capacitance between the floating gate and the substrate is substantially equal to a capacitance between one input gate electrode of the plurality of input gates and the floating gate. A first wiring layer connected to the first p-type diffusion region and the one input gate electrode and applying a power supply voltage;
A second wiring layer connected to the first n-type diffusion region and grounded;
A third wiring layer connected to the first p-type diffusion region and the first n-type diffusion region and outputting an output voltage;
The neuron CMOS circuit according to claim 4, further comprising: A substrate,
An n-well and a p-well formed on the substrate;
A first p-type diffusion region formed in the n-well;
A first n-type diffusion region formed in the p-well;
A floating gate disposed over the first p-type diffusion region and the first n-type diffusion region;
A neuron CMOS circuit comprising a plurality of input gate electrodes disposed on the floating gate. 7. The neuron CMOS circuit according to claim 6, wherein the substrate is a substrate not containing impurities, a substrate having a low impurity concentration, or an insulating substrate. A second n-type diffusion region formed in the n-well;
A second p-type diffusion region formed in the p-well;
The neuron CMOS circuit according to claim 6, further comprising: A substrate,
An n-well formed on the substrate;
A first p-type diffusion region formed in the n-well;
A first n-type diffusion region formed in the substrate;
A floating gate disposed over the first p-type diffusion region and the first n-type diffusion region;
A plurality of input gate electrodes disposed on the floating gate, and
The neuron CMOS circuit, wherein the n-well is arranged so as to overlap an area of half of the floating gate. A second n-type diffusion region formed in the n-well;
A second p-type diffusion region formed in the substrate;
The neuron CMOS circuit according to claim 9, further comprising: A first wiring layer connected to the first p-type diffusion region and applying a power supply voltage;
A second wiring layer connected to the first n-type diffusion region and grounded;
A third wiring layer connected to the first p-type diffusion region and the first n-type diffusion region and outputting an output voltage;
The neuron CMOS circuit according to claim 6, further comprising: Each of the plurality of input gate electrodes has a predetermined capacitance;
The neuron CMOS circuit according to claim 4, wherein an output voltage is output in accordance with a voltage input to each of the plurality of input gate electrodes. An electronic circuit comprising the neuron CMOS circuit according to any one of claims 1 to 12.

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