JP2013034359A - Control circuit for controlling power conversion circuit and grid-connection inverter system having the control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control circuit capable of reducing switching loss by periodically stopping switching of switching elements and capable of reducing the difference between the time in which switching elements at a positive electrode side are in an on-state and the time in which switching elements at a negative electrode side are in the on-state.SOLUTION: A control circuit includes: command-value signal generating means for generating command-value signals Xu1, Xv1, and Xw1 from line-voltage command-value signals Xuv, Xvw, and Xwu; and PWM signal generating means for generating PWM signals on the basis of the command-value signals Xu1, Xv1, and Xw1. The command-value signals Xu1, Xv1, and Xw1 are continuously at "0" for a predetermined period, and are continuously at "2" for another predetermined period. As a result, the difference is reduced between the period in which the PWM signals are at a low level and the period in which the signals are at a high level.

Description

  The present invention relates to a control circuit for controlling a power conversion circuit with a PWM signal, a grid-connected inverter system including the control circuit, a program for realizing the control circuit, and a recording medium on which the program is recorded.

  In recent years, distributed power sources using natural energy such as sunlight have been in widespread use. A grid-connected inverter system has been developed that includes an inverter circuit that converts DC power generated by this distributed power source into AC power, and supplies the converted AC power to a connected load or power system.

  FIG. 31 is a block diagram for explaining a general grid-connected inverter system A ′ for supplying power to a three-phase power system B (hereinafter abbreviated as “system B”).

  The grid interconnection inverter system A ′ includes a DC power supply 100, an inverter circuit 200, a filter circuit 300, a transformer circuit 400, and a control circuit 500. The inverter circuit 200 is a three-phase full-bridge inverter, and converts a DC voltage input from the DC power supply 100 into an AC voltage by switching between the ON state and the OFF state of the six switching elements. The control circuit 500 generates a PWM signal for controlling the inverter circuit 200 based on signals input from various sensors. Inverter circuit 200 switches between an on state and an off state of the switching element based on the PWM signal input from control circuit 500. This switching is hereinafter referred to as “switching”. The filter circuit 300 removes high-frequency components due to switching from the AC voltage input from the inverter circuit 200. The transformer circuit 400 boosts or steps down the AC voltage input from the filter circuit 300 to substantially the same level as the system voltage of the system B.

  The power consumed by the switching of the switching element is called switching loss, and reduces the power conversion efficiency of the inverter circuit 200. In order to improve power conversion efficiency, a method for reducing switching loss has been developed. For example, a method of reducing a switching loss by providing a period in which no pulse is periodically generated in a PWM signal and periodically stopping switching by this period has been developed.

  In this method, the neutral point potential of the three phases is changed every 1/3 period, and the potential of each phase is fixed to the negative side potential by 1/3 period, so that the switching of each phase is fixed to the negative side potential. The control is to stop for a specified period, which is called NVS (Neutral Voltage Shift) control. Since NVS control can reduce the number of switching times, switching loss can be reduced. In this specification, each of the three phases is designated as a U phase, a V phase, and a W phase, the phase of the V phase system voltage is delayed by 2π / 3 from the U phase, and the phase of the W phase system voltage is from the U phase. It is assumed that it is delayed by 4π / 3 (2π / 3 advanced).

  Specifically, the NVS control generates a command value signal (hereinafter referred to as “NVS command value signal”) having a special waveform in which 1/3 of the cycle is “0”, and the NVS command value signal. This is done by controlling the inverter circuit 200 with the PWM signal generated based on the above. The NVS command value signal includes a line voltage command value signal for commanding the waveform of the output line voltage of the grid interconnection inverter system A ′, a signal obtained by inverting the polarity of the line voltage command value signal, a value Is generated by switching to a zero signal whose “0” is “0”. The line voltage command value signal is generated by the difference between the phase voltage command value signals for commanding the waveform of the output phase voltage of the grid interconnection inverter system A '.

  FIG. 32 is a diagram for explaining the waveform of the NVS command value signal.

  A waveform Xuv shown in FIG. 5A is a waveform of the line voltage command value signal Xuv for commanding the waveform of the U-phase line voltage with respect to the V phase. The line voltage command value signal Xuv is a difference signal between the phase voltage command value signal Xu for commanding the waveform of the U-phase phase voltage and the phase voltage command value signal Xv for commanding the waveform of the V-phase phase voltage. It is. Since the amplitude of the phase voltage command value signal Xu is set to “1”, the amplitude of the line voltage command value signal Xuv is √ (3). The waveform Xvw is a waveform of the line voltage command value signal Xvw for commanding the waveform of the V phase line voltage with respect to the W phase. The line voltage command value signal Xvw is a difference signal between the phase voltage command value signal Xv for commanding the waveform of the V-phase voltage and the phase voltage command value signal Xw for commanding the waveform of the W-phase voltage. It is. The waveform Xwu is a waveform of the line voltage command value signal Xwu for commanding the waveform of the W phase line voltage with respect to the U phase. The line voltage command value signal Xwu is a difference signal between the phase voltage command value signal Xw for commanding the waveform of the W phase voltage and the phase voltage command value signal Xu for commanding the waveform of the U phase voltage. It is. In the figure, the phase of the U-phase phase voltage command value signal Xu is described as a reference.

  A waveform Xvu shown in FIG. 5B is a waveform of the signal Xvu obtained by inverting the polarity of the line voltage command value signal Xuv. The waveform Xwv is the waveform of the signal Xwv obtained by inverting the polarity of the line voltage command value signal Xvw, and the waveform Xuw is the waveform of the signal Xuw obtained by inverting the polarity of the line voltage command value signal Xwu.

  A waveform Xu ′ shown in FIG. 5C is a waveform of the U-phase NVS command value signal Xu ′. The NVS command value signal Xu ′ is generated by switching between the line voltage command value signal Xuv, the signal Xvu, and the zero signal. The waveform Xu ′ becomes the waveform Xuv during the period of −π / 6 ≦ θ ≦ π / 2 (= 3π / 6), and becomes the waveform Xuw during the period of 3π / 6 ≦ θ ≦ 7π / 6, and 7π / 6 ≦ θ ≦. The period of 11π / 6 is “0”. Note that the phase of the phase voltage command value signal Xu is θ. Similarly, the waveform Xv ′, which is the waveform of the V-phase NVS command value signal Xv ′, is “0” during the period −π / 6 ≦ θ ≦ π / 2 (= 3π / 6), and 3π / 6 ≦ θ. A period of ≦ 7π / 6 has a waveform Xvw, and a period of 7π / 6 ≦ θ ≦ 11π / 6 has a waveform Xvu. The waveform Xw ′, which is the waveform of the W-phase NVS command value signal Xw ′, has a waveform Xwv during the period −π / 6 ≦ θ ≦ π / 2 (= 3π / 6), and 3π / 6 ≦ θ ≦ 7π. The period of / 6 is “0”, and the period of 7π / 6 ≦ θ ≦ 11π / 6 is the waveform Xwu. The waveform of the difference signal between the NVS command value signals Xu ′ and Xv ′ is the same as the waveform Xuv of the line voltage command value signal Xuv (see (a) in the figure). Therefore, the grid interconnection inverter system A ′ can output a line voltage having the same waveform as the line voltage command value signal Xuv.

  The PWM signal for controlling the inverter circuit 200 is generated by comparing the NVS command value signals Xu ′, Xv ′, and Xw ′ with the carrier signals.

  FIG. 33 is a diagram for explaining a method of generating a U-phase PWM signal from the NVS command value signal Xu ′ and the carrier signal. In the figure, the NVS command value signal Xu ′ is indicated by a waveform X, and the carrier signal is indicated by a waveform C. The PWM signal is generated as a pulse signal that becomes high level when the NVS command value signal Xu ′ is larger than the carrier signal and becomes low level when the NVS command value signal Xu ′ is equal to or lower than the carrier signal. A waveform P1 shown in the figure is a waveform of a U-phase PWM signal generated from the NVS command value signal Xu ′ and the carrier signal. The waveform P1 is at a high level during a period when the waveform X is greater than the waveform C, and the waveform P1 is at a low level during a period when the waveform X is equal to or less than the waveform C. The U-phase PWM signal is input to a switching element on the positive side of the U-phase to control switching. On the other hand, a PWM signal obtained by inverting the U-phase PWM signal (see the waveform P4 shown in the figure) is input to the switching element on the negative side of the U-phase to control switching. The V-phase and W-phase PWM signals are generated in the same manner.

  As indicated by the waveform P1 in the figure, the U-phase PWM signal (waveform P1) continues to be at a low level during the period when the NVS command value signal Xu ′ (waveform X) is “0”. The device switching stops. Therefore, since the number of times of switching of the switching element is reduced to 2/3, switching loss can be reduced.

JP 2010-136547 A

  However, in the case of the above-described method, there is a problem in that the on-state time differs between the positive-side switching element and the negative-side switching element. That is, during the period when the NVS command value signal Xu ′ (waveform X) is “0”, the PWM signal (waveform P1) input to the positive-side switching element continues to be at a low level. Fixed to the off state. On the other hand, since the PWM signal (waveform P4) input to the negative-side switching element continues to be at a high level, the negative-side switching element is fixed to the on state. Therefore, the time for which the switching element on the positive electrode side is turned off becomes longer, and the time for which the switching element on the negative electrode side is turned on becomes longer. The switching element deteriorates due to heat generated by the flow of current. The switching element on the negative electrode side is longer in the ON state and the time for current to flow is increased, so that the deterioration proceeds more than the switching element on the positive electrode side. Therefore, the switching element on the negative electrode side has a shorter lifetime than the switching element on the positive electrode side. Further, since the heat generated from the switching element on the negative electrode side is further radiated, the design of the cooling member becomes complicated.

  The present invention has been conceived under the circumstances described above, and can periodically stop switching of the switching element to reduce the switching loss, and the positive side switching element is turned on. It is an object of the present invention to provide a control circuit that can reduce the difference between the time during which the switching element is on and the time during which the switching element on the negative electrode side is on.

  In order to solve the above problems, the present invention takes the following technical means.

  A control circuit provided by the first aspect of the present invention is a control circuit that controls driving of a plurality of switching means in a power conversion circuit related to three-phase AC power by a PWM signal, the output of the power conversion circuit or The PWM signal is generated and output so that the waveform of the input AC phase voltage has a waveform in which the predetermined lower limit voltage value is continued in a predetermined period and the predetermined upper limit voltage value is continued in another predetermined period. It is characterized by doing.

  In a preferred embodiment of the present invention, the predetermined period and the other predetermined period are each 1/6 period.

  In a preferred embodiment of the present invention, a first command in which a waveform of one cycle is a waveform having a predetermined upper limit value in a 1/6 period and a predetermined lower limit value in another 1/6 period. A value signal, a second command value signal whose phase is delayed by 2π / 3 with respect to the first command value signal, and a third whose phase is delayed by 4π / 3 with respect to the first command value signal. Command value signal generating means for generating the command value signal, and PWM signal generating means for generating a PWM signal based on each command value signal.

  In a preferred embodiment of the present invention, the first command value signal has a one-cycle waveform of “0” in a 1/6 period and a phase of 5π / 3 in a subsequent 1/6 period. Is a waveform obtained by shifting the waveform of the sine wave in the interval from 2 to 2π upward by a predetermined value, and is a waveform of the sine wave in the interval from π / 3 to 2π / 3 in the subsequent 1/6 period. It is the predetermined value in a period of 1/6, and is a sine wave waveform with a phase of 2π / 3 to π in the subsequent 1/6 period, and the phase is 4π / 3 in the subsequent 1/6 period. Is a waveform obtained by shifting the sine wave waveform in the interval of 5π / 3 upward by the predetermined value.

In a preferred embodiment of the present invention, the command value signal generating means includes three phase voltage command value signals generated for commanding the waveforms of the three-phase phase voltages output from the power conversion circuit, and The first to third command value signals are generated by the following method using three line voltage command value signals that are differential signals of the phase voltage command value signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xuv is greater than the absolute value of Xvw and the absolute value of Xwu, and Xu is a positive value, the first command value signal Xu1 is set to Xuv, and the second command value signal Xv1 is set to “0”, and the third command value signal Xw1 is set to a negative value of Xvw.
(C) When the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xu is a negative value, Xu1 is the value obtained by adding Xuv to the predetermined value, and Xv1 is the predetermined value. , Xw1 is a value obtained by subtracting Xvw from the predetermined value.
(D) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a positive value, Xu1 is set to a negative value of Xwu, Xv1 is set to Xvw, and Xw1 is set to “0”. To do.
(E) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a negative value, Xu1 is set to a value obtained by subtracting Xwu from the predetermined value, and Xv1 is set to the predetermined value. A value obtained by adding Xvw is used, and Xw1 is used as the predetermined value.
(F) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a positive value, Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu. To do.
(G) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a negative value, Xu1 is the predetermined value, and Xv1 is a value obtained by subtracting Xuv from the predetermined value. , Xw1 is a value obtained by adding Xwu to the predetermined value.

  In a preferred embodiment of the present invention, the first command value signal has a one-cycle waveform of “0” in a 1/6 period and a phase of 4π / 3 in a subsequent 1/6 period. Is a waveform obtained by shifting the sine wave waveform in the interval from 5 to π / 3 upward by a predetermined value, and is a sine wave waveform in the interval from 0 to π / 3 in the subsequent 1/6 period. It is the predetermined value in a period of 1/6, and in the subsequent 1/6 period, it is a sine wave waveform with a phase of π / 3 to 2π / 3, and in the subsequent 1/6 period, the phase is π To a 4π / 3 interval, the waveform of the sine wave is shifted upward by the predetermined value.

In a preferred embodiment of the present invention, the command value signal generating means includes three phase voltage command value signals generated for commanding the waveforms of the three-phase phase voltages output from the power conversion circuit, and The first to third command value signals are generated by the following method using three line voltage command value signals that are differential signals of the phase voltage command value signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xu is a positive value, the first command value signal Xu2 is set as the predetermined value, and the second command The value signal Xv2 is a value obtained by subtracting Xuv from the predetermined value, and the third command value signal Xw2 is a value obtained by adding Xwu to the predetermined value.
(C) When the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xu is a negative value, Xu2 is set to “0”, Xv2 is set to a negative value of Xuv, and Xw2 is set to Xwu. To do.
(D) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a positive value, Xu2 is the value obtained by adding Xuv to the predetermined value, and Xv2 is the predetermined value. , Xw2 is a value obtained by subtracting Xvw from the predetermined value.
(E) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a negative value, Xu2 is set to Xuv, Xv2 is set to “0”, Xw2 is set to a negative value of Xvw, To do.
(F) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a positive value, Xu2 is set to a value obtained by subtracting Xwu from the predetermined value, and Xv2 is set to the predetermined value. A value obtained by adding Xvw is used, and Xw2 is set as the predetermined value.
(G) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a negative value, Xu2 is set to a negative value of Xwu, Xv2 is set to Xvw, and Xw2 is set to “0”. To do.

  In a preferred embodiment of the present invention, the first command value signal has a one-cycle waveform of “0” in a 1/6 period, and a phase of 3π / 2 in a subsequent 1/6 period. Is a waveform obtained by shifting the waveform of the sine wave in the interval from 11 to 11π / 6 upward by a predetermined value, and is the waveform of the sine wave in the interval from π / 6 to π / 2 in the subsequent 1/6 period. In the following 1/6 period, the predetermined value is obtained, and in the subsequent 1/6 period, the phase is a sine wave waveform in the interval from π / 2 to 5π / 6, and in the subsequent 1/6 period, the phase Is a waveform obtained by shifting the waveform of the sine wave in the section from 7π / 6 to 3π / 2 upward by the predetermined value.

In a preferred embodiment of the present invention, the command value signal generating means includes three phase voltage command value signals generated for commanding the waveforms of the three-phase phase voltages output from the power conversion circuit, and The first to third command value signals are generated by the following method using three line voltage command value signals that are differential signals of the phase voltage command value signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xu is greater than the absolute value of Xv and the absolute value of Xw, and Xu is a positive value, the first command value signal Xu3 is set as the predetermined value, and the second command The value signal Xv3 is set to a value obtained by subtracting Xuv from the predetermined value, and the third command value signal Xw3 is set to a value obtained by adding Xwu to the predetermined value.
(C) When the absolute value of Xu is larger than the absolute value of Xv and the absolute value of Xw, and Xu is a negative value, Xu3 is set to “0”, Xv3 is set to a negative value of Xuv, and Xw3 is set to Xwu. To do.
(D) When the absolute value of Xv is larger than the absolute value of Xu and the absolute value of Xw, and Xv is a positive value, Xu3 is set to a value obtained by adding Xuv to the predetermined value, and Xv3 is set to the predetermined value. , Xw3 is a value obtained by subtracting Xvw from the predetermined value.
(E) When the absolute value of Xv is larger than the absolute value of Xu and the absolute value of Xw, and Xv is a negative value, Xu3 is set to Xuv, Xv3 is set to “0”, and Xw3 is set to a negative value of Xvw. To do.
(F) When the absolute value of Xw is larger than the absolute value of Xu and the absolute value of Xv, and Xw is a positive value, Xu3 is set to a value obtained by subtracting Xwu from the predetermined value, and Xv3 is set to the predetermined value. A value obtained by adding Xvw is used, and Xw3 is used as the predetermined value.
(G) When the absolute value of Xw is larger than the absolute value of Xu and the absolute value of Xv, and Xw is a negative value, Xu3 is set to a negative value of Xwu, Xv3 is set to Xvw, and Xw3 is set to “0”. To do.

  In a preferred embodiment of the present invention, the waveform of the output or input AC phase voltage of the power conversion circuit continues the predetermined upper limit voltage value in a period of 1/12 of one cycle, and the other 1/12 The predetermined lower limit voltage value is continued during the period, the upper limit voltage value is continued during another 1/12 period, and the lower limit voltage value is continued during another 1/12 period. In addition, the PWM signal is generated and output.

  In a preferred embodiment of the present invention, a waveform of one cycle is “0” in a period of 1/12, and a waveform of a sine wave having a phase of 0 to π / 6 in a subsequent period of 1/12. In the subsequent period of 1/12, the waveform is a waveform obtained by shifting the waveform of the sine wave having a phase of 11π / 6 to 2π upward by a predetermined value, and is the predetermined value in the subsequent period of 1/12. A sine wave having a phase of π / 2 to 2π / 3 in the subsequent 1/12 period, and a sine wave having a phase of π / 3 to π / 2 in the subsequent 1/12 period A waveform obtained by shifting the waveform of the sine wave in the interval of π to 7π / 6 upward by a predetermined value in the subsequent 1/12 period. In the following 1/12 period, the phase is a sine wave waveform in the interval from 5π / 6 to π, and the following 1/12 period Is a waveform obtained by shifting the waveform of the sine wave in the interval of 3π / 2 to 5π / 3 upward by a predetermined value in the subsequent 1/12 period, A first command value signal having a waveform obtained by shifting the waveform of a sine wave in a period of 4π / 3 to 3π / 2 upward by a predetermined value in a period, and a phase with respect to the first command value signal Command value signal generating means for generating a second command value signal delayed by 2π / 3 and a third command value signal delayed in phase by 4π / 3 with respect to the first command value signal; PWM signal generating means for generating a PWM signal based on each command value signal.

In a preferred embodiment of the present invention, the command value signal generating means includes three phase voltage command value signals generated for commanding the waveforms of the three-phase phase voltages output from the power conversion circuit, and The first to third command value signals are generated by the following method using three line voltage command value signals that are differential signals of the phase voltage command value signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xu is a magnitude between the absolute value of Xv and the absolute value of Xw, and Xu is a positive value, the first command value signal Xu4 is set as the predetermined value, The second command value signal Xv4 is a value obtained by subtracting Xuv from the predetermined value, and the third command value signal Xw4 is a value obtained by adding Xwu to the predetermined value.
(C) When the absolute value of Xu is a magnitude between the absolute value of Xv and the absolute value of Xw, and Xu is a negative value, Xu4 is set to “0”, and Xv4 is set to a negative value of Xuv. , Xw4 is Xwu.
(D) When the absolute value of Xv is a magnitude between the absolute value of Xu and the absolute value of Xw, and Xv is a positive value, Xu4 is set to a value obtained by adding Xuv to the predetermined value, and Xv4 Is the predetermined value, and Xw4 is a value obtained by subtracting Xvw from the predetermined value.
(E) When the absolute value of Xv is a magnitude between the absolute value of Xu and the absolute value of Xw, and Xv is a negative value, Xu4 is set to Xuv, Xv4 is set to “0”, and Xw4 is set to Let Xvw be a negative value.
(F) When the absolute value of Xw is a magnitude between the absolute value of Xu and the absolute value of Xv, and Xw is a positive value, Xu4 is a value obtained by subtracting Xwu from the predetermined value, and Xv4 Is a value obtained by adding Xvw to the predetermined value, and Xw4 is the predetermined value.
(G) When the absolute value of Xw is a magnitude between the absolute value of Xu and the absolute value of Xv, and Xw is a negative value, Xu4 is set to a negative value of Xwu, Xv4 is set to Xvw, and Xw4 Is “0”.

  In a preferred embodiment of the present invention, a first command value signal obtained by combining the first signal and the second signal, a signal whose phase is delayed by 2π / 3 with respect to the first signal, A second command value signal combining a signal delayed in phase by 2π / 3 relative to the second signal, a signal delayed in phase by 4π / 3 relative to the first signal, and the second signal Command value signal generating means for generating a third command value signal obtained by combining a signal whose phase is delayed by 4π / 3 with respect to the signal, and PWM signal generation for generating a PWM signal based on each command value signal The first signal is a sine in which the waveform of one cycle is “0” in the period of 1/3, and the phase is in the range of 0 to 2π / 3 in the subsequent period of 1/3. It is a waveform of a wave, and in the remaining 1/3 period, it is a waveform of a sine wave with a phase of π / 3 to π. In the second signal, the waveform of one cycle has a predetermined value in a period of 1/3, and the waveform of a sine wave in the interval of π to 5π / 3 in the subsequent 1/3 period is the predetermined signal. This is a waveform shifted upward by a value, and a waveform obtained by shifting the waveform of a sine wave in the interval of 4π / 3 to 2π upward by the predetermined value in the remaining 1/3 period.

  In a preferred embodiment of the present invention, the command value signal generating means generates a flag signal that repeats a high level and a low level at a predetermined cycle, and the first signal and the first signal are generated based on the flag signal. The first command value signal is generated by switching between two signals.

In a preferred embodiment of the present invention, the command value signal generation means includes three phase voltage command value signals generated for commanding the waveforms of the three-phase phase voltages output from the power conversion circuit. Using the three line voltage command value signals, which are differential signals, and the flag signal, the first to third command value signals are generated by the following method.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B1) When the flag signal is at a low level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, the first command value signal Xu5 is set to Xuv. The second command value signal Xv5 is set to “0”, and the third command value signal Xw5 is set to a negative value of Xvw.
(C1) When the flag signal is at a low level and the absolute value of Xuv is greater than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, Xu5 is set to “0” and Xv5 is set to Xuv Let it be a negative value, and let Xw5 be Xwu.
(D1) When the flag signal is at a low level and the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, Xu5 is set to a negative value of Xwu, and Xv5 is set to Xvw And Xw5 is set to “0”.
(E1) When the flag signal is at a low level and the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu5 is set to Xuv and Xv5 is set to “0”. , Xw5 is a negative value of Xvw.
(F1) When the flag signal is at a low level and the absolute value of Xwu is larger than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu5 is set to “0” and Xv5 is set to Xuv Let it be a negative value, and let Xw5 be Xwu.
(G1) When the flag signal is at a low level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu5 is set to a negative value of Xwu, and Xv5 is set to Xvw And Xw5 is set to “0”.
(B2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, Xu5 is set as the predetermined value, and Xv5 is set as the predetermined value. Xuv is subtracted from the value, and Xw5 is the value obtained by adding Xwu to the predetermined value.
(C2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, a value obtained by adding Xuv to the predetermined value and Xuv Xv5 is the predetermined value, and Xw5 is a value obtained by subtracting Xvw from the predetermined value.
(D2) When the flag signal is at a high level, the absolute value of Xvw is greater than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, Xu5 is a value obtained by adding Xuv to the predetermined value Xv5 is the predetermined value, and Xw5 is a value obtained by subtracting Xvw from the predetermined value.
(E2) When the flag signal is at a high level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu5 is a value obtained by subtracting Xwu from the predetermined value Xv5 is a value obtained by adding Xvw to the predetermined value, and Xw5 is the predetermined value.
(F2) When the flag signal is at a high level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu5 is obtained by subtracting Xwu from the predetermined value Xv5 is a value obtained by adding Xvw to the predetermined value, and Xw5 is the predetermined value.
(G2) When the flag signal is at a high level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu5 is set as the predetermined value, and Xv5 is set as the predetermined value. Xuv is subtracted from the value, and Xw5 is the value obtained by adding Xwu to the predetermined value.

  In a preferred embodiment of the present invention, the cycle of the flag signal is an even multiple of the cycle of the phase voltage command value signal.

  In a preferred embodiment of the present invention, the frequency of the flag signal is a multiple of 3/4 of the frequency of the phase voltage command value signal.

  In a preferred embodiment of the present invention, the flag signal has the same length of the high level period and the low level period.

  In a preferred embodiment of the present invention, the PWM signal generating means generates the PWM signal by comparing the three command value signals with predetermined carrier signals, respectively.

  In a preferred embodiment of the present invention, the carrier signal is a signal that changes between a predetermined value of the command value signal to be compared and “0”.

  The grid-connected inverter system provided by the second aspect of the present invention includes an inverter circuit and a control circuit provided by the first aspect of the present invention that controls the inverter circuit. And

  A program provided by the third aspect of the present invention causes a computer to function as a control circuit provided by the first aspect of the present invention.

  The recording medium provided by the fourth aspect of the present invention is a computer-readable recording medium that records the program provided by the third aspect of the present invention.

  According to the present invention, the PWM signal input to the power conversion circuit continues to be at a low level for a predetermined period, and continues to be at a high level for another predetermined period. Therefore, the switching means of the power conversion circuit stops switching during these periods. Thereby, the frequency | count of switching can be reduced and a switching loss can be reduced. In addition, since the PWM signal has both a low-level duration and a high-level duration, the positive-side switching element is on and the negative-side switching element is on. A period of time during which the condition continues. Therefore, compared to the case where only one of the positive-side switching element and the negative-side switching element continues to be in the on state, the time during which the positive-side switching element is on and the negative-side switching element is on. The difference from the time in the state can be reduced. Thereby, the unbalance of the progress of deterioration can be suppressed between the switching element on the positive electrode side and the switching element on the negative electrode side. In addition, the complexity of the design of the cooling member can be alleviated.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a figure for demonstrating the phase voltage signal and line voltage signal of each phase of a three-phase alternating current of a three-phase equilibrium state by a vector. It is a figure for demonstrating the concept of NVS control by a vector. It is a figure for demonstrating the concept of the control which concerns on 1st Embodiment with a vector. It is a figure for demonstrating the waveform of the command value signal which concerns on 1st Embodiment. It is a block diagram for demonstrating the grid connection inverter system provided with the control circuit which concerns on 1st Embodiment. It is a circuit diagram for demonstrating the internal structure of an inverter circuit. It is a block diagram for demonstrating the internal structure of a control circuit. It is a flowchart for demonstrating the command value signal generation process which concerns on 1st Embodiment. It is a flowchart for demonstrating other command value signal generation processing. It is a figure for demonstrating the method to produce | generate a PWM signal from a command value signal and a carrier signal. It is a figure for demonstrating the concept of the control which concerns on 2nd Embodiment with a vector. It is a flowchart for demonstrating the command value signal generation process which concerns on 2nd Embodiment. It is a figure for demonstrating the waveform of the command value signal which concerns on 2nd Embodiment. It is a figure for demonstrating the concept of the control which concerns on 3rd Embodiment with a vector. It is a flowchart for demonstrating the command value signal generation process which concerns on 3rd Embodiment. It is a figure for demonstrating the waveform of the command value signal which concerns on 3rd Embodiment. It is a figure for demonstrating the concept of the control which concerns on 4th Embodiment with a vector. It is a figure for demonstrating the concept of the control which concerns on 4th Embodiment with a vector. It is a flowchart for demonstrating the command value signal generation process which concerns on 4th Embodiment. It is a figure for demonstrating the waveform of the command value signal which concerns on 4th Embodiment. It is a block diagram for demonstrating the internal structure of the command value signal generation part which concerns on 5th Embodiment. It is a figure for demonstrating the concept of the control which concerns on 5th Embodiment with a vector. It is a figure for demonstrating the waveform of the command value signal which concerns on 5th Embodiment. It is a figure for demonstrating the waveform of the command value signal which concerns on 5th Embodiment. It is a flowchart for demonstrating the command value signal generation process which concerns on 5th Embodiment. It is a figure for demonstrating the simulation result of the command value signal which concerns on 5th Embodiment. It is a figure for demonstrating the simulation result of the command value signal which concerns on 5th Embodiment. It is a figure for demonstrating the simulation result of the command value signal which concerns on 5th Embodiment. It is a figure for demonstrating the simulation result of the command value signal which concerns on 5th Embodiment. It is a figure for demonstrating the simulation result of the command value signal which concerns on 5th Embodiment. It is a block diagram for demonstrating a general grid connection inverter system. It is a figure for demonstrating the waveform of a NVS command value signal. It is a figure for demonstrating the method to produce | generate a PWM signal from a NVS command value signal and a carrier signal.

  Hereinafter, the first embodiment of the present invention will be specifically described with reference to the drawings, taking as an example the case where the control circuit according to the present invention is used in a grid-connected inverter system.

  First, the basic concept of the present invention will be described.

  FIG. 1 is a diagram for describing a phase voltage signal and a line voltage signal of each phase of a three-phase alternating current in a three-phase equilibrium state with vectors.

  If the phase voltage signal of the U phase is Vu = A · sin (ωt), the phase of the V phase is delayed by 2π / 3 from the U phase, so the phase voltage signal of the V phase is Vv = A · sin (ωt−2π). / 3). Further, since the phase of the W phase is delayed by 4π / 3 from the U phase (advanced by 2π / 3), Vw = A · sin (ωt + 2π / 3). The U-phase line voltage signal for the V phase is Vuv = Vu−Vv = √ (3) · A · sin (ωt + π / 6), and the V-phase line voltage signal for the W phase is Vvw = Vv−Vw = √ (3) · A · sin (ωt−π / 2), the W-phase line voltage signal for the U phase is Vwu = Vw−Vu = √ (3) · A · sin (ωt−7π / 6) .

  In FIG. 1, the phase voltage signals Vu, Vv, and Vw are represented by vectors Pu, Pv, and Pw, and the line voltage signals Vuv, Vvw, and Vwu are represented by vectors Puv, Pvw, and Pwu. A regular triangle T connecting the end points of the vectors Pu, Pv, and Pw starting from the neutral point N is indicated by a broken line, and each vertex is indicated by u, v, and w. This figure shows the state when the X axis is the phase reference (θ = 0 °) and the vector Pu corresponding to the U-phase phase voltage signal Vu matches the X axis. Further, the vectors Pvu, Pwv, and Puw are obtained by reversing the directions of the vectors Puv, Pvw, and Pwu, respectively. Therefore, the signals Vvu, Vwv, and Vuw corresponding to the vectors Pvu, Pwv, and Puw are obtained by shifting the phase of the line voltage signals Vuv, Vvw, and Vwu by π, and Vvu = −Vuv = √ (3) · A Sin (ωt + 7π / 6), Vwv = −Vvw = √ (3) · A · sin (ωt + π / 2), Vuw = −Vwu = √ (3) · A · sin (ωt−π / 6).

  In FIG. 1, a state in which the vectors Pu, Pv, and Pw maintain a phase difference of 2π / 3 and rotate around the neutral point N at an angular velocity ω represents a three-phase equilibrium state. ing. Generally, since the neutral point N is set to a reference voltage of 0 [v], each phase voltage signal Vu, Vv, Vw is an orthogonal projection of the vectors Pu, Pv, Pw on the Y axis, as described above. The sine wave signals are out of phase with each other by 2π / 3.

  FIG. 2 is a diagram for explaining the concept of NVS control using vectors as in FIG. In the NVS control, the neutral point N is not fixed to 0 [v], but is changed every 1/3 period, and the potential of each phase is changed to the negative side potential (for example, 0 [v]) by 1/3 period. ).

  In FIG. 2, the neutral point N and the vector Pu are shown, and the vectors Pv and Pw are omitted except for the diagram on the left side of FIG. A regular triangle T connecting the end points of the vectors Pu, Pv, and Pw starting from the neutral point N is indicated by a broken line, and each vertex is indicated by u, v, and w. Moreover, in each figure, the white vertex is attached | subjected to the fixed vertex.

  FIG. 4A shows a state where the angle (hereinafter referred to as “angle θ”) made by the vector Pu with the X axis changes from −π / 6 to π / 2. When −π / 6 ≦ θ ≦ π / 2, the V-phase potential is fixed at 0 [v]. This state is referred to as “mode 1”. In mode 1, the vertex v of the regular triangle T is fixed at the origin, and the regular triangle T is counterclockwise about the vertex v (in the direction of the dashed arrow shown in the figure, and the same applies hereinafter) 2π / 3. Represented by rotating. The left figure shows θ = −π / 6, the middle figure shows θ = π / 6, and the right figure shows θ = π / 2. When θ = π / 2, the W-phase potential is fixed at 0 [v]. The figure on the right shows that the phase to be fixed changes from the V phase to the W phase. The equilateral triangle T moves so that the vertex w coincides with the origin, and the neutral point N transitions. It is shown that.

  FIG. 5B shows a state when the angle θ changes from π / 2 to 7π / 6. When π / 2 ≦ θ ≦ 7π / 6, the W-phase potential is fixed at 0 [v]. This state is referred to as “mode 2”. Mode 2 is represented by the vertex w of the equilateral triangle T being fixed at the origin, and the equilateral triangle T being rotated counterclockwise by 2π / 3 around the vertex w. The left figure shows when θ = π / 2, the middle figure shows when θ = 5π / 6, and the right figure shows when θ = 7π / 6. The left figure is the same figure after the neutral point transition of the right figure of FIG. When θ = 7π / 6, the U-phase potential is fixed at 0 [v]. The right figure shows that the phase to be fixed changes from the W phase to the U phase. The equilateral triangle T moves so that the vertex u coincides with the origin, and the neutral point N transitions. It is shown that.

  FIG. 4C shows a state when the angle θ changes from 7π / 6 to 11π / 6 (= −π / 6). When 7π / 6 ≦ θ ≦ 11π / 6, the U-phase potential is fixed at 0 [v]. This state is referred to as “mode 3”. Mode 3 is represented by the fact that the vertex u of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by 2π / 3 around the vertex u. The left figure shows θ = 7π / 6, the middle figure shows θ = 3π / 2, and the right figure shows θ = 11π / 6. The diagram on the left is the same diagram as after the neutral point transition in the diagram on the right in FIG. When θ = 11π / 6, the V-phase potential is fixed at 0 [v]. The figure on the right shows that the phase to be fixed changes from the U phase to the V phase, and the neutral triangle N is moved by moving the equilateral triangle T so that the vertex v coincides with the origin. It is shown that. The diagram after this transition is the same as the diagram on the left in FIG. Thereafter, modes 1 to 3 are repeated.

  In the vector diagram shown in FIG. 2, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. For example, the phase voltage of the U phase is represented by the Y coordinate of the vertex u. In mode 1, since the vertex v is fixed at the origin, the orthogonal projection on the Y axis of the vector Puv obtained by subtracting the vector Pv from the vector Pu from the vertex v, that is, the vector Pu is the U-phase phase voltage. (See (a) of the same figure). Therefore, the U-phase phase voltage signal Vu ′ of the NVS control in the mode 1 becomes the U-phase line voltage signal Vuv for the V-phase.

  In mode 2, since the vertex w is fixed at the origin, the orthogonal projection onto the Y-axis of the vector Puw obtained by subtracting the vector Pw from the vector Pu, that is, the vector Pu from the vertex Pu becomes the U-phase phase voltage. (See (b) of the figure). Accordingly, the U-phase phase voltage signal Vu ′ of the NVS control in the mode 2 is the signal Vuw (= −Vwu). In mode 3, since the vertex u is fixed at the origin, the phase voltage of the U phase is “0” (see FIG. 10C). Therefore, the U-phase phase voltage signal Vu ′ of the NVS control in the mode 3 is a zero signal whose value is “0”.

  Similarly, the VVS phase voltage signal Vv ′ under NVS control is a zero signal in mode 1, a line voltage signal Vvw in mode 2, and a signal Vvu in mode 3. Further, the phase voltage signal Vw ′ of the N-phase control W phase is the signal Vwv in the mode 1, the zero signal in the mode 2, and the line voltage signal Vwu in the mode 3.

  From the above, the NVS command value signal Xu ′ is generated by switching the line voltage command value signal Xuv, the signal Xuw, and the zero signal according to each mode. The same applies to the NVS command value signals Xv ′ and Xw ′. The waveforms of the generated NVS command value signals Xu ′, Xv ′, and Xw ′ are as shown in FIG.

  As shown in FIG. 32C, the NVS command value signals Xu ′, Xv ′, and Xw ′ are fixed to “0” in 1/3 of the cycle. Therefore, the NVS command value signals Xu ′, Xv ′, and Xw ′ are fixed to “0” in the PWM signal generated by comparing the NVS command value signals Xu ′, Xv ′, and Xw ′ with the carrier signal. The low level or the high level is continued for a certain period. Since the PWM signal continues only at either the low level or the high level, there is a problem in that the on-state time differs between the positive-side switching element and the negative-side switching element.

  In order to solve this problem, the low-level duration and the high-level duration in the PWM signal may be set to the same length. That is, the command value signal for comparison with the carrier signal is not fixed to only “0”, but is fixed to the minimum value (for example, “0”) and the maximum value in a period of the same length. do it. Considering this as a vector diagram as in FIG. 2, the vertex of the regular triangle T is not fixed only to the origin, but the X coordinate is “0” in the same period as fixing to the origin. What is necessary is just to fix to the point whose Y coordinate is a predetermined value.

  FIG. 3 is a diagram for explaining the concept of control according to the first embodiment as a vector. Each vertex of the equilateral triangle T has an origin, an X coordinate of “0”, and a Y coordinate of B (below, , “The maximum point”).

  FIG. 3 shows the neutral point N, the vector Pu, and the equilateral triangle T, as in FIG. 2, and omits the vectors Pv and Pw except for the left diagram of FIG. Yes. Moreover, in each figure, the white vertex is attached | subjected to the fixed vertex.

  FIG. 6A shows a state where the angle θ (the angle that the vector Pu makes with the X axis) changes from −π / 6 to π / 6. When −π / 6 ≦ θ ≦ π / 6, the vertex w of the regular triangle T is fixed at the maximum point, and the regular triangle T is counterclockwise around the vertex w (in the direction of the broken line arrow shown in the figure, However, the same is true). This state is referred to as “mode 1”. FIG. 5A shows that the W-phase potential is fixed to B in mode 1. The left figure shows θ = −π / 6, the middle figure shows θ = 0, and the right figure shows θ = π / 6. When θ = π / 6, the equilateral triangle T moves so that the vertex v coincides with the origin, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to B changes to the state in which the V-phase potential is fixed to “0”.

  FIG. 4B shows a state when the angle θ changes from π / 6 to π / 2 (= 3π / 6). When π / 6 ≦ θ ≦ π / 2, the vertex v of the regular triangle T is fixed at the origin, and the regular triangle T rotates π / 3 counterclockwise around the vertex v. This state is referred to as “mode 2”. FIG. 5B shows that in mode 2, the V-phase potential is fixed at “0”. The left figure shows θ = π / 6, the middle figure shows θ = π / 3 (= 2π / 6), and the right figure shows θ = π / 2 (= 3π / 6). Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = π / 2, the equilateral triangle T moves so that the vertex u coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to “0” changes to the state in which the U-phase potential is fixed to B.

  FIG. 4C shows a state when the angle θ changes from π / 2 (= 3π / 6) to 5π / 6. When π / 2 ≦ θ ≦ 5π / 6, the vertex u of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates π / 3 counterclockwise around the vertex u. This state is referred to as “mode 3”. FIG. 5C shows that in the mode 3, the U-phase potential is fixed to B. The left figure shows θ = π / 2 (= 3π / 6), the middle figure shows θ = 2π / 3 (= 4π / 6), and the right figure shows θ = 5π / 6. Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 5π / 6, the regular triangle T moves so that the vertex w coincides with the origin, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to B changes to the state in which the W-phase potential is fixed to “0”.

  FIG. 4D shows a state when the angle θ changes from 5π / 6 to 7π / 6. When 5π / 6 ≦ θ ≦ 7π / 6, the vertex w of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 3 around the vertex w. This state is referred to as “mode 4”. FIG. 4D shows that in mode 4, the W-phase potential is fixed to “0”. The left figure shows when θ = 5π / 6, the middle figure shows when θ = π (= 6π / 6), and the right figure shows when θ = 7π / 6. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 7π / 6, the equilateral triangle T moves so that the vertex v coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to “0” changes to the state in which the V-phase potential is fixed to B.

  FIG. 5E shows a state when the angle θ changes from 7π / 6 to 3π / 2 (= 9π / 6). When 7π / 6 ≦ θ ≦ 3π / 2, the vertex v of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 3 around the vertex v. This state is referred to as “mode 5”. FIG. 4E shows that in mode 5, the V-phase potential is fixed to B. The left figure shows when θ = 7π / 6, the middle figure shows when θ = 4π / 3 (= 8π / 6), and the right figure shows when θ = 3π / 2 (= 9π / 6). Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 3π / 2, the equilateral triangle T moves so that the vertex u coincides with the origin, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to B changes to the state in which the U-phase potential is fixed to “0”.

  FIG. 5F shows a state where the angle θ changes from 3π / 2 (= 9π / 6) to 11π / 6 (= −π / 6). When 3π / 2 ≦ θ ≦ 11π / 6, the vertex u of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 3 around the vertex u. This state is referred to as “mode 6”. FIG. 5F shows that in mode 6, the U-phase potential is fixed at “0”. The left figure shows θ = 3π / 2 (= 9π / 6), the middle figure shows θ = 5π / 3 (= 10π / 6), and the right figure shows θ = 11π / 6. Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 11π / 6, the equilateral triangle T moves so that the vertex w coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to “0” changes to the state in which the W-phase potential is fixed to B. The figure after this transition is the same as the left figure of FIG. Thereafter, modes 1 to 6 are repeated.

  In the vector diagram shown in FIG. 3, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. For example, the phase voltage of the U phase is represented by the Y coordinate of the vertex u. In mode 1, since the vertex w is fixed at the maximum point, the value obtained by adding B to the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y axis is the U-phase phase voltage (FIG. a)). Therefore, in mode 1, the command value signal Xu1 for commanding the waveform of the U-phase voltage may be obtained by adding B to the signal Xuw (= −Xwu). In mode 2, since the vertex v is fixed at the origin, the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y-axis becomes the U-phase phase voltage (see FIG. 5B). Therefore, in mode 2, the command value signal Xu1 may be the line voltage command value signal Xuv. In mode 3, since the vertex u is fixed at the maximum point, the phase voltage of the U phase is B (see (c) in the figure). Therefore, in mode 3, the command value signal Xu1 may be a signal whose value is B. In mode 4, since the vertex w is fixed at the origin, the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y-axis becomes the U-phase phase voltage (see FIG. 4D). Therefore, in mode 4, the command value signal Xu1 may be the signal Xuw (= −Xwu). In mode 5, the vertex v is fixed at the maximum point, so the value obtained by adding B to the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y axis is the U-phase voltage (see FIG. e)). Therefore, in mode 5, the command value signal Xu1 may be obtained by adding B to the line voltage command value signal Xuv. In mode 6, since the vertex u is fixed at the origin, the phase voltage of the U phase is “0” (see FIG. 8F). Therefore, in mode 6, the command value signal Xu1 may be a zero signal whose value is “0”.

  Similarly, command value signal Xv1 for commanding the waveform of the V-phase voltage is assumed to be obtained by adding B to line voltage command value signal Xvw in mode 1, zero signal in mode 2, and mode 3 , B is added to the signal Xvu, the line voltage command value signal Xvw is set in mode 4, the signal is B in mode 5, and the signal Xvu is set in mode 6. The command value signal Xw1 for commanding the waveform of the W-phase voltage is a signal having a value B in mode 1, a signal Xwv in mode 2, and a line voltage command value signal in mode 3. It is assumed that B is added to Xwu, a zero signal is used in mode 4, B is added to signal Xwv in mode 5, and a line voltage command value signal Xwu is used in mode 6.

  FIG. 4 is a diagram for explaining the waveforms of the command value signals Xu1, Xv1, and Xw1.

  The waveforms Xuv, Xvw, and Xwu shown in FIG. 4A are the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. 32A, and the waveforms Xvu, Xwv, and Xwu shown in FIG. Since it is the same as the waveforms Xvu, Xwv, and Xuw shown in FIG. Also in FIG. 4, the phase of the phase voltage command value signal Xu is described as a reference. The angle θ in the description of the vector diagram such as FIG. 3 is an angle formed by the vector Pu and the X axis, and indicates the phase of the phase voltage command value signal Xu. Therefore, the phase shown in FIG. 4 corresponds to the angle θ.

  A waveform Xu1 shown in FIG. 4C is a waveform of the U-phase command value signal Xu1. The command value signal Xu1 is generated by being divided into modes 1 to 6, as described with reference to FIG. FIG. 4C shows each waveform when B = 2. The waveform Xu1 is a waveform obtained by shifting the waveform Xuw upward by “2” in mode 1 (−π / 6 ≦ θ ≦ π / 6), and a waveform in mode 2 (π / 6 ≦ θ ≦ π / 2). Xuv, mode 3 (π / 2 ≦ θ ≦ 5π / 6), a waveform fixed to “2”, mode 4 (5π / 6 ≦ θ ≦ 7π / 6), Xuw, mode 5 (7π / 6 ≦ In θ ≦ 3π / 2), the waveform Xuv is shifted upward by “2”, and in mode 6 (3π / 2 ≦ θ ≦ 11π / 6), the waveform is fixed to “0”. Similarly, the waveform Xv1 is a waveform obtained by shifting the waveform Xvw upward by “2” in mode 1, a waveform fixed to “0” in mode 2, and a waveform Xvu upward by “2” in mode 3. , The waveform Xvw in mode 4, the waveform fixed to “2” in mode 5, and Xvu in mode 6. The waveform Xw1 is a waveform fixed at “2” in mode 1, Xwv in mode 2, a waveform obtained by shifting the waveform Xwu upward by “2” in mode 3, and “0” in mode 4. In mode 5, the waveform Xwv is shifted upward by “2”, and in mode 6, the waveform is Xwu.

  The command value signals Xu1, Xv1, and Xw1 are fixed to “0” at 1/6 of the cycle and fixed to “2” at 1/6 of the cycle. Therefore, the PWM signal continues to be at a low level (or high level) while the command value signals Xu1, Xv1, and Xw1 are fixed to “0”, and the command value signals Xu1, Xv1, and Xw1 are fixed to “2”. The high level (or low level) will be continued during the period. Since the low level continuation time and the high level continuation time of the PWM signal are equal, the time during which the positive switching element is on and the negative switching element are equal.

  Next, a control circuit that generates the above-described command value signals Xu1, Xv1, and Xw1 and outputs a PWM signal based on the command value signals to the inverter circuit will be described.

  FIG. 5 is a block diagram for explaining a grid-connected inverter system including a control circuit according to the present invention.

  As shown in FIG. 5, the grid interconnection inverter system A includes a DC power source 1, an inverter circuit 2, a filter circuit 3, a transformer circuit 4, and a control circuit 5. The DC power source 1 is connected to the inverter circuit 2. The inverter circuit 2 is a three-phase inverter, and the inverter circuit 2, the filter circuit 3, and the transformer circuit 4 are connected in series by output lines of output voltages of U phase, V phase, and W phase in this order. . The output line is connected to the three-phase power system B (system B) via a switch (not shown). A control circuit 5 is connected to the inverter circuit 2. The grid interconnection inverter system A is linked to the grid B by a switch, converts the DC power output from the DC power supply 1 into AC power by the inverter circuit 2 and supplies the AC power to the grid B. Note that various sensors are provided in the grid-connected inverter system A, and the control circuit 5 performs control based on the detection value of the sensor. However, illustration of various sensors is omitted in FIG. Moreover, the structure of the grid connection inverter system A is not restricted to this. For example, instead of the transformer circuit 4, a so-called transformerless system in which a DC / DC converter circuit is provided between the DC power supply 1 and the inverter circuit 2 may be used.

  The DC power source 1 outputs DC power and includes, for example, a solar battery. A solar cell generates direct-current power by converting solar energy into electrical energy. The DC power source 1 outputs the generated DC power to the inverter circuit 2. Note that the DC power source 1 is not limited to one that generates DC power from a solar cell. For example, the DC power source 1 may be a fuel cell, a storage battery, an electric double layer capacitor, a lithium ion battery, or the like. Moreover, the apparatus which converts and outputs the alternating current power produced | generated by the diesel engine generator, the micro gas turbine generator, the wind turbine generator, etc. to direct current power may be sufficient.

  The inverter circuit 2 is a three-phase full-bridge inverter having six switching elements, and the DC power source 1 is switched on and off based on the PWM signal P input from the control circuit 5. DC voltage input from is converted to AC voltage. Note that the PWM signal P includes six PWM signals input to each switching element.

  FIG. 6 is a circuit diagram for explaining the internal configuration of the inverter circuit 2.

  As shown in the figure, the inverter circuit 2 includes six switching elements S1 to S6, freewheeling diodes D1 to D6, and a smoothing capacitor C. In the present embodiment, IGBTs (Insulated Gate Bipolar Transistors) are used as the switching elements S1 to S6. Note that the switching elements S1 to S6 are not limited to IGBTs, and may be bipolar transistors, MOSFETs, reverse blocking thyristors, or the like. Further, the types of the freewheeling diodes D1 to D6 and the smoothing capacitor C are not limited.

  The switching elements S1 and S4 are connected in series by connecting the emitter terminal of the switching element S1 and the collector terminal of the switching element S4. The collector terminal of the switching element S1 is connected to the positive side of the DC power source 1, and the emitter terminal of the switching element S4 is connected to the negative side of the DC power source 1 to form a bridge structure. Similarly, switching elements S2 and S5 are connected in series to form a bridge structure, and switching elements S3 and S6 are connected in series to form a bridge structure. The bridge structure formed of switching elements S1 and S4 is a U-phase arm, the bridge structure formed of switching elements S2 and S5 is a V-phase arm, and the bridge structure formed of switching elements S3 and S6 is W Phase arm. The U-phase output line is connected to the connection point between the switching elements S1 and S4 of the U-phase arm, the V-phase output line is connected to the connection point between the switching elements S2 and S5 of the V-phase arm, and the W-phase. A W-phase output line is connected to a connection point between the arm switching elements S3 and S6. The PWM signal P output from the control circuit 5 is input to the base terminals of the switching elements S1 to S6.

  Each of the switching elements S1 to S6 can be switched between an on state and an off state based on the PWM signal P. Since both ends of each arm are connected to the positive electrode and the negative electrode of the DC power source 1, respectively, when the positive side switching element is on and the negative side switching element is off, the potential of the output line of the phase is DC The potential is on the positive side of the power supply 1. On the other hand, when the switching element on the positive electrode side is in the off state and the switching element on the negative electrode side is in the on state, the potential of the output line of the phase becomes the potential on the negative electrode side of the DC power supply 1. As a result, a pulsed voltage signal in which the positive potential and the negative potential of the DC power supply 1 are switched is output from each output line, and the line voltage, which is the voltage between the output lines, becomes an AC voltage.

  The freewheeling diodes D1 to D6 are connected in antiparallel between the collector terminals and the emitter terminals of the switching elements S1 to S6, respectively. That is, the anode terminals of the freewheeling diodes D1 to D6 are connected to the emitter terminals of the switching elements S1 to S6, respectively, and the cathode terminals of the freewheeling diodes D1 to D6 are connected to the collector terminals of the switching elements S1 to S6, respectively. Each switching element S1 to S6 generates a back electromotive force due to switching. The free-wheeling diodes D1 to D6 are for preventing a high reverse voltage due to the back electromotive force from being applied to the switching elements S1 to S6.

  The smoothing capacitor C smoothes the DC voltage input from the DC power source 1.

  Note that the configuration of the inverter circuit 2 is not limited to this. For example, the inverter circuit 2 may be a multi-level inverter such as a three-level inverter, or an inverter to which a soft switching technique is applied. Moreover, the inverter circuit 2 is not limited to a full bridge type inverter, and may be a half bridge type inverter.

  The filter circuit 3 removes high frequency components due to switching from the AC voltage input from the inverter circuit 2. The filter circuit 3 includes a low-pass filter (not shown) composed of a reactor and a capacitor. The AC voltage from which the high frequency component has been removed by the filter circuit 3 is output to the transformer circuit 4. The configuration of the filter circuit 3 is not limited to this, and any known filter circuit for removing high frequency components may be used. The transformer circuit 4 boosts or steps down the AC voltage output from the filter circuit 3 to a level substantially the same as the system voltage of the system B.

  The control circuit 5 generates a PWM signal P that controls switching of the switching elements of the inverter circuit 2. The control circuit 5 receives detection signals from various sensors (not shown) and outputs a PWM signal P to the inverter circuit 2.

  The control circuit 5 generates command value signals Xu1, Xv1, Xw1 for commanding the waveform of the output voltage output from the grid interconnection inverter system A based on detection signals input from various sensors, and the command value signal A PWM signal P is generated based on Xu1, Xv1, and Xw1. The inverter circuit 2 outputs voltage signals corresponding to the command value signals Xu1, Xv1, and Xw1 by switching each switching element on and off based on the input PWM signal P. The control circuit 5 controls the output current by changing the output voltage signal of the inverter circuit 2 by changing the waveforms of the command value signals Xu1, Xv1, and Xw1. Thereby, the control circuit 5 performs various feedback controls. Note that the control circuit 5 has a configuration for detecting an overcurrent, a ground fault, a short circuit, a single operation, etc., and stopping the operation of the inverter circuit 2, and a configuration for tracking the maximum power. The description and explanation in FIG. 5 are omitted.

  Next, the internal configuration of the control circuit 5 and the method for generating the command value signals Xu1, Xv1, Xw1 and the PWM signal P will be described in detail with reference to FIGS.

  FIG. 7 is a block diagram for explaining the internal configuration of the control circuit 5.

  The control circuit 5 includes a feedback control unit 51, a command value signal generation unit 52, and a PWM signal generation unit 53.

  The feedback control unit 51 performs feedback control based on a deviation between detection signals input from various sensors and a preset target value, and commands the waveform of the output phase voltage of the grid-connected inverter system A. The generated phase voltage command value signals Xu, Xv, Xw are output to the command value signal generator 52. Details of feedback control performed by the feedback control unit 51 are omitted. The feedback control performed by the feedback control unit 51 may control the output current, output voltage, output active power, and output reactive power output by the grid interconnection inverter system A, or may be output from the DC power supply 1. It may control a DC voltage.

  The command value signal generation unit 52 generates command value signals Xu 1, Xv 1, Xw 1 based on the phase voltage command value signals Xu, Xv, Xw input from the feedback control unit 51 and outputs them to the PWM signal generation unit 53. . The command value signals Xu1, Xv1, and Xw1 are signals for actually commanding the waveform of the phase voltage output from the grid interconnection inverter system A. The waveform of the command value signals Xu1, Xv1, and Xw1 has a special shape like the waveforms Xu1, Xv1, and Xw1 shown in FIG. That is, the command value signal generation unit 52 converts the phase voltage command value signals Xu, Xv, Xw into command value signals Xu1, Xv1, Xw1.

  The command value signal generation unit 52 generates line voltage command value signals Xuv, Xvw, Xwu from the phase voltage command value signals Xu, Xv, Xw. That is, the line voltage command value signal Xuv is generated by the difference between the phase voltage command value signals Xu and Xv, the line voltage command value signal Xvw is generated by the difference between the phase voltage command value signals Xv and Xw, and the phase voltage A line voltage command value signal Xwu is generated based on the difference between the command value signals Xw and Xu. The line voltage command value signals Xuv, Xvw, and Xwu are signals for commanding the waveform of the line voltage output from the grid interconnection inverter system A.

  Further, the command value signal generation unit 52 generates signals Xvu, Xwv, and Xuw obtained by inverting the polarities of the line voltage command value signals Xuv, Xvw, and Xwu. Instead of inverting the polarity, the signal Xvu is generated by the difference between the phase voltage command value signals Xv and Xu, the signal Xwv is generated by the difference between the phase voltage command value signals Xw and Xv, and the phase voltage command value The signal Xuw may be generated based on the difference between the signals Xu and Xw.

  The command value signal generator 52 uses line voltage command value signals Xuv, Xvw, Xwu, signals Xvu, Xwv, Xuw, a zero signal whose value is “0”, and a signal whose value is “2”. The command value signals Xu1, Xv1, and Xw1 are generated. In the present embodiment, the amplitudes of the phase voltage command value signals Xu, Xv, Xw are set to “1” for normalization, so the amplitudes of the line voltage command value signals Xuv, Xvw, Xwu are √ (3). (See FIG. 4 (a)). The upper limit value of the command value signals Xu1, Xv1, and Xw1 needs to be a value that is greater than or equal to the amplitude of the line voltage command value signals Xuv, Xvw, and Xwu. Therefore, in this embodiment, in order to set the upper limit value to “2”, a signal whose value is “2” is used. Since the upper limit value only needs to be a value greater than the amplitude of the line voltage command value signals Xuv, Xvw, Xwu, a predetermined value of √ (3) or more is set as the upper limit value according to the modulation degree to be set. Is done. The amplitude of a carrier signal to be described later is set according to the upper limit value.

  FIG. 8 shows a process of generating command value signals Xu1, Xv1, and Xw1 from line voltage command value signals Xuv, Xvw, and Xwu (hereinafter referred to as “command value signal generation process”) performed by the command value signal generator 52. It is a flowchart for demonstrating. The command value signal generation process is executed at a predetermined timing.

  First, phase voltage command value signals Xu, Xv, Xw and line voltage command value signals Xuv, Xvw, Xwu are acquired (S1). Next, it is determined whether or not the absolute value of Xuv is larger than the absolute value of Xvw (S2). When the absolute value of Xuv is larger (S2: YES), it is determined whether or not the absolute value of Xuv is larger than the absolute value of Xwu (S3). When the absolute value of Xuv is larger (S3: YES), that is, when the absolute value of Xuv is the maximum, the process proceeds to step S5. On the other hand, if the absolute value of Xuv is less than or equal to the absolute value of Xwu (S3: NO), that is, if the absolute value of Xwu is maximum, the process proceeds to step S6. In step S2, if the absolute value of Xuv is less than or equal to the absolute value of Xvw (S2: NO), it is determined whether or not the absolute value of Xvw is greater than the absolute value of Xwu (S4). When the absolute value of Xvw is larger (S4: YES), that is, when the absolute value of Xvw is the maximum, the process proceeds to step S7. On the other hand, when the absolute value of Xvw is equal to or smaller than the absolute value of Xwu (S4: NO), that is, when the absolute value of Xwu is the maximum, the process proceeds to step S6. In steps S2 to S4, it is determined which of Xuv, Xvw, and Xwu has the maximum absolute value.

  When it is determined that the absolute value of Xuv is the maximum and the process proceeds to step S5, it is determined whether Xu is a positive value (S5). When Xu is a positive value (S5: YES), the command value signal Xu1 is set to Xuv, the command value signal Xv1 is set to “0”, and the command value signal Xw1 is set to a negative value of Xvw (S8). On the other hand, when Xu is “0” or less (S5: NO), Xu1 is a value obtained by adding Xuv to “2”, Xv1 is “2”, and Xw1 is a value obtained by subtracting Xvw from “2”. (S9).

  When it is determined that the absolute value of Xwu is the maximum and the process proceeds to step S6, it is determined whether Xw is a positive value (S6). When Xw is a positive value (S6: YES), Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu (S10). On the other hand, when Xw is “0” or less (S6: NO), Xu1 is set to “2”, Xv1 is set to a value obtained by subtracting Xuv from “2”, and Xw1 is set to a value obtained by adding Xwu to “2”. (S11).

  If it is determined that the absolute value of Xvw is the maximum and the process proceeds to step S7, it is determined whether Xv is a positive value (S7). When Xv is a positive value (S7: YES), Xu1 is set to a negative value of Xwu, Xv1 is set to Xvw, and Xw1 is set to “0” (S12). On the other hand, when Xv is “0” or less (S7: NO), Xu1 is a value obtained by subtracting Xwu from “2”, Xv1 is a value obtained by adding Xvw to “2”, and Xw1 is “2”. (S13).

  That is, in the command value signal generation process, the line voltage command value signals Xuv, Xvw, Xwu are determined to have the maximum absolute value, and the phase voltage command value signal corresponding to the maximum absolute value is determined to be positive or negative. The command value signals Xu1, Xv1, and Xw1 are determined according to the determination result. That is, it is determined which mode is in the vector diagram shown in FIG. 3, and the command value signals Xu1, Xv1, Xw1 of each phase are determined so as to correspond to the vector diagram of the determined mode.

  In the mode 1 state shown in FIG. 3A, the length of the orthogonal projection on the Y axis of the side vw connecting the vertex v and the vertex w of the regular triangle T is the Y axis of the other sides wu and uv. It becomes more than the length of the orthogonal projection above. That is, the length of the orthogonal projection of the vector Pvw on the Y axis is equal to or longer than the length of the orthogonal projection of the vectors Pwu and Puv on the Y axis (each vector is not shown). This indicates that the absolute value of the line voltage command value signal Xvw is greater than or equal to the absolute value of the line voltage command value signals Xwu and Xuv. In the mode 1 state, the Y coordinate of the vector Pv is a negative value. This indicates that the phase voltage command value signal Xv is a negative value. That is, in the mode 1 state, the absolute value of the line voltage command value signal Xvw is the maximum, and the phase voltage command value signal Xv is a negative value.

  In the mode 1 state, the Y coordinate of the apex u of the regular triangle T is B (in FIG. 8, the case of B = “2” has been described, and is set to “2” below). ) To the value obtained by adding the Y coordinate of the vector Puw (that is, the value obtained by subtracting the Y coordinate of the vector Pwu from “2”). This indicates that the phase voltage command value signal Xu1 is obtained by subtracting the line voltage command value signal Xwu from “2”. Further, the Y coordinate of the vertex v of the regular triangle T is a value obtained by adding the Y coordinate of the vector Pvw to “2”. This indicates that the phase voltage command value signal Xv1 is obtained by adding “2” to the line voltage command value signal Xvw. Further, since the vertex w of the regular triangle T is fixed to the maximum point, the Y coordinate of the vertex w is fixed to “2”. This indicates that the phase voltage command value signal Xw1 is “2”.

  Therefore, in the flowchart shown in FIG. 8, when the absolute value of Xvw is the maximum and Xv is a negative value (S7: NO), it is the mode 1 state, and at this time, Xu1 is subtracted from “2”. Xv1 is a value obtained by adding Xvw to “2”, and Xw1 is “2” (S13).

  Similarly, in the mode 2 state shown in FIG. 3B, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Pu is a positive value. That is, the absolute value of the line voltage command value signal Xuv is maximized, and the phase voltage command value signal Xu is a positive value (S5: YES in FIG. 8). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu1 is set to Xuv, Xv1 is set to “0”, and Xw1 is set to a negative value of Xvw (S8 in FIG. 8).

  In the mode 3 state shown in FIG. 3C, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pw is a negative value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the phase voltage command value signal Xw becomes a negative value (S6: NO in FIG. 8). At this time, the Y coordinates of the vertices u, v, and w are values obtained by subtracting the Y coordinate of the vector Puv from “2” and “2”, respectively, and the values obtained by adding the Y coordinate of the vector Pwu to “2”. Accordingly, Xu1 is “2”, Xv1 is a value obtained by subtracting Xuv from “2”, and Xw1 is a value obtained by adding Xwu to “2” (S11 in FIG. 8).

  In the mode 4 state shown in FIG. 3D, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pv is a positive value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the phase voltage command value signal Xv becomes a positive value (S7: YES in FIG. 8). At this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Therefore, Xu1 is a negative value of Xwu, Xv1 is Xvw, and Xw1 is “0” (S12 in FIG. 8).

  In the mode 5 state shown in FIG. 3 (e), the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Pu is a negative value. That is, the absolute value of the line voltage command value signal Xuv is maximized, and the phase voltage command value signal Xu is a negative value (S5: NO in FIG. 8). At this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. Therefore, Xu1 is a value obtained by adding Xuv to “2”, Xv1 is “2”, and Xw1 is a value obtained by subtracting Xvw from “2” (S9 in FIG. 8).

  In the mode 6 state shown in FIG. 3 (f), the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pw is a positive value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the phase voltage command value signal Xw becomes a positive value (S6: YES in FIG. 8). At this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu (S10 in FIG. 8).

  The waveforms of the command value signals Xu1, Xv1, and Xw1 generated by the command value signal generation processing are as shown by waveforms Xu1, Xv1, and Xw1 shown in FIG. That is, in mode 1, since the process proceeds to step S13 in the flowchart of FIG. 8, the waveform Xu1 is a waveform obtained by shifting the waveform Xuw (see FIG. 4B) upward by “2”, and the waveform Xv1 is the waveform Xvw ( 4 (a)) is shifted upward by “2”, and the waveform Xw1 is a waveform fixed at “2”. In mode 2, since the process proceeds to step S8 in the flowchart of FIG. 8, the waveform Xu1 becomes the waveform Xuv, the waveform Xv1 becomes a waveform fixed to “0”, and the waveform Xw1 becomes the waveform Xwv. In mode 3, since the process proceeds to step S11 in the flowchart of FIG. 8, the waveform Xu1 is a waveform fixed to “2”, the waveform Xv1 is a waveform obtained by shifting the waveform Xvu upward by “2”, and the waveform Xw1 is The waveform Xwu is shifted upward by “2”. In mode 4, since the process proceeds to step S12 in the flowchart of FIG. 8, the waveform Xu1 becomes the waveform Xuw, the waveform Xv1 becomes the waveform Xvw, and the waveform Xw1 becomes a waveform fixed to “0”. In mode 5, since the process proceeds to step S9 in the flowchart of FIG. 8, the waveform Xu1 is a waveform obtained by shifting the waveform Xuv upward by “2”, the waveform Xv1 is a waveform fixed to “2”, and the waveform Xw1 is This is a waveform obtained by shifting the waveform Xwv upward by “2”. In mode 6, since the process proceeds to step S10 in the flowchart of FIG. 8, the waveform Xu1 becomes a waveform fixed to “0”, the waveform Xv1 becomes the waveform Xvu, and the waveform Xw1 becomes the waveform Xwu.

  The flowchart shown in FIG. 8 is an example of the command value signal generation process, and is not limited to this. For example, using the fact that each line voltage command value signal Xuv, Xvw, Xwu is calculated by the difference between the phase voltage command value signals Xu, Xv, Xw, the command value signals Xu1, Xv1, Xw1 in steps S8 to S13 are used. May be calculated using the phase voltage command value signals Xu, Xv, Xw. For example, in the case of step S8, Xu1 = Xu-Xv, Xv1 = 0, Xw1 = Xw-Xv, and in the case of step S9, Xu1 = 2 + Xu-Xv, Xv1 = 2, Xw1 = 2 + Xw-Xv may be used.

  The command value signals Xu1, Xv1, and Xw1 may be generated according to the phase of the U-phase phase voltage command value signal Xu.

  FIG. 9 is a flowchart for explaining another command value signal generation process. In the command value signal generation process, command value signals Xu1, Xv1, and Xw1 are generated according to the phase of the phase voltage command value signal Xu.

  First, the line voltage command value signals Xuv, Xvw, Xwu and the phase θ of the phase voltage command value signal Xu are acquired (S21). The phase θ is adjusted so that −π / 6 ≦ θ <11π / 6. Next, it is determined whether or not the phase θ is −π / 6 or more and less than π / 6 (S22). When the phase θ corresponds to this (S22: YES), Xu1 is a value obtained by subtracting Xwu from “2”, Xv1 is a value obtained by adding Xvw to “2”, and Xw1 is set to “2”. (S23). That is, when −π / 6 ≦ θ <π / 6, it is determined that the state is in the mode 1 of the vector diagram shown in FIG. 3, and the command value signal for each phase is determined so as to correspond to the vector diagram of the mode 1 Is done.

  If the phase θ does not fall within the range of step S22 (S22: NO), it is determined whether or not the phase θ is greater than or equal to π / 6 and less than π / 2 (S24). When the phase θ corresponds to this (S24: YES), Xu1 is set to Xuv, Xv1 is set to “0”, and Xw1 is set to a negative value of Xvw (S25). In other words, when π / 6 ≦ θ <π / 2, it is determined that the state is in the mode 2 of the vector diagram shown in FIG. The

  If the phase θ does not fall within the range of step S24 (S24: NO), it is determined whether or not the phase θ is greater than or equal to π / 2 and less than 5π / 6 (S26). When the phase θ corresponds to this (S26: YES), Xu1 is “2”, Xv1 is a value obtained by subtracting Xuv from “2”, and Xw1 is a value obtained by adding Xwu to “2”. (S27). That is, when π / 2 ≦ θ <5π / 6, it is determined that the state is in the mode 3 of the vector diagram shown in FIG. 3, and the command value signal of each phase is determined so as to correspond to the vector diagram of the mode 3. The

  When the phase θ does not fall within the range of step S26 (S26: NO), it is determined whether or not the phase θ is 5π / 6 or more and less than 7π / 6 (S28). When the phase θ corresponds to this (S28: YES), Xu1 is set to a negative value of Xwu, Xv1 is set to Xvw, and Xw1 is set to “0” (S29). That is, if 5π / 6 ≦ θ <7π / 6, it is determined that the state is in the mode 4 of the vector diagram shown in FIG. The

  When the phase θ does not fall within the range of step S28 (S28: NO), it is determined whether or not the phase θ is 7π / 6 or more and less than 3π / 2 (S30). When the phase θ corresponds to this (S30: YES), Xu1 is a value obtained by adding Xuv to “2”, Xv1 is set to “2”, and Xw1 is a value obtained by subtracting Xvw from “2”. (S31). That is, when 7π / 6 ≦ θ <3π / 2, it is determined that the state is in the mode 5 of the vector diagram shown in FIG. 3, and the command value signal for each phase is determined so as to correspond to the vector diagram of the mode 5. The

  When the phase θ does not fall within the range of step S30 (S26: NO), that is, when the phase θ is 7π / 6 or more and less than 11π / 6, Xu1 is set to “0” and Xv1 is a negative value of Xuv. Xw1 is set to Xwu (S32). That is, in the case of 7π / 6 ≦ θ <11π / 6, it is determined that the state is the mode 6 state of the vector diagram shown in FIG. 3, and the command value signal of each phase is determined so as to correspond to the mode 6 vector diagram. The

  The command value signal generation unit 52 is not limited to one that individually generates the command value signals Xu1, Xv1, and Xw1. For example, the command value signal generation unit 52 generates only the command value signal Xu1, sets the signal obtained by delaying the phase of the command value signal Xu1 by 2π / 3 as the command value signal Xv1, and delays the phase of the command value signal Xu1 by 4π / 3. The output signal may be output as the command value signal Xw1.

  Returning to FIG. 7, the PWM signal generation unit 53 includes a carrier signal (for example, a triangular wave signal) having a predetermined frequency (for example, 4 kHz) generated therein and a command value input from the command value signal generation unit 52. A PWM signal P is generated based on the signals Xu1, Xv1, and Xw1, and is output to the inverter circuit 2. The PWM signal generation unit 53 sets the lower limit value as the lower limit value (ie, “0”) of the command value signals Xu1, Xv1, and Xw1, and sets the upper limit value as the upper limit value (ie, “2”) of the command value signals Xu1, Xv1, and Xw1. Then, a triangular wave signal changing between them is generated as a carrier signal. In the present embodiment, the upper limit value and the lower limit value of the carrier signal are matched with the upper limit value and the lower limit value of the command value signals Xu1, Xv1, and Xw1, respectively, but the present invention is not limited to this. For example, the amplitude of the carrier signal may be smaller than the amplitude of the command value signals Xu1, Xv1, and Xw1. However, in this case, overmodulation occurs and the accuracy of modulation deteriorates, so it is desirable to match the upper limit value and the lower limit value.

  The PWM signal generation unit 53 outputs a pulse signal that becomes a high level during a period when the command value signal Xu1 is equal to or higher than the carrier signal and becomes a low level when the command value signal Xu1 is smaller than the carrier signal. 6) to generate a PWM signal P1. Note that, when generating the PWM signal P1, a pulse having a pulse width smaller than a predetermined value is removed. Therefore, even if the carrier signal becomes “0” during the period in which the command value signal Xu1 is fixed to “0”, the low level is maintained instead of instantaneously becoming the high level. Similarly, the PWM signal generation unit 53 generates a PWM signal P2 input to the switching element S2 by comparing the command value signal Xv1 and the carrier signal, and performs switching by comparing the command value signal Xw1 and the carrier signal. A PWM signal P3 to be input to the element S3 is generated. The PWM signal generation unit 53 inverts the polarities of the PWM signals P1, P2, and P3 to generate PWM signals P4, P5, and P6 that are input to the switching elements S4, S5, and S6, respectively. The generated PWM signals P1 to P6 are input to the base terminals of the switching elements S1 to S6 of the inverter circuit 2, respectively.

  FIG. 10 is a diagram for explaining a method of generating PWM signals P1 and P4 from the command value signal Xu1 and the carrier signal. In the figure, the command value signal Xu1 is indicated by the waveform X, the carrier signal is indicated by the waveform C, and the PWM signals P1 and P4 are indicated by the waveforms P1 and P4. In FIG. 10, the waveform P1 is at a high level during a period when the waveform X is equal to or greater than the waveform C, and the waveform P1 is at a low level during a period when the waveform X is smaller than the waveform C. The waveform P4 is a waveform obtained by inverting the polarity of the waveform P1.

  Note that the configuration of the PWM signal generation unit 53 is not limited to that described above. Other methods may be used as long as the PWM signal P can be generated from the command value signals Xu1, Xv1, and Xw1. For example, the carrier signal may be a sawtooth wave signal instead of a triangular wave signal. Further, a method other than the method based on comparison with the carrier signal may be used. Further, a pulse width (hereinafter referred to as “pulse width with respect to the line voltage”) is calculated from the line voltage command value signals Xuv, Xvw, and Xwu using the PWM hold method, and the line voltage is detected with a predetermined algorithm. The pulse width may be converted into a pulse width corresponding to the phase voltage, and the PWM signal P may be generated based on the pulse width corresponding to the phase voltage (see JP 2010-68630 A).

  The control circuit 5 may be realized as an analog circuit or a digital circuit. Further, the processing performed by each unit may be designed by a program, and the computer may function as the control circuit 5 by executing the program. The program may be recorded on a recording medium and read by a computer.

  In the present embodiment, the command value signal generator 52 of the control circuit 5 outputs command value signals Xu1, Xv1, and Xw1 having waveforms shown in FIG. 4C, and the PWM signal generator 53 outputs the command value signals Xu1, Xv1. , Xw1 to generate a PWM signal P and output it to the inverter circuit 2. The inverter circuit 2 performs switching of the switching elements S1 to S6 based on the PWM signal P. Thereby, the DC power output from the DC power source 1 is converted into AC power and output.

  The waveforms of the phase voltage signals Vu1, Vv1, and Vw1 output from the grid interconnection inverter system A are the same as the waveforms of the command value signals Xu1, Xv1, and Xw1 shown in FIG. As is apparent from FIG. 4, the difference signal between the command value signals Xu1 and Xv1 matches the line voltage command value signal Xuv. For example, in mode 1, Xu1 = 2−Xwu, Xv1 = 2 + Xvw, Xwu = √ (3) · sin (ωt−7π / 6), and Xvw = √ (3) · sin (ωt−π / 2). Therefore, the difference is Xu1-Xv1 = 2-Xwu-2-Xvw = -√ (3) · sin (ωt−7π / 6) −√ (3) · sin (ωt−π / 2) = √ (3 ) · Sin (ωt−π / 6) = Xuv. That is, it can be confirmed by calculation that the difference signal between the command value signals Xu1 and Xv1 matches the line voltage command value signal Xuv. Similarly, in modes 2 to 6, it can be confirmed that Xu1-Xv1 = Xuv. Similarly, the difference signal between the command value signals Xv1 and Xw1 matches the line voltage command value signal Xvw, and the difference signal between the command value signals Xw1 and Xu1 matches the line voltage command value signal Xwu. Therefore, the waveforms of the line voltage signals Vuv, Vvw, Vwu, which are the differential signals of the phase voltage signals Vu1, Vv1, Vw1, are the waveforms Xuv, Xvw, Xwu of the line voltage command value signals Xuv, Xvw, Xwu shown in FIG. It becomes the same as Xvw and Xwu. That is, the line voltage signals Vuv, Vvw, and Vwu are sine wave signals balanced in three phases, and can be synchronized with the system voltage of the system B. Therefore, the AC power output from the grid interconnection inverter system A can be supplied to the grid B.

  As shown by the waveform P1 in FIG. 10, the PWM signal P1 continues to be at a low level during the period in which the command value signal Xu1 (waveform X) is fixed to “0”, and in the period in which the command value signal Xu1 is fixed at “2”. Continue high level. During these periods, the switching element S1 stops switching. Therefore, since the number of times of switching of the switching element is reduced, the switching loss can be reduced. Further, the time during which the PWM signal P1 continues at the high level is equal to the time during which the PWM signal P1 continues at the low level. The PWM signal P4 is obtained by inverting the polarity of the PWM signal P1. Therefore, the time during which the PWM signal P1 continues to be at the high level is equal to the time during which the PWM signal P4 continues to be at the high level. Thereby, the time for which the switching element S1 is in the ON state is equal to the time for which the switching element S4 is in the ON state. Therefore, the deterioration of the switching element S1 and the switching element S4 proceeds in the same manner, and the lifetimes of both are equal. In addition, since the amount of heat generated by both is equal, the design of the cooling member is facilitated.

  In the control circuit 5 of this embodiment, the feedback control unit 51 and the PWM signal generation unit 53 are common to those of the conventional control circuit 500 (see FIG. 31). Therefore, it can be realized only by adding the command value signal generation unit 52 in the conventional control circuit 500.

  In the above embodiment, the case where the lower limit value of the command value signals Xu1, Xv1, and Xw1 is “0” and the upper limit value is “2” has been described, but the present invention is not limited to this. For example, the command value signals Xu1, Xv1, and Xw1 may be generated so that the lower limit value is “−1” and the upper limit value is “1”. In this case, it is necessary to set the lower limit value and the upper limit value of the carrier signal used in the PWM signal generation unit 53 in accordance with the lower limit value and the upper limit value of the command value signals Xu1, Xv1, and Xw1.

  In the above embodiment, the case where the negative electrode of the DC power supply 1 is grounded and the potential of the negative electrode is “0” has been described, but the present invention is not limited to this. For example, the present invention is applied even when the positive electrode of the DC power supply 1 is grounded and the positive electrode potential is “0”, or when the positive electrode potential is positive and the negative electrode potential is negative. Can do.

  In the embodiment described above, the inverter circuit 2 is controlled by generating the command value signals Xu1, Xv1, and Xw1 having the waveforms Xu1, Xv1, and Xw1 shown in FIG. 4C. However, the present invention is not limited to this. The inverter circuit 2 may be controlled by generating a command value signal having another waveform. A control method for generating command value signals of other waveforms will be described below as second to fourth embodiments. The command value signals according to the second embodiment are Xu2, Xv2, Xw2, the command value signals according to the third embodiment are Xu3, Xv3, Xw3, and the command value signals according to the fourth embodiment are Xu4, Xv4, Xw4. To do. The second to fourth embodiments differ from the first embodiment only in the command value signal generation process performed by the command value signal generation unit 52. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

  FIG. 11 is a diagram for explaining the concept of control according to the second embodiment in terms of vectors.

  The control concept of the second embodiment shown in FIG. 11 is the same as the control concept of the first embodiment shown in FIG. The point whose coordinates are B). However, the fixed vertex differs in 2nd Embodiment and 1st Embodiment. FIG. 11 shows the neutral point N, the vector Pu, and the equilateral triangle T, as in FIG. Yes. Moreover, in each figure, the white vertex is attached | subjected to the fixed vertex.

  FIG. 6A shows a state where the angle θ (the angle that the vector Pu makes with the X axis) changes from −π / 6 to π / 6. When −π / 6 ≦ θ ≦ π / 6, the vertex v of the equilateral triangle T is fixed at the origin, and the equilateral triangle T is counterclockwise around the vertex v (in the direction of the broken-line arrow shown in FIG. The same is true). This state is referred to as “mode 1”. FIG. 5A shows that in mode 1, the V-phase potential is fixed at “0”. The left figure shows θ = −π / 6, the middle figure shows θ = 0, and the right figure shows θ = π / 6. When θ = π / 6, the equilateral triangle T moves so that the vertex u coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to “0” changes to the state in which the U-phase potential is fixed to B.

  FIG. 4B shows a state when the angle θ changes from π / 6 to π / 2 (= 3π / 6). When π / 6 ≦ θ ≦ π / 2, the vertex u of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates π / 3 counterclockwise around the vertex u. This state is referred to as “mode 2”. FIG. 4B shows that in mode 2, the U-phase potential is fixed to B. The left figure shows θ = π / 6, the middle figure shows θ = π / 3 (= 2π / 6), and the right figure shows θ = π / 2 (= 3π / 6). Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = π / 2, the equilateral triangle T moves so that the vertex w coincides with the origin, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to B changes to the state in which the W-phase potential is fixed to “0”.

  FIG. 4C shows a state when the angle θ changes from π / 2 (= 3π / 6) to 5π / 6. When π / 2 ≦ θ ≦ 5π / 6, the vertex w of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 3 around the vertex w. This state is referred to as “mode 3”. FIG. 5C shows that in mode 3, the W-phase potential is fixed to “0”. The left figure shows θ = π / 2 (= 3π / 6), the middle figure shows θ = 2π / 3 (= 4π / 6), and the right figure shows θ = 5π / 6. Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 5π / 6, the equilateral triangle T moves so that the vertex v coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to “0” changes to the state in which the V-phase potential is fixed to B.

  FIG. 4D shows a state when the angle θ changes from 5π / 6 to 7π / 6. When 5π / 6 ≦ θ ≦ 7π / 6, the vertex v of the regular triangle T is fixed to the maximum point, and the regular triangle T rotates counterclockwise by π / 3 around the vertex v. This state is referred to as “mode 4”. FIG. 4D shows that the V-phase potential is fixed to B in mode 4. The left figure shows when θ = 5π / 6, the middle figure shows when θ = π (= 6π / 6), and the right figure shows when θ = 7π / 6. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 7π / 6, the equilateral triangle T moves so that the vertex u coincides with the origin, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to B changes to the state in which the U-phase potential is fixed to “0”.

  FIG. 5E shows a state when the angle θ changes from 7π / 6 to 3π / 2 (= 9π / 6). When 7π / 6 ≦ θ ≦ 3π / 2, the vertex u of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 3 around the vertex u. This state is referred to as “mode 5”. FIG. 5E shows that in mode 5, the U-phase potential is fixed at “0”. The left figure shows when θ = 7π / 6, the middle figure shows when θ = 4π / 3 (= 8π / 6), and the right figure shows when θ = 3π / 2 (= 9π / 6). Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 3π / 2, the equilateral triangle T moves so that the vertex w coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to “0” changes to the state in which the W-phase potential is fixed to B.

  FIG. 5F shows a state where the angle θ changes from 3π / 2 (= 9π / 6) to 11π / 6 (= −π / 6). When 3π / 2 ≦ θ ≦ 11π / 6, the vertex w of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 3 around the vertex w. This state is referred to as “mode 6”. FIG. 5F shows that in mode 6, the W-phase potential is fixed to B. The left figure shows θ = 3π / 2 (= 9π / 6), the middle figure shows θ = 5π / 3 (= 10π / 6), and the right figure shows θ = 11π / 6. Yes. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 11π / 6, the equilateral triangle T moves so that the vertex v coincides with the origin, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to B changes to the state in which the V-phase potential is fixed to “0”. The figure after this transition is the same as the left figure of FIG. Thereafter, modes 1 to 6 are repeated.

  In the vector diagram shown in FIG. 11, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. In mode 1, since the vertex v is fixed at the origin, the orthogonal projection on the Y axis of the vector Puv from the vertex v to the vertex u becomes the U-phase phase voltage (see FIG. 5A). Therefore, in mode 1, the command value signal Xu2 may be the line voltage command value signal Xuv. In mode 2, the vertex u is fixed at the maximum point, so the phase voltage of the U phase is B (see FIG. 5B). Therefore, in mode 2, the command value signal Xu2 may be a signal whose value is B. In mode 3, since the vertex w is fixed at the origin, the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y-axis becomes the U-phase phase voltage (see FIG. 3C). Therefore, in mode 3, the command value signal Xu2 may be the signal Xuw (= −Xwu). In mode 4, since the vertex v is fixed at the maximum point, the value obtained by adding B to the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y axis is the U-phase phase voltage (FIG. d)). Therefore, in mode 4, the command value signal Xu2 may be obtained by adding B to the signal Xuv. In mode 5, since the vertex u is fixed at the origin, the phase voltage of the U phase is “0” (see FIG. 5E). Therefore, in mode 5, the command value signal Xu2 may be a zero signal whose value is “0”. In mode 6, since the vertex w is fixed at the maximum point, the value obtained by adding B to the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y axis is the U-phase phase voltage (FIG. f)). Therefore, in mode 6, the command value signal Xu2 may be obtained by adding B to the signal Xuw (= −Xwu).

  Similarly, V-phase command value signal Xv2 is a zero signal in mode 1, B is added to signal Xvu in mode 2, line voltage command value signal Xvw in mode 3, and mode 4 Is a signal having a value of B, a signal Xvu in mode 5, and a signal obtained by adding B to the line voltage command value signal Xvw in mode 6. The W-phase command value signal Xw2 is the signal Xwv in mode 1, B is added to the line voltage command value signal Xwu in mode 2, the zero signal in mode 3, and the mode 4 It is assumed that B is added to the signal Xwv, the line voltage command value signal Xwu is set in the mode 5, and the signal having the value B is set in the mode 6.

  FIG. 12 is a flowchart for explaining a command value signal generation process performed by the command value signal generator 52 according to the second embodiment. The command value signal generation process is executed at a predetermined timing.

  In the flowchart shown in the figure, steps S41 to S47 are the same as steps S1 to S7 in the flowchart (see FIG. 8) of the command value signal generation process according to the first embodiment. Therefore, detailed description of steps S41 to S47 is omitted. Steps S41 to S47 determine the line voltage command value signals Xuv, Xvw, Xwu having the maximum absolute value, and determine whether the phase voltage command value signal corresponding to the maximum absolute value is positive or negative. . In steps S48 to S53, the command value signals Xu2, Xv2, and Xw2 are determined according to the determination result. That is, it is determined which mode is in the vector diagram shown in FIG. 11, and the command value signals Xu2, Xv2, Xw2 of each phase are determined so as to correspond to the vector diagram of the determined mode.

  When it is determined that the absolute value of Xuv is the maximum and Xu is a positive value (S45: YES), the command value signal Xu2 is set to “2”, and the command value signal Xv2 is changed from “2” to Xuv. The instruction value signal Xw2 is a value obtained by adding Xwu to “2” (S48). When it is determined that the absolute value of Xuv is the maximum and Xu is a negative value (S45: NO), the command value signal Xu2 is set to “0”, and the command value signal Xv2 is set to a negative value of Xuv. The command value signal Xw2 is set to Xwu (S49). When it is determined that the absolute value of Xwu is the maximum and Xw is a positive value (S46: YES), the command value signal Xu2 is a value obtained by subtracting Xwu from “2”, and the command value signal Xv2 is A value obtained by adding Xvw to “2” is set, and the command value signal Xw2 is set to “2” (S50). When it is determined that the absolute value of Xwu is the maximum and Xw is a negative value (S46: NO), the command value signal Xu2 is a negative value of Xwu, the command value signal Xv2 is Xvw, and the command The value signal Xw2 is set to “0” (S51). When it is determined that the absolute value of Xvw is the maximum and Xv is a positive value (S47: YES), the command value signal Xu2 is a value obtained by adding Xuv to “2”, and the command value signal Xv2 is “2” is set, and the command value signal Xw2 is set to a value obtained by subtracting Xvw from “2” (S52). When it is determined that the absolute value of Xvw is the maximum and Xv is a negative value (S47: NO), the command value signal Xu2 is set to Xuv, the command value signal Xv2 is set to “0”, and the command value The signal Xw2 is a negative value of Xvw (S53).

  In the case of the mode 1 state shown in FIG. 11A, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pv has a negative value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the phase voltage command value signal Xv becomes a negative value (S47: NO in FIG. 12). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu2 is set to Xuv, Xv2 is set to “0”, and Xw2 is set to a negative value of Xvw (S53 in FIG. 12).

  In the mode 2 state shown in FIG. 11B, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Pu has a positive value. That is, the absolute value of the line voltage command value signal Xuv is maximized, and the phase voltage command value signal Xu is a positive value (S45: YES in FIG. 12). At this time, the Y coordinates of the vertices u, v, and w are respectively B (in FIG. 12, since the case of B = “2” has been described, it is referred to as “2” below). A value obtained by adding the Y coordinate of the vector Pvu to “2” (ie, a value obtained by subtracting the Y coordinate of the vector Puv from “2”), and a value obtained by adding the Y coordinate of the vector Pwu to “2”. Therefore, Xu2 is “2”, Xv2 is a value obtained by subtracting Xuv from “2”, and Xw2 is a value obtained by adding Xwu to “2” (S48 in FIG. 12).

  In the mode 3 state shown in FIG. 11C, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pw has a negative value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the phase voltage command value signal Xw becomes a negative value (S46: NO in FIG. 12). At this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Therefore, Xu2 is a negative value of Xwu, Xv2 is Xvw, and Xw2 is “0” (S51 in FIG. 12).

  In the mode 4 state shown in FIG. 11D, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pv is a positive value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the phase voltage command value signal Xv becomes a positive value (S47: YES in FIG. 12). At this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. Therefore, Xu2 is a value obtained by adding Xuv to “2”, Xv2 is “2”, and Xw2 is a value obtained by subtracting Xvw from “2” (S52 in FIG. 12).

  In the mode 5 state shown in FIG. 11 (e), the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Pu is a negative value. That is, the absolute value of the line voltage command value signal Xuv is maximized, and the phase voltage command value signal Xu is a negative value (S45: NO in FIG. 12). At this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu2 is set to “0”, Xv2 is set to a negative value of Xuv, and Xw2 is set to Xwu (S49 in FIG. 12).

  In the mode 6 state shown in FIG. 11 (f), the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pw is a positive value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the phase voltage command value signal Xw becomes a positive value (S46: YES in FIG. 12). At this time, the Y coordinates of the vertices u, v, and w are “2”, a value obtained by subtracting the Y coordinate of the vector Pwu from “2”, a value obtained by adding the Y coordinate of the vector Pvw to “2”, and “2”. Therefore, Xu2 is a value obtained by subtracting Xwu from “2”, Xv2 is a value obtained by adding Xvw to “2”, and Xw2 is “2” (S50 in FIG. 12).

  Note that the flowchart shown in FIG. 12 is an example of the command value signal generation process, and is not limited to this.

  The waveforms of the command value signals Xu2, Xv2, and Xw2 generated by the command value signal generation processing according to the second embodiment are as shown by waveforms Xu2, Xv2, and Xw2 shown in FIG.

  FIG. 13 is a diagram for explaining the waveforms of the command value signals Xu2, Xv2, and Xw2.

  The waveforms Xuv, Xvw, and Xwu shown in FIG. 13A are the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. 32A, and the waveforms Xvu, Xwv, and Xwu shown in FIG. Since it is the same as the waveforms Xvu, Xwv, and Xuw shown in FIG. Also in FIG. 13, the phase of the phase voltage command value signal Xu is described as a reference.

  Waveforms Xu2, Xv2, and Xw2 shown in FIG. 13C are the waveforms of the command value signals Xu2, Xv2, and Xw2, respectively. As described with reference to FIGS. 11 and 12, the command value signals Xu2, Xv2, and Xw2 are generated separately in modes 1 to 6. FIG. 13C shows each waveform when B = 2.

  In mode 1 (−π / 6 ≦ θ ≦ π / 6), the process proceeds to step S53 in the flowchart of FIG. 12, so that the waveform Xu2 becomes the waveform Xuv (see FIG. 13A), and the waveform Xv2 becomes “0”. The waveform becomes fixed, and the waveform Xw2 becomes the waveform Xwv (see FIG. 13B). Further, in mode 2 (π / 6 ≦ θ ≦ π / 2), the process proceeds to step S48 in the flowchart of FIG. ”And the waveform Xw2 is a waveform obtained by shifting the waveform Xwu upward by“ 2 ”. In mode 3 (π / 2 ≦ θ ≦ 5π / 6), the process proceeds to step S51 in the flowchart of FIG. 12, so that waveform Xu2 becomes waveform Xuw, waveform Xv2 becomes waveform Xvw, and waveform Xw2 is fixed to “0”. Waveform. In mode 4 (5π / 6 ≦ θ ≦ 7π / 6), since the process proceeds to step S52 in the flowchart of FIG. 12, the waveform Xu2 is a waveform obtained by shifting the waveform Xuv upward by “2”, and the waveform Xv2 is “2”. The waveform Xw2 is a waveform obtained by shifting the waveform Xwv upward by “2”. In mode 5 (7π / 6 ≦ θ ≦ 3π / 2), the process proceeds to step S49 in the flowchart of FIG. 12, so that the waveform Xu2 becomes a waveform fixed to “0”, the waveform Xv2 becomes the waveform Xvu, and the waveform Xw2 becomes Waveform Xwu is obtained. In mode 6 (3π / 2 ≦ θ ≦ 11π / 6), the process proceeds to step S50 in the flowchart of FIG. 12, so waveform Xu2 is a waveform obtained by shifting waveform Xuw upward by “2”, and waveform Xv2 is waveform Xvw. Is shifted upward by “2”, and the waveform Xw2 is a waveform fixed at “2”.

  As is apparent from FIG. 13, the difference signal between the command value signals Xu2 and Xv2, the difference signal between Xv2 and Xw2, and the difference signal between Xw2 and Xu2 respectively match the line voltage command value signals Xuv, Xvw, and Xwu. To do. Therefore, the difference between the line voltage signals Vuv and Vv2 which are the difference signals between the phase voltage signals Vu2 and Vv2 output from the grid interconnection inverter system A and the difference between the line voltage signals Vvw and Vw2 which are the difference signals between Vv2 and Vw2. The waveform of the line voltage signal Vwu that is a signal is the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. That is, the line voltage signals Vuv, Vvw, and Vwu are sine wave signals balanced in three phases, and can be synchronized with the system voltage of the system B. Therefore, the AC power output from the grid interconnection inverter system A can be supplied to the grid B.

  The command value signals Xu2, Xv2, and Xw2 are fixed to “0” at 1/6 of the cycle and fixed to “2” at 1/6 of the cycle (waveforms Xu2, Xv2, FIG. 13C). Xw2). Therefore, the same effect as that of the first embodiment can be obtained.

  Also in the second embodiment, similarly to the first embodiment, the lower limit value and the upper limit value of the command value signals Xu2, Xv2, and Xw2 are not limited. For example, the command value signals Xu2, Xv2, and Xw2 may be generated so that the lower limit value is “−1” and the upper limit value is “1”. In this case, it is necessary to set the lower limit value and the upper limit value of the carrier signal used in the PWM signal generation unit 53 according to the lower limit value and the upper limit value of the command value signals Xu2, Xv2, and Xw2.

  Next, a third embodiment will be described.

  FIG. 14 is a diagram for explaining the concept of control according to the third embodiment in terms of vectors.

  The control concept of the third embodiment shown in FIG. 14 is the same as the control concept of the first embodiment shown in FIG. The point whose coordinates are B). However, the timing at which the fixed vertex is switched is different between the third embodiment and the first embodiment. In FIG. 14, the neutral point N, the vector Pu, and the equilateral triangle T are shown as in FIG. Yes. Moreover, in each figure, the white vertex is attached | subjected to the fixed vertex.

  FIG. 5A shows a state where the angle θ (the angle that the vector Pu makes with the X axis) changes from 0 to π / 3. When 0 ≦ θ ≦ π / 3, the vertex v of the equilateral triangle T is fixed at the origin, and the equilateral triangle T is counterclockwise around the vertex v (in the direction of the broken line arrow shown in the figure, and the same applies hereinafter) )). This state is referred to as “mode 1”. FIG. 5A shows that in mode 1, the V-phase potential is fixed at “0”. The left figure shows when θ = 0, the middle figure shows when θ = π / 6, and the right figure shows when θ = π / 3. When θ = π / 3, the equilateral triangle T moves so that the vertex u coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to “0” changes to the state in which the U-phase potential is fixed to B.

  FIG. 5B shows a state when the angle θ changes from π / 3 to 2π / 3. When π / 3 ≦ θ ≦ 2π / 3, the vertex u of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 3 around the vertex u. This state is referred to as “mode 2”. FIG. 4B shows that in mode 2, the U-phase potential is fixed to B. The left figure shows θ = π / 3, the middle figure shows θ = π / 2, and the right figure shows θ = 2π / 3. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 2π / 3, the equilateral triangle T moves so that the vertex w coincides with the origin, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to B changes to the state in which the W-phase potential is fixed to “0”.

  FIG. 4C shows a state when the angle θ changes from 2π / 3 to π (= 3π / 3). When 2π / 3 ≦ θ ≦ π, the vertex w of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 3 around the vertex w. This state is referred to as “mode 3”. FIG. 5C shows that in mode 3, the W-phase potential is fixed to “0”. The left figure shows θ = 2π / 3, the middle figure shows θ = 5π / 6, and the right figure shows θ = π. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = π, the equilateral triangle T moves so that the vertex v coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to “0” changes to the state in which the V-phase potential is fixed to B.

  FIG. 4D shows a state when the angle θ changes from π to 4π / 3. When π ≦ θ ≦ 4π / 3, the vertex v of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates π / 3 counterclockwise around the vertex v. This state is referred to as “mode 4”. FIG. 4D shows that the V-phase potential is fixed to B in mode 4. The left diagram shows the case when θ = π, the middle diagram shows the case when θ = 7π / 6, and the right diagram shows the case when θ = 4π / 3. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 4π / 3, the equilateral triangle T moves so that the vertex u coincides with the origin, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to B changes to the state in which the U-phase potential is fixed to “0”.

  FIG. 5E shows a state when the angle θ changes from 4π / 3 to 5π / 3. When 4π / 3 ≦ θ ≦ 5π / 3, the vertex u of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 3 around the vertex u. This state is referred to as “mode 5”. FIG. 5E shows that in mode 5, the U-phase potential is fixed at “0”. The left diagram shows the case when θ = 4π / 3, the middle diagram shows the case when θ = 3π / 2 (= 9π / 6), and the right diagram shows the case when θ = 5π / 3. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 5π / 3, the equilateral triangle T moves so that the vertex w coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to “0” changes to the state in which the W-phase potential is fixed to B.

  FIG. 5F shows a state when the angle θ changes from 5π / 3 to 2π (= 6π / 3 = 0). When 5π / 3 ≦ θ ≦ 2π, the vertex w of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 3 around the vertex w. This state is referred to as “mode 6”. FIG. 5F shows that in mode 6, the W-phase potential is fixed to B. The left figure shows θ = 5π / 3, the middle figure shows θ = 11π / 6, and the right figure shows θ = 2π. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 2π, the equilateral triangle T moves so that the vertex v coincides with the origin, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to B changes to the state in which the V-phase potential is fixed to “0”. The figure after this transition is the same as the left figure of FIG. Thereafter, modes 1 to 6 are repeated.

  In the vector diagram shown in FIG. 14, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. In mode 1, since the vertex v is fixed at the origin, the orthogonal projection on the Y axis of the vector Puv from the vertex v to the vertex u becomes the U-phase phase voltage (see FIG. 5A). Therefore, in mode 1, the command value signal Xu3 may be the line voltage command value signal Xuv. In mode 2, the vertex u is fixed at the maximum point, so the phase voltage of the U phase is B (see FIG. 5B). Therefore, in mode 2, the command value signal Xu3 may be a signal whose value is B. In mode 3, since the vertex w is fixed at the origin, the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y-axis becomes the U-phase phase voltage (see FIG. 3C). Therefore, in mode 3, the command value signal Xu3 may be the signal Xuw (= −Xwu). In mode 4, since the vertex v is fixed at the maximum point, the value obtained by adding B to the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y axis is the U-phase phase voltage (FIG. d)). Therefore, in mode 4, the command value signal Xu3 may be obtained by adding B to the signal Xuv. In mode 5, since the vertex u is fixed at the origin, the phase voltage of the U phase is “0” (see FIG. 5E). Therefore, in mode 5, the command value signal Xu3 may be a zero signal whose value is “0”. In mode 6, since the vertex w is fixed at the maximum point, the value obtained by adding B to the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y axis is the U-phase phase voltage (FIG. f)). Therefore, in mode 6, the command value signal Xu3 may be obtained by adding B to the signal Xuw (= −Xwu).

  Similarly, V-phase command value signal Xv3 is a zero signal in mode 1, B is added to signal Xvu in mode 2, line voltage command value signal Xvw in mode 3, and mode 4 Is a signal having a value of B, a signal Xvu in mode 5, and a signal obtained by adding B to the line voltage command value signal Xvw in mode 6. The W-phase command value signal Xw3 is the signal Xwv in mode 1, B is added to the line voltage command value signal Xwu in mode 2, the zero signal in mode 3, and the mode 4 It is assumed that B is added to the signal Xwv, the line voltage command value signal Xwu is set in the mode 5, and the signal having the value B is set in the mode 6.

  FIG. 15 is a flowchart for explaining command value signal generation processing performed by the command value signal generation unit 52 according to the third embodiment. The command value signal generation process is executed at a predetermined timing.

  The flowchart shown in the figure is that the command value signal generation processing according to the first embodiment is determined in that the absolute value of the phase voltage command value signals Xu, Xv, Xw is determined in steps S62 to S64. Different from the flowchart (see FIG. 8).

  First, phase voltage command value signals Xu, Xv, Xw and line voltage command value signals Xuv, Xvw, Xwu are acquired (S61). Next, it is determined whether or not the absolute value of Xu is larger than the absolute value of Xv (S62). If the absolute value of Xu is larger (S62: YES), it is determined whether or not the absolute value of Xu is larger than the absolute value of Xw (S63). When the absolute value of Xu is larger (S63: YES), that is, when the absolute value of Xu is the maximum, the process proceeds to step S65. On the other hand, if the absolute value of Xu is less than or equal to the absolute value of Xw (S63: NO), that is, if the absolute value of Xw is the maximum, the process proceeds to step S66. In step S62, when the absolute value of Xu is equal to or smaller than the absolute value of Xv (S62: NO), it is determined whether or not the absolute value of Xv is larger than the absolute value of Xw (S64). When the absolute value of Xv is larger (S64: YES), that is, when the absolute value of Xv is the maximum, the process proceeds to step S67. On the other hand, if the absolute value of Xv is less than or equal to the absolute value of Xw (S64: NO), that is, if the absolute value of Xw is maximum, the process proceeds to step S66. In steps S62 to S64, it is determined which of Xu, Xv, and Xw has the maximum absolute value.

  When it is determined that the absolute value of Xu is the maximum and the process proceeds to step S65, it is determined whether Xu is a positive value (S65). When Xu is a positive value (S65: YES), the command value signal Xu3 is “2”, the command value signal Xv3 is a value obtained by subtracting Xuv from “2”, and the command value signal Xw3 is “2”. Xwu is added to (S68). On the other hand, when Xu is equal to or smaller than “0” (S65: NO), Xu3 is set to “0”, Xv3 is set to a negative value of Xuv, and Xw3 is set to Xwu (S69).

  When it is determined that the absolute value of Xw is the maximum and the process proceeds to step S66, it is determined whether Xw is a positive value (S66). When Xw is a positive value (S66: YES), Xu3 is a value obtained by subtracting Xwu from “2”, Xv3 is a value obtained by adding Xvw to “2”, and Xw3 is set to “2”. (S70). On the other hand, when Xw is “0” or less (S66: NO), Xu3 is set to a negative value of Xwu, Xv3 is set to Xvw, and Xw3 is set to “0” (S71).

  When it is determined that the absolute value of Xv is the maximum and the process proceeds to step S67, it is determined whether Xv is a positive value (S67). When Xv is a positive value (S67: YES), Xu3 is a value obtained by adding Xuv to “2”, Xv3 is set to “2”, and Xw3 is a value obtained by subtracting Xvw from “2”. (S72). On the other hand, when Xv is “0” or less (S67: NO), Xu3 is set to Xuv, Xv3 is set to “0”, and Xw3 is set to a negative value of Xvw (S73).

  That is, in the command value signal generation processing according to the third embodiment, the phase voltage command value signal Xu, Xv, Xw is determined with the maximum absolute value, and the sign of the phase voltage command value signal with the maximum absolute value is determined. The command value signals Xu3, Xv3, and Xw3 are determined according to the determination result. That is, it is determined which mode is in the vector diagram shown in FIG. 14, and the command value signals Xu3, Xv3, and Xw3 for each phase are determined so as to correspond to the vector diagram of the determined mode.

  In the case of the mode 1 state shown in FIG. 14A, the length of the orthogonal projection of the vector Pv on the Y axis is the maximum, and the Y coordinate of the vector Pv is a negative value. That is, the absolute value of the phase voltage command value signal Xv becomes the maximum, and the phase voltage command value signal Xv becomes a negative value (S67: NO in FIG. 15). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu3 is set to Xuv, Xv3 is set to “0”, and Xw3 is set to a negative value of Xvw (S73 in FIG. 15).

  In the mode 2 state shown in FIG. 14B, the length of the orthogonal projection of the vector Pu on the Y axis is the maximum, and the Y coordinate of the vector Pu has a positive value. That is, the absolute value of phase voltage command value signal Xu is maximized, and phase voltage command value signal Xu is a positive value (S65: YES in FIG. 15). At this time, the Y coordinates of the vertices u, v, and w are respectively B (in FIG. 15, since the case of B = “2” is described, it is referred to as “2” below). A value obtained by adding the Y coordinate of the vector Pvu to “2” (ie, a value obtained by subtracting the Y coordinate of the vector Puv from “2”), and a value obtained by adding the Y coordinate of the vector Pwu to “2”. Therefore, Xu3 is “2”, Xv3 is a value obtained by subtracting Xuv from “2”, and Xw3 is a value obtained by adding Xwu to “2” (S68 in FIG. 15).

  In the mode 3 state shown in FIG. 14C, the length of the orthogonal projection of the vector Pw on the Y axis is the maximum, and the Y coordinate of the vector Pw has a negative value. That is, the absolute value of the phase voltage command value signal Xw becomes the maximum, and the phase voltage command value signal Xw becomes a negative value (S66: NO in FIG. 15). At this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Therefore, Xu3 is a negative value of Xwu, Xv3 is Xvw, and Xw3 is “0” (S71 in FIG. 15).

  In the mode 4 state shown in FIG. 14D, the length of the orthogonal projection of the vector Pv on the Y axis is the maximum, and the Y coordinate of the vector Pv is a positive value. That is, the absolute value of the phase voltage command value signal Xv becomes the maximum, and the phase voltage command value signal Xv becomes a positive value (S67: YES in FIG. 15). At this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. Therefore, Xu3 is set to a value obtained by adding Xuv to “2”, Xv3 is set to “2”, and Xw3 is set to a value obtained by subtracting Xvw from “2” (S72 in FIG. 15).

  In the mode 5 state shown in FIG. 14 (e), the length of the orthogonal projection of the vector Pu on the Y axis is the maximum, and the Y coordinate of the vector Pu is a negative value. That is, the absolute value of phase voltage command value signal Xu is maximized and phase voltage command value signal Xu is a negative value (S65: NO in FIG. 15). At this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu3 is set to “0”, Xv3 is set to a negative value of Xuv, and Xw3 is set to Xwu (S69 in FIG. 15).

  In the state of mode 6 shown in FIG. 14F, the length of the orthogonal projection of the vector Pw on the Y axis is the maximum, and the Y coordinate of the vector Pw is a positive value. That is, the absolute value of the phase voltage command value signal Xw becomes the maximum, and the phase voltage command value signal Xw becomes a positive value (S66: YES in FIG. 15). At this time, the Y coordinates of the vertices u, v, and w are “2”, a value obtained by subtracting the Y coordinate of the vector Pwu from “2”, a value obtained by adding the Y coordinate of the vector Pvw to “2”, and “2”. Therefore, Xu3 is set to a value obtained by subtracting Xwu from “2”, Xv3 is set to a value obtained by adding Xvw to “2”, and Xw3 is set to “2” (S70 in FIG. 15).

  Note that the flowchart shown in FIG. 15 is an example of command value signal generation processing, and is not limited to this.

  The waveforms of the command value signals Xu3, Xv3, and Xw3 generated by the command value signal generation processing according to the third embodiment are as shown by waveforms Xu3, Xv3, and Xw3 shown in FIG.

  FIG. 16 is a diagram for explaining the waveforms of the command value signals Xu3, Xv3, and Xw3.

  The waveforms Xuv, Xvw, and Xwu shown in FIG. 16A are the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. 32A, and the waveforms Xvu, Xwv, and Xwu shown in FIG. Since it is the same as the waveforms Xvu, Xwv, and Xuw shown in FIG. Also in FIG. 16, the phase of the phase voltage command value signal Xu is described as a reference.

  Waveforms Xu3, Xv3, and Xw3 shown in FIG. 16C are the waveforms of the command value signals Xu3, Xv3, and Xw3, respectively. As described with reference to FIGS. 14 and 15, the command value signals Xu3, Xv3, and Xw3 are generated by being divided into modes 1 to 6. FIG. 16C shows each waveform when B = 2.

  In mode 1 (0 ≦ θ ≦ π / 3), the process proceeds to step S73 in the flowchart of FIG. Waveform Xw3 becomes waveform Xwv (see FIG. 16B). Further, in mode 2 (π / 3 ≦ θ ≦ 2π / 3), the process proceeds to step S68 in the flowchart of FIG. ”And the waveform Xw3 is a waveform obtained by shifting the waveform Xwu upward by“ 2 ”. In mode 3 (2π / 3 ≦ θ ≦ π), the process proceeds to step S71 in the flowchart of FIG. 15, so that the waveform Xu3 becomes the waveform Xuw, the waveform Xv3 becomes the waveform Xvw, and the waveform Xw3 is fixed to “0”. It becomes. In mode 4 (π ≦ θ ≦ 4π / 3), the process proceeds to step S72 in the flowchart of FIG. The waveform Xw3 is a waveform obtained by shifting the waveform Xwv upward by “2”. In mode 5 (4π / 3 ≦ θ ≦ 5π / 3), since the process proceeds to step S69 in the flowchart of FIG. 15, the waveform Xu3 becomes a waveform fixed to “0”, the waveform Xv3 becomes the waveform Xvu, and the waveform Xw3 becomes Waveform Xwu is obtained. In mode 6 (5π / 3 ≦ θ ≦ 2π), the process proceeds to step S70 in the flowchart of FIG. 15. Therefore, the waveform Xu3 is a waveform obtained by shifting the waveform Xuw upward by “2”, and the waveform Xv3 The waveform is shifted upward by 2 ”, and the waveform Xw3 is a waveform fixed at“ 2 ”.

  As is apparent from FIG. 16, the difference signal between the command value signals Xu3 and Xv3, the difference signal between Xv3 and Xw3, and the difference signal between Xw3 and Xu3 match the line voltage command value signals Xuv, Xvw, Xwu, respectively. To do. Therefore, the line voltage signals Vuv, which are the difference signals between the phase voltage signals Vu3 and Vv3 output from the grid interconnection inverter system A, and the differences between the line voltage signals Vvw, Vw3 and Vu3 which are the difference signals between Vv3 and Vw3. The waveform of the line voltage signal Vwu that is a signal is the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. That is, the line voltage signals Vuv, Vvw, and Vwu are sine wave signals balanced in three phases, and can be synchronized with the system voltage of the system B. Therefore, the AC power output from the grid interconnection inverter system A can be supplied to the grid B.

  Further, the command value signals Xu3, Xv3, and Xw3 are fixed to “0” at 1/6 of the cycle and fixed to “2” at 1/6 of the cycle (the waveforms Xu3, Xv3, FIG. 16C). Xw3). Therefore, the same effect as that of the first embodiment can be obtained.

  Also in the third embodiment, similarly to the first embodiment, the lower limit value and the upper limit value of the command value signals Xu3, Xv3, Xw3 are not limited. For example, the command value signals Xu3, Xv3, and Xw3 may be generated so that the lower limit value is “−1” and the upper limit value is “1”. In this case, it is necessary to set the lower limit value and the upper limit value of the carrier signal used in the PWM signal generation unit 53 according to the lower limit value and the upper limit value of the command value signals Xu3, Xv3, and Xw3.

  In the first to third embodiments, the case where one cycle of the command value signal is divided into six modes has been described, but the present invention is not limited to this. For example, one cycle of the command value signal may be divided into 12 modes, and the phase to be fixed when the mode is switched may be changed. Even in this case, the command value signal is fixed to the lower limit value in two modes and fixed to the upper limit value in two modes. Accordingly, the time during which the generated PWM signal continues to be at the high level is equal to the time during which the generated PWM signal continues to be at the low level, so that the time during which the positive-side switching element is on and the negative-side switching The time during which the element is on can be made equal. Therefore, even in this case, the same effect as the first to third embodiments can be obtained. The same applies when one cycle of the command value signal is divided into 24 modes or 36 modes. In addition, since switching may be necessary at the time of mode switching, the number of times of switching increases as the number of modes increases. Therefore, the smaller the number of modes, the better. The first to third embodiments having six modes are more effective.

  A case where one cycle of the command value signal is divided into 12 modes will be described below as a fourth embodiment.

  FIGS. 17 and 18 are diagrams for explaining the concept of control according to the fourth embodiment in terms of vectors.

  The control concept of the fourth embodiment shown in FIG. 17 and FIG. 18 is similar to the control concept of the first embodiment shown in FIG. ”And a point whose Y coordinate is B). However, the timing at which the fixed vertex is switched differs between the fourth embodiment and the first embodiment. 17 and 18, the neutral point N, the vector Pu, and the equilateral triangle T are shown as in FIG. 3, and the vectors Pv and Pw are described except for the left diagram in FIG. Omitted. Moreover, in each figure, the white vertex is attached | subjected to the fixed vertex.

  FIG. 17A shows a state where the angle θ (the angle that the vector Pu makes with the X axis) changes from 0 to π / 6. When 0 ≦ θ ≦ π / 6, the vertex w of the regular triangle T is fixed at the maximum point, and the regular triangle T is counterclockwise around the vertex w (in the direction of the broken line arrow shown in the figure, and the same applies hereinafter) There is a π / 6 rotation. This state is referred to as “mode 1”. FIG. 5A shows that the W-phase potential is fixed to B in mode 1. The left figure shows the case when θ = 0, and the right figure shows the case when θ = π / 6.

  FIG. 17B shows a state when the angle θ changes from π / 6 to π / 3 (= 2π / 6). When π / 6 ≦ θ ≦ π / 3, the vertex u of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 6 around the vertex u. This state is referred to as “mode 2”. FIG. 4B shows that in mode 2, the U-phase potential is fixed to B. The left figure shows the case when θ = π / 6, and the right figure shows the case when θ = π / 3. The left figure is obtained by changing the point fixed to the maximum point from the vertex w to the vertex u in the right figure of FIG. When θ = π / 3, the equilateral triangle T moves so that the vertex v coincides with the origin, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to B changes to the state in which the V-phase potential is fixed to “0”.

  FIG. 17C shows a state when the angle θ changes from π / 3 to π / 2 (= 3π / 6). When π / 3 ≦ θ ≦ π / 2, the vertex v of the regular triangle T is fixed at the origin, and the regular triangle T rotates π / 6 counterclockwise around the vertex v. This state is referred to as “mode 3”. FIG. 5C shows that in mode 3, the V-phase potential is fixed at “0”. The left figure shows the case when θ = π / 3, and the right figure shows the case when θ = π / 2.

  FIG. 17D shows a state when the angle θ changes from π / 2 to 2π / 3 (= 4π / 6). When π / 2 ≦ θ ≦ 2π / 3, the vertex w of the regular triangle T is fixed at the origin, and the regular triangle T rotates π / 6 counterclockwise around the vertex w. This state is referred to as “mode 4”. FIG. 4D shows that in mode 4, the W-phase potential is fixed to “0”. The left figure shows the case when θ = π / 2, and the right figure shows the case when θ = 2π / 3. The left figure is obtained by changing the point fixed to the origin from the vertex v to the vertex w in the right figure of FIG. When θ = 2π / 3, the equilateral triangle T moves so that the vertex u coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to “0” changes to the state in which the U-phase potential is fixed to B.

  FIG. 17E shows a state where the angle θ changes from 2π / 3 to 5π / 6. When 2π / 3 ≦ θ ≦ 5π / 6, the vertex u of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 6 around the vertex u. This state is referred to as “mode 5”. FIG. 4E shows that in mode 5, the U-phase potential is fixed to B. The left figure shows the case when θ = 2π / 3, and the right figure shows the case when θ = 5π / 6.

  FIG. 17F shows a state where the angle θ changes from 5π / 6 to π (= 6π / 6). When 5π / 6 ≦ θ ≦ π, the vertex v of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 6 around the vertex v. This state is referred to as “mode 6”. FIG. 5F shows that in mode 6, the V-phase potential is fixed to B. The left figure shows when θ = 5π / 6, and the right figure shows when θ = π. The left figure is obtained by changing the point fixed to the maximum point from the vertex u to the vertex v in the right figure of FIG. When θ = π, the equilateral triangle T moves so that the vertex w coincides with the origin, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to B changes to the state in which the W-phase potential is fixed to “0”.

  FIG. 18A shows a state when the angle θ changes from π to 7π / 6. When π ≦ θ ≦ 7π / 6, the vertex w of the regular triangle T is fixed at the origin, and the regular triangle T rotates π / 6 counterclockwise around the vertex w. This state is referred to as “mode 7”. FIG. 5A shows that in mode 7, the W-phase potential is fixed to “0”. The left figure shows when θ = π, and the right figure shows when θ = 7π / 6.

  FIG. 18B shows a state when the angle θ changes from 7π / 6 to 4π / 3 (= 8π / 6). When 7π / 6 ≦ θ ≦ 4π / 3, the vertex u of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 6 around the vertex u. This state is referred to as “mode 8”. FIG. 4B shows that in mode 8, the U-phase potential is fixed at “0”. The figure on the left shows when θ = 7π / 6, and the figure on the right shows when θ = 4π / 3. The left figure is obtained by changing the point fixed to the origin from the vertex w to the vertex u in the right figure of FIG. When θ = 4π / 3, the equilateral triangle T moves so that the vertex v coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the U-phase potential is fixed to “0” changes to the state in which the V-phase potential is fixed to B.

  FIG. 18C shows a state when the angle θ changes from 4π / 3 to 3π / 2 (= 9π / 6). When 4π / 3 ≦ θ ≦ 3π / 2, the vertex v of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 6 around the vertex v. This state is referred to as “mode 9”. FIG. 5C shows that in mode 9, the V-phase potential is fixed to B. The left figure shows the case when θ = 4π / 3, and the right figure shows the case when θ = 3π / 2.

  FIG. 18D shows a state when the angle θ changes from 3π / 2 to 5π / 3 (= 10π / 6). When 3π / 2 ≦ θ ≦ 5π / 3, the vertex w of the regular triangle T is fixed at the maximum point, and the regular triangle T rotates counterclockwise by π / 6 around the vertex w. This state is referred to as “mode 10”. FIG. 4D shows that the W-phase potential is fixed to B in mode 10. The figure on the left shows when θ = 3π / 2, and the figure on the right shows when θ = 5π / 3. The left figure is obtained by changing the point fixed to the maximum point from the vertex v to the vertex w in the right figure of FIG. When θ = 5π / 3, the equilateral triangle T moves so that the vertex u coincides with the origin, and the neutral point N transitions. This indicates that the state in which the W-phase potential is fixed to B changes to the state in which the U-phase potential is fixed to “0”.

  FIG. 18E shows a state where the angle θ changes from 5π / 3 to 11π / 6. When 5π / 3 ≦ θ ≦ 11π / 6, the vertex u of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 6 around the vertex u. This state is referred to as “mode 11”. FIG. 5E shows that in mode 11, the U-phase potential is fixed at “0”. The left figure shows the case when θ = 5π / 3, and the right figure shows the case when θ = 11π / 6.

  FIG. 18F shows a state where the angle θ changes from 11π / 6 to 2π (= 12π / 6). When 11π / 6 ≦ θ ≦ 2π, the vertex v of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by π / 6 around the vertex v. This state is referred to as “mode 12”. FIG. 5F shows that in the mode 12, the V-phase potential is fixed to “0”. The figure on the left shows when θ = 11π / 6, and the figure on the right shows when θ = 2π. The left figure is obtained by changing the point fixed to the origin from the vertex u to the vertex v in the right figure of FIG. When θ = 2π, the equilateral triangle T moves so that the vertex w coincides with the maximum point, and the neutral point N transitions. This indicates that the state in which the V-phase potential is fixed to “0” changes to the state in which the W-phase potential is fixed to B. The diagram after this transition is the same as the diagram on the left in FIG. Thereafter, modes 1 to 12 are repeated.

  In the vector diagrams shown in FIGS. 17 and 18, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. In mode 1, since the vertex w is fixed at the maximum point, the value obtained by adding B to the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y axis is the U-phase phase voltage (FIG. 17 ( a)). Therefore, in mode 1, the command value signal Xu4 may be obtained by adding B to the signal Xuw (= −Xwu). In mode 2, the vertex u is fixed at the maximum point, so the phase voltage of the U phase is B (see FIG. 5B). Therefore, in mode 2, the command value signal Xu4 may be a signal whose value is B. In mode 3, since the vertex v is fixed at the origin, the orthogonal projection onto the Y axis of the vector Puv from the vertex v to the vertex u becomes the U-phase phase voltage (see FIG. 3C). Therefore, in mode 3, the command value signal Xu4 may be the line voltage command value signal Xuv. In mode 4, since the vertex w is fixed at the origin, the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y-axis becomes the U-phase phase voltage (see FIG. 4D). Therefore, in mode 4, the command value signal Xu4 may be the signal Xuw. In mode 5, since the vertex u is fixed at the maximum point, the phase voltage of the U phase is B (see (e) in the figure). Therefore, in mode 5, the command value signal Xu4 may be a signal whose value is B. In mode 6, the vertex v is fixed at the maximum point, so the value obtained by adding B to the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y axis is the U-phase phase voltage (FIG. f)). Therefore, in mode 6, the command value signal Xu4 may be obtained by adding B to the line voltage command value signal Xuv.

  In mode 7, since the vertex w is fixed at the origin, the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y-axis becomes the U-phase phase voltage (see FIG. 18A). Therefore, in mode 7, the command value signal Xu4 may be the signal Xuw. In mode 8, the apex u is fixed at the origin, so the phase voltage of the U phase is “0” (see FIG. 5B). Therefore, in mode 8, the command value signal Xu4 may be a zero signal whose value is “0”. In mode 9, the vertex v is fixed at the maximum point, so the value obtained by adding B to the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y axis is the U-phase phase voltage (FIG. c)). Therefore, in mode 9, the command value signal Xu4 may be a value obtained by adding B to the line voltage command value signal Xuv. In mode 10, since the vertex w is fixed at the maximum point, the value obtained by adding B to the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y axis is the U-phase voltage (see FIG. d)). Therefore, in mode 10, the command value signal Xu4 may be a value obtained by adding B to the signal Xuw. In mode 11, since the vertex u is fixed at the origin, the phase voltage of the U phase is “0” (see (e) in the figure). Therefore, in mode 11, the command value signal Xu4 may be a zero signal whose value is “0”. In mode 12, the vertex v is fixed at the origin, so that the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y-axis becomes the U-phase phase voltage (see FIG. 8F). Therefore, in mode 12, the command value signal Xu4 may be the line voltage command value signal Xuv.

  Similarly, V-phase command value signal Xv4 is obtained by adding B to line voltage command value signal Xvw in mode 1, adding B to signal Xvu in mode 2, and zero in mode 3. The signal is a line voltage command value signal Xvw in mode 4, B is added to the signal Xvu in mode 5, a signal having a value B in mode 6, and a line voltage command signal in mode 7 The value signal is Xvw, the signal is Xvu in mode 8, the value is B in mode 9, the value obtained by adding B to the line voltage command value signal Xvw in mode 10, and the signal Xvu in mode 11 In mode 12, a zero signal may be used. The W-phase command value signal Xw4 is a signal having a value of B in mode 1, B is added to the line voltage command value signal Xwu in mode 2, and a signal Xwv in mode 3. In mode 4, the signal is zero, in mode 5, B is added to the line voltage command value signal Xwu, in mode 6, B is added to signal Xwv, in mode 7, the signal is zero, 8 is the line voltage command value signal Xwu, mode 9 is the signal Xwv plus B, mode 10 is the value B, and mode 11 is the line voltage command value signal Xwu. In mode 12, the signal Xwv may be used.

  FIG. 19 is a flowchart for explaining the command value signal generation processing performed by the command value signal generation unit 52 according to the fourth embodiment. The command value signal generation process is executed at a predetermined timing.

  The flowchart shown in the figure is that command values according to the first embodiment are determined in steps S81 to 86 in which intermediate values of the absolute values of the phase voltage command value signals Xu, Xv, and Xw are determined. This is different from the signal generation processing flowchart (see FIG. 8).

  First, phase voltage command value signals Xu, Xv, Xw and line voltage command value signals Xuv, Xvw, Xwu are acquired (S81). Next, it is determined whether or not the absolute value of Xu is larger than the absolute value of Xv (S82). When the absolute value of Xu is larger (S82: YES), it is determined whether or not the absolute value of Xv is larger than the absolute value of Xw (S83). If the absolute value of Xv is larger (S83: YES), that is, if the absolute value of Xv is an intermediate value, the process proceeds to step S87. On the other hand, if the absolute value of Xv is less than or equal to the absolute value of Xw (S83: NO), it is determined whether or not the absolute value of Xu is greater than the absolute value of Xw (S84). If the absolute value of Xu is larger (S84: YES), that is, if the absolute value of Xw is an intermediate value, the process proceeds to step S88. On the other hand, if the absolute value of Xu is equal to or smaller than the absolute value of Xw (S84: NO), that is, if the absolute value of Xu is an intermediate value, the process proceeds to step S89. If the absolute value of Xu is less than or equal to the absolute value of Xv in step S82 (S82: NO), it is determined whether or not the absolute value of Xv is greater than the absolute value of Xw (S85). When the absolute value of Xv is larger (S85: YES), it is determined whether or not the absolute value of Xu is larger than the absolute value of Xw (S86). If the absolute value of Xu is larger (S86: YES), that is, if the absolute value of Xu is an intermediate value, the process proceeds to step S89. On the other hand, if the absolute value of Xu is less than or equal to the absolute value of Xw (S86: NO), that is, if the absolute value of Xw is intermediate, the process proceeds to step S88. In step S85, if the absolute value of Xv is equal to or smaller than the absolute value of Xw (S85: NO), that is, if the absolute value of Xv is an intermediate value, the process proceeds to step S87. In steps S82 to S86, the absolute value of Xu, Xv, and Xw is determined to have an intermediate size.

  When the absolute value of Xv is determined to be an intermediate value and the process proceeds to step S87, it is determined whether Xv is a positive value (S87). When Xv is a positive value (S87: YES), the command value signal Xu4 is a value obtained by adding Xuv to “2”, the command value signal Xv4 is “2”, and the command value signal Xw4 is “2”. Xvw is subtracted from (S90). On the other hand, when Xv is “0” or less (S87: NO), Xu4 is set to Xuv, Xv4 is set to “0”, and Xw4 is set to a negative value of Xvw (S91).

  When it is determined that the absolute value of Xw is an intermediate value and the process proceeds to step S88, it is determined whether Xw is a positive value (S88). When Xw is a positive value (S88: YES), Xu4 is a value obtained by subtracting Xwu from “2”, Xv4 is a value obtained by adding Xvw to “2”, and Xw4 is set to “2”. (S92). On the other hand, when Xw is “0” or less (S88: NO), Xu4 is set to a negative value of Xwu, Xv4 is set to Xvw, and Xw4 is set to “0” (S93).

  When it is determined that the absolute value of Xu is an intermediate value and the process proceeds to step S89, it is determined whether Xu is a positive value (S89). When Xu is a positive value (S89: YES), Xu4 is “2”, Xv4 is a value obtained by subtracting Xuv from “2”, and Xw4 is a value obtained by adding Xwu to “2”. (S94). On the other hand, when Xv is equal to or less than “0” (S89: NO), Xu4 is set to “0”, Xv4 is set to a negative value of Xuv, and Xw4 is set to Xwu (S95).

  That is, in the command value signal generation processing according to the fourth embodiment, the absolute value of the phase voltage command value signals Xu, Xv, and Xw is determined to have an intermediate magnitude, and the phase of the absolute value is an intermediate magnitude. Whether the voltage command value signal is positive or negative is determined, and the command value signals Xu4, Xv4, Xw4 are determined according to the determination result. That is, it is determined which mode is in the vector diagrams shown in FIGS. 17 and 18, and the command value signals Xu4, Xv4, and Xw4 for each phase are determined so as to correspond to the determined mode vector diagram. Yes.

  In the case of the mode 1 state shown in FIG. 17A, the length of the orthogonal projection of the vector Pw on the Y axis has an intermediate magnitude, and the Y coordinate of the vector Pw has a positive value. That is, the absolute value of the phase voltage command value signal Xw becomes an intermediate value, and the phase voltage command value signal Xw becomes a positive value (S88: YES in FIG. 19). At this time, the Y-coordinates of the vertices u, v, and w are respectively B (in FIG. 19, since the case of B = “2” has been described, it is referred to as “2” below). A value obtained by adding the value of the Y coordinate of the vector Puw (that is, a value obtained by subtracting the Y coordinate of the vector Pwu from “2”), a value obtained by adding the Y coordinate of the vector Pvw to “2”, and “2”. Therefore, Xu4 is set to a value obtained by subtracting Xwu from “2”, Xv4 is set to a value obtained by adding Xvw to “2”, and Xw4 is set to “2” (S92 in FIG. 19).

  In the state of mode 2 shown in FIG. 17B, the length of the orthogonal projection of the vector Pu on the Y-axis has an intermediate size, and the Y coordinate of the vector Pu has a positive value. That is, the absolute value of the phase voltage command value signal Xu has an intermediate magnitude, and the phase voltage command value signal Xu has a positive value (S89: YES in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are values obtained by subtracting the Y coordinate of the vector Puv from “2” and “2”, respectively, and the values obtained by adding the Y coordinate of the vector Pwu to “2”. Therefore, Xu4 is “2”, Xv4 is a value obtained by subtracting Xuv from “2”, and Xw4 is a value obtained by adding Xwu to “2” (S94 in FIG. 19).

  In the case of the mode 3 state shown in FIG. 17C, the length of the orthogonal projection of the vector Pv on the Y axis is an intermediate size, and the Y coordinate of the vector Pv is a negative value. That is, the absolute value of the phase voltage command value signal Xv becomes an intermediate magnitude, and the phase voltage command value signal Xv becomes a negative value (S87: NO in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu4 is set to Xuv, Xv4 is set to “0”, and Xw4 is set to a negative value of Xvw (S91 in FIG. 19).

  In the case of the mode 4 state shown in FIG. 17D, the length of the orthogonal projection of the vector Pw on the Y axis has an intermediate magnitude, and the Y coordinate of the vector Pw has a negative value. That is, the absolute value of the phase voltage command value signal Xw becomes an intermediate value, and the phase voltage command value signal Xw becomes a negative value (S88: NO in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Accordingly, Xu4 is a negative value of Xwu, Xv4 is Xvw, and Xw4 is “0” (S93 in FIG. 19).

  In the mode 5 state shown in FIG. 17E, the length of the orthogonal projection of the vector Pu on the Y-axis has an intermediate magnitude, and the Y coordinate of the vector Pu has a positive value. That is, the absolute value of the phase voltage command value signal Xu has an intermediate magnitude, and the phase voltage command value signal Xu has a positive value (S89: YES in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are values obtained by subtracting the Y coordinate of the vector Puv from “2” and “2”, respectively, and the values obtained by adding the Y coordinate of the vector Pwu to “2”. Therefore, Xu4 is “2”, Xv4 is a value obtained by subtracting Xuv from “2”, and Xw4 is a value obtained by adding Xwu to “2” (S94 in FIG. 19).

  In the state of mode 6 shown in FIG. 17 (f), the length of the orthogonal projection of the vector Pv on the Y-axis has an intermediate magnitude, and the Y coordinate of the vector Pv has a positive value. That is, the absolute value of the phase voltage command value signal Xv becomes an intermediate value, and the phase voltage command value signal Xv becomes a positive value (S87: YES in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. Therefore, Xu4 is a value obtained by adding Xuv to “2”, Xv4 is “2”, and Xw4 is a value obtained by subtracting Xvw from “2” (S90 in FIG. 19).

  In the state of mode 7 shown in FIG. 18A, the length of the orthogonal projection of the vector Pw on the Y-axis has an intermediate magnitude, and the Y coordinate of the vector Pw has a negative value. That is, the absolute value of the phase voltage command value signal Xw becomes an intermediate value, and the phase voltage command value signal Xw becomes a negative value (S88: NO in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Accordingly, Xu4 is a negative value of Xwu, Xv4 is Xvw, and Xw4 is “0” (S93 in FIG. 19).

  In the state of mode 8 shown in FIG. 18B, the length of the orthogonal projection of the vector Pu on the Y-axis has an intermediate magnitude, and the Y coordinate of the vector Pu has a negative value. That is, the absolute value of the phase voltage command value signal Xu has an intermediate magnitude, and the phase voltage command value signal Xu has a negative value (S89: NO in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu4 is set to “0”, Xv4 is set to a negative value of Xuv, and Xw4 is set to Xwu (S95 in FIG. 19).

  In the case of the mode 9 state shown in FIG. 18C, the length of the orthogonal projection of the vector Pv on the Y axis is an intermediate size, and the Y coordinate of the vector Pv is a positive value. That is, the absolute value of the phase voltage command value signal Xv becomes an intermediate value, and the phase voltage command value signal Xv becomes a positive value (S87: YES in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. Therefore, Xu4 is a value obtained by adding Xuv to “2”, Xv4 is “2”, and Xw4 is a value obtained by subtracting Xvw from “2” (S90 in FIG. 19).

  In the state of the mode 10 shown in FIG. 18D, the length of the orthogonal projection of the vector Pw on the Y-axis has an intermediate magnitude, and the Y coordinate of the vector Pw has a positive value. That is, the absolute value of the phase voltage command value signal Xw becomes an intermediate value, and the phase voltage command value signal Xw becomes a positive value (S88: YES in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are “2”, a value obtained by subtracting the Y coordinate of the vector Pwu from “2”, a value obtained by adding the Y coordinate of the vector Pvw to “2”, and “2”. Therefore, Xu4 is set to a value obtained by subtracting Xwu from “2”, Xv4 is set to a value obtained by adding Xvw to “2”, and Xw4 is set to “2” (S92 in FIG. 19).

  In the state of the mode 11 shown in FIG. 18E, the length of the orthogonal projection of the vector Pu on the Y-axis has an intermediate size, and the Y coordinate of the vector Pu has a negative value. That is, the absolute value of the phase voltage command value signal Xu has an intermediate magnitude, and the phase voltage command value signal Xu has a negative value (S89: NO in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu4 is set to “0”, Xv4 is set to a negative value of Xuv, and Xw4 is set to Xwu (S95 in FIG. 19).

  In the state of the mode 12 shown in FIG. 18F, the length of the orthogonal projection of the vector Pv on the Y-axis has an intermediate magnitude, and the Y coordinate of the vector Pv has a negative value. That is, the absolute value of the phase voltage command value signal Xv becomes an intermediate magnitude, and the phase voltage command value signal Xv becomes a negative value (S87: NO in FIG. 19). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu4 is set to Xuv, Xv4 is set to “0”, and Xw4 is set to a negative value of Xvw (S91 in FIG. 19).

  Note that the flowchart shown in FIG. 19 is an example of a command value signal generation process, and is not limited thereto.

  The waveform of the command value signals Xu4, Xv4, Xw4 generated by the command value signal generation processing according to the fourth embodiment is as shown by waveforms Xu4, Xv4, Xw4 shown in FIG.

  FIG. 20 is a diagram for explaining the waveforms of the command value signals Xu4, Xv4, and Xw4.

  The waveforms Xuv, Xvw, and Xwu shown in FIG. 20A are the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. 32A, and the waveforms Xvu, Xwv, and Xwu shown in FIG. Since it is the same as the waveforms Xvu, Xwv, and Xuw shown in FIG. Also in FIG. 20, the phase of the phase voltage command value signal Xu is described as a reference.

  Waveforms Xu4, Xv4, and Xw4 shown in FIG. 20C are the waveforms of the command value signals Xu4, Xv4, and Xw4, respectively. As described with reference to FIGS. 17, 18, and 19, the command value signals Xu4, Xv4, and Xw4 are generated separately for modes 1 to 12. In FIG. 20C, each waveform when B = 2 is shown.

  In mode 1 (0 ≦ θ ≦ π / 6), since the process proceeds to step S92 in the flowchart of FIG. 19, the waveform Xu4 is a waveform obtained by shifting Xuw upward by “2” (see FIG. 20B). The waveform Xv4 is a waveform obtained by shifting the waveform Xvw (see FIG. 20A) upward by “2”, and the waveform Xw4 is a waveform fixed to “2”. In mode 2 (π / 6 ≦ θ ≦ π / 3), since the process proceeds to step S94 in the flowchart of FIG. 19, the waveform Xu4 becomes a waveform fixed to “2”, and the waveform Xv4 changes the waveform Xvu to “2”. ”And the waveform Xw4 is a waveform obtained by shifting the waveform Xwu upward by“ 2 ”. In mode 3 (π / 3 ≦ θ ≦ π / 2), the process proceeds to step S91 in the flowchart of FIG. 19, so that the waveform Xu4 is the waveform Xuv, the waveform Xv4 is a waveform fixed to “0”, and the waveform Xw4 is Waveform Xwv. In mode 4 (π / 2 ≦ θ ≦ 2π / 3), the process proceeds to step S93 in the flowchart of FIG. 19, so that the waveform Xu4 becomes the waveform Xuw, the waveform Xv4 becomes the waveform Xvw, and the waveform Xw4 is fixed to “0”. Waveform. In mode 5 (2π / 3 ≦ θ ≦ 5π / 6), since the process proceeds to step S94 in the flowchart of FIG. 19, the waveform Xu4 becomes a waveform fixed to “2”, and the waveform Xv4 sets the waveform Xvu to “2”. The waveform is shifted upward, and the waveform Xw4 is a waveform obtained by shifting the waveform Xwu upward by “2”. In mode 6 (5π / 6 ≦ θ ≦ π), the process proceeds to step S90 in the flowchart of FIG. 19, so that the waveform Xu4 is a waveform obtained by shifting the waveform Xuv upward by “2”, and the waveform Xv4 becomes “2”. The waveform is fixed, and the waveform Xw4 is a waveform obtained by shifting the waveform Xwv upward by “2”.

  In mode 7 (π ≦ θ ≦ 7π / 6), the process proceeds to step S93 in the flowchart of FIG. 19, so that the waveform Xu4 becomes the waveform Xuw, the waveform Xv4 becomes the waveform Xvw, and the waveform Xw4 is fixed to “0”. It becomes. In mode 8 (7π / 6 ≦ θ ≦ 4π / 3), since the process proceeds to step S95 in the flowchart of FIG. 19, the waveform Xu4 becomes a waveform fixed to “0”, the waveform Xv4 becomes the waveform Xvu, and the waveform Xw4 becomes the waveform Xwu. In mode 9 (4π / 3 ≦ θ ≦ 3π / 2), since the process proceeds to step S90 in the flowchart of FIG. 19, the waveform Xu4 is a waveform obtained by shifting the waveform Xuv upward by “2”, and the waveform Xv4 is “2”. The waveform Xw4 is a waveform obtained by shifting the waveform Xwv upward by “2”. In mode 10 (3π / 2 ≦ θ ≦ 5π / 3), since the process proceeds to step S92 in the flowchart of FIG. 19, the waveform Xu4 is a waveform obtained by shifting Xuw upward by “2”, and the waveform Xv4 is the waveform Xvw. The waveform is shifted upward by “2”, and the waveform Xw4 is a waveform fixed at “2”. In mode 11 (5π / 3 ≦ θ ≦ 11π / 6), the process proceeds to step S95 in the flowchart of FIG. 19, so that the waveform Xu4 becomes a waveform fixed to “0”, the waveform Xv4 becomes the waveform Xvu, and the waveform Xw4 becomes Waveform Xwu is obtained. In mode 12 (11π / 6 ≦ θ ≦ 2π), the process proceeds to step S91 in the flowchart of FIG. 19, so that the waveform Xu4 becomes the waveform Xuv, the waveform Xv4 becomes a waveform fixed to “0”, and the waveform Xw4 becomes the waveform Xwv. It becomes.

  As is clear from FIG. 20, the difference signal between the command value signals Xu4 and Xv4, the difference signal between Xv4 and Xw4, and the difference signal between Xw4 and Xu4 match the line voltage command value signals Xuv, Xvw, Xwu, respectively. To do. Therefore, the line voltage signals Vuv, which are the difference signals between the phase voltage signals Vu4 and Vv4 output from the grid interconnection inverter system A, and the differences between the line voltage signals Vvw, Vw4 and Vu4 which are the difference signals between Vv4 and Vw4. The waveform of the line voltage signal Vwu that is a signal is the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. That is, the line voltage signals Vuv, Vvw, and Vwu are sine wave signals balanced in three phases, and can be synchronized with the system voltage of the system B. Therefore, the AC power output from the grid interconnection inverter system A can be supplied to the grid B.

  The command value signals Xu4, Xv4, and Xw4 are fixed to “0” at 1/6 of the cycle and fixed to “2” at 1/6 of the cycle (waveforms Xu4, Xv4, FIG. 20C). Xw4). Therefore, the same effect as that of the first embodiment can be obtained.

  Also in the fourth embodiment, similarly to the first embodiment, the lower limit value and the upper limit value of the command value signals Xu4, Xv4, Xw4 are not limited. For example, the command value signals Xu4, Xv4, and Xw4 may be generated so that the lower limit value is “−1” and the upper limit value is “1”. In this case, it is necessary to set the lower limit value and the upper limit value of the carrier signal used in the PWM signal generation unit 53 in accordance with the lower limit value and the upper limit value of the command value signals Xu4, Xv4, Xw4.

  Next, a control method for generating a command value signal having a waveform different from that of the first to fourth embodiments will be described below as a fifth embodiment. The command value signals according to the fifth embodiment are Xu5, Xv5, and Xw5. The fifth embodiment is different from the first embodiment only in the command value signal generation process. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

  The command value signals Xu5, Xv5, and Xw5 according to the fifth embodiment are NVS command value signals Xu ′, Xv ′, and Xw ′ (see FIG. 32C) and are inverted by inverting the polarities of the waveforms of these signals. And a waveform having a waveform shifted upward by the value of X (hereinafter referred to as “second signal”) Xu ″, Xv ″, Xw ″ (see FIG. 23C described later). In the following description, the “NVS command value signal” is referred to as a “first signal”.

  FIG. 21 is a block diagram for explaining an internal configuration of a command value signal generation unit according to the fifth embodiment.

  As shown in the figure, the command value signal generation unit 52 ′ includes a first signal generation unit 521, a second signal generation unit 522, a flag signal generation unit 523, and a signal combination unit 524.

  The first signal generation unit 521 generates the first signals Xu ′, Xv ′, and Xw ′. The first signal generation unit 521 generates the first signals Xu ′, Xv ′, Xw ′ based on the phase voltage command value signals Xu, Xv, Xw input from the feedback control unit 51 to generate the signal combination unit 524. Output to. The first signal generation unit 521 generates line voltage command value signals Xuv, Xvw, and Xwu from the phase voltage command value signals Xu, Xv, and Xw, and generates signals Xvu, Xwv, and Xuw in which these polarities are inverted. . The first signal generation unit 521 generates a first signal Xu ′ from the line voltage command value signal Xuv, the signal Xuw, and the zero signal, and generates a first signal from the line voltage command value signal Xvw, the signal Xvu, and the zero signal. The signal Xv ′ is generated, and the first signal Xw ′ is generated from the line voltage command value signal Xwu, the signal Xwv, and the zero signal (see FIG. 32).

  Waveforms Xu ′, Xv ′, Xw ′ of the first signals (NVS command value signals) Xu ′, Xv ′, Xw ′ are as shown in FIG. That is, the waveform Xu ′ becomes the waveform Xuv in mode 1 (−π / 6 ≦ θ ≦ π / 2 (= 3π / 6)), and the waveform Xuw in mode 2 (π / 2 ≦ θ ≦ 7π / 6). Thus, in mode 3 (7π / 6 ≦ θ ≦ 11π / 6), the waveform is fixed to “0”. The waveform Xv ′ is a waveform fixed to “0” in the mode 1, the waveform Xvw in the mode 2, and the waveform Xvu in the mode 3. The waveform Xw ′ is a waveform Xwv in mode 1, a waveform fixed to “0” in mode 2, and a waveform Xwu in mode 3.

  The second signal generator 522 generates the second signals Xu ″, Xv ″, and Xw ″. The second signal generator 522 receives the phase voltage command value signal Xu, Based on Xv and Xw, second signals Xu ″, Xv ″ and Xw ″ are generated and output to the signal combination unit 524. The second signal generation unit 522 generates line voltage command value signals Xuv, Xvw, Xwu from the phase voltage command value signals Xu, Xv, Xw, and generates signals Xvu, Xwv, Xuw in which these polarities are inverted. . The second signal generator 522 generates the second signals Xu ″, Xv ″, Xw ″ using the line voltage command value signals Xuv, Xvw, Xwu and the signals Xvu, Xwv, Xuw.

  22 is a diagram for explaining the concept of generation of the second signals Xu ″, Xv ″, Xw ″ in terms of vectors. In FIG. 22, the generation of the first signals Xu ′, Xv ′, Xw ′. The neutral point N, the vector Pu, and the equilateral triangle T are shown in the same manner as the vector diagram (see FIG. 2) showing the concept of the above, and the vectors Pv and Pw are described except for the left diagram in FIG. In each figure, white dots are attached to the fixed vertices, while each vertex of the regular triangle T is fixed at the origin in the vector diagram shown in FIG. In the vector diagram shown, each vertex of the equilateral triangle T is fixed to the maximum point.

  FIG. 6A shows a state where the angle θ (the angle that the vector Pu makes with the X axis) changes from π / 6 to 5π / 6. When π / 6 ≦ θ ≦ 5π / 6, the U-phase potential is fixed to B. This state is referred to as “mode 1 ′”. In mode 1 ′, the vertex u of the equilateral triangle T is fixed at the maximum point, and the equilateral triangle T is counterclockwise about the vertex u (in the direction of the broken line arrow shown in the figure, the same applies hereinafter) 2π. It is expressed by rotating 3/3. The left figure shows θ = π / 6, the middle figure shows θ = π / 2 (= 3π / 6), and the right figure shows θ = 5π / 6. When θ = 5π / 6, the V-phase potential is fixed to B. The right figure shows that the phase to be fixed changes from the U phase to the V phase. When the equilateral triangle T moves so that the vertex v coincides with the maximum point, the neutral point N changes. It shows that.

  FIG. 4B shows a state when the angle θ changes from 5π / 6 to 3π / 2 (= 9π / 6). When 5π / 6 ≦ θ ≦ 3π / 2, the V-phase potential is fixed to B. This state is referred to as “mode 2 ′”. Mode 2 ′ is represented by the vertex v of the equilateral triangle T being fixed at the maximum point, and the equilateral triangle T being rotated counterclockwise by 2π / 3 around the vertex v. The left figure shows the case when θ = 5π / 6, the middle figure shows the case when θ = 7π / 6, and the right figure shows the case when θ = 3π / 2 (= 9π / 6). The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 3π / 2, the W-phase potential is fixed to B. The figure on the right shows that the phase to be fixed changes from the V phase to the W phase. The equilateral triangle T moves so that the vertex w coincides with the maximum point, and the neutral point N transitions. It shows that.

  FIG. 4C shows a state when the angle θ changes from 3π / 2 (= 9π / 6) to 13π / 6 (= π / 6). When 3π / 2 ≦ θ ≦ 13π / 6, the potential of the W phase is fixed to B. This state is referred to as “mode 3 ′”. Mode 3 ′ is represented by the vertex w of the regular triangle T being fixed at the maximum point, and the regular triangle T being rotated 2π / 3 counterclockwise around the vertex w. The left figure shows θ = 3π / 2 (= 9π / 6), the middle figure shows θ = 11π / 6, and the right figure shows θ = 13π / 6. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 13π / 6, the U-phase potential is fixed to B. The right figure shows that the phase to be fixed changes from the W phase to the U phase. The equilateral triangle T moves so that the vertex u coincides with the maximum point, and the neutral point N transitions. It shows that. The figure after this transition is the same as the left figure of FIG. Thereafter, modes 1 'to 3' are repeated.

  In the vector diagram shown in FIG. 22, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. In mode 1 ', the vertex u is fixed at the maximum point, so the phase voltage of the U phase is B (see FIG. 5A). Therefore, in the mode 1 ′, the U-phase second signal Xu ″ may be a signal whose value is B.

  In mode 2 ′, the vertex v is fixed at the maximum point, so the value obtained by adding B to the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y axis is the U-phase voltage (see FIG. (See (b)). Therefore, in the mode 2 ′, the U-phase second signal Xu ″ may be obtained by adding B to the line voltage command value signal Xuv. In the mode 3 ′, the vertex w is fixed at the maximum point. Therefore, the value obtained by adding B to the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y axis is the phase voltage of the U phase (see FIG. 5C). The U-phase second signal Xu ″ may be obtained by adding B to the signal Xuw (= −Xwu).

  Similarly, the V-phase second signal Xv ″ is obtained by adding B to the signal Xvu in mode 1 ′, a signal having a value B in mode 2 ′, and a line voltage in mode 3 ′. It is sufficient that B is added to the command value signal Xvw. Also, the second signal Xw ″ of the W phase is added to B in the line voltage command value signal Xwu in the mode 1 ′, and the mode 2 In “′”, it is assumed that B is added to the signal Xwv.

  FIG. 23 is a diagram for explaining the waveforms of the second signals Xu ″, Xv ″, and Xw ″.

  The waveforms Xuv, Xvw, and Xwu shown in FIG. 23A are the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. 32A, and the waveforms Xvu, Xwv, and Xwu shown in FIG. Since it is the same as the waveforms Xvu, Xwv, and Xuw shown in FIG. Also in FIG. 23, the phase of the phase voltage command value signal Xu is described as a reference.

  Waveforms Xu ″, Xv ″, Xw ″ shown in FIG. 23C are waveforms of the second signals Xu ″, Xv ″, Xw ″, respectively. As described with reference to FIG. 22, the second signals Xu ″, Xv ″, and Xw ″ are generated by being divided into modes 1 ′ to 3 ′. In FIG. The waveform is shown.

  The U-phase second signal Xu ″ switches between a signal obtained by adding “2” to the line voltage command value signal Xuv, a signal obtained by adding “2” to the signal Xuw, and a signal having a value “2”. Generated. The waveform Xu ″ is a waveform fixed to “2” in the mode 1 ′ (π / 6 ≦ θ ≦ 5π / 6), and the mode 2 ′ (5π / 6 ≦ θ ≦ 3π / 2 (= 9π / 6) ) Is a waveform obtained by shifting the waveform Xuv upward by “2”. In mode 3 ′ (3π / 2 ≦ θ ≦ 13π / 6), the waveform Xuv is shifted upward by “2”. Yes. Note that the phase of the phase voltage command value signal Xu is θ.

  Similarly, the V-phase second signal Xv ″ includes a signal obtained by adding “2” to the line voltage command value signal Xvw, a signal obtained by adding “2” to the signal Xvu, and a signal having a value “2”. It is generated by switching. The waveform Xv ″ is a waveform obtained by shifting the waveform Xvu upward by “2” in the mode 1 ′, is a waveform fixed to “2” in the mode 2 ′, and the waveform Xvw is “2” in the mode 3 ′. The waveform is shifted upward by "."

  The second signal Xw "for the W phase includes a signal obtained by adding" 2 "to the line voltage command value signal Xwu, a signal obtained by adding" 2 "to the signal Xwv, and a signal having a value" 2 ". Generated by switching. The waveform Xw ″ is a waveform obtained by shifting the waveform Xwu upward by “2” in the mode 1 ′, a waveform obtained by shifting the waveform Xwv upward by “2” in the mode 2 ′, and in the mode 3 ′. The waveform is fixed at “2”.

  Returning to FIG. 21, the flag signal generation unit 523 generates a flag signal fg for switching between the first signal and the second signal. The flag signal fg is a signal that switches between “0” (low level) and “1” (high level) in a predetermined cycle. In the present embodiment, the period of the flag signal fg is twice as long as the period of the first signals Xu ′, Xv ′, Xw ′ and the second signals Xu ″, Xv ″, Xw ″ (1/2 frequency). The period “0” and the period “1” are the same.

  The signal combination unit 524 includes first signals Xu ′, Xv ′, and Xw ′ input from the first signal generation unit 521 and second signals Xu ″, Xv ″, Xw ″ is combined to generate command value signals Xu5, Xv5, Xw5. The signal combination unit 524 is based on the flag signal fg input from the flag signal generation unit 523, and generates the first signal Xu ′. , Xv ′, Xw ′ and the second signals Xu ″, Xv ″, Xw ″. That is, the signal combination unit 524 outputs the second signals Xu ″, Xv ″, and Xw ″ while the flag signal fg is “1”, and the first signal Xu ′ while the flag signal fg is “0”. , Xv ′, Xw ′. Signals output from the signal combination unit 524 are output to the PWM signal generation unit 53 as command value signals Xu5, Xv5, and Xw5.

  FIG. 24 is a diagram for explaining the waveforms of the command value signals Xu5, Xv5, and Xw5.

  A waveform fg shown in FIG. 5A shows the waveform of the flag signal fg. The cycle of the flag signal fg is set to be twice the cycle of the first signals Xu ′, Xv ′, Xw ′ and the second signals Xu ″, Xv ″, Xw ″. The first signal Xu ′. Is a cycle of the phase voltage command value signal Xu (hereinafter, the cycle is “T”. Since the cycle T is made to coincide with the cycle of the system voltage, for example, T = 1/60) [S].), The period of the flag signal fg is twice the period T (2T). Further, in the present embodiment, the flag signal fg is switched to “1” when θ = 0 with reference to the phase θ of the phase voltage command value signal Xu. Therefore, the flag signal fg is switched to “0” when θ = 2π, and is switched to “1” when θ = 4π.

  A waveform Xu5 shown in FIG. 5B is a waveform of the U-phase command value signal Xu5. Since the flag signal fg is “1” in the period of 0 ≦ θ ≦ 2π, the command value signal Xu5 is the second signal Xu ″, and in the period of 2π ≦ θ ≦ 4π, the flag signal fg is “0”. The command value signal Xu5 becomes the first signal Xu ′. Therefore, the waveform Xu5 becomes the waveform Xu ″ (see FIG. 23C) in the period of 0 ≦ θ ≦ 2π, and becomes the waveform Xu ′ (see FIG. 32C) in the period of 2π ≦ θ ≦ 4π. .

  Similarly, the waveform Xv5 of the V-phase command value signal Xv5 becomes the waveform Xv ″ in the period of 0 ≦ θ ≦ 2π, and becomes the waveform Xv ′ in the period of 2π ≦ θ ≦ 4π. The waveform Xw5 of the value signal Xw5 becomes the waveform Xw ″ during the period of 0 ≦ θ ≦ 2π, and becomes the waveform Xw ′ during the period of 2π ≦ θ ≦ 4π.

  The difference signal between the command value signals Xu5 and Xv5 is a difference signal between the second signals Xu ″ and Xv ″ in the period of 0 ≦ θ ≦ 2π, and the first signal Xu ′ in the period of 2π ≦ θ ≦ 4π. And Xv ′. The difference signal between the second signals Xu ″ and Xv ″ matches the line voltage command value signal Xuv (see FIG. 23A). Further, the difference signal between the first signals Xu ′ and Xv ′ also matches the line voltage command value signal Xuv (see FIG. 32A). Therefore, the difference signal between the command value signals Xu5 and Xv5 matches the line voltage command value signal Xuv. Similarly, the difference signal between the command value signals Xv5 and Xw5 matches the line voltage command value signal Xvw, and the difference signal between the command value signals Xw5 and Xu5 matches the line voltage command value signal Xwu. Therefore, the line voltage signals Vuv, which are the difference signals between the phase voltage signals Vu4 and Vv4 output from the grid interconnection inverter system A, and the differences between the line voltage signals Vvw, Vw4 and Vu4 which are the difference signals between Vv4 and Vw4. The waveform of the line voltage signal Vwu, which is a signal, is the same as the waveforms Xuv, Xvw, and Xwu shown in FIGS. 23 (a) and 32 (a). That is, the line voltage signals Vuv, Vvw, and Vwu are sine wave signals balanced in three phases, and can be synchronized with the system voltage of the system B. Therefore, the AC power output from the grid interconnection inverter system A can be supplied to the grid B.

  FIG. 25 is a flowchart for explaining the command value signal generation process performed by the command value signal generation unit 52 ′ according to the fifth embodiment. The command value signal generation process is executed at a predetermined timing.

  First, line voltage command value signals Xuv, Xvw, Xwu and a flag signal fg are acquired (S101). Next, it is determined whether or not fg is “0” (S102). When fg is “0” (S102: YES), the process proceeds to step S103, and processing for generating the first signals Xu ′, Xv ′, and Xw ′ is performed (S103 to S114). On the other hand, if fg is not “0” (S102: NO), that is, if fg is “1”, the process proceeds to step S115, and processing for generating the second signals Xu ″, Xv ″, Xw ″ is performed ( S115 to S126).

  Steps S103 to S105 and steps S115 to S117 are the same as steps S2 to S4 in the flowchart (see FIG. 8) of the command value signal generation process according to the first embodiment, respectively. That is, in these steps, it is determined which of the line voltage command value signals Xuv, Xvw, Xwu has the maximum absolute value.

  If it is determined in step S102 that fg is “0” and the absolute value of Xuv is the maximum (S102: YES, S103: YES, S104: YES), it is determined whether Xuv is a positive value. (S106). When Xuv is a positive value (S106: YES), the command value signal Xu5 is set to Xuv, the command value signal Xv5 is set to “0”, and the command value signal Xw5 is set to a negative value of Xvw (S109). On the other hand, when Xuv is “0” or less (S106: NO), Xu5 is set to “0”, Xv5 is set to a negative value of Xuv, and Xw5 is set to Xwu (S110).

  When it is determined in step S102 that fg is “0” and the absolute value of Xwu is the maximum (S102: YES, S103: YES to S104: NO, or S103: NO to S105: NO), Xwu is It is determined whether or not the value is a positive value (S107). When Xwu is a positive value (S107: YES), Xu5 is set to “0”, Xv5 is set to a negative value of Xuv, and Xw5 is set to Xwu (S111). On the other hand, when Xwu is “0” or less (S107: NO), Xu5 is set to a negative value of Xwu, Xv5 is set to Xvw, and Xw5 is set to “0” (S112).

  When it is determined in step S102 that fg is “0” and the absolute value of Xvw is the maximum (S102: YES, S103: NO, S105: YES), it is determined whether Xvw is a positive value. (S108). When Xvw is a positive value (S108: YES), Xu5 is set to a negative value of Xwu, Xv5 is set to Xvw, and Xw5 is set to “0” (S113). On the other hand, when Xvw is equal to or less than “0” (S108: NO), Xu5 is set to Xuv, Xv5 is set to “0”, and Xw5 is set to a negative value of Xvw (S114).

  When it is determined in step S102 that fg is “1” and the absolute value of Xuv is the maximum (S102: NO, S115: YES, S116: YES), it is determined whether Xuv is a positive value. (S118). When Xuv is a positive value (S118: YES), Xu5 is set to “2”, Xv5 is set to a value obtained by subtracting Xuv from “2”, and Xw5 is set to a value obtained by adding Xwu to “2”. (S121). On the other hand, when Xuv is “0” or less (S118: NO), Xu5 is a value obtained by adding Xuv to “2”, Xv5 is “2”, and Xw5 is a value obtained by subtracting Xvw from “2”. (S122).

  When it is determined in step S102 that fg is “1” and the absolute value of Xwu is the maximum (S102: NO, S115: YES to S116: NO, or S115: NO to S117: NO), Xwu is It is determined whether or not the value is a positive value (S119). When Xwu is a positive value (S119: YES), Xu5 is a value obtained by subtracting Xwu from “2”, Xv5 is a value obtained by adding Xvw to “2”, and Xw5 is set to “2”. (S123). On the other hand, when Xwu is “0” or less (S119: NO), Xu5 is set to “2”, Xv5 is set to a value obtained by subtracting Xuv from “2”, and Xw5 is set to a value obtained by adding Xwu to “2”. (S124).

  When it is determined in step S102 that fg is “1” and the absolute value of Xvw is the maximum (S102: NO, S115: NO, S117: YES), it is determined whether Xvw is a positive value. (S120). When Xvw is a positive value (S120: YES), Xu5 is a value obtained by adding Xuv to “2”, Xv5 is set to “2”, and Xw5 is a value obtained by subtracting Xvw from “2”. (S125). On the other hand, when Xvw is equal to or less than “0” (S120: NO), Xu5 is a value obtained by subtracting Xwu from “2”, Xv5 is a value obtained by adding Xvw to “2”, and Xw5 is “2”. (S126).

  That is, in the command value signal generation process, it is determined whether fg is “0” or “1”, the line voltage command value signals Xuv, Xvw, and Xwu are determined to have the maximum absolute value, Whether the phase voltage command value signal having the maximum absolute value is positive or negative is determined, and the command value signals Xu5, Xv5, Xw5 are determined according to the determination result. That is, it is determined whether the state is one of modes 1 to 3 in the vector diagram shown in FIG. 2 or modes 1 ′ to 3 ′ in the vector diagram shown in FIG. 22, and corresponds to the vector diagram of the determined mode. The command value signals Xu5, Xv5 and Xw5 for each phase are determined.

  In the period from the left figure to the middle figure in the mode 1 state shown in FIG. 2A (hereinafter referred to as “first half part”), the orthogonal projection of the vector Pvw onto the Y axis is performed. The length is the maximum, and the Y coordinate of the vector Pvw is a negative value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a negative value (S108: NO in FIG. 25). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu5 is set to Xuv, Xv5 is set to “0”, and Xw5 is set to a negative value of Xvw (S114 in FIG. 25).

  In the period from the center diagram to the right diagram in the mode 1 state shown in FIG. 2A (hereinafter referred to as “second half portion”), the orthogonal projection of the vector Puv on the Y axis is performed. The length is the maximum, and the Y coordinate of the vector Puv is a positive value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a positive value (S106: YES in FIG. 25). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu5 is set to Xuv, Xv5 is set to “0”, and Xw5 is set to a negative value of Xvw (S109 in FIG. 25).

  In the case of the first half of the mode 2 states shown in FIG. 2B, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu is a negative value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a negative value (S107: NO in FIG. 25). At this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Therefore, Xu5 is a negative value of Xwu, Xv5 is Xvw, and Xw5 is “0” (S112 in FIG. 25).

  In the second half of the mode 2 state shown in FIG. 2B, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pvw is a positive value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a positive value (S108: YES in FIG. 25). Also at this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Therefore, Xu5 is a negative value of Xwu, Xv5 is Xvw, and Xw5 is “0” (S113 in FIG. 25).

  In the case of the first half of the mode 3 state shown in FIG. 2C, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Puv is a negative value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a negative value (S106: NO in FIG. 25). At this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu5 is set to “0”, Xv5 is set to a negative value of Xuv, and Xw5 is set to Xwu (S110 in FIG. 25).

  In the latter half of the mode 3 state shown in FIG. 2C, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu has a positive value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a positive value (S107: YES in FIG. 25). Also at this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu5 is set to “0”, Xv5 is set to a negative value of Xuv, and Xw5 is set to Xwu (S111 in FIG. 25).

  In the first half of the mode 1 'state shown in FIG. 22A, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Puv is a positive value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a positive value (S118: YES in FIG. 25). At this time, the Y coordinates of the vertices u, v, and w are values obtained by subtracting the Y coordinate of the vector Puv from “2” and “2”, respectively, and the values obtained by adding the Y coordinate of the vector Pwu to “2”. Therefore, Xu5 is “2”, Xv5 is a value obtained by subtracting Xuv from “2”, and Xw5 is a value obtained by adding Xwu to “2” (S121 in FIG. 25).

  In the case of the latter half of the mode 1 'state shown in FIG. 22A, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu is a negative value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a negative value (S119: NO in FIG. 25). Also at this time, the Y coordinates of the vertices u, v, and w are values obtained by subtracting the Y coordinate of the vector Puv from “2” and “2”, respectively, and the value obtained by adding the Y coordinate of the vector Pwu to “2”. . Therefore, Xu5 is “2”, Xv5 is a value obtained by subtracting Xuv from “2”, and Xw5 is a value obtained by adding Xwu to “2” (S124 in FIG. 25).

  In the case of the first half of the mode 2 'state shown in FIG. 22B, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pvw is a positive value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a positive value (S120: YES in FIG. 25). At this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. Accordingly, Xu5 is a value obtained by adding Xuv to “2”, Xv5 is “2”, and Xw5 is a value obtained by subtracting Xvw from “2” (S125 in FIG. 25).

  In the second half of the mode 2 'state shown in FIG. 22B, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Puv is a negative value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a negative value (S118: NO in FIG. 25). Also at this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and the values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. . Accordingly, Xu5 is a value obtained by adding Xuv to “2”, Xv5 is “2”, and Xw5 is a value obtained by subtracting Xvw from “2” (S122 in FIG. 25).

  In the first half of the mode 3 'state shown in FIG. 22C, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu is a positive value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a positive value (S119: YES in FIG. 25). At this time, the Y coordinates of the vertices u, v, and w are “2”, a value obtained by subtracting the Y coordinate of the vector Pwu from “2”, a value obtained by adding the Y coordinate of the vector Pvw to “2”, and “2”. Therefore, Xu5 is a value obtained by subtracting Xwu from “2”, Xv5 is a value obtained by adding Xvw to “2”, and Xw5 is “2” (S123 in FIG. 25).

In the case of the latter half of the mode 3 ′ state shown in FIG. 22C, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pvw is a negative value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a negative value (S120: NO in FIG. 25). Also at this time, the Y coordinates of the vertices u, v, and w are “2”, which is a value obtained by subtracting the Y coordinate of the vector Pwu from “2”, and a value obtained by adding the Y coordinate of the vector Pvw to “2”, respectively. . Therefore, Xu5 is a value obtained by subtracting Xwu from “2”, Xv5 is a value obtained by adding Xvw to “2”, and Xw5 is “2” (S126 in FIG. 25).

  The waveform of the command value signals Xu5, Xv5, and Xw5 generated by the command value signal generation processing is as shown by waveforms Xu5, Xv5, and Xw5 shown in FIG. That is, in mode 1 ′, since the process proceeds to step S121 or S124 in the flowchart of FIG. 25, the waveform Xu5 becomes a waveform fixed to “2”, and the waveform Xv5 changes the waveform Xvu (see FIG. 23B) to “2”. ”And the waveform Xw5 is a waveform obtained by shifting the waveform Xwu (see FIG. 23A) upward by“ 2 ”. In mode 2 ′, since the process proceeds to step S122 or S125 in the flowchart of FIG. 25, the waveform Xu5 is a waveform obtained by shifting the waveform Xuv upward by “2”, and the waveform Xv5 is a waveform fixed to “2”. Thus, the waveform Xw5 is a waveform obtained by shifting the waveform Xwv upward by “2”. In mode 3 ′, since the process proceeds to step S123 or S126 in the flowchart of FIG. 25, the waveform Xu5 is a waveform obtained by shifting the waveform Xuw upward by “2”, and the waveform Xv5 is shifted upward by “2”. The waveform Xw5 is a waveform fixed to “2”. In mode 1, since the process proceeds to step S109 or S114 in the flowchart of FIG. 25, the waveform Xu5 becomes the waveform Xuv (see FIG. 32A), the waveform Xv5 becomes a waveform fixed to “0”, and the waveform Xw5 becomes the waveform. Xwv (see FIG. 32B). In mode 2, since the process proceeds to step S112 or S113 in the flowchart of FIG. 25, the waveform Xu5 becomes the waveform Xuw, the waveform Xv5 becomes the waveform Xvw, and the waveform Xw5 becomes a waveform fixed to “0”. In mode 3, since the process proceeds to step S110 or S111 in the flowchart of FIG. 25, the waveform Xu5 becomes a waveform fixed to “0”, the waveform Xv5 becomes the waveform Xvu, and the waveform Xw5 becomes the waveform Xwu.

  The flowchart shown in FIG. 25 is an example of the command value signal generation process, and is not limited to this.

  As shown in FIG. 24B, the command value signals Xu5, Xv5, and Xw5 are periodic signals, and are fixed to “0” for a predetermined period and fixed to “2” for another predetermined period. . Therefore, the PWM signal generated by comparing the command value signals Xu5, Xv5, Xw5 and the carrier signal is low during the period when the command value signals Xu5, Xv5, Xw5 are fixed to “0” or “2”. The level or high level will continue. Since switching of the switching element is stopped during these periods, the number of switching operations can be reduced, and switching loss can be reduced. In addition, since the PWM signal has both a low-level duration and a high-level duration, the positive-side switching element is on and the negative-side switching element is on. A period of time during which the condition continues. Therefore, compared to the case where only one of the positive-side switching element and the negative-side switching element continues to be in the on state, the time during which the positive-side switching element is on and the negative-side switching element is on. The difference from the time in the state can be reduced. Thereby, the unbalance of the progress of deterioration can be suppressed between the switching element on the positive electrode side and the switching element on the negative electrode side. In addition, the complexity of the design of the cooling member can be alleviated.

  Also in the fifth embodiment, similarly to the first embodiment, the lower limit value and the upper limit value of the command value signals Xu5, Xv5, and Xw5 are not limited. For example, the command value signals Xu5, Xv5, and Xw5 may be generated so that the lower limit value is “−1” and the upper limit value is “1”. In this case, it is necessary to set the lower limit value and the upper limit value of the carrier signal used in the PWM signal generation unit 53 according to the lower limit value and the upper limit value of the command value signals Xu5, Xv5, and Xw5.

  In the fifth embodiment, the period in which the command value signals Xu5, Xv5, and Xw5 are fixed to “0” and the period that is fixed to “2” are all 1/6 of one period. ing. Therefore, the time during which the positive-side switching element is in the on state is equal to the time during which the negative-side switching element is in the on state. However, it is fixed to “0” of the command value signals Xu5, Xv5, and Xw5 depending on the cycle of the flag signal fg, the duty ratio (the ratio of the high level period to the cycle), and the phase (timing to switch to “1”) The period and the period fixed at “2” are different.

  26 to 30 are diagrams for explaining simulation results of the command value signals Xu5, Xv5, and Xw5. 26 to 28 show the waveforms of the command value signals Xu5, Xv5 and Xw5 and the waveform of the flag signal fg when the duty ratio and phase of the flag signal fg are fixed and the period is changed.

  FIG. 26A shows a waveform when the cycle of the flag signal fg is 2T (= 1/30 [s]: frequency 30 Hz), and FIG. 26B shows the waveform of the flag signal fg is T (= 1). / 60 [s]: frequency 60 Hz), the waveform (c) shows the waveform when the period of the flag signal fg is 0.5T (= 1/120 [s]: frequency 120 Hz). Show. The phase of the flag signal fg is matched with the phase θ of the phase voltage command value signal Xu (that is, the flag signal fg is switched to “1” when θ = 0). Further, the duty ratio of the flag signal fg is set to “0.5”.

  The waveform shown in FIG. 26 (a) is based on the same conditions as in FIG. 24, and therefore matches the waveform shown in FIG.

  Since the waveform shown in FIG. 26B is obtained by halving the cycle of the flag signal fg in the case of FIG. 26A, the portion of the waveform of FIG. 23C in the period of 0 ≦ θ ≦ π and FIG. The waveform in (c) is a combination of the period of π ≦ θ ≦ 2π. In this case, as compared with the waveform of FIG. 26A, the period in which the command value signal Xu5 is fixed to “0” and the period in which the command value signal Xu5 is fixed to “2” become longer, and the command value signals Xv5 and Xw5 The period fixed at “0” and the period fixed at “2” are shortened. However, the period fixed to “0” and the period fixed to “2” in the command value signals Xu5, Xv5, and Xw5 are the same. Also in this case, the time during which the positive-side switching element is in the on state is equal to the time during which the negative-side switching element is in the on state. However, the switching stop time differs between the U-phase switching element and the V-phase and W-phase switching elements.

  Since the waveform shown in FIG. 26C is obtained by setting the cycle of the flag signal fg to ¼ that in FIG. 26A, the waveform in FIG. 23C has a period of 0 ≦ θ ≦ π / 2. 32c, the portion of the waveform of FIG. 32C in the period of π / 2 ≦ θ ≦ π, the portion of the waveform of FIG. 23C in the period of π ≦ θ ≦ 3π / 2, and the portion of FIG. The waveform is a combination of portions of a period of 3π / 2 ≦ θ ≦ 2π. In this case, the period in which the command value signal Xu5 is fixed to “0” and the period in which the command value signal Xu5 is fixed to “2” are the same, but the period in which the command value signals Xv5 and Xw5 are fixed to “0”. And the period fixed at “2” is different. In this case, in the V-phase and the W-phase, the time during which the positive-side switching element is in the on state is not equal to the time during which the negative-side switching element is in the on-state. Compared to the case where only one of the element and the negative-side switching element continues to be on, the time during which the positive-side switching element is on and the time during which the negative-side switching element is on And the difference can be reduced.

  FIG. 27 shows a case where the period of the flag signal fg is made larger than that in the case of FIG. FIG. 27A shows a waveform when the period of the flag signal fg is 3T (= 1/20 [s]: frequency 20 Hz). FIG. 27B shows the waveform of the flag signal fg is 4T (= 1). / 15 [s]: Frequency in the case of 15 Hz). The phase of the flag signal fg is matched with the phase θ of the phase voltage command value signal Xu (that is, the flag signal fg is switched to “1” when θ = 0). Further, the duty ratio of the flag signal fg is set to “0.5”.

  Since the waveform shown in FIG. 27A is obtained by multiplying the period of the flag signal fg by 1.5 times that in FIG. 26A, the portion of the period of 0 ≦ θ ≦ 3π of the waveform of FIG. And a portion of the waveform of FIG. 32C in the period of π ≦ θ ≦ 3π. In this case, the period fixed to “0” and the period fixed to “2” in the command value signals Xu5, Xv5, and Xw5 are the same. Also in this case, the time during which the positive-side switching element is in the on state is equal to the time during which the negative-side switching element is in the on state. However, the switching stop time differs between the U-phase switching element and the V-phase and W-phase switching elements.

  Since the waveform shown in FIG. 27B is obtained by doubling the cycle of the flag signal fg in the case of FIG. 26A, the portion of the waveform of FIG. The waveform is a combination of the portion of the period of 0 ≦ θ ≦ 4π of the waveform of 32 (c). In this case, when compared with the waveform of FIG. 26A, each of the period in which the command value signals Xu5, Xv5, and Xw5 are fixed to “0” and the period that is fixed to “2” is one cycle. The period is 1/6. Therefore, the time during which the positive-side switching element is in the on state is equal to the time during which the negative-side switching element is in the on state.

  As shown in FIGS. 26 and 27, the command value signals Xu5, Xv5, and Xw5 have different waveforms from each other. In particular, when the period is T (see FIG. 26B), the difference between the waveforms is remarkable. When the command value signals Xu5, Xv5, and Xw5 have different waveforms, the influence of the error voltage due to the dead time inserted when generating the PWM signal may differ depending on the phase. In order to solve this problem, the command value signals Xu5, Xv5, and Xw5 may have the same waveform.

  FIG. 28 is a diagram for explaining a case where the command value signals Xu5, Xv5, and Xw5 have the same waveform. In the figure, the phase of the flag signal fg is matched with the phase θ of the phase voltage command value signal Xu. Further, the duty ratio of the flag signal fg is set to “0.5”.

  When the cycle of the flag signal fg is 4T / 3 (= 1/45 [s]: frequency 45 Hz), the command value signals Xu5, Xv5, and Xw5 have the same waveform. FIG. 28A shows a waveform when the cycle of the flag signal fg is 4T / 3. The waveform corresponds to a portion of the waveform of FIG. 23C in the period of 0 ≦ θ ≦ 4π / 3, a portion of the waveform of FIG. 32C in the period of 4π / 3 ≦ θ ≦ 8π / 3, and FIG. ) Of the waveform of 2π / 3 ≦ θ ≦ 2π, the portion of the waveform of FIG. 32C of 0 ≦ θ ≦ 4π / 3, and 4π / 3 ≦ θ ≦ of the waveform of FIG. The waveform is a combination of the period of 8π / 3 and the period of 2π / 3 ≦ θ ≦ 2π of the waveform of FIG. In this case, the command value signals Xu5, Xv5, and Xw5 have the same waveform. When the frequency of the flag signal fg is a multiple of 3 / 4T (45 Hz) (that is, 3 / 2T (90 Hz), 9 / 4T (135 Hz), 3 / T (180 Hz), etc.), the command value signals Xu5, Xv5 The waveform of Xw5 becomes the same waveform. FIG. 28 (b) shows a waveform when the frequency of the flag signal fg is 3 / 2T, and FIG. 28 (c) shows a waveform when the frequency of the flag signal fg is 3 / T.

  When the frequency of the flag signal fg is 3 / T and the duty ratio is “0.5”, if the phase of the flag signal fg is changed, the waveforms of the command value signals Xu5, Xv5, and Xw5 change, In some cases, the waveform is specific.

  In FIG. 29, the command value signal when the phase of the flag signal fg is changed while the frequency of the flag signal fg is fixed to 3 / T (period is T / 3) and the duty ratio is fixed to “0.5”. The waveforms of Xu5, Xv5, and Xw5 are shown.

  FIG. 5A shows the waveforms of the command value signals Xu5, Xv5, and Xw5 when the phase of the flag signal fg is delayed by π / 6 (when the flag signal fg is switched to “1” when θ = π / 6). It is. In this case, the waveforms of the command value signals Xu5, Xv5, and Xw5 are the same as the waveforms of the command value signals Xu2, Xv2, and Xw2 (see FIG. 13) in the second embodiment. FIG. 6B shows the waveforms of the command value signals Xu5, Xv5, and Xw5 when the phase of the flag signal fg is delayed by π / 3 (when the flag signal fg is switched to “1” when θ = π / 3). It is. In this case, the waveforms of the command value signals Xu5, Xv5, Xw5 are the same as the waveforms of the command value signals Xu3, Xv3, Xw3 in the third embodiment (see FIG. 16). FIG. 5C shows the waveforms of the command value signals Xu5, Xv5, and Xw5 when the phase of the flag signal fg is delayed by π / 2 (when the flag signal fg is switched to “1” when θ = π / 2). It is. In this case, the waveforms of the command value signals Xu5, Xv5, Xw5 are the same as the waveforms of the command value signals Xu1, Xv1, Xw1 in the first embodiment (see FIG. 4). In other words, each command value signal according to the first to third embodiments has a specific condition in the command value signals Xu5, Xv5, Xw5 according to the fifth embodiment (the cycle of the flag signal fg is the cycle of the phase voltage command value signal Xu). 1/3, the duty ratio is “0.5”, and the phase is delayed by π / 6, π / 3, π / 2 from the phase of the phase voltage command value signal Xu). Since the phase θ of the phase voltage command value signal Xu is used as a reference, it is delayed by π / 6, π / 3, and π / 2. However, when the period of the flag signal fg is used as a reference, the flag signal fg The phase is delayed by π / 2, π, and 3π / 2. The waveform shown in FIG. 28C is the waveform of the command value signals Xu5, Xv5, and Xw5 when the phase of the flag signal fg is not changed (when the flag signal fg is switched to “1” when θ = 0). Thus, the waveform is the same as the waveform of the command value signals Xu4, Xv4, Xw4 (see FIG. 20) in the fourth embodiment.

  Note that the period (frequency) of the flag signal fg is not limited to that described above. When the duty ratio is “0.5”, the waveform of the command value signals Xu5, Xv5, and Xw5 differs depending on the period of the flag signal fg, but the period fixed at “2” and the period fixed at “0” Will occur. Therefore, a period in which the positive-side switching element continues to be on and a period in which the negative-side switching element continues to be on are generated, so that only one of the positive-side switching element and the negative-side switching element is Compared with the case where the ON state is continued, the difference between the time during which the positive-side switching element is in the ON state and the time during which the negative-side switching element is in the ON state can be reduced.

  When the duty ratio is “0.5” and the cycle of the flag signal fg is nT (n is a natural number), that is, when the cycle is a multiple of the cycle T of the phase voltage command value signal Xu, the command value signals Xu5, Xv5 , Xw5, the period fixed to “0” and the period fixed to “2” are the same, the time when the positive side switching element is in the on state and the negative side switching element are in the on state The time that is When the duty ratio is “0.5” and the cycle of the flag signal fg is 2nT (n is a natural number), that is, when the cycle is an even multiple of the cycle of the phase voltage command value signal Xu, the command value signal Xu5 , Xv5, and Xw5 are fixed to “0” and fixed to “2”, which is 1/6 of one cycle. In this case, the time during which the positive-side switching element is on and the time during which the negative-side switching element is on are equal, and the U-phase, V-phase, and W-phase switching elements are on. The time in the state is equivalent.

  The waveform of the command value signals Xu5, Xv5, and Xw5 varies depending on the phase of the flag signal fg, but when the duty ratio is “0.5”, the period is fixed to “2” and fixed to “0”. Period. Therefore, a period in which the positive-side switching element continues to be on and a period in which the negative-side switching element continues to be on are generated, so that only one of the positive-side switching element and the negative-side switching element is Compared with the case where the ON state is continued, the difference between the time during which the positive-side switching element is in the ON state and the time during which the negative-side switching element is in the ON state can be reduced.

  Although the case where the duty ratio of the flag signal fg is set to “0.5” has been described above, the present invention is not limited to this. Depending on the duty ratio of the flag signal fg, the period of the command value signals Xu5, Xv5, and Xw5 fixed at “0” and the period fixed at “2” are different.

  FIG. 30 shows the waveforms of the command value signals Xu5, Xv5, Xw5 and the flag signal fg when the duty ratio is changed with the period and phase of the flag signal fg fixed. FIG. 4A shows a waveform when the duty ratio of the flag signal fg is “0.45”, and FIG. 4B shows a waveform when the duty ratio of the flag signal fg is “0.5”. FIG. 8C shows a waveform when the duty ratio of the flag signal fg is “0.55”. The phase of the flag signal fg is matched with the phase θ of the phase voltage command value signal Xu. The period of the flag signal fg is 2T (= 1/30 [s]: frequency 30 Hz).

  The waveform shown in FIG. 30B is based on the same conditions as in FIG. 24, and therefore matches the waveform shown in FIG.

  The waveform shown in FIG. 30A is obtained by making the duty ratio of the flag signal fg smaller than that in the case of FIG. 30B, and 0 ≦ θ ≦ 1.8π (= 4π ··) of the waveform of FIG. The waveform is a combination of the 0.45) period portion and the 1.8π ≦ θ ≦ 4π period portion of the waveform in FIG. In this case, as compared with the waveform of FIG. 30B, the period in which the command value signals Xu5 and Xv5 are fixed to “0” becomes longer, and the period in which the command value signal Xw5 is fixed to “2” is shorter. It has become. Therefore, the period fixed to “0” in each command value signal Xu5, Xv5, Xw5 is longer than the period fixed to “2”. In this case, the time during which the positive-side switching element is on and the time during which the negative-side switching element is on are not equivalent, but the positive-side switching element and the negative-side switching element are Compared to the case where only one of them continues to be on, the difference between the time when the positive-side switching element is on and the time when the negative-side switching element is on can be reduced. it can.

  The waveform shown in FIG. 30C is obtained by increasing the duty ratio of the flag signal fg as compared with the case of FIG. 30B, and 0 ≦ θ ≦ 2.2π (= 4π · The waveform is a combination of the portion of 0.55) and the portion of 2.2π ≦ θ ≦ 4π of the waveform of FIG. In this case, as compared with the waveform of FIG. 30B, the period in which the command value signals Xu5 and Xw5 are fixed to “2” becomes longer, and the period in which the command value signal Xv5 is fixed to “0” is shorter. It has become. Therefore, the period fixed to “0” in each of the command value signals Xu5, Xv5, and Xw5 is shorter than the period fixed to “2”. In this case, the time during which the positive-side switching element is on and the time during which the negative-side switching element is on are not equivalent, but the positive-side switching element and the negative-side switching element are Compared to the case where only one of them continues to be on, the difference between the time when the positive-side switching element is on and the time when the negative-side switching element is on can be reduced. it can.

  Note that the duty ratio of the flag signal fg is not limited to that described above. The command value signals Xu5, Xv5, and Xw5 have different waveforms depending on the duty ratio of the flag signal fg. As the duty ratio becomes smaller, the period in which the command value signals Xu5, Xv5, and Xw5 are fixed to “0” becomes longer than the period in which the instruction value signals Xu5, Xv5, and Xw5 are fixed to “2”. A period fixed to “2” does not occur. Further, as the duty ratio increases, the period in which the command value signals Xu5, Xv5, and Xw5 are fixed to “0” becomes shorter than the period in which the command value signals Xu5, Xv5, and Xw5 are fixed to “2”, and the duty ratio becomes too large. And a period fixed at “0” does not occur. Therefore, the duty ratio of the flag signal fg is preferably closer to “0.5”, and is most preferably “0.5”.

  In the said 1st-5th embodiment, although the control circuit which controls the inverter circuit of a grid connection inverter system was demonstrated, it is not restricted to this. The present invention can also be applied to a control circuit that controls an inverter circuit of another system. Further, the present invention can be applied to other than the control circuit of the inverter circuit that converts DC power into AC power. For example, the present invention can also be applied to a control circuit for a power conversion circuit that uses three-phase AC power, such as a converter circuit that converts AC power into DC power. Even when the present invention is applied to these control circuits, the switching element can be periodically stopped to reduce the switching loss, and the positive side switching element and the negative side switching element are turned on. The effect that the time which is in a state can be made equal can be show | played.

  The control circuit according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the control circuit according to the present invention can be modified in various ways.

A Grid-connected inverter system 1 DC power supply 2 Inverter circuit (power conversion circuit)
S1 to S6 Switching elements D1 to D6 Free-wheeling diode C Smoothing capacitor 3 Filter circuit 4 Transformer circuit 5 Control circuit 51 Feedback control unit 52, 52 ′ Command value signal generation unit 521 First signal generation unit 522 Second signal generation unit 523 Flag signal Generation unit 524 Signal combination unit 53 PWM signal generation unit B Three-phase power system

Claims (23)

A control circuit that controls driving of a plurality of switching means in a power conversion circuit related to three-phase AC power by a PWM signal,
The waveform of the output or input AC phase voltage of the power conversion circuit is a waveform in which a predetermined lower limit voltage value is continued in a predetermined period and a predetermined upper limit voltage value is continued in another predetermined period. A control circuit that generates and outputs a PWM signal.   2. The control circuit according to claim 1, wherein each of the predetermined period and the other predetermined period is a period of 1/6 of one cycle. A first command value signal in which a waveform of one cycle is a waveform having a predetermined upper limit value in a period of 1/6 and a predetermined lower limit value in another period of 1/6;
A second command value signal whose phase is delayed by 2π / 3 with respect to the first command value signal;
A third command value signal whose phase is delayed by 4π / 3 with respect to the first command value signal;
Command value signal generating means for generating
PWM signal generating means for generating a PWM signal based on each command value signal;
With
The control circuit according to claim 2. The first command value signal has a waveform of one cycle,
"0" in 1/6 period,
In the following 1/6 period, the waveform is a waveform obtained by shifting the waveform of the sine wave in the interval from 5π / 3 to 2π upward by a predetermined value,
In the following 1/6 period, it is a sine wave waveform with a phase of π / 3 to 2π / 3,
It is the predetermined value in the following 1/6 period,
In the following 1/6 period, the phase is a sine wave waveform in the interval from 2π / 3 to π,
In the following 1/6 period, the waveform is a waveform obtained by shifting the waveform of the sine wave in the interval of 4π / 3 to 5π / 3 upward by the predetermined value.
The control circuit according to claim 3. The command value signal generation means is a difference between the three phase voltage command value signals generated to command the waveforms of the three-phase phase voltages output from the power conversion circuit and the phase voltage command value signals. 5. The control circuit according to claim 4, wherein the first to third command value signals are generated by the following method using three line voltage command value signals that are signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xuv is greater than the absolute value of Xvw and the absolute value of Xwu, and Xu is a positive value, the first command value signal Xu1 is set to Xuv, and the second command value signal Xv1 is set to “0”, and the third command value signal Xw1 is set to a negative value of Xvw.
(C) When the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xu is a negative value, Xu1 is the value obtained by adding Xuv to the predetermined value, and Xv1 is the predetermined value. , Xw1 is a value obtained by subtracting Xvw from the predetermined value.
(D) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a positive value, Xu1 is set to a negative value of Xwu, Xv1 is set to Xvw, and Xw1 is set to “0”. To do.
(E) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a negative value, Xu1 is set to a value obtained by subtracting Xwu from the predetermined value, and Xv1 is set to the predetermined value. A value obtained by adding Xvw is used, and Xw1 is used as the predetermined value.
(F) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a positive value, Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu. To do.
(G) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a negative value, Xu1 is the predetermined value, and Xv1 is a value obtained by subtracting Xuv from the predetermined value. , Xw1 is a value obtained by adding Xwu to the predetermined value. The first command value signal has a waveform of one cycle,
"0" in 1/6 period,
In the following 1/6 period, the waveform is a waveform obtained by shifting the waveform of the sine wave having a phase of 4π / 3 to 5π / 3 upward by a predetermined value,
In the following 1/6 period, the waveform is a sine wave with a phase of 0 to π / 3,
It is the predetermined value in the following 1/6 period,
In the following 1/6 period, it is a sine wave waveform with a phase of π / 3 to 2π / 3,
In the subsequent 1/6 period, the waveform of the sine wave having a phase of π to 4π / 3 is shifted upward by the predetermined value.
The control circuit according to claim 3. The command value signal generation means is a difference between the three phase voltage command value signals generated to command the waveforms of the three-phase phase voltages output from the power conversion circuit and the phase voltage command value signals. 7. The control circuit according to claim 6, wherein the first to third command value signals are generated by the following method using the three line voltage command value signals that are signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xu is a positive value, the first command value signal Xu2 is set as the predetermined value, and the second command The value signal Xv2 is a value obtained by subtracting Xuv from the predetermined value, and the third command value signal Xw2 is a value obtained by adding Xwu to the predetermined value.
(C) When the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xu is a negative value, Xu2 is set to “0”, Xv2 is set to a negative value of Xuv, and Xw2 is set to Xwu. To do.
(D) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a positive value,
Xu2 is a value obtained by adding Xuv to the predetermined value, Xv2 is the predetermined value, and Xw2 is a value obtained by subtracting Xvw from the predetermined value.
(E) When the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xv is a negative value, Xu2 is set to Xuv, Xv2 is set to “0”, Xw2 is set to a negative value of Xvw, To do.
(F) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a positive value, Xu2 is set to a value obtained by subtracting Xwu from the predetermined value, and Xv2 is set to the predetermined value. A value obtained by adding Xvw is used, and Xw2 is set as the predetermined value.
(G) When the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xw is a negative value, Xu2 is set to a negative value of Xwu, Xv2 is set to Xvw, and Xw2 is set to “0”. To do. The first command value signal has a waveform of one cycle,
"0" in 1/6 period,
In the subsequent 1/6 period, the waveform is a waveform obtained by shifting the waveform of the sine wave in the interval of 3π / 2 to 11π / 6 upward by a predetermined value,
In the following 1/6 period, the phase is a sine wave waveform with a phase of π / 6 to π / 2,
It is the predetermined value in the following 1/6 period,
In the following 1/6 period, the phase is a sine wave waveform with a phase of π / 2 to 5π / 6,
In the subsequent 1/6 period, the waveform is a waveform obtained by shifting the waveform of the sine wave having a phase of 7π / 6 to 3π / 2 upward by the predetermined value.
The control circuit according to claim 3. The command value signal generation means is a difference between the three phase voltage command value signals generated to command the waveforms of the three-phase phase voltages output from the power conversion circuit and the phase voltage command value signals. The control circuit according to claim 8, wherein the first to third command value signals are generated by the following method using three line voltage command value signals as signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xu is greater than the absolute value of Xv and the absolute value of Xw, and Xu is a positive value, the first command value signal Xu3 is set as the predetermined value, and the second command The value signal Xv3 is set to a value obtained by subtracting Xuv from the predetermined value, and the third command value signal Xw3 is set to a value obtained by adding Xwu to the predetermined value.
(C) When the absolute value of Xu is larger than the absolute value of Xv and the absolute value of Xw, and Xu is a negative value, Xu3 is set to “0”, Xv3 is set to a negative value of Xuv, and Xw3 is set to Xwu. To do.
(D) When the absolute value of Xv is larger than the absolute value of Xu and the absolute value of Xw, and Xv is a positive value, Xu3 is set to a value obtained by adding Xuv to the predetermined value, and Xv3 is set to the predetermined value. , Xw3 is a value obtained by subtracting Xvw from the predetermined value.
(E) When the absolute value of Xv is larger than the absolute value of Xu and the absolute value of Xw, and Xv is a negative value, Xu3 is set to Xuv, Xv3 is set to “0”, and Xw3 is set to a negative value of Xvw. To do.
(F) When the absolute value of Xw is larger than the absolute value of Xu and the absolute value of Xv, and Xw is a positive value, Xu3 is set to a value obtained by subtracting Xwu from the predetermined value, and Xv3 is set to the predetermined value. A value obtained by adding Xvw is used, and Xw3 is used as the predetermined value.
(G) When the absolute value of Xw is larger than the absolute value of Xu and the absolute value of Xv, and Xw is a negative value, Xu3 is set to a negative value of Xwu, Xv3 is set to Xvw, and Xw3 is set to “0”. To do.   The waveform of the output or input AC phase voltage of the power conversion circuit continues the predetermined upper limit voltage value in a period of 1/12 of one cycle, and the predetermined lower limit voltage value in the other period of 1/12. The PWM signal is generated and output so as to have a waveform that continues the upper limit voltage value in another 1/12 period and further continues the lower limit voltage value in another 1/12 period. The control circuit according to claim 1. One period of waveform is
“0” in 1/12 period,
In the following 1/12 period, the waveform is a sine wave with a phase of 0 to π / 6,
In the subsequent period of 1/12, the waveform is a waveform obtained by shifting the waveform of the sine wave in the section from 11π / 6 to 2π upward by a predetermined value,
It is the predetermined value in the following 1/12 period,
In the following 1/12 period, the phase is a sine wave waveform with a phase of π / 2 to 2π / 3,
In the following 1/12 period, the waveform is a sine wave waveform with a phase of π / 3 to π / 2,
It is the predetermined value in the following 1/12 period,
In the following 1/12 period, the waveform is a waveform obtained by shifting the waveform of the sine wave in the interval from π to 7π / 6 upward by a predetermined value,
In the subsequent 1/12 period, the phase is a sine wave waveform in the interval from 5π / 6 to π,
In the following 1/12 period, it is “0”,
In the following 1/12 period, the waveform is a waveform obtained by shifting the waveform of the sine wave in the interval of 3π / 2 to 5π / 3 upward by a predetermined value,
A first command value signal having a waveform obtained by shifting the waveform of the sine wave in the interval of 4π / 3 to 3π / 2 upward by a predetermined value in a subsequent 1/12 period;
A second command value signal whose phase is delayed by 2π / 3 with respect to the first command value signal;
A third command value signal whose phase is delayed by 4π / 3 with respect to the first command value signal;
Command value signal generating means for generating
PWM signal generating means for generating a PWM signal based on each command value signal;
With
The control circuit according to claim 1. The command value signal generation means is a difference between the three phase voltage command value signals generated to command the waveforms of the three-phase phase voltages output from the power conversion circuit and the phase voltage command value signals. The control circuit according to claim 11, wherein the first to third command value signals are generated by the following method using three line voltage command value signals as signals.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B) When the absolute value of Xu is a magnitude between the absolute value of Xv and the absolute value of Xw, and Xu is a positive value, the first command value signal Xu4 is set as the predetermined value, The second command value signal Xv4 is a value obtained by subtracting Xuv from the predetermined value, and the third command value signal Xw4 is a value obtained by adding Xwu to the predetermined value.
(C) When the absolute value of Xu is a magnitude between the absolute value of Xv and the absolute value of Xw, and Xu is a negative value, Xu4 is set to “0”, and Xv4 is set to a negative value of Xuv. , Xw4 is Xwu.
(D) When the absolute value of Xv is a magnitude between the absolute value of Xu and the absolute value of Xw, and Xv is a positive value, Xu4 is set to a value obtained by adding Xuv to the predetermined value, and Xv4 Is the predetermined value, and Xw4 is a value obtained by subtracting Xvw from the predetermined value.
(E) When the absolute value of Xv is a magnitude between the absolute value of Xu and the absolute value of Xw, and Xv is a negative value, Xu4 is set to Xuv, Xv4 is set to “0”, and Xw4 is set to Let Xvw be a negative value.
(F) When the absolute value of Xw is a magnitude between the absolute value of Xu and the absolute value of Xv, and Xw is a positive value, Xu4 is a value obtained by subtracting Xwu from the predetermined value, and Xv4 Is a value obtained by adding Xvw to the predetermined value, and Xw4 is the predetermined value.
(G) When the absolute value of Xw is a magnitude between the absolute value of Xu and the absolute value of Xv, and Xw is a negative value, Xu4 is set to a negative value of Xwu, Xv4 is set to Xvw, and Xw4 Is “0”. A first command value signal obtained by combining the first signal and the second signal, a signal delayed in phase by 2π / 3 with respect to the first signal, and a phase of 2π with respect to the second signal A second command value signal combined with a signal delayed by / 3, a signal delayed in phase by 4π / 3 with respect to the first signal, and a phase by 4π / 3 with respect to the second signal. Command value signal generating means for generating a third command value signal in combination with the delayed signal;
PWM signal generating means for generating a PWM signal based on each command value signal;
With
The first signal is a waveform of a sine wave in which the waveform of one cycle is “0” in a period of 1/3, and the phase is 0 to 2π / 3 in the subsequent period of 1/3, and the rest Is a sine wave waveform with a phase of π / 3 to π in a period of 1/3 of
In the second signal, a waveform of one cycle has a predetermined value in a period of 1/3, and in the subsequent 1/3 period, a waveform of a sine wave having a phase of π to 5π / 3 is only the predetermined value. It is a waveform shifted upward, and is a waveform obtained by shifting the waveform of a sine wave in the interval of 4π / 3 to 2π upward by the predetermined value in the remaining 1/3 period.
The control circuit according to claim 1. The command value signal generating means is
Generate a flag signal that repeats high level and low level at a predetermined cycle,
Based on the flag signal, the first command value signal is generated by switching between the first signal and the second signal.
The control circuit according to claim 13. The command value signal generating means includes three line voltage commands that are differential signals of the three phase voltage command value signals generated to command the waveforms of the three-phase phase voltages output from the power conversion circuit. 15. The control circuit according to claim 14, wherein the first to third command value signals are generated by the following method using the value signal and the flag signal.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B1) When the flag signal is at a low level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, the first command value signal Xu5 is set to Xuv. The second command value signal Xv5 is set to “0”, and the third command value signal Xw5 is set to a negative value of Xvw.
(C1) When the flag signal is at a low level and the absolute value of Xuv is greater than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, Xu5 is set to “0” and Xv5 is set to Xuv Let it be a negative value, and let Xw5 be Xwu.
(D1) When the flag signal is at a low level and the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, Xu5 is set to a negative value of Xwu, and Xv5 is set to Xvw And Xw5 is set to “0”.
(E1) When the flag signal is at a low level and the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu5 is set to Xuv and Xv5 is set to “0”. , Xw5 is a negative value of Xvw.
(F1) When the flag signal is at a low level and the absolute value of Xwu is larger than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu5 is set to “0” and Xv5 is set to Xuv Let it be a negative value, and let Xw5 be Xwu.
(G1) When the flag signal is at a low level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu5 is set to a negative value of Xwu, and Xv5 is set to Xvw And Xw5 is set to “0”.
(B2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, Xu5 is set as the predetermined value, and Xv5 is set as the predetermined value. Xuv is subtracted from the value, and Xw5 is the value obtained by adding Xwu to the predetermined value.
(C2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, a value obtained by adding Xuv to the predetermined value and Xuv Xv5 is the predetermined value, and Xw5 is a value obtained by subtracting Xvw from the predetermined value.
(D2) When the flag signal is at a high level, the absolute value of Xvw is greater than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, Xu5 is a value obtained by adding Xuv to the predetermined value Xv5 is the predetermined value, and Xw5 is a value obtained by subtracting Xvw from the predetermined value.
(E2) When the flag signal is at a high level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu5 is a value obtained by subtracting Xwu from the predetermined value Xv5 is a value obtained by adding Xvw to the predetermined value, and Xw5 is the predetermined value.
(F2) When the flag signal is at a high level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu5 is obtained by subtracting Xwu from the predetermined value Xv5 is a value obtained by adding Xvw to the predetermined value, and Xw5 is the predetermined value.
(G2) When the flag signal is at a high level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu5 is set as the predetermined value, and Xv5 is set as the predetermined value. Xuv is subtracted from the value, and Xw5 is the value obtained by adding Xwu to the predetermined value.   The control circuit according to claim 15, wherein a period of the flag signal is an even multiple of a period of the phase voltage command value signal.   The control circuit according to claim 15, wherein the frequency of the flag signal is a multiple of 3/4 of the frequency of the phase voltage command value signal.   18. The control circuit according to claim 14, wherein the flag signal has the same length of a high level period and a low level period.   The control circuit according to claim 4, wherein the PWM signal generation unit generates the PWM signal by comparing the three command value signals with a predetermined carrier signal. The carrier signal is a signal that changes between the predetermined value and “0”.
The control circuit according to claim 19.   The grid connection inverter system provided with the inverter circuit and the control circuit in any one of Claim 1 thru | or 20 which controls the said inverter circuit.   A program for causing a computer to function as the control circuit according to any one of claims 1 to 20.   A computer-readable recording medium on which the program according to claim 22 is recorded.