JP2013033887A - Nitride semiconductor substrate manufacturing method - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 61
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 40
- 239000013078 crystal Substances 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 239000007789 gas Substances 0.000 claims abstract description 38
- 239000012298 atmosphere Substances 0.000 claims abstract description 28
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 23
- 239000011261 inert gas Substances 0.000 claims abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 17
- 239000010410 layer Substances 0.000 description 123
- 239000010408 film Substances 0.000 description 15
- 238000011156 evaluation Methods 0.000 description 12
- 239000010409 thin film Substances 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000000523 sample Substances 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- 238000001947 vapour-phase growth Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000012299 nitrogen atmosphere Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000001737 promoting effect Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 3
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000572 ellipsometry Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 229910052743 krypton Inorganic materials 0.000 description 2
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- -1 compound compound Chemical class 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
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- 230000011218 segmentation Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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Abstract
Description
本発明は、電子デバイス用の窒化物半導体に用いられる窒化物半導体基板の製造方法に関する。 The present invention relates to a method for manufacturing a nitride semiconductor substrate used for a nitride semiconductor for electronic devices.
次世代電子デバイス材料として期待されている窒化ガリウム(GaN)等の窒化物半導体の製造方法の一例として、大口径化や低コスト化に有利といわれる、シリコン単結晶基板上に窒化物半導体を形成する方法があり、その製造方法もいくつか知られている。 Forming a nitride semiconductor on a silicon single crystal substrate, which is said to be advantageous for increasing the diameter and cost, as an example of a method for manufacturing a nitride semiconductor such as gallium nitride (GaN), which is expected as a next-generation electronic device material There are several methods for manufacturing the same.
特許文献1には、基板と、前記基板上に形成されたAlN系超格子バッファ層と、前記AlN系超格子バッファ層の上に形成された窒化物半導体層とからなる窒化物半導体素子の製造方法であって、前記基板上に、AlxGa1−xN(0.5≦x≦1)の組成を持つ第1のバッファ層を形成するステップと、前記第1のバッファ層の上に、AlyGa1−yN(0.01≦y≦0.2)の組成を持つ第2のバッファ層を形成するステップと、前記第1のバッファ層を形成するステップおよび前記第2のバッファ層を形成するステップを交互に繰り返して前記AlN系超格子バッファ層を形成するステップと、を備えたことを特徴とする窒化物半導体素子の製造方法の発明が開示されている。 Japanese Patent Application Laid-Open No. 2004-228561 discloses a method for manufacturing a nitride semiconductor device including a substrate, an AlN-based superlattice buffer layer formed on the substrate, and a nitride semiconductor layer formed on the AlN-based superlattice buffer layer. Forming a first buffer layer having a composition of Al x Ga 1-x N (0.5 ≦ x ≦ 1) on the substrate; and on the first buffer layer. Forming a second buffer layer having a composition of Al y Ga 1-y N (0.01 ≦ y ≦ 0.2), forming the first buffer layer, and the second buffer And a step of forming the AlN-based superlattice buffer layer by alternately repeating the step of forming the layer, and an invention of a method of manufacturing a nitride semiconductor device, comprising:
特許文献2には、単結晶シリコン基板上に絶縁膜を形成する工程、前記絶縁膜上にチッ化ガリウム系化合物半導体層を成膜してバッファ層とする工程、前記バッファ層上にチッ化ガリウム系化合物半導体からなる下部クラッド層、活性層、上部クラッド層およびキャップ層を順次積層する工程、前記単結晶シリコン基板に垂直にエッチングして、前記バッファ層を露出させる工程、前記キャップ層および前記エッチングにより露出したバッファ層上に電極を形成する工程、およびダイシングまたは劈開によってチップに分離する工程、からなる半導体発光素子の製法の発明が開示されている。 Patent Document 2 discloses a step of forming an insulating film on a single crystal silicon substrate, a step of forming a gallium nitride-based compound semiconductor layer on the insulating film to form a buffer layer, and gallium nitride on the buffer layer. A step of sequentially laminating a lower clad layer, an active layer, an upper clad layer and a cap layer made of a compound compound semiconductor, a step of etching perpendicularly to the single crystal silicon substrate to expose the buffer layer, the cap layer and the etching An invention of a method for producing a semiconductor light-emitting device comprising a step of forming an electrode on the buffer layer exposed by the above and a step of separating the chip by dicing or cleaving is disclosed.
特許文献1は、シリコン基板上に、AlxGa1−xN(0.5≦x≦1)の組成を持つ第1のバッファ層を形成するステップにおいて、アンモニア等の原料ガスあるいは水素等のキャリアガスによってシリコン基板表面がエッチングされ、シリコン基板表面に凹凸が発生する、としている。 Patent Document 1 discloses that in a step of forming a first buffer layer having a composition of Al x Ga 1-x N (0.5 ≦ x ≦ 1) on a silicon substrate, a source gas such as ammonia or hydrogen The silicon substrate surface is etched by the carrier gas, and unevenness is generated on the silicon substrate surface.
しかし、この凹凸が存在する状態で、新たな窒化物の膜を形成すると、この凹凸に起因する欠陥が窒化物の膜中に発生し、窒化物半導体面上にmmオーダーの広い面積の電極を形成したとき、絶縁破壊電圧低下による絶縁破壊不良が多発する。 However, if a new nitride film is formed in the presence of the irregularities, defects due to the irregularities occur in the nitride film, and an electrode with a wide area on the order of mm is formed on the nitride semiconductor surface. When formed, dielectric breakdown defects frequently occur due to a decrease in dielectric breakdown voltage.
そこで、シリコン基板上に窒化物半導体層を形成する場合、シリコン基板上に窒化ケイ素の膜を形成するという技術が知られており、この方法によれば、比較的簡易な方法で、窒化物半導体層への転位発生の抑制や、平坦性の向上が図れるとされている。 Therefore, when a nitride semiconductor layer is formed on a silicon substrate, a technique of forming a silicon nitride film on the silicon substrate is known. According to this method, a nitride semiconductor is formed by a relatively simple method. It is said that the occurrence of dislocation to the layer can be suppressed and the flatness can be improved.
特許文献2には、チッ素雰囲気中500〜900℃で熱処理、単結晶シリコン基板上の表面をチッ化、Si3N4の絶縁膜を1〜5nmの厚さで形成、その上に気相成長法で窒化物半導体からなる各層を形成、という半導体発光素子の製法が開示されている。 In Patent Document 2, heat treatment is performed in a nitrogen atmosphere at 500 to 900 ° C., the surface on the single crystal silicon substrate is nitrided, an Si 3 N 4 insulating film is formed to a thickness of 1 to 5 nm, and a vapor phase is formed thereon. A manufacturing method of a semiconductor light emitting device is disclosed in which each layer made of a nitride semiconductor is formed by a growth method.
しかし、特許文献2に記載の技術には、シリコン上に窒化ケイ素の膜を形成するにあたり、詳細な保持時間、保持雰囲気のガス種類については具体的な開示がない。このため、窒化物半導体面上にmmオーダーの広い面積の電極を形成したときの絶縁破壊電圧低下を、効果的に低減することが困難であった。 However, the technique disclosed in Patent Document 2 does not specifically disclose the detailed holding time and the type of gas in the holding atmosphere when forming a silicon nitride film on silicon. For this reason, it has been difficult to effectively reduce the dielectric breakdown voltage drop when an electrode having a wide area on the order of mm is formed on the nitride semiconductor surface.
これらの課題を鑑み、本発明は、シリコン単結晶基板上に窒化物を堆積させるときに発生する凹凸に起因する、窒化物半導体層の絶縁破壊電圧低下を、簡易かつ効果的に低減することの出来る、窒化物半導体基板の製造方法を提供する。 In view of these problems, the present invention can easily and effectively reduce the dielectric breakdown voltage drop of a nitride semiconductor layer caused by unevenness generated when nitride is deposited on a silicon single crystal substrate. Provided is a method for manufacturing a nitride semiconductor substrate.
本発明に係る窒化物半導体基板の製造方法は、シリコン単結晶基板の一主面上に窒化ケイ素層を形成する工程と、前記窒化ケイ素層上に窒化物半導体からなる中間層を形成する工程と、前記中間層上に窒化物半導体からなる活性層を形成する工程と、を含む窒化物半導体基板の製造方法であって、前記窒化ケイ素層を形成する工程は、窒素ガスが90vol%以上100vol%以下で残部は前記窒素ガス以外の不活性ガスからなるガス雰囲気にて室温から900℃以上1000℃以下の到達温度まで昇温する第1ステップと、前記ガス雰囲気と前記到達温度のままで所定時間保持する第2ステップと、その後還元性ガス含有雰囲気に切り替えて所定時間保持する第3ステップと、からなることを特徴とする。 The method for manufacturing a nitride semiconductor substrate according to the present invention includes a step of forming a silicon nitride layer on one main surface of a silicon single crystal substrate, and a step of forming an intermediate layer made of a nitride semiconductor on the silicon nitride layer. Forming an active layer made of a nitride semiconductor on the intermediate layer, wherein the step of forming the silicon nitride layer includes nitrogen gas of 90 vol% or more and 100 vol% In the following, the remainder is a first step of raising the temperature from room temperature to an ultimate temperature of 900 ° C. to 1000 ° C. in a gas atmosphere composed of an inert gas other than the nitrogen gas, and the gas atmosphere and the ultimate temperature for a predetermined time. It is characterized by comprising the second step of holding and the third step of switching to the reducing gas-containing atmosphere and holding it for a predetermined time.
これにより、絶縁破壊電圧低下が低減された窒化物半導体基板を、簡易かつ効果的に製造することができる。 Thereby, the nitride semiconductor substrate in which the dielectric breakdown voltage drop is reduced can be manufactured easily and effectively.
本発明に係る窒化物半導体基板の製造方法は、第3ステップの還元性ガス含有雰囲気が、還元性ガス30vol%以上70vol%以下で残部は不活性ガスからなることが望ましい。 In the method for manufacturing a nitride semiconductor substrate according to the present invention, it is desirable that the reducing gas-containing atmosphere in the third step is 30 vol% or more and 70 vol% or less of the reducing gas, and the balance is made of an inert gas.
本発明によれば、シリコン単結晶基板上に窒化物を堆積させるときに発生する凹凸に起因する窒化物半導体層の絶縁破壊電圧低下を、簡易かつ効果的に低減した窒化物半導体基板の作製が可能となる。特に、面積の大きい電極を窒化物半導体層に形成した場合において、より顕著な効果を呈するものである。 According to the present invention, it is possible to easily and effectively reduce the breakdown voltage drop of a nitride semiconductor layer caused by unevenness generated when depositing nitride on a silicon single crystal substrate. It becomes possible. In particular, when an electrode having a large area is formed in the nitride semiconductor layer, a more remarkable effect is exhibited.
本発明を、図面を参照して説明する。図1は、本発明に係る窒化物半導体基板の製造方法で作製された窒化物半導体基板の構造を、断面方向から見たときの概念図である。 The present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram of a structure of a nitride semiconductor substrate manufactured by the method for manufacturing a nitride semiconductor substrate according to the present invention as viewed from a cross-sectional direction.
本発明は、シリコン単結晶基板1の一主面上に窒化ケイ素層2を形成する工程と、窒化ケイ素層2上に窒化物半導体からなる中間層3を形成する工程と、中間層3上に窒化物半導体からなる活性層4を形成する工程と、を含む窒化物半導体基板Wの製造方法であって、窒化ケイ素層2を形成する工程は、窒素ガスが90vol%以上100vol%以下で残部は前記窒素ガス以外の不活性ガスからなるガス雰囲気にて室温から900℃以上1000℃以下の到達温度まで昇温する第1ステップと、前記ガス雰囲気と前記到達温度のままで所定時間保持する第2ステップと、その後還元性ガス含有雰囲気に切り替えて所定時間保持する第3ステップと、からなる。 The present invention includes a step of forming a silicon nitride layer 2 on one main surface of a silicon single crystal substrate 1, a step of forming an intermediate layer 3 made of a nitride semiconductor on the silicon nitride layer 2, A method of manufacturing a nitride semiconductor substrate W including a step of forming an active layer 4 made of a nitride semiconductor, wherein the step of forming the silicon nitride layer 2 includes nitrogen gas of 90 vol% or more and 100 vol% or less, and the remainder A first step of raising the temperature from room temperature to an ultimate temperature of 900 ° C. to 1000 ° C. in a gas atmosphere composed of an inert gas other than the nitrogen gas; and a second step of maintaining the gas atmosphere and the ultimate temperature for a predetermined time. And a third step of switching to a reducing gas-containing atmosphere and holding for a predetermined time.
窒化物半導体基板Wの製造方法には、広く公知の製法が適用できるが、優れた成膜制御性と扱いやすさの点で、有機金属化学気相成長(MOCVD)法が好適である。以下、MOCVD法での製造工程に準じて説明する。 A widely known manufacturing method can be applied to the method for manufacturing the nitride semiconductor substrate W, but a metal organic chemical vapor deposition (MOCVD) method is preferable in terms of excellent film formation controllability and ease of handling. Hereinafter, description will be made according to the manufacturing process by the MOCVD method.
まず、シリコン単結晶基板1を、MOCVD装置にセットする。このとき、シリコン単結晶基板1の表面は、自然酸化膜あるいは有機物等が残存しない状態が好ましい。このため、MOCVD装置にセットする前に、シリコン単結晶基板1を、あらかじめ公知の半導体基板の洗浄方法を適用するとよい。 First, the silicon single crystal substrate 1 is set in an MOCVD apparatus. At this time, the surface of the silicon single crystal substrate 1 is preferably in a state where no natural oxide film or organic matter remains. For this reason, a known semiconductor substrate cleaning method may be applied to the silicon single crystal substrate 1 in advance before setting the MOCVD apparatus.
シリコン単結晶基板1は、窒化物半導体基板Wにおける下地基板となる。その口径、厚さ、抵抗、ドーパントタイプ、面方位、表裏面の面仕上げ状態、欠陥密度、酸素濃度、等については、設計される窒化物半導体基板Wの仕様に応じて、適時設定してよい。シリコン単結晶基板1の製造方法としては、例えば、チョクラルスキー(CZ)法、フローティングゾーン(FZ)法、貼りあわせ法、が挙げられる。 The silicon single crystal substrate 1 becomes a base substrate in the nitride semiconductor substrate W. The aperture, thickness, resistance, dopant type, surface orientation, surface finish state of front and back surfaces, defect density, oxygen concentration, etc. may be set as appropriate according to the specifications of the nitride semiconductor substrate W to be designed. . Examples of the method for manufacturing the silicon single crystal substrate 1 include a Czochralski (CZ) method, a floating zone (FZ) method, and a bonding method.
次に、窒化ケイ素層2を形成する工程を行う。まず、第1ステップとして、窒素ガスが90vol%以上100vol%以下で残部は前記窒素ガス以外の不活性ガスからなるガス雰囲気にて室温から900℃以上1000℃以下の到達温度まで昇温する。 Next, a step of forming the silicon nitride layer 2 is performed. First, as a first step, the temperature is raised from room temperature to an ultimate temperature of 900 ° C. or higher and 1000 ° C. or lower in a gas atmosphere composed of 90 vol% or more and 100 vol% or less of the nitrogen gas and an inert gas other than the nitrogen gas.
MOCVD装置にセットされたシリコン単結晶基板1の処理雰囲気は、大気雰囲気から窒素雰囲気に切り替えられる。その切り替えのタイミングは、室温状態でも、あるいは昇温途中でもよいが、後者の場合、600℃に達する前に窒素雰囲気への置換が完了されることが好ましい。これは、反応室内に残留する酸素や水分が、温度が高いことでシリコンと活発に反応し、次工程の窒化ケイ素層2の形成に悪影響を及ぼす懸念があることによる。 The processing atmosphere of the silicon single crystal substrate 1 set in the MOCVD apparatus is switched from the air atmosphere to the nitrogen atmosphere. The switching timing may be at room temperature or during the temperature increase. In the latter case, it is preferable that the replacement with the nitrogen atmosphere is completed before reaching 600 ° C. This is because oxygen and moisture remaining in the reaction chamber react actively with silicon due to the high temperature, and there is a concern that the formation of the silicon nitride layer 2 in the next step may be adversely affected.
ガス雰囲気は、窒素ガスが90vol%以上100vol%以下で残部は前記窒素ガス以外の不活性ガスからなることが望ましい。窒素ガスが90vol%未満では、次工程において、窒化ケイ素層2が、均等な厚さでかつ高品質に形成されないおそれがある。好適には窒素ガス濃度が98vol%以上、より好適には100vol%である。 As for gas atmosphere, it is desirable for nitrogen gas to be 90 vol% or more and 100 vol% or less, and the remainder to consist of inert gas other than the said nitrogen gas. If the nitrogen gas is less than 90 vol%, the silicon nitride layer 2 may not be formed with a uniform thickness and high quality in the next step. The nitrogen gas concentration is preferably 98 vol% or more, more preferably 100 vol%.
窒素ガスは、例えば、純度99.999%以上の半導体製造用高純度窒素ガスが好適である。なお、窒素ガス濃度が100%未満の場合における窒素ガス以外の残部は、不活性ガスが好ましく、一例として、アルゴン、キセノン、クリプトンが挙げられる。 The nitrogen gas is preferably, for example, a high-purity nitrogen gas for semiconductor production having a purity of 99.999% or higher. In addition, the inert gas is preferable as the remainder other than the nitrogen gas when the nitrogen gas concentration is less than 100%, and examples thereof include argon, xenon, and krypton.
次に、MOCVD装置にセットされたシリコン単結晶基板1は、室温から900℃以上1000℃以下の到達温度まで昇温される。このとき、シリコン単結晶基板1の表層部が窒素雰囲気下で窒化され、窒化ケイ素層2が形成される。 Next, the silicon single crystal substrate 1 set in the MOCVD apparatus is heated from room temperature to an ultimate temperature of 900 ° C. to 1000 ° C. At this time, the surface layer portion of the silicon single crystal substrate 1 is nitrided in a nitrogen atmosphere to form the silicon nitride layer 2.
室温は、厳密に規定されるものではないが、5℃以上35℃以下の範囲である。 The room temperature is not strictly defined but is in the range of 5 ° C. or more and 35 ° C. or less.
到達温度は、900℃以上1000℃以下の範囲、好ましくは、950℃以上1000℃以下である。 The ultimate temperature is in the range of 900 ° C. or higher and 1000 ° C. or lower, preferably 950 ° C. or higher and 1000 ° C. or lower.
到達温度が900℃未満では、必要とされる窒化ケイ素層2を構成する窒化ケイ素の生成が不十分となるおそれがある。1000℃を越えると、成長速度が必要以上に速くなり、窒化ケイ素が、シリコン単結晶基板1の一主面における平面方向に対して、均等に成膜せず、その結果、窒化ケイ素層2の表層凹凸の最大高低差が増大する懸念がある。 When the ultimate temperature is less than 900 ° C., the required generation of silicon nitride constituting the silicon nitride layer 2 may be insufficient. When the temperature exceeds 1000 ° C., the growth rate becomes unnecessarily high, and silicon nitride is not formed evenly in the planar direction on one main surface of the silicon single crystal substrate 1, and as a result, the silicon nitride layer 2 is not formed. There is a concern that the maximum height difference of the surface irregularities increases.
なお、窒化ケイ素層2の表層凹凸とその最大高低差については、図2および実施例で説明する。 The surface unevenness of the silicon nitride layer 2 and the maximum height difference thereof will be described with reference to FIG.
ここで、昇温には、10分以上200分以下の時間をかけることが望ましい。この範囲であると、シリコン単結晶基板1の表層部にあるシリコン原子と窒素分子とが反応して、窒化ケイ素が生成する成長速度は非常に遅くなり、極端に大きい表層凹凸が生成しにくい。 Here, it is desirable to spend 10 minutes or more and 200 minutes or less for raising the temperature. Within this range, the silicon atoms and nitrogen molecules in the surface layer portion of the silicon single crystal substrate 1 react with each other, so that the growth rate of silicon nitride is extremely slow, and extremely large surface irregularities are not easily generated.
昇温時間が10分未満では、昇温速度が速すぎて、窒化ケイ素層2が、シリコン単結晶基板1上の全面に対して、均等な膜厚で生成されにくい。その結果として、層の厚さの均一性が低下する。昇温時間が200分以上では、本発明の温度領域では、窒化ケイ素層2の平均厚さがほとんど増加せず、製造プロセス上の工程ロスに繋がる。 If the temperature rising time is less than 10 minutes, the temperature rising speed is too high, and the silicon nitride layer 2 is not easily formed with a uniform film thickness on the entire surface of the silicon single crystal substrate 1. As a result, the layer thickness uniformity is reduced. When the temperature rising time is 200 minutes or more, the average thickness of the silicon nitride layer 2 hardly increases in the temperature range of the present invention, which leads to a process loss in the manufacturing process.
引き続き、第一ステップのガス雰囲気および到達温度のままで、所定時間保持する第2ステップに移る。この第2ステップは、昇温工程の遅い成長速度で生成された窒化ケイ素層2が、シリコン単結晶基板1上で均等な厚さとなるように、必要にして十分な時間保持する、いわゆる層厚の均等化の役目を有する。 Subsequently, the process proceeds to the second step in which the gas atmosphere and the ultimate temperature in the first step are maintained for a predetermined time. This second step is a so-called layer thickness in which the silicon nitride layer 2 generated at a slow growth rate in the temperature raising process is maintained for a sufficient time as necessary so that the silicon nitride layer 2 has a uniform thickness on the silicon single crystal substrate 1. It has the role of equalization.
第2ステップの保持時間は、1分以上10分以下であることが望ましい。1分未満では、層厚の均等化の効果が十分得られない。10分を超えると、窒化ケイ素層2の形成が進行する過程で、窒化ケイ素層2の表層凹凸の最大高低差T2が大きくなるおそれがある。 The holding time of the second step is desirably 1 minute or more and 10 minutes or less. If it is less than 1 minute, the effect of equalizing the layer thickness cannot be sufficiently obtained. If it exceeds 10 minutes, the maximum height difference T2 of the surface irregularities of the silicon nitride layer 2 may increase in the process of forming the silicon nitride layer 2.
第2ステップに続いて、雰囲気を、還元性ガス含有雰囲気に変更して所定時間保持する第3ステップが実施される。還元性ガスが存在することにより、窒化ケイ素層2の表層凹凸を埋めるように、窒化ケイ素分子が移動するのを促進する作用が引き起こされる。 Subsequent to the second step, a third step is performed in which the atmosphere is changed to a reducing gas-containing atmosphere and held for a predetermined time. The presence of the reducing gas causes an action of promoting the movement of silicon nitride molecules so as to fill the surface irregularities of the silicon nitride layer 2.
よって、第2ステップのみで窒化ケイ素を形成する場合と比べて、より一層表層凹凸が低減される。また、必要以上の膜厚増加が生じないので、シリコン単結晶基板1の結晶面方位情報が、上方に形成される窒化物半導体に対して、より的確に伝えられる。 Therefore, the surface layer unevenness is further reduced as compared with the case of forming silicon nitride only in the second step. Further, since the film thickness does not increase more than necessary, the crystal plane orientation information of the silicon single crystal substrate 1 is more accurately transmitted to the nitride semiconductor formed above.
還元性ガス含有雰囲気は、還元性ガスが30vol%以上70vol%以下で残部が不活性ガスであることが望ましい。還元性ガスが30vol%未満では、還元性ガス不足で、窒化ケイ素分子の移動を促進する作用が十分発揮されない懸念がある。一方、還元性ガスが70vol%を越えると、還元性ガス過多になり、窒化ケイ素分子の移動を促進する作用が過大になり、表層凹凸が大きくなる懸念がある。 In the reducing gas-containing atmosphere, it is desirable that the reducing gas is 30 vol% or more and 70 vol% or less and the balance is an inert gas. If the reducing gas is less than 30 vol%, there is a concern that the action of promoting the movement of silicon nitride molecules is not sufficiently exhibited due to the lack of reducing gas. On the other hand, when the reducing gas exceeds 70 vol%, the reducing gas becomes excessive, the action of promoting the movement of silicon nitride molecules becomes excessive, and there is a concern that the surface irregularities become large.
還元性ガスは、高純度品が入手容易で取扱いも周知である点から、水素が好ましい。例えば、純度99.999%以上の半導体製造用高純度水素ガスが挙げられる。不活性ガスとしては、窒素ガス、アルゴン、キセノン、クリプトン等が挙げられる。 The reducing gas is preferably hydrogen because a high-purity product is easily available and handling is well known. For example, high-purity hydrogen gas for semiconductor production having a purity of 99.999% or more can be given. Examples of the inert gas include nitrogen gas, argon, xenon, and krypton.
なお、第3ステップにおける保持時間は、1分以上10分以下であることが望ましい。1分未満では、均一な成膜が行われず、10分を超えると、膜厚が厚いことによる表層凹凸の増大が懸念されるためである。 The holding time in the third step is desirably 1 minute or more and 10 minutes or less. If it is less than 1 minute, uniform film formation is not performed, and if it exceeds 10 minutes, there is a concern about increase in surface irregularities due to the thick film thickness.
さらに、還元性ガス含有雰囲気での保持温度は、第1ステップの到達温度から、±50℃の範囲で温度を変更してから実施してもよい。この範囲内であれば、本発明の混合ガス雰囲気での保持効果が、著しく損なわれるおそれはないからである。 Further, the holding temperature in the reducing gas-containing atmosphere may be implemented after changing the temperature within the range of ± 50 ° C. from the temperature reached in the first step. This is because, within this range, the holding effect in the mixed gas atmosphere of the present invention is not likely to be significantly impaired.
続いて、第3ステップが終了したシリコン単結晶基板1の一主面上に、窒化物半導体からなる中間層3を気相成長法にて少なくとも1層形成する。そして、中間層3上に、窒化物半導体層からなる活性層4を、少なくとも1層以上形成する。ここでは、設計されるデバイスの仕様に合わせて、任意の組成、厚さ、層数の窒化物半導体層を形成してよい。 Subsequently, at least one intermediate layer 3 made of a nitride semiconductor is formed on one main surface of the silicon single crystal substrate 1 for which the third step has been completed by a vapor deposition method. Then, at least one active layer 4 made of a nitride semiconductor layer is formed on the intermediate layer 3. Here, a nitride semiconductor layer having an arbitrary composition, thickness, and number of layers may be formed in accordance with the specifications of the device to be designed.
本発明に係る窒化物半導体基板の製造方法で製造された窒化物半導体基板Wは、図1に示すように、シリコン単結晶基板1の一主面上に窒化ケイ素層2が形成され、その上には、少なくとも1層の窒化物半導体からなる中間層3と、中間層3上に少なくとも1層の窒化物半導体からなる活性層4を備える。中間層3と活性層4は、作製する製品の目的や仕様に応じて、広く公知の窒化物半導体基板の構成を適用できる。 A nitride semiconductor substrate W manufactured by the method for manufacturing a nitride semiconductor substrate according to the present invention has a silicon nitride layer 2 formed on one main surface of a silicon single crystal substrate 1, as shown in FIG. Includes an intermediate layer 3 made of at least one nitride semiconductor and an active layer 4 made of at least one nitride semiconductor on the intermediate layer 3. For the intermediate layer 3 and the active layer 4, a well-known configuration of a nitride semiconductor substrate can be applied according to the purpose and specification of the product to be manufactured.
窒化ケイ素層2は、シリコン単結晶基板1の一主表面に対して、窒化物半導体層を気相成長法などの手段で形成する際に生じる、微小な表層凹凸の発生を抑制する。この表層凹凸が大きいと、窒化物半導体基板Wの絶縁破壊電圧の低下を招く。 The silicon nitride layer 2 suppresses the occurrence of minute surface irregularities that occur when a nitride semiconductor layer is formed on the main surface of the silicon single crystal substrate 1 by means such as vapor phase growth. If the surface irregularities are large, the breakdown voltage of the nitride semiconductor substrate W is lowered.
窒化ケイ素層2の平均厚さT1は、1nm以上3nm以下であることが望ましい。1nm以下では、表層凹凸発生を抑制する効果が不十分である。しかし、3nmを超えると、シリコン単結晶基板1の結晶情報が、中間層3および活性層4に正確に伝播されず、中間層3および活性層4の結晶性が損なわれる懸念がある。 The average thickness T1 of the silicon nitride layer 2 is desirably 1 nm or more and 3 nm or less. If it is 1 nm or less, the effect of suppressing the occurrence of surface irregularities is insufficient. However, if the thickness exceeds 3 nm, the crystal information of the silicon single crystal substrate 1 is not accurately propagated to the intermediate layer 3 and the active layer 4, and there is a concern that the crystallinity of the intermediate layer 3 and the active layer 4 is impaired.
窒化ケイ素層2の表層凹凸の最大高低差T2は、0.3nm以下であることが望ましい。これは、完全に平坦な窒化ケイ素の層が理想であるが、実際にはその実現が困難であることを考慮し、実用上窒化ケイ素1分子径なら、その上に形成する中間層3の平坦性確保には問題のないレベルであるとする。それでも、T2が0.3nmを超えると、絶縁破壊電圧の低下が大きくなるおそれがある。 The maximum height difference T2 of the surface irregularities of the silicon nitride layer 2 is desirably 0.3 nm or less. In consideration of the fact that a completely flat silicon nitride layer is ideal, but it is difficult to realize it in practice, if the silicon nitride has a single molecular diameter in practical use, the intermediate layer 3 formed thereon is flat. It is assumed that there is no problem in ensuring safety. Still, if T2 exceeds 0.3 nm, the dielectric breakdown voltage may decrease significantly.
なお、窒化ケイ素層2の表層凹凸の最大高低差T2は、絶対値が0.3nm近辺という表層凹凸としては非常に小さい値であるにもかかわらず、絶縁破壊電圧に非常に敏感に作用する。この点を考慮して、本発明の窒化物半導体基板Wは、窒化ケイ素層2の厚さと表層凹凸を低く抑えて設計される。 Note that the maximum height difference T2 of the surface unevenness of the silicon nitride layer 2 is very sensitive to the dielectric breakdown voltage even though the absolute value is very small as the surface unevenness of around 0.3 nm. Considering this point, the nitride semiconductor substrate W of the present invention is designed with the thickness of the silicon nitride layer 2 and the surface irregularities being kept low.
以上のとおり、本発明に係る窒化物半導体基板の製造方法によれば、シリコン単結晶基板上に、窒化物半導体を堆積させるときに発生する表層凹凸に起因する、窒化物半導体層の絶縁破壊電圧低下を、簡易かつ効果的に抑制することが可能となる。 As described above, according to the method for manufacturing a nitride semiconductor substrate according to the present invention, the dielectric breakdown voltage of the nitride semiconductor layer caused by surface irregularities generated when the nitride semiconductor is deposited on the silicon single crystal substrate. It is possible to suppress the decrease easily and effectively.
以下、本発明の好ましい実施形態を実施例に基づき説明するが、本発明はこの実施例により限定されるものではない。 Hereinafter, preferred embodiments of the present invention will be described based on examples, but the present invention is not limited to these examples.
[実施例1]
CZ法で製造された、面方位(111)、直径4インチ、厚さ625μm、比抵抗25Ωcmの、Nタイプシリコン単結晶基板1を準備し、この一主面に対して、窒化ケイ素層2と中間層3、および活性層4を、MOCVD法により積層して、評価用窒化物半導体基板を作製した。
[Example 1]
An N-type silicon single crystal substrate 1 having a plane orientation (111), a diameter of 4 inches, a thickness of 625 μm, and a specific resistance of 25 Ωcm, prepared by the CZ method, is prepared. The intermediate layer 3 and the active layer 4 were laminated by the MOCVD method to produce a nitride semiconductor substrate for evaluation.
まず、シリコン単結晶基板1を、室温でMOCVD装置にセットし、窒素ガス100%に置換した後、950℃まで30分の時間をかけて、一定の昇温速度にて昇温し、950℃で5分保持した。このときの窒素ガス流量は、6リットル/分とした。 First, the silicon single crystal substrate 1 was set in a MOCVD apparatus at room temperature and replaced with 100% nitrogen gas. Then, the temperature was increased to 950 ° C. over 30 minutes at a constant temperature increase rate, and 950 ° C. Held for 5 minutes. The nitrogen gas flow rate at this time was 6 liters / minute.
引き続き、窒素ガス100%から、窒素ガス50volと%水素ガス50vol%の混合ガス雰囲気に置換したのち、温度はそのままにして5分間保持した。このようにして、窒化ケイ素層2をシリコン単結晶基板1の一主面上に形成した。 Subsequently, after replacing the nitrogen gas 100% with a mixed gas atmosphere of nitrogen gas 50 vol% and hydrogen gas 50 vol%, the temperature was kept as it was for 5 minutes. Thus, the silicon nitride layer 2 was formed on one main surface of the silicon single crystal substrate 1.
次に、窒化ケイ素層2上に、以下の内容で中間層3を形成した。原料としてトリメチルアルミニウム(TMA)、およびアンモニア(NH3)を用い、1000℃での気相成長により、厚さ5nmのAlN単結晶層を積層させた。続けて、トリメチルガリウム(TMG)、TMAおよびNH3を用い、1000℃での気相成長により、厚さ20nmのGaN単結晶層を積層させた。前記AlN単結晶層およびGaN単結晶層を同様の工程にて交互に繰り返し、積層数を50として、多層バッファ領域を形成した。このようにした多層バッファ領域を中間層3とした。 Next, the intermediate layer 3 was formed on the silicon nitride layer 2 with the following contents. Trimethylaluminum (TMA) and ammonia (NH 3 ) were used as raw materials, and an AlN single crystal layer having a thickness of 5 nm was stacked by vapor phase growth at 1000 ° C. Subsequently, a GaN single crystal layer having a thickness of 20 nm was laminated by vapor phase growth at 1000 ° C. using trimethylgallium (TMG), TMA, and NH 3 . The AlN single crystal layer and the GaN single crystal layer were alternately repeated in the same process to form a multilayer buffer region with the number of stacked layers set to 50. The multilayer buffer region thus formed was used as the intermediate layer 3.
中間層3上に、原料としてTMGおよびNH3を用い、1000℃での気相成長により、厚さ2000nmのGaN単結晶層を積層させた。これを活性層4とした。 A GaN single crystal layer having a thickness of 2000 nm was stacked on the intermediate layer 3 by vapor phase growth at 1000 ° C. using TMG and NH 3 as raw materials. This was designated as active layer 4.
以上の工程を経て、実施例1の評価用窒化物半導体基板を作製した。なお、気相成長により形成した各層の厚さは、ガス流量および供給時間の調整により行った。 The nitride semiconductor substrate for evaluation of Example 1 was manufactured through the above steps. Note that the thickness of each layer formed by vapor phase growth was adjusted by adjusting the gas flow rate and the supply time.
実施例1の評価用窒化物半導体基板の中央1点について、窒化ケイ素層2の形成直後に、エリプソメトリを用いて、窒化ケイ素層2の平均厚さT1を測定した。 At one central point of the nitride semiconductor substrate for evaluation of Example 1, immediately after the formation of the silicon nitride layer 2, the average thickness T1 of the silicon nitride layer 2 was measured using ellipsometry.
ここで、窒化ケイ素層2の平均厚さは図2のT1に、窒化ケイ素層2の表層凹凸の最大高低差は図2のT2に、それぞれ相当する。T1とT2の測定、評価方法としては、窒化物半導体基板Wを直径方向に対して劈開し、その断面を原子力間顕微鏡(AFM)で測定する手法を好適に用いることができる。以下に、その評価例を示す。 Here, the average thickness of the silicon nitride layer 2 corresponds to T1 in FIG. 2, and the maximum height difference of the surface irregularities of the silicon nitride layer 2 corresponds to T2 in FIG. As a method for measuring and evaluating T1 and T2, a method of cleaving the nitride semiconductor substrate W in the diameter direction and measuring the cross section with an atomic force microscope (AFM) can be suitably used. The evaluation example is shown below.
窒化物半導体基板Wの、主面の中心点を含む領域から、径方向に測定箇所1mm幅を有した短冊状のサンプルを劈開して切り出す。そして、サンプルの断面をAFMで観察し、シリコン単結晶基板1と中間層3の界面に存在する、窒化ケイ素層2の断面方向の距離を計測する。 A strip-shaped sample having a width of 1 mm in the radial direction is cleaved and cut out from a region including the center point of the main surface of the nitride semiconductor substrate W. Then, the cross section of the sample is observed with an AFM, and the distance in the cross sectional direction of the silicon nitride layer 2 existing at the interface between the silicon single crystal substrate 1 and the intermediate layer 3 is measured.
計測箇所は、測定箇所1mm幅を均等に5分割した箇所とする。このときのAFM観察範囲T3は、径方向に500nmから2000nmをとる。なお、この計測箇所、分割ピッチ、測定範囲は、測定精度やサンプルの状態、評価仕様に応じて、適時変更してよい。 The measurement location is a location where the measurement location 1 mm width is equally divided into five. The AFM observation range T3 at this time ranges from 500 nm to 2000 nm in the radial direction. In addition, you may change this measurement location, a division | segmentation pitch, and a measurement range timely according to a measurement precision, a sample state, and evaluation specification.
AFM観察範囲T3において、シリコン単結晶基板1と薄膜層2の境界にラインL1を引く。そして、窒化ケイ素層2と中間層3の境界近傍において、目視で観察できる範囲で、表層凹凸を平均化したラインL2を引く。このようにして得られたL1とL2の距離T1を、中心部と外周部それぞれの箇所における窒化ケイ素層2の平均厚さとする。 In the AFM observation range T3, a line L1 is drawn at the boundary between the silicon single crystal substrate 1 and the thin film layer 2. Then, in the vicinity of the boundary between the silicon nitride layer 2 and the intermediate layer 3, a line L2 in which surface irregularities are averaged is drawn within a range that can be visually observed. The distance T1 between L1 and L2 obtained in this way is defined as the average thickness of the silicon nitride layer 2 at the central portion and the outer peripheral portion.
あるいは、窒化ケイ素層2の平均厚さT1は、薄膜層2が形成された直後に、MOCVD装置にインラインで膜厚保測定装置、好適にはエリプソメトリで評価してもよい。 Alternatively, the average thickness T1 of the silicon nitride layer 2 may be evaluated by an in-line film thickness measuring device, preferably ellipsometry, in-line with the MOCVD apparatus immediately after the thin film layer 2 is formed.
また、AFM観察範囲T3内において、観察される限度において窒化ケイ素層2の厚さが最大の箇所と、最小の箇所を選択し、L1と平行な仮想ラインL3、L4を、図2に示すように設定する。そして、L3とL4との距離T2のうち、AFM観察範囲T3内において最大の値を、窒化ケイ素層2の表層凹凸の最大高低差とする。 Further, within the AFM observation range T3, a portion where the thickness of the silicon nitride layer 2 is the maximum and a portion where the thickness is minimum is selected within the limit to be observed, and virtual lines L3 and L4 parallel to L1 are shown in FIG. Set to. Then, among the distance T2 between L3 and L4, the maximum value within the AFM observation range T3 is defined as the maximum height difference of the surface irregularities of the silicon nitride layer 2.
なお、サンプルを切り出す箇所は、窒化物半導体基板Wの主面中心点を含む領域以外の、任意の箇所を複数選択してもよい。 A plurality of arbitrary locations other than the region including the center point of the main surface of the nitride semiconductor substrate W may be selected as the location where the sample is cut out.
実施例1の評価用窒化物半導体基板の中央1点から、幅1mm角の切片を切り出し、任意の1辺について、切片の断面部2000nmをAFM観察して、窒化ケイ素層2の表層凹凸の最大高低差T2を測定した。 From the central point of the nitride semiconductor substrate for evaluation of Example 1, a slice with a width of 1 mm square was cut out, and a section of 2000 nm of the slice of an arbitrary side was observed with AFM, and the maximum surface roughness of the silicon nitride layer 2 was observed. The height difference T2 was measured.
評価用窒化物半導体基板の一主表面上に、直径2mmのAu電極箔を、中心点を通る十字線上に対して、中心に1枚、3mmピッチで縦横各2枚、計9枚を蒸着した。評価用窒化物半導体基板の裏面と、各電極箔との間に、市販のプローブ装置と電界印加、測定回路を有する装置を用いて、600Vの電界を印加して、絶縁破壊の有無を確認した。 On one main surface of the nitride semiconductor substrate for evaluation, an Au electrode foil having a diameter of 2 mm was deposited on the cross line passing through the center point, one in the center and two in each length and width at a pitch of 3 mm, for a total of nine. . Between the back surface of the nitride semiconductor substrate for evaluation and each electrode foil, a 600 V electric field was applied using a commercially available probe device and a device having an electric field application and measurement circuit to confirm the presence or absence of dielectric breakdown. .
実施例1は、平均厚さT1が1.5nm、表層凹凸の最大高低差T2が0.2nmであった。すなわち、還元性ガスを含む追加熱処理による、表層凹凸の低減がみられた。また、絶縁破壊不良も、9枚全ての電極で発生していなかった。 In Example 1, the average thickness T1 was 1.5 nm, and the maximum height difference T2 of the surface irregularities was 0.2 nm. That is, the surface unevenness was reduced by the additional heat treatment containing the reducing gas. Further, no breakdown failure occurred in all nine electrodes.
[比較例1]
窒化ケイ素層2を形成せず、その他は実施例1と同様に作製、評価した評価用窒化物半導体基板を比較例1とした。
[Comparative Example 1]
A comparative nitride semiconductor substrate was prepared and evaluated in the same manner as in Example 1 except that the silicon nitride layer 2 was not formed.
比較例1の評価用窒化物半導体基板は、電極9枚のうち、8枚が絶縁破壊不良を示した。このことから、窒化ケイ素層2の効果が顕著に現れていることが確認できた。 As for the nitride semiconductor substrate for evaluation of Comparative Example 1, 8 out of 9 electrodes showed a breakdown failure. From this, it was confirmed that the effect of the silicon nitride layer 2 appeared remarkably.
[比較例2]
第3ステップを省略して、その他は実施例1と同様に作製、評価した評価用窒化物半導体基板を比較例2とした。
[Comparative Example 2]
The nitride semiconductor substrate for evaluation, which was prepared and evaluated in the same manner as in Example 1 except that the third step was omitted, was used as Comparative Example 2.
比較例2の評価用窒化物半導体基板は、5枚の電極で絶縁破壊不良が発生した。また、平均厚さT1が1.8nm、表層凹凸の最大高低差T2が0.3nmであり、表層凹凸が実施例1と比べて大きいものであった。 In the nitride semiconductor substrate for evaluation of Comparative Example 2, a breakdown failure occurred with five electrodes. Further, the average thickness T1 was 1.8 nm, the maximum height difference T2 of the surface layer unevenness was 0.3 nm, and the surface layer unevenness was larger than that of Example 1.
[実施例2〜9、比較例3〜5]表1の内容で製造条件を変更し、その他の製造条件、評価方法は実施例1に準じた。 [Examples 2 to 9, Comparative Examples 3 to 5] The production conditions were changed in accordance with the contents of Table 1, and other production conditions and evaluation methods were the same as in Example 1.
表1より、本発明の実施範囲を外れた場合は、絶縁破壊不良の発生数が9枚中5枚以上、または、窒化ケイ素層2の膜厚均一性の低下、凹凸増大がみられ、本発明の実施範囲に比べて劣るものであった。 From Table 1, when the implementation range of the present invention is outside the range, the number of occurrences of dielectric breakdown failure is 5 or more out of 9, or the film thickness uniformity of the silicon nitride layer 2 is decreased and the unevenness is increased. It was inferior to the scope of the invention.
また、第3ステップの還元性ガスの濃度が、本発明のより好ましい範囲を外れると、絶縁破壊不良の発生数が9枚中2枚となり、本発明の実施範囲外よりは良好であるが、若干見劣りするものであった。 Further, if the concentration of the reducing gas in the third step is outside the more preferable range of the present invention, the number of occurrences of dielectric breakdown defects is 2 out of 9 sheets, which is better than outside the implementation range of the present invention. It was a little inferior.
本発明は、発光ダイオード、レーザ発光素子、高速・高温での動作可能な電子素子等に用いられる窒化物半導体基板として好適である。また、さまざま材料のヘテロエピタキシャル成長における、基板の平坦性を向上させる方法に応用できる。 The present invention is suitable as a nitride semiconductor substrate used for a light emitting diode, a laser light emitting element, an electronic element operable at high speed and high temperature, and the like. Further, it can be applied to a method for improving the flatness of a substrate in heteroepitaxial growth of various materials.
W 窒化物半導体基板
1 シリコン単結晶基板
2 窒化ケイ素層
3 窒化物半導体からなる中間層
4 窒化物半導体からなる活性層
L1 シリコン単結晶基板1と薄膜層2の境界ライン
L2 薄膜層2の凹凸を平均化したライン
L3 薄膜層2の厚さが最大の箇所を仮想したL1と平行な仮想ライン
L4 薄膜層2の厚さが最小の箇所を仮想したL1と平行な仮想ライン
T1 薄膜層2の平均厚さ
T2 薄膜層2の表層凹凸の最大高低差
T3 AFM観察範囲
W nitride semiconductor substrate 1 silicon single crystal substrate 2 silicon nitride layer 3 intermediate layer 4 made of nitride semiconductor active layer L1 made of nitride semiconductor boundary line L2 between silicon single crystal substrate 1 and thin film layer 2 unevenness of thin film layer 2 Averaged line L3 Virtual line L4 parallel to L1 hypothesized at the point where the thickness of the thin film layer 2 is maximum The hypothetical line T1 parallel to L1 hypothesized at the point where the thickness of the thin film layer 2 is minimum Average of the thin film layer 2 Thickness T2 Maximum height difference of surface irregularities of thin film layer 2 T3 AFM observation range
Claims (2)
前記窒化ケイ素層上に窒化物半導体からなる中間層を形成する工程と、
前記中間層上に窒化物半導体からなる活性層を形成する工程と、
を含む窒化物半導体基板の製造方法であって、
前記窒化ケイ素層を形成する工程は、
窒素ガスが90vol%以上100vol%以下で残部は前記窒素ガス以外の不活性ガスからなるガス雰囲気にて室温から900℃以上1000℃以下の到達温度まで昇温する第1ステップと、
前記ガス雰囲気と前記到達温度のままで所定時間保持する第2ステップと、
その後還元性ガス含有雰囲気に切り替えて所定時間保持する第3ステップと、
からなることを特徴とする窒化物半導体基板の製造方法。 Forming a silicon nitride layer on one principal surface of the silicon single crystal substrate;
Forming an intermediate layer made of a nitride semiconductor on the silicon nitride layer;
Forming an active layer made of a nitride semiconductor on the intermediate layer;
A method for producing a nitride semiconductor substrate comprising:
The step of forming the silicon nitride layer includes:
A first step in which the temperature of the nitrogen gas is 90 vol% or more and 100 vol% or less and the balance is raised from room temperature to an ultimate temperature of 900 ° C or more and 1000 ° C or less in a gas atmosphere composed of an inert gas other than the nitrogen gas;
A second step of maintaining the gas atmosphere and the ultimate temperature for a predetermined time;
A third step of switching to a reducing gas-containing atmosphere and holding for a predetermined time;
A method for producing a nitride semiconductor substrate comprising:
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