JP2013033323A - Integrated circuit, image formation device and integrated circuit inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inexpensively and adequately evaluate an integrated circuit such as ASIC, while reducing a man-hour with an element.SOLUTION: As for an engine ASIC 11, when a test mode is set on an operation mode changeover register 39, an S2M image processing module 31 executes an image process with respect to image data input from a scanner 5 based on a line synchronization signal s_lsync_n and a frame effective signal s_fgate_n, and WDMAC 33a-33d store the image data in a buffer control part 38 through an arbiter 35 for write and a read data selector (R_SEL) 40, and RDMAC 34a-34d read the image data of the buffer control part 38 through an arbiter 36 for read and a read data selector (R_SEL) 41 to transmit them to an M2P image processing module 32. The M2P image processing module 32 executes the image process with respect to the image data to output it to a plotter 6.

Description

  The present invention relates to an integrated circuit, an image forming apparatus, and an integrated circuit inspection method, and more specifically, an integrated circuit for image processing such as an ASIC (Application Specific Integrated Circuit) mounted on an engine board of a composite apparatus or the like. The present invention relates to an integrated circuit, an image forming apparatus, and an integrated circuit inspection method that are evaluated by a single board.

  In recent years, an image forming apparatus such as a copying apparatus, a printer apparatus, a composite apparatus, or a scanner apparatus is connected to a scanner that reads an image of a document or a plotter that forms and outputs an image on a paper sheet. An engine board on which an integrated circuit for image processing such as DMA (Direct Memory Access) for transferring data and ASIC (Application Specific Integrated Circuit) for performing necessary image processing is mounted.

  In such an integrated circuit, various inputs are given, the output signal from the integrated circuit is compared with the expected output value, and after verifying that it operates as expected, the actual device is evaluated. ing.

  For example, as shown in FIG. 7, an engine ASIC 100 and an engine CPU (Central Processing Unit) (not shown) are conventionally mounted on an engine board (not shown). The engine ASIC 100 includes a scanner 101 and a plotter 102 as an engine. In addition to being connected, it is connected to the controller board 103. Although not shown, the controller board 103 is equipped with a controller ASIC, CPU, hard disk, memory, etc., and the engine ASIC 100 and the controller ASIC on the controller board 103 separate requests and responses without waiting for a response. It is connected by PCI (Peripheral Component Interconnect) Express (hereinafter referred to as PCIe) that can issue the next request.

  The engine ASIC 100 includes an S2M image processing module 111, an M2P image processing module 112, four WDMAC (write DMAC) 113a to 113d and four RDMAC (read DMAC) 114a to 114d, a write arbiter 115, A read arbiter 116, an EP (end point) 117, a PCIe transfer buffer unit 118, and the like are provided. S2M is an abbreviation for Scanner to Memory, and M2P is an abbreviation for Memory to Plotter. The same applies hereinafter.

  The engine ASIC 100 receives the line synchronization signal s_lsync_n, the frame valid signal s_fgate_n, and the image data for four channels (4ch) from the scanner 101 to the S2M image processing module 111, and the line from the plotter 102 to the M2P image processing module 112. The synchronization signal p_lsync_n and the frame valid signal p_fgate_n are input, and image data for 4ch is input from the RDMACs 114a to 114d.

  The S2M image processing module 111 performs image processing for one line and one page of image data input from the scanner 101 in synchronization with the line synchronization signal s_lsync_n and the frame valid signal s_fgate_n, and the M2P image processing module 112 Image processing for one line unit and one page is performed in synchronization with the line synchronization signal p_lsync_n and the frame valid signal p_fgate_n input from the plotter.

  The WDMACs 113a to 113d transfer the image data input from the S2M image processing module 111 to the controller 103 connected via PCIe and write the data to the memory of the controller 103. The write arbiter 115 includes the WDMAC 113a for 4ch. Arbitrate the write request input from .about.113d.

  The RDMACs 114a to 114d read the image data stored in the memory of the controller 103 connected via PCIe and output the image data to the M2P image processing module 112.

  The read arbiter 116 arbitrates read requests input from the RDMACs 114a to 114d for 4 channels.

  The EP 117 controls data transfer between the engine ASIC 100 and the controller 103 in accordance with the PCIe standard, and temporarily writes image data to be written and read to the PCIe transfer buffer unit 118 in order to control the flow at the time of this data transfer. To save.

  In such an engine ASIC 100, conventionally, image data is input from the scanner 101 side to the engine ASIC 100 to evaluate whether the operation is normally performed (see Patent Document 1). .

  However, in the above prior art, in the evaluation of the engine ASIC, particularly in the evaluation of the S2M bus and the M2P bus that are image buses in the engine ASIC, the memory of the controller that is the transfer destination of the write data using the S2M path Because the memory that is the source of the read data using the M2P path is used, it is not possible to evaluate the engine board alone with the engine ASIC installed, and it is necessary to prepare a controller board for evaluation. The use of the controller board has a problem that the cost is increased, the evaluation space is increased, and a lot of man-hours for evaluating the controller board are required.

  In this case, for example, if a page memory is mounted on the engine board or in the engine ASIC in order to perform the evaluation on the engine board alone, the circuit scale increases and the cost of the engine board increases. In addition, since the S2M path and the M2P path operate asynchronously, simply mounting a memory results in an abnormal image if there is a mismatch between the write speed from the S2M path and the read speed from the M2P path. Evaluation cannot be performed.

  Accordingly, an object of the present invention is to perform evaluation of an integrated circuit, in particular, evaluation of an image bus at a low cost and appropriately while reducing the number of steps.

  In order to achieve the above object, an integrated circuit according to the present invention includes: input data image processing means for performing predetermined image processing on input image data based on an input line synchronization signal and an input frame valid signal; Data storage means for temporarily storing the image data in order to adjust timing when the image data processed by the input data image processing means is transferred to the external storage means; and image data processed by the input data image processing means Is transferred to the external storage means via the data storage means, data capture means for capturing the image data of the external storage means via the data storage means, and capture of the data capture means The image data is subjected to predetermined image processing based on the output line synchronization signal and the output frame valid signal. Output data image processing means for inputting, and a mode signal for designating the operation mode of the normal mode and the inspection mode, and when the mode signal is in the normal mode, the output destination of the image data by the data transfer output means is When the mode signal is set to the external storage means and the mode signal is the inspection mode, the output destination switching means for setting the output destination of the image data by the data transfer output means to the data storage means, and the mode signal are input, When the mode signal is a normal mode, the image data capturing unit by the data capturing unit is set in the external storage unit, and when the mode signal is an inspection mode, the image data capturing unit by the data capturing unit is set. Input destination switching means for setting the destination in the data storage means, and the mode signal is inputted, and the mode signal is inspected The input line synchronization signal is input to the output data image processing means instead of the output line synchronization signal, and the input frame valid signal is delayed by a predetermined delay amount instead of the output frame valid signal. And a signal switching means for inputting the delayed input frame valid signal to the output data image processing means.

  In order to achieve the above object, the image forming apparatus of the present invention includes an image reading unit that reads an image of a document and outputs image data based on an input line synchronization signal and an input frame valid signal, and an output line synchronization signal. And an image output means for recording and outputting an image corresponding to the image data, an external storage means for storing the image data, and image data output from the image reading means based on the output frame valid signal. And an integrated circuit that stores the image data in the external storage means, performs predetermined image processing and outputs the image data to the image output means, and the integrated circuit includes the image reading means An image input from the image reading means based on the input line synchronization signal and the input frame valid signal input from Input data image processing means for performing predetermined image processing on the data, and temporarily transferring the image data for timing adjustment when transferring the image data processed by the input data image processing means to the external storage means Data storage means for storing, data transfer output means for transferring and outputting image data processed by the input data image processing means to the external storage means via the data storage means, and the image data of the external storage means Data fetching means fetched via the data storage means, and predetermined data based on the output line synchronization signal and the output frame valid signal inputted from the image output means for the image data fetched by the data fetching means Output data image processing means for performing image processing and outputting to the image output means, normal mode and inspection When a mode signal designating an operation mode of the mode is input and the mode signal is in the normal mode, the output destination of the image data by the data transfer output unit is set in the external storage unit, and the mode signal is inspected. When in the mode, the output destination switching means for setting the output destination of the image data by the data transfer output means in the data storage means, the mode signal is input, and when the mode signal is in the normal mode, the data Input destination switching for setting the image data acquisition destination by the acquisition means in the external storage means, and setting the image data acquisition destination by the data acquisition means in the data storage means when the mode signal is in the inspection mode. And when the mode signal is input and the mode signal is in the inspection mode, the input line is replaced with the input line synchronization signal. A power line synchronization signal is input to the output data image processing means, and a delayed input frame valid signal obtained by delaying the input frame valid signal by a predetermined delay amount instead of the output frame valid signal is supplied to the output data image processing means. And an input signal switching means.

  Furthermore, in order to achieve the above object, the integrated circuit inspection method of the present invention performs input data image processing for performing predetermined image processing on input image data based on an input line synchronization signal and an input frame valid signal. A data storage processing step for temporarily storing the image data in the data storage means for performing timing adjustment when transferring the image data processed in the input data image processing step to the external storage means; and the input data Data transfer output processing step for transferring and outputting the image data processed in the image processing step to the external storage means via the data storage means, and data for capturing the image data of the external storage means via the data storage means A capture process step and image data captured in the data capture process step; The output data image processing step for performing the predetermined image processing based on the output line synchronization signal and the output frame valid signal, and the mode signal designating the operation mode of the normal mode and the inspection mode are the normal mode, When the output destination of the image data in the data transfer output processing step is set in the external storage means, and the mode signal is in the inspection mode, the output destination of the image data in the data transfer output processing step is the data storage If the output signal switching processing step set in the means and the mode signal is in the normal mode, the capture destination of the image data in the data capture processing step is set in the external storage means, and the mode signal is in the inspection mode. And the data storage means for setting the image data acquisition destination in the data acquisition processing step. When the input signal switching processing step and the mode signal are in the inspection mode, the input line synchronization signal is input to the output data image processing step instead of the output line synchronization signal, and the output frame valid signal is replaced. And a signal switching processing step of inputting a delayed input frame valid signal obtained by delaying the input frame valid signal by a predetermined delay amount to the output data image processing step.

  According to the present invention, the evaluation of the engine ASIC, in particular, the evaluation of the image bus can be performed inexpensively and appropriately while reducing the number of steps.

1 is a block diagram of a main part of an image forming apparatus to which an embodiment of the present invention is applied. The block block diagram of engine ASIC. The block block diagram of a buffer control part. The sequence diagram at the time of test mode. The timing diagram of 0ch in the test mode of a buffer control part. The block block diagram of engine ASIC into which a mode signal is input from the outside. The block diagram of the conventional engine ASIC.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 6 are diagrams illustrating an embodiment of an integrated circuit, an image forming apparatus, and an integrated circuit inspection method according to the present invention. FIG. 1 illustrates an integrated circuit, an image forming apparatus, and an integrated circuit inspection method according to the present invention. 1 is a block configuration diagram of an image forming apparatus 1 to which an embodiment is applied.

  In FIG. 1, the image forming apparatus 1 includes an engine board 2, a controller board 3, an operation display unit (not shown), and the like. The engine board 2 and the controller board 3 are connected by a PCIe bus 4.

  The engine board 2 includes an engine ASIC 11 and an engine CPU 12. The engine ASIC 11 is connected to a scanner 5 and a plotter 6.

  A scanner (image reading means) 5 uses a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) as a photoelectric conversion element, and scans a document transported in a sub-scanning direction by a document transport mechanism (not shown) in the main scanning direction. , The photoelectric conversion element photoelectrically converts the reflected light of the reading light applied to the original, reads the original image line by line, and performs A (analog) / D (digital) conversion. Output to engine ASIC11.

  The plotter (image output means) 6 is, for example, an electrophotographic recording apparatus or the like, which records and outputs a document image read by a scanner, a received image received by a network communication unit (not shown), and the like on a sheet. Record the report on paper.

  The controller board 3 includes a controller ASIC 21, a hard disk (HDD) 22, a north bridge (NB) 23, a controller CPU 24, a memory (external storage means) 25, and the like. The controller ASIC 21 and the north bridge (NB) 23 are Connected by a PCIe bus.

  The north bridge (NB) 23 is a bridge for connecting the controller CPU 24, the memory 25, the controller ASIC 21, and the like. The memory 25 is a memory for temporarily storing image data read by the scanner 5 of the image reading apparatus 1. Used.

  The controller CPU 24 controls each part of the image reading device 1 based on a program stored in a hard disk (HDD) 22 or the like, and controls basic operation processing as the image reading device 1.

  A hard disk (HDD) 22 is used for storing programs and image data, and data and the like are written and read by the controller ASIC 21 under the control of the controller CPU 24.

  The controller ASIC 21 performs various image processing such as data compression / decompression under the control of the CPU 23.

  As shown in FIG. 2, the engine ASIC (integrated circuit) 11 includes an S2M image processing module 31, an M2P image processing module 32, a WDMAC (Write Direct Memory Access Controller) 33 a to 33 d, and an RDMAC. (Write Direct Memory Access Controller) 34a to 34d, write arbiter 35, read arbiter 36, end point (EP) 37, buffer control unit 38, operation mode switching register 39, write A data selector (W_SEL) 40, a read data selector (R_SEL) 41, a plotter LSYNC selector (P_LS_SEL) 42, a frame valid signal delay amount setting register 43, a P_FGATE generator 44, a plotter FGATE selector (P_FG_SEL) 45, and the like are provided.

  The engine ASIC 11 transfers the image data to the controller ASIC 21 of the controller board 3 at a time-out interval that is a predetermined writing interval set by the engine CPU 12, and outputs image data output from the scanner 11 based on the parameters set by the engine CPU 12. Necessary image processing is performed on the image. Further, the engine ASIC 11 performs image processing necessary for image formation by the plotter 6 on the image data acquired from the controller board 3 and transfers the image data to the plotter 6.

  The S2M image processing module (input data image processing means) 31 receives line synchronization signal (input line synchronization signal) s_lsync_n, frame valid signal (input frame valid signal) s_fgate_n, and image data for 4 channels (4ch) from the scanner 5. The input S2M image processing module 31 performs image processing for one line and one page of image data input from the scanner 5 in synchronization with the line synchronization signal s_lsync_n and the frame valid signal s_fgate_n.

  The M2P image processing module (output data image processing means) 32 receives a line synchronization signal (output line synchronization signal) p_lsync_n and a frame valid signal (output frame valid signal) p_fgate_n from the plotter 6, and 4ch from the RDMACs 34a to 34d. The M2P image processing module 32 synchronizes with the line synchronization signal p_lsync_n and the frame valid signal p_fgate_n, and the M2P image processing module 32 performs one line unit and one page for the 4ch image data transferred from the RDMACs 34a to 34d. Perform image processing.

  WDMAC (data transfer output means) 33a to 33d send the image data input from the S2M image processing module 111 to the write arbiter 35, the write data selector (W_SEL) 40, and the end point (EP) 37. The data is transferred from the (EP) 37 to the controller 3 connected via the PCIe 4 and written into the memory 25 or the buffer control unit 38 of the controller 3.

  The write arbiter (capture request arbitration means) 35 arbitrates write requests input from the WDMACs 33a to 33d for 4ch.

  The RDMAC (data fetching means) 34 a to 34 d are image data stored in the memory 25 of the controller 3 or images stored in the buffer control unit 38 via the read data selector (R_SEL) 41 and the read arbiter 36. Data is read and output to the M2P image processing module 32.

  The read arbiter (fetch request arbitration means) 36 arbitrates read requests input from the RDMACs 34a to 34d for 4ch.

  The EP 37 controls data transfer between the engine ASIC 11 and the controller 3 in accordance with the PCIe standard, and temporarily writes image data to be written and read to a PCIe transfer buffer in order to control the flow at the time of this data transfer. The data is stored in the control unit 38.

  The operation mode switching register (mode setting means) 39 sets the operation mode of the normal mode and the test mode by the engine CPU 12, and the mode signal mode (mode = 0 in the normal mode, test 0) according to the set operation mode. In the mode, mode = 1) is output to the write data selector (W_SEL) 40, the read data selector (R_SEL) 41, the plotter LSYNC selector (P_LS_SEL) 42, and the plotter FGATE selector (P_FG_SEL) 45. That is, the engine ASIC 11 has a normal mode in which the engine ASIC 11 operates normally and a test mode in which the engine ASIC 11 is inspected, in particular, an inspection of the image data transfer bus. 39.

  The buffer control unit (data storage means) 38 functions as a PCIe transfer buffer in the normal mode (mode = 0), and stores the image data in the test mode in the test mode (mode = 1). The memory functions as a write destination memory of the S2M path or a read destination memory of the M2P path. Details will be described later.

  The write data selector (W_SEL) (output destination switching means) 40 receives a write request (from the WDMACs 33a to 33d via the write arbiter 35 in accordance with the mode signal mode input from the operation mode switching register 39 ( The transfer destination of the image data by the (write request) is switched between the end point (EP) 37 and the buffer control unit 38. That is, when the mode signal mode is mode = 0 and the normal mode is selected, the write data selector (W_SEL) 40 sets the transfer destination, which is the image data write request destination, to the endpoint (EP) 37 and the mode signal mode is mode = 1. In the test mode, the transfer destination of the image data is the buffer control unit 38.

  A read data selector (R_SEL) (input destination switching means) 41 reads a read request (read request) from the read arbiter 36 and an image data destination (image) according to the mode signal mode input from the operation mode switching register 39. The data reading source) is switched to the end point (EP) 37 and the buffer control unit 38, and the image data returned in response to the read request is output to the read arbiter 36. That is, when the mode signal mode is mode = 0 and the normal mode is selected, the read data selector (R_SEL) 41 sends the read access to the endpoint (EP) 37 and reads the image data returned from the endpoint (EP) 37. When the mode signal mode is mode = 1 and the test mode is selected, the read access is sent to the buffer control unit 38 and the image data returned from the buffer control unit 38 is output to the read arbiter 36.

  The plotter LSYNC selector (P_LS_SEL) 42 switches between the line synchronization signal s_lsync_n input from the scanner 5 and the line synchronization signal p_lsync_n input from the plotter 6 according to the mode signal mode, and outputs it to the M2P image processing module 32. That is, when the mode signal mode is mode = 0 and the normal mode is selected, the plotter LSYNC selector (P_LS_SEL) 42 outputs the line synchronization signal p_lsync_n from the plotter 6 to the M2P image processing module 32, and the mode signal mode is mode = 1. In the test mode, the line synchronization signal s_lsync_n from the scanner 5 is output to the M2P image processing module 32.

  The frame valid signal delay setting register (delay amount setting means) 43 determines how many lines the test mode frame synchronization signal p_fgate_test_n generated by the P_FGATE generation unit 44 described later is delayed from the assertion of the frame valid signal s_fgate_n from the scanner 5. The frame effective signal delay amount fg_dly to be set is output to the P_FGATE generator 44.

  The frame valid signal delay amount fg_dly from the frame valid signal delay setting register 43 and the frame valid signal s_fgate_n from the scanner 5 are input to the P_FGATE generator 44, and the P_FGATE generator 44 receives the frame valid signal s_fgate_n from the scanner 5. Is delayed by the value of the frame valid signal delay amount fg_dly set by the frame valid signal delay setting register 43, and the plotter FGATE selector (P_FG_SEL) 45 is used as the delayed frame valid signal p_fgate_test_n used by the M2P image processing module 32 in the test mode. Output to.

  The plotter FGATE selector (P_FG_SEL) 45 switches the delayed frame valid signal p_fgate_test_n from the P_FGATE generation unit 44 and the frame valid signal p_fgate_n from the plotter 6 according to the mode signal mode, and outputs them to the M2P image processing module 32. That is, when the mode signal mode is mode = 0 and the normal mode is selected, the plotter FGATE selector (P_FG_SEL) 45 outputs the frame valid signal p_fgate_n input from the plotter 6 to the M2P image processing module 32, and the mode signal mode is mode = When the test mode is 1, the delayed frame valid signal p_fgate_test_n from the P_FGATE generator 44 is output to the M2P image processing module 32. The plotter LSYNC selector (P_LS_SEL) 42, the frame valid signal delay setting register 43, and the plotter FGATE selector (P_FG_SEL) 45 function as signal switching means as a whole.

  As shown in FIG. 3, the buffer control unit 38 reads the write data decoders (W_SEL *, * = 0 to 3) 52a to 52d for the write address decoder 51 and 4ch, and the read data for the buffers 53 and 4ch. Selectors (R_SEL *, * = 0 to 3) 54a to 54d, a read address recorder 55, a select signal generation unit 56, and the like, and a buffer 53 includes FIFO0_a, FIFO0_b, FIFO1_a, 4ch for each channel pair. FIFO1_b, FIFO2_a, FIFO2_b, FIFO3_a, and FIFO3_b are provided.

  A buffer (line buffer) 53 operates a pair of 4 channel FIFO * _a and FIFO * _b (* = 0 to 3) of each channel as a PCIe transfer buffer in the normal mode (mode = 0). After the data from (EP) 37 is temporarily stored, it is sent to the end point (EP) 37.

  In the test mode (mode = 1), the buffer 53 is operated as a memory of a write destination of the S2M path or a read destination of the M2P path, and the lines FIFO * _a and FIFO * _b (* = 0 to 3) for 2 lines × 4 channels. ) With toggle.

  The line synchronization signal s_lsync_n is input from the scanner 5 to the select signal generator 56, and the select signal generator 56 controls the toggle operation of the line FIFO * _a and FIFO * _b (* = 0 to 3) of the buffer 53. The select signal sel is inverted and output every time the line synchronization signal s_lsync_n is input.

  Image data and a write address are input from a write data selector (W_SEL) 40 to a write address decoder (write address decoding means) 51. The address decoder 51 receives a write request from any channel (ch) in the S2M path. It is determined whether there is a line FIFO * _a, FIFO * _b (* = 0 to 3) of the corresponding channel of the buffer 53 via the write data selector (W_SEL *, * = 0 to 3) 52a to 52d. Write image data wd * (* = 0 to 3).

  The read address decoder (capture address decoding means) 55 determines the read request from which channel (ch) of the M2P path based on the read address from the read data selector (R_SEL) 41, and the read data selector (R_SEL *, * = 0 to 3) Read image data rd * (* = 0 to 3) from line FIFO * _a and FIFO * _b (* = 0 to 3) of the corresponding channel via 54a to 54d. The data is transferred to the read data selector (R_SEL) 41.

  The write data selectors (W_SEL *, * = 0 to 3) 52a to 52d, based on the select signal sel from the select signal generation unit 56, image data wd from the address decoder 51, which is image data written from the S2M path. * Switch (* = 0 to 3) to image data wd * _a and image data wd * _b (* = 0 to 3) and switch to FIFO * _a and FIFO * _b (* = 0 to 3) Write.

  The read data selectors (R_SEL *, * = 0 to 3) 54a to 54d are read destination buffers based on the select signal sel from the select signal generation unit 56 by the address decoder 55 that is the read destination of the image data from the M2P path. Are switched to FIFO * _a and FIFO * _b (* = 0 to 3), and the read image data rd * _a and image data rd * _b (* = 0 to 3) are changed to rd * (* = 0 to 3). ) To the read data selector (R_SEL) 41.

  Next, the operation of this embodiment will be described. The image forming apparatus 1 according to the present exemplary embodiment performs the evaluation of the engine ASIC 11, particularly the evaluation of the image bus, at a low cost and appropriately while reducing the number of steps.

  In the image forming apparatus 1, in the normal mode, the engine CPU 12 sets the normal mode in the operation mode switching register 39, and when the normal mode is set, the operation mode switching register 39 sets the mode signal mode ( mode = 0) is output to the write data selector (W_SEL) 40, the read data selector (R_SEL) 41, the plotter LSYNC selector (P_LS_SEL) 42, and the plotter FGATE selector (P_FG_SEL) 45.

  In this normal mode, the engine ASIC 11 uses the 4ch image data input from the scanner 5 for each line and page by the S2M image processing module 31 in synchronization with the line synchronization signal s_lsync_n and the frame valid signal s_fgate_n. The image data is output to the WDMACs 33a to 33d. The WDMACs 33a to 33d convert the image data input from the S2M image processing module 111 into the write arbiter 35, the write data selector (W_SEL) 40, and the end point (EP) 37. And transferred from the end point (EP) 37 to the controller 3 via the PCIe 4 and written in the memory 25 of the controller 3.

  Then, the engine ASIC 11 operates the FIFO * _a and FIFO * _b (* = 0 to 3) for 4 channels of the buffer control unit 38 as a PCIe transfer buffer when transferring the image data to the controller 3 via the PCIe 4. The image data from the end point (EP) 37 is temporarily stored and then sent to the end point (EP) 37.

  In the engine ASIC 11, the RDMACs 34 a to 34 d read the image data stored in the memory 25 of the controller 3 via the read data selector (R_SEL) 41 and the read arbiter 36, and output them to the M2P image processing module 32. At this time, when transferring the image data to the M2P image processing module 32 via the PCIe 4, the engine ASIC 11 transfers the FIFO * _a and FIFO * _b (* = 0 to 3) for 4ch of the buffer control unit 38 to the PCIe transfer. The image data from the end point (EP) 37 is temporarily stored and then sent to the end point (EP) 37. The end point (EP) 37 receives the read data selector (R_SEL) 41 and the read arbiter. 36 to the RDMACs 34a to 34d. In the engine ASIC 11, the M2P image processing module 32 performs necessary image processing on the image data received from the RDMACs 34a to 34d, and sends the image data to the plotter 6. The plotter 6 forms an image on a sheet based on the image data.

  On the other hand, in the test mode, the image forming apparatus 1 sends appropriate data from the scanner 5 to the engine ASIC 11 to perform a test (inspection) of the engine ASIC 11, particularly, a bus test. At this time, as shown in FIG. 4, the engine CPU 12 sets a test mode in the operation mode switching register 39 of the engine ASIC 11, and sets the control parameters of the S2M image processing module 31 and the M2P image processing module 32 to the engine ASIC 11. When the test mode is set, the operation mode switching register 39 sets the mode signal mode (mode = 1) of “1” to the write data selector (W_SEL) 40, the read data selector (R_SEL) 41, and the plotter LSYNC. The data is output to the selector (P_LS_SEL) 42 and the plotter FGATE selector (P_FG_SEL) 45.

  Next, the engine CPU 11 activates the WDMACs 33a to 33d and the RDMACs 34a to 34d.

  In this test mode, the engine ASIC 11 uses the 4ch image data input from the scanner 5 for one line in synchronization with the line synchronization signal s_lsync_n and the frame valid signal s_fgate_n by the S2M image processing module 31 as in the normal mode. The image processing is performed for each minute and one page and output to the WDMACs 33a to 33d. The WDMACs 33a to 33d receive the image data input from the S2M image processing module 31 via the write arbiter 35 and the write data selector (W_SEL). Send to 40. At this time, the write data selector (W_SEL) 40 determines the transfer destination of the image data sent from the WDMACs 33 a to 33 d via the write arbiter 35 in accordance with the mode signal mode input from the operation mode switching register 39. Then, switching from the end point (EP) 37 to the buffer control unit 38, the buffer control unit 38 operates the buffer 53 as a write destination memory of the S2M path, and the line FIFO * _a, FIFO * _b for 2 lines × 4ch. (* = 0-3) is operated by toggle.

  Then, as shown in FIG. 4, when the frame valid signal s_fgate_n from the scanner 5 is asserted and the input of image data is started, the engine ASIC 11 performs image processing necessary for the image data as described above. Is processed by the S2M image processing module 31 and stored in the buffer control unit 38. The frame valid signal s_fgate_n is delayed by the value of the frame valid signal delay amount fg_dly set in the frame valid signal delay setting register 43, and the test is performed. The delayed frame valid signal p_fgate_test_n used by the M2P image processing module 32 in the mode is output to the plotter FGATE selector (P_FG_SEL) 45.

  The plotter FGATE selector (P_FG_SEL) 45 outputs the delayed frame valid signal p_fgate_test_n from the P_FGATE generation unit 44 to the M2P image processing module 32 when the mode signal mode is mode = 1 and the test mode is set.

  Next, in the engine ASIC 11, the RDMACs 34a to 34d send a read request to the read data selector (R_SEL) 41 via the read arbiter 36. When the read data selector (R_SEL) 41 is in the test mode, the buffer access is controlled. The image data sent to the unit 38 and returned from the buffer control unit 38 is sent to the RDMACs 34 a to 34 d via the read arbiter 36.

  The engine ASIC 11 sends the image data read by the RDMACs 34a to 34d to the M2P image processing module 32, and the M2P image processing module 32 receives the frame valid signal p_fgate_n from the plotter 6 and the delayed frame valid from the plotter FGATE selector (P_FG_SEL). Necessary image processing is performed on the image data based on the signal p_fgate_test_n, and the image data is sent to the plotter 6 to form an image on a sheet. As described above, the output start timing of the image data to the plotter 6 is a timing delayed from the assertion of the frame valid signal s_fgate_n by the number of lines of the frame valid signal delay amount fg_dly set in the frame valid signal delay setting register 43. is there.

  Then, the buffer control unit 38 of the engine ASIC 11 shows the timing diagram of 0ch, as shown in FIG. 5, the select signal generation unit 56 performs the line FIFO * _a and FIFO * _b () of the buffer 53 in the cycle of the line synchronization signal s_lsync_n. * = 0 to 3) The select signal sel for controlling the toggle operation is inverted, and the S2M image processing module is applied to the line FIFO * _a and FIFO * _b (* = 0 to 3) selected by the select signal sel. The image data (wd0_a / wd0_b) sent from 31 through the S2M path is written.

  The buffer control unit 56 is deasserted at a timing delayed by the number of lines of the frame valid signal delay amount fg_dly set in the frame valid signal delay setting register 43 from the assertion of the frame valid signal s_fgate_n. The image data of FIFO * _a and FIFO * _b (* = 0 to 3) is read as image data (rd0_a / rd0_b) to the M2P image processing module 32.

  The WDMACs 33a to 33d and the RDMACs 34a to 34d perform the same control as in the normal mode in the test mode, and operate as if the memory 25 of the controller board 3 is being accessed.

  In the test mode, the image data input from the scanner 5 is subjected to image processing equivalent to the image processing performed by the engine ASIC 11 using software or the like, and an expected value is created and output to the plotter 6. The engine ASIC 11 checks and confirms whether or not the desired image processing has been realized by comparing the expected image data with the expected value.

  In the above description, the engine ASIC 11 includes the operation mode switching register 39 that sets the operation mode of the normal mode and the test mode by the engine CPU 12 and outputs the mode signal mode corresponding to the operation mode. The mode signal mode is not limited to the one output by the operation mode switching register 39. For example, as shown in FIG. 6, the mode signal mode is input from the outside without mounting the operation mode switching register 39. Also good. In this case, the engine ASIC 11a includes an external terminal for inputting the mode signal mode.

  As described above, in the image forming apparatus 1 according to the present embodiment, the engine ASIC 11 mounted on the engine board 2 receives the line synchronization signal (input line synchronization signal) s_lsync_n and the frame valid signal ( An S2M image processing module (input data image processing means) 31 that performs predetermined image processing based on the input frame valid signal) s_fgate_n, and image data processed by the S2M image processing module 31 is stored in the memory (external storage means) of the controller board 3 ) A buffer control unit (data storage means) 38 that temporarily stores the image data to adjust timing when transferring to 25, and the image data processed by the S2M image processing module 31 via the buffer control unit 38 WDMAC (data transfer output means) 33a to 33d for transfer and output to the memory 25; RDMAC (data fetching means) 34a to 34d for fetching the image data of 25 via the buffer control unit 38, and line sync signal (output line sync signal) p_lsync_n and frame valid for the image data fetched by RDMAC 34a to 34d M2P image processing module (output data image processing means) 32 that performs predetermined image processing on the basis of the signal (output frame valid signal) p_fgate_n, and a mode that designates the operation mode of the normal mode and the test mode (inspection mode) When the signal mode is input and the mode signal is the normal mode, the output destination of the image data by the WDMACs 33a to 33d is set in the memory 25. When the mode signal is the test mode, the image data of the WDMACs 33a to 33d is output. Write data that sets the output destination to the buffer control unit 38 When the selector (W_SEL) (output destination switching means) 40 and the mode signal mode are input and the mode signal mode is the normal mode, the image data capturing destinations by the RDMACs 34a to 34d are set in the memory 25, and the mode signal mode Is a test mode, a read data selector (R_SEL) (input destination switching means) 41 for setting the image data capture destination by the RDMACs 34a to 34d in the buffer control unit 38, a mode signal mode, and a mode signal mode are input. In the test mode, the line synchronization signal s_lsync_n output from the scanner 5 is input to the M2P image processing module 32 instead of the line synchronization signal p_lsync_n, and the frame effective signal s_fgate_n is replaced by the frame effective signal delay amount instead of the frame effective signal p_fgate_n. (Predetermined delay amount) Frame valid signal delayed by fg_dly (delay A plotter FGATE selector (P_FG_SEL) (signal switching means) 45 for inputting an input frame valid signal) P_fgate_test_n to M2P image processing module 32, a.

  Therefore, when a test page memory is not provided in the engine board 2 or the engine ASIC 11, or when a test controller board is prepared and not connected to the engine board 2, the image data is written to and read from the memory. The test can be executed while preventing the occurrence of an abnormal image due to the inconsistency, and the evaluation of the engine ASIC 11, particularly the evaluation of the image bus, can be performed inexpensively and appropriately while reducing the man-hours.

  In addition, the image forming apparatus 1 according to the present embodiment reads a document image and outputs image data based on a line synchronization signal (input line synchronization signal) s_lsync_n and a frame valid signal (input frame valid signal) s_fgate_n ( An image reading means) 5, a plotter (image output means) 6 for recording and outputting an image according to the image data based on the line synchronization signal (output line synchronization signal) p_lsync_n and the frame valid signal (output frame valid signal) p_fgate_n; The image data stored in the memory (external storage means) 25 and the image data output from the scanner 5 are subjected to predetermined image processing and stored in the memory 25, and the image data in the memory 25 is taken in to perform predetermined image processing. And an engine ASIC (integrated circuit) that outputs the result to the plotter 6. The S2M image processing module 31 that performs predetermined image processing on the image data input from the scanner 5 based on the line synchronization signal s_lsync_n and the frame valid signal s_fgate_n input from the S5 and the S2M image processing module 31 In order to adjust the timing when transferring the image data to the memory 25 of the controller board 3, the buffer control unit 38 temporarily stores the image data, and the image data processed by the S2M image processing module 31 is buffer control unit 38. The line synchronization signals p_lsync_n and the WDMACs 33a to 33d that are transferred to the memory 25 via the RD, the RDMACs 34a to 34d that capture the image data of the memory 25 via the buffer control unit 38, and the image data captured by the RDMACs 34a to 34d Based on frame valid signal p_fgate_n The M2P image processing module 32 that performs predetermined image processing and outputs, and the mode signal mode that specifies the operation mode of the normal mode and the test mode are input, and when the mode signal is the normal mode, the images by the WDMACs 33a to 33d When the data output destination is set in the memory 25 and the mode signal is in the test mode, the write data selector (W_SEL) 40 for setting the output destination of the image data by the WDMACs 33a to 33d in the buffer control unit 38, and the mode signal When mode is input and the mode signal mode is the normal mode, the image data capturing destination by the RDMACs 34a to 34d is set in the memory 25, and when the mode signal mode is the test mode, the image data capturing by the RDMACs 34a to 34d is performed. Read data selector for setting the destination in the buffer control unit 38 ( R_SEL) 41 and the mode signal mode are input, and when the mode signal mode is the test mode, the line synchronization signal s_lsync_n output from the scanner 5 is input to the M2P image processing module 32 instead of the line synchronization signal p_lsync_n, and the frame A plotter FGATE selector (P_FG_SEL) 45 for inputting a frame valid signal p_fgate_test_n obtained by delaying the frame valid signal s_fgate_n by a frame valid signal delay amount fg_dly to the M2P image processing module 32 instead of the valid signal p_fgate_n.

  Therefore, when a test page memory is not provided in the engine board 2 or the engine ASIC 11, or when a test controller board is prepared and not connected to the engine board 2, the image data is written to and read from the memory. The test can be executed while preventing the occurrence of an abnormal image due to the inconsistency, and the evaluation of the engine ASIC 11, particularly the evaluation of the image bus, can be performed inexpensively and appropriately while reducing the man-hours.

  Further, the image forming apparatus 1 according to the present embodiment performs predetermined image processing on input image data based on a line synchronization signal (input line synchronization signal) s_lsync_n and a frame valid signal (input frame valid signal) s_fgate_n. An input data image processing step to be performed; and a data storage processing step for temporarily storing the image data in the buffer control unit 38 in order to adjust timing when the image data processed in the input data image processing step is transferred to the memory 25; A data transfer output processing step for transferring and outputting the image data processed in the input data image processing step to the memory 25 via the buffer control unit 38; and a data fetching process for capturing the image data in the memory 25 via the buffer control unit 38 Step and the image data captured in the data capture processing step Specify the output data image processing step to be output after applying the predetermined image processing based on the line synchronization signal (output line synchronization signal) p_lsync_n and the frame valid signal (output frame valid signal) p_fgate_n, and specify the operation mode of normal mode and test mode When the mode signal mode to be performed is the normal mode, the output destination of the image data at the data transfer output processing step is set in the memory 25, and when the mode signal mode is the test mode, the image data output at the data transfer output processing step is If the output destination switching processing step for setting the output destination in the buffer control unit 38 and the mode signal mode is the normal mode, the image data capturing destination in the data capturing processing step is set in the memory 25, and the mode signal mode is the test mode. If this is the case, the image data capture destination in the data capture processing step is backed up. If the input destination switching processing step set in the key control unit 38 and the mode signal mode is the test mode, the line synchronization signal s_lsync_n is input to the output data image processing step instead of the line synchronization signal p_lsync_n, and the frame valid signal p_fgate_n Instead of the frame valid signal (input frame valid signal) s_fgate_n by the frame valid signal delay amount fg_dly, the frame valid signal p_fgate_test_n is input to the output data image processing step, and the integrated circuit inspection method is provided. Running.

  Therefore, when a test page memory is not provided in the engine board 2 or the engine ASIC 11, or when a test controller board is prepared and not connected to the engine board 2, the image data is written to and read from the memory. The test can be executed while preventing the occurrence of an abnormal image due to the inconsistency, and the evaluation of the engine ASIC 11, particularly the evaluation of the image bus, can be performed inexpensively and appropriately while reducing the man-hours.

  Further, in the image forming apparatus 1 of the present embodiment, the engine ASIC 11 that is an integrated circuit has an S2M image processing module (input data image processing means) 31 for a plurality of channels (4ch in the embodiment), a WDMAC (data transfer output means). ) 33a to 33d, RDMAC (data capturing means) 34a to 34d, and M2P image processing module (output data image processing means) 32, and a write request for arbitrating write requests (data transfer output requests) from WDMACs 33a to 33d of each channel An arbiter (output request arbitration means) 35, and a read arbiter (capture request arbitration means) 36 that arbitrates read requests (data capture requests) from the RDMACs 34a to 34d of each channel, and a buffer control unit (data storage means) 38 is the S2M image processing module 31 and M2 FIFO0_a, FIFO0_b, FIFO1_a, FIFO1_b, FIFO2_a, FIFO2_b, FIFO3_a, FIFO3_b, which are line buffers that are twice the number of channels of the image processing module 32, and a write signal input from the write arbiter 35 when the mode signal mode is in the test mode An address decoder (write address decoding means) 51 that determines a channel based on the request and writes image data to the WDMACs 33a to 33d in the FIFO0_a, FIFO0_b, FIFO1_a, FIFO1_b, FIFO2_a, FIFO2_b, FIFO3_a, and FIFO3_b of the corresponding channel; When the mode signal mode is the test mode, the channel is determined based on the read request input from the read arbiter 36, and the channel And an address decoder (capture address decoding means) 55 that captures image data from the FIFO0_a, FIFO0_b, FIFO1_a, FIFO1_b, FIFO2_a, FIFO2_b, FIFO3_a, and FIFO3_b of the corresponding channel to the RDMACs 34a to 34d.

  Therefore, it is possible to perform a test by setting a plurality of channels corresponding to each color component of the image data of a plurality of colors, and to reduce the man-hours for evaluating the engine ASIC 11 that handles the image data of a plurality of colors, in particular, evaluating the image bus. However, it can be performed inexpensively and appropriately.

  Further, in the image forming apparatus 1 of the present embodiment, the engine ASIC 11 includes a frame effective signal delay setting register (delay amount setting means) 43 in which the frame effective signal delay amount fg_dly is appropriately set from the outside. The plotter FGATE selector (P_FG_SEL) (signal switching means) 45 replaces the frame valid signal p_fgate_test_n obtained by delaying the frame valid signal s_fgate_n by the frame valid signal delay amount fg_dly set in the frame valid signal delay setting register 43 instead of the frame valid signal p_fgate_n. This is input to the image processing module 32.

  Therefore, even when the S2M image processing module 31 internally causes a line delay, the frame effective signal p_fgate_n with respect to the frame effective signal s_fgate_n is set as a frame effective signal delay amount fg_dly by software or the like according to the delay amount. By setting the valid signal delay setting register 43, it is possible to appropriately evaluate without causing an abnormal image.

  Further, in the image forming apparatus 1 of the present embodiment, the engine ASIC 11 outputs an operation mode switching register (mode setting unit) 39 that outputs a mode signal mode corresponding to an operation mode set from the outside, or the mode signal mode is output from the outside. An input terminal (signal input means) is provided.

  Therefore, the test of the engine ASIC 11 can be executed by setting the test mode from software control or from the outside, and the usability can be improved.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 2 Engine board 3 Controller board 4 PCIe bus 5 Scanner 6 Plotter 11 Engine ASIC
12 Engine CPU
21 Controller ASIC
22 Hard disk (HDD)
23 North Bridge (NB)
24 Controller CPU
25 Memory 31 S2M Image Processing Module 32 M2P Image Processing Module 33a-33d WDMAC
34a-34d RDMAC
35 Arbiter for writing 36 Arbiter for reading 37 Endpoint (EP)
38 Buffer control unit 39 Operation mode switching register 40 Write data selector (W_SEL)
41 Read data selector (R_SEL)
42 Plotter LSYNC selector (P_LS_SEL)
43 Frame valid signal delay setting register 44 P_FGATE generator 45 Plotter FGATE selector (P_FG_SEL)
51 Address decoder 52a to 52d Write data selector (W_SEL *, * = 0 to 3)
53 Buffers 54a to 54d Read data selector (R_SEL *, * = 0 to 3)
55 Address recorder 56 Select signal generator 0_a, 0_b, 1_a, 1_b, 2_a, 2_b, 3_a, 3_b FIFO

JP 2008-226186 A

Claims (6)

Input data image processing means for performing predetermined image processing on input image data based on an input line synchronization signal and an input frame valid signal;
Data storage means for temporarily storing the image data in order to perform timing adjustment when transferring the image data processed by the input data image processing means to the external storage means;
Data transfer output means for transferring and outputting the image data processed by the input data image processing means to the external storage means via the data storage means;
Data capture means for capturing the image data of the external storage means via the data storage means;
Output data image processing means for performing predetermined image processing on the image data captured by the data capturing means based on an output line synchronization signal and an output frame valid signal; and
When a mode signal designating an operation mode of the normal mode and the inspection mode is input, and the mode signal is the normal mode, the output destination of the image data by the data transfer output unit is set in the external storage unit, and the mode Output destination switching means for setting the output destination of the image data by the data transfer output means in the data storage means when the signal is in the inspection mode;
When the mode signal is input and the mode signal is in the normal mode, the image data capturing unit by the data capturing unit is set in the external storage unit, and when the mode signal is in the inspection mode, the data capturing is performed. Input destination switching means for setting the image data capture destination by the means in the data storage means;
When the mode signal is input and the mode signal is in the inspection mode, the input line synchronization signal is input to the output data image processing means instead of the output line synchronization signal, and the output frame valid signal is replaced. A signal switching means for inputting a delayed input frame valid signal obtained by delaying the input frame valid signal by a predetermined delay amount to the output data image processing means;
An integrated circuit comprising: The integrated circuit comprises:
The input data image processing means for a plurality of channels, the data transfer output means, the data capture means and the output data image processing means;
Output request arbitration means for arbitrating a data transfer output request from the data transfer output means of each channel;
Capture request arbitration means for arbitrating data capture requests from the data capture means of each channel;
With
The data storage means is
A line buffer twice the number of channels of the input data image processing means and the output data image processing means;
When the mode signal is in the inspection mode, the channel is determined based on the data transfer output request input from the output request arbitration unit, and the image data is written in the data transfer output unit to the line buffer of the corresponding channel. Write address decoding means
When the mode signal is in the inspection mode, a channel is determined based on a data capture request input from the capture request arbitration unit, and capture is performed so that the data capture unit captures image data from the line buffer of the corresponding channel. Address decoding means;
The integrated circuit according to claim 1, further comprising: The integrated circuit comprises:
A delay amount setting means for appropriately setting the delay amount from the outside;
The signal switching means is
The delayed input frame valid signal obtained by delaying the input frame valid signal by the delay amount set in the delay amount setting means is input to the output data image processing means instead of the output frame valid signal. An integrated circuit according to claim 1 or 2. The integrated circuit comprises:
4. The apparatus according to claim 1, further comprising mode setting means for outputting the mode signal corresponding to an operation mode set from outside, or signal input means for inputting the mode signal from outside. An integrated circuit according to claim 1. Image reading means for reading an image of a document based on an input line synchronization signal and an input frame valid signal and outputting image data;
Image output means for recording and outputting an image according to the image data based on the output line synchronization signal and the output frame valid signal;
External storage means for storing image data;
The image data output from the image reading means is subjected to predetermined image processing and stored in the external storage means, and the image data in the external storage means is taken in, subjected to predetermined image processing and output to the image output means. An integrated circuit;
With
The integrated circuit comprises:
Input data image processing means for performing predetermined image processing on image data input from the image reading means based on the input line synchronization signal and the input frame valid signal input from the image reading means;
Data storage means for temporarily storing the image data in order to perform timing adjustment when transferring the image data processed by the input data image processing means to the external storage means;
Data transfer output means for transferring and outputting the image data processed by the input data image processing means to the external storage means via the data storage means;
Data capture means for capturing the image data of the external storage means via the data storage means;
The image data captured by the data capturing unit is subjected to predetermined image processing based on the output line synchronization signal and the output frame valid signal input from the image output unit, and is output to the image output unit. Output data image processing means;
When a mode signal designating an operation mode of the normal mode and the inspection mode is input, and the mode signal is the normal mode, the output destination of the image data by the data transfer output unit is set in the external storage unit, and the mode Output destination switching means for setting the output destination of the image data by the data transfer output means in the data storage means when the signal is in the inspection mode;
When the mode signal is input and the mode signal is in the normal mode, the image data capturing unit by the data capturing unit is set in the external storage unit, and when the mode signal is in the inspection mode, the data capturing is performed. Input destination switching means for setting the image data capture destination by the means in the data storage means;
When the mode signal is input and the mode signal is in the inspection mode, the input line synchronization signal is input to the output data image processing means instead of the output line synchronization signal, and the output frame valid signal is replaced. A signal switching means for inputting a delayed input frame valid signal obtained by delaying the input frame valid signal by a predetermined delay amount to the output data image processing means;
An image forming apparatus comprising: An input data image processing step for performing predetermined image processing on input image data based on an input line synchronization signal and an input frame valid signal;
A data storage processing step for temporarily storing the image data in the data storage means in order to perform timing adjustment when transferring the image data processed in the input data image processing step to the external storage means;
A data transfer output processing step for transferring and outputting the image data processed in the input data image processing step to the external storage means via the data storage means;
A data capture processing step for capturing the image data of the external storage means via the data storage means;
An output data image processing step for performing predetermined image processing on the image data captured in the data capturing processing step based on an output line synchronization signal and an output frame valid signal, and outputting the image data;
When the mode signal for specifying the operation mode of the normal mode and the inspection mode is the normal mode, the output destination of the image data in the data transfer output processing step is set in the external storage means, and the mode signal is in the inspection mode. If there is, an output destination switching processing step for setting the output destination of the image data in the data transfer output processing step in the data storage means,
When the mode signal is the normal mode, the image data capture destination by the data capture processing step is set in the external storage means, and when the mode signal is the inspection mode, the image data by the data capture processing step An input destination switching processing step for setting the data storage means in the data storage means;
When the mode signal is in the inspection mode, the input line synchronization signal is input to the output data image processing step instead of the output line synchronization signal, and the input frame validity signal is predetermined instead of the output frame validity signal. A signal switching processing step for inputting a delayed input frame valid signal delayed by a delay amount to the output data image processing step;
An integrated circuit inspection method comprising:

Images