JP2013030667A - Nitride semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a normally-off type nitride semiconductor device, along with its manufacturing method, capable of suppressing increase in on-resistance and reducing a gate leak current and a drain leak current during off period.SOLUTION: A nitride semiconductor layer 15 in an upper layer is such material as has a larger lattice constant than that of a nitride semiconductor layer 14 in a lower layer. A surface of the nitride semiconductor layer 15 in the upper layer among a gate electrode, a source electrode, and a drain electrode is applied with a plasma treatment with nitrogen gas. By performing the plasma treatment, a two-dimensional electronic gas layer 16 is formed which has a carrier concentration higher than that of a two-dimensional electronic gas layer formed with a lamination structure of the nitride semiconductor layer with no plasma treatment, which makes a normally-off type nitride semiconductor device having an excellent characteristic.

Description

The present invention relates to a nitride semiconductor device using a nitride semiconductor layer as an active layer, and more particularly to a high electron mobility transistor (HEMT).
The present invention relates to a normally-off type nitride semiconductor device having a control electrode in contact with a semiconductor device, such as a transistor, and applied to a switching device such as an inverter or a converter, and a manufacturing method thereof.

  FIG. 5 shows a cross-sectional view of a conventional semiconductor device made of a group III-V nitride semiconductor. The semiconductor device shown in FIG. 5 has a so-called HEMT structure, on a substrate 11 made of a sapphire substrate, a buffer layer 12 made of gallium nitride (GaN) grown at a low temperature, a channel layer 13 made of gallium nitride, and non-doped. The carrier supply layer 14 made of aluminum gallium nitride (AlGaN) and the cap layer 15 made of non-doped indium gallium nitride (InGaN) are sequentially stacked, except for the formation region of the gate electrode 18 (control electrode), The cap layer 15 is removed, and the recess 20 is formed. Here, indium gallium nitride constituting the cap layer 15 has a larger lattice constant than aluminum nitride constituting the lower carrier supply layer 14, and therefore is in a state where compressive stress is applied.

  This type of semiconductor device includes a channel layer 13 and a carrier supply layer 14 in a region other than immediately below the gate electrode 18, when no voltage is applied to the gate electrode 18, just below the gate electrode 18. Near the heterojunction interface, a two-dimensional electron gas layer 16 made of a potential well and having a very high electron mobility is formed. In the semiconductor device having such a structure, the two-dimensional electron gas layer 16 (channel) flowing between the source electrode 17a and the drain electrode 17b is controlled by controlling the voltage applied to the gate electrode 18. That is, when the control voltage applied to the gate electrode 18 is 0 V, carriers do not exist in the channel immediately below the gate electrode 18 due to the effect of the compressive stress applied to the cap layer 15, and the channels other than directly below the gate electrode 18 Is a normally-off type where carriers exist.

  FIG. 6 shows a cross-sectional view of another conventional semiconductor device made of a group III-V nitride semiconductor. In the semiconductor device shown in FIG. 6, instead of forming the cap layer 15 described in FIG. 5, the composition of the carrier supply layer 14 is made of aluminum indium gallium nitride (AlInGaN) and lattice-matched with the channel layer 13, and the carrier supply layer The pinch-off voltage is reduced by reducing the sheet carrier concentration of the two-dimensional electron gas layer 16 by reducing the composition of the aluminum 14 to about 0.1, so that a normally-off type is achieved. This type of semiconductor device is disclosed in Non-Patent Document 1, for example.

Hayashi, et al., “Characteristic evaluation of AlInGaN / GaN HEMT on Sapphire substrate”, 3rd volume of the 66th JSAP Autumn Meeting, 2005, JSAP, 2005 September 7, p. 1258

  In the conventional nitride semiconductor device shown in FIG. 5, the cap layer 15 other than the region where the gate electrode 18 is formed is etched away by a dry etching method using a reactive etching gas to form the recess 20, so that the exposed carrier is supplied. Damage or surface defects due to plasma occur on the surface of the layer 14. As a result, the two-dimensional electron gas layer 16 formed at the interface between the channel layer 13 and the carrier supply layer 14 decreases, the channel resistance between the source and gate or between the gate and drain increases, and the on-resistance increases. There was a problem.

  In another conventional nitride semiconductor device shown in FIG. 6, the carrier supply layer 14 is lattice-matched with the channel layer 13 as a composition containing indium, thereby eliminating piezo-polarization and further reducing the aluminum composition to about 0.1. In order to reduce the sheet carrier concentration of the two-dimensional electron gas layer 16, there is a problem that the channel resistance during operation is high and the on-resistance is also high.

  An object of the present invention is to provide a normally-off type nitride semiconductor device that can solve the above problems, suppress an increase in on-resistance, and can reduce gate leakage current and drain leakage current when off, and a method for manufacturing the same. And

  In order to achieve the above object, the invention according to claim 1 of the present application provides a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and at least one of the group consisting of nitrogen, phosphorus and arsenic. In a nitride semiconductor device including a group III-V nitride semiconductor layer composed of a group V element containing nitrogen, a first nitride semiconductor layer including the group III-V nitride semiconductor layer stacked on a substrate; And the group III-V nitride semiconductor layer laminated on the first nitride semiconductor layer, and has a lattice constant larger than that of the first nitride semiconductor layer, and compressive stress from the first nitride semiconductor layer. Receiving the second nitride semiconductor layer, two ohmic electrodes in ohmic contact with the first nitride semiconductor layer, spaced apart, and disposed between the ohmic electrodes, A control electrode in contact with the nitride semiconductor layer, a plasma treatment region on the surface of the second nitride semiconductor layer exposed between the control electrode and the ohmic electrode, and a voltage applied to the control electrode When 0 V, no carrier exists immediately below the control electrode, and carriers generated by forming the plasma processing region immediately below the plasma processing region exist.

  The invention according to claim 2 of the present application is composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and a group V element containing at least nitrogen among the group consisting of nitrogen, phosphorus and arsenic. In the method for manufacturing a nitride semiconductor device comprising the group III-V nitride semiconductor layer, a first nitride semiconductor layer comprising the group III-V nitride semiconductor layer on a substrate, and the III-V Forming a second nitride semiconductor layer comprising a group nitride semiconductor layer and having a lattice constant larger than that of the first nitride semiconductor layer and receiving compressive stress from the first nitride semiconductor layer; Forming an ohmic contact with the first nitride semiconductor layer and forming two ohmic electrodes spaced apart from each other; contacting the second nitride semiconductor layer between the ohmic electrodes; When the voltage to be applied is 0 V, a step of forming a control electrode in which no carrier exists immediately below, and a surface of the second nitride semiconductor layer exposed between the control electrode and the ohmic electrode are subjected to plasma treatment, And a step of generating carriers that were not present before the plasma treatment immediately below the plasma treatment region.

  In the nitride semiconductor device of the present invention, the plasma treatment region exposed to the plasma of the inert gas is formed on the surface of the second nitride semiconductor layer in the vicinity of the control electrode formation region. Carriers are generated in the vicinity. Therefore, the channel resistance during operation is lower and the on-resistance is lower than that of a conventional nitride semiconductor device, and a nitride semiconductor device with favorable characteristics can be obtained.

  In particular, compared to a conventional nitride semiconductor device having a structure in which the second nitride semiconductor layer other than the control electrode formation region is completely removed to expose the first nitride semiconductor layer, the on-current is increased and turned off. The reduction in current could be confirmed.

  The nitride semiconductor device manufacturing method of the present invention is a simple manufacturing method that does not require a special manufacturing apparatus, and only requires plasma treatment of an inert gas used in a normal semiconductor device manufacturing process. .

1 is a cross-sectional view of a nitride semiconductor device according to a first embodiment of the present invention. It is explanatory drawing of the manufacturing method of the nitride semiconductor device which is 1st Example based on this invention. It is sectional drawing of the nitride semiconductor device which is 2nd Example based on this invention. It is a figure which shows the transfer characteristic of the nitride semiconductor device of this invention. It is sectional drawing of the conventional nitride semiconductor device. It is sectional drawing of another conventional nitride semiconductor device.

  The present invention is a nitride semiconductor device in which nitride semiconductor layers selected so that the lattice constant of the lower nitride semiconductor layer is made of a material smaller than the lattice constant of the upper nitride semiconductor layer are stacked. A control electrode (gate electrode) is formed on the upper nitride semiconductor layer. Furthermore, the surface of the upper nitride semiconductor layer is a plasma processing region exposed to an inert gas plasma. Hereinafter, the nitride semiconductor device of the present invention will be described in detail according to a manufacturing process, taking a HEMT as a group III-V nitride semiconductor device as an example.

  FIG. 1 is a sectional view of a nitride semiconductor device according to a first embodiment of the present invention, and FIG. 2 is an explanatory view of the manufacturing method. As in the conventional example, a buffer layer 12 made of gallium nitride grown at a low temperature of about 30 nm on a substrate 11 made of sapphire, and has an energy gap smaller than the energy gap of a carrier supply layer 14 described later at a normal film formation temperature. A channel layer 13 made of non-doped gallium nitride having a thickness of 2 μm, and a carrier supply layer 14 made of non-doped aluminum gallium nitride having a thickness of 10 nm forming a two-dimensional electron gas layer serving as a carrier at the interface with the channel layer 13 (first nitride) A substrate in which a cap layer 15 (corresponding to a second nitride semiconductor layer) made of non-doped indium gallium nitride having a thickness of 10 nm is sequentially laminated is prepared (FIG. 2a). Here, as shown in FIG. 2A, since the cap layer 15 is laminated, a two-dimensional electron gas layer is not formed at the interface between the channel layer 13 and the carrier supply layer 14.

  Next, a photoresist that opens the source electrode and drain electrode formation scheduled regions is patterned on the cap layer 15 by a normal photolithographic method, and the exposed surface of the cap layer 15 is etched away by a chlorine-based dry etching method. After that, a carrier film is formed by forming a laminated film of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) by RTA treatment at 850 ° C. for 30 seconds by a normal lift-off method. A source electrode 17a and a drain electrode 17b are formed in ohmic contact with the layer 14 (FIG. 2b). Here, by removing the cap layer 15, a two-dimensional element gas layer 16 is formed at the interface between the channel layer 13 and the carrier supply layer 14 immediately below the source electrode 17a and the drain electrode 17b.

  Next, a gate electrode 18 made of a nickel (Ni) / gold (Au) laminated film or the like is formed on the cap layer 15, and a Schottky contact is formed with the cap layer 15 (FIG. 2c).

  Thereafter, using the gate electrode 18, the source electrode 17a and the drain electrode 17b as a mask, the exposed surface of the cap layer 15 is exposed to an inert gas plasma to complete the nitride semiconductor device. Here, when nitrogen is used as the inert gas, the surface of the cap layer 15 is subjected to nitrogen plasma treatment. As a result, a two-dimensional electron gas layer 16 is generated at the interface between the channel layer 13 and the carrier supply layer 14 other than the gate electrode 18 formation region (FIG. 2d). Here, the plasma treatment of the surface of the cap layer 15 uses, for example, an ICP (inductively coupled plasma) type dry etching apparatus, RF power 30 W, RF bias 10 W, pressure 0.5 Pa, nitrogen flow rate 20 sccm, treatment time 5 minutes, etc. Perform under the conditions of In addition to nitrogen gas, helium, argon, xenon, etc. can be used as the inert gas.

  FIG. 4 shows the transfer characteristics (current-voltage characteristics when the drain voltage Vd = 5 V) of the nitride semiconductor device thus formed. In this graph, the horizontal axis indicates the gate-source electrode voltage Vg (V), and the vertical axis indicates the source-drain current Id (A). FIG. 4B is a logarithmic display of FIG. For comparison, the transfer characteristic of the nitride semiconductor device having the structure shown in FIG. 6 described in the conventional example is shown by a solid line, and the first example (■) in FIG. 4 is shown. In the nitride semiconductor device of this example, it can be seen that the on-current at a gate voltage of 0 V or higher is about twice as high as that of the conventional example. Furthermore, the off-current was reduced by about one digit. Thus, in this example, it was confirmed that a nitride semiconductor device having excellent characteristics can be provided.

  This is because, when the cap layer 15 is treated with nitrogen plasma, damage or defects due to plasma occurs in the cap layer 15 to which compressive stress is applied, the compressive stress is relaxed, or the surface level is changed, so that the two-dimensional electron gas is changed. This is probably because the layer 16 was generated. On the other hand, depending on the conditions of the plasma treatment, for example, when the power to be applied is large or the plasma treatment time is long, new defects also occur in the cap layer 15 and the carrier supply layer 14, and the two-dimensional electron gas The generation amount may be reduced. Therefore, it is necessary to adjust the applied power, the processing time, and the like to such an extent that the two-dimensional electron gas is generated and the carrier supply layer 14 does not cause defects or the like that reduce the generation amount of the two-dimensional electron gas.

  FIG. 3 is a sectional view of a nitride semiconductor device according to the second embodiment of the present invention. In this embodiment, the process is the same up to the step of forming the gate electrode 18 described in Embodiment 1 (FIG. 2c). Thereafter, in this embodiment, the gate electrode 18, the source electrode 17a, and the drain electrode 17b are used as a mask, and the cap layer 15 is plasma-etched by 2 nm with silicon tetrachloride gas. Thereafter, the exposed surface of the cap layer 15 is treated with an inert gas plasma to complete the nitride semiconductor device (FIG. 3). Here, when nitrogen is used as the inert gas, the surface of the cap layer 15 is subjected to nitrogen plasma treatment. As a result, a two-dimensional electron gas layer 16 is generated at the interface between the channel layer 13 and the carrier supply layer 14 other than the region below the gate electrode 18. Here, the plasma treatment of the surface of the cap layer 15 uses, for example, an ICP (inductively coupled plasma) type dry etching apparatus, RF power 30 W, RF bias 10 W, pressure 0.5 Pa, nitrogen flow rate 20 sccm, treatment time 5 minutes, etc. Perform under the conditions of In addition to nitrogen gas, helium, argon, xenon, etc. can be used as the inert gas.

  FIG. 4 shows the transfer characteristics (current-voltage characteristics when the drain voltage Vd = 5 V) of the nitride semiconductor device thus formed. As shown in FIG. 4 in the second embodiment (▲), the nitride semiconductor device according to this embodiment has an on-current that is about twice as high as that of the comparative example when the gate voltage is 0 V or higher. It was found that the values were almost the same. Further, it can be seen that the off-state current is lower than that of the first embodiment and is reduced by about three orders of magnitude compared to the conventional example. Thus, it was confirmed that the nitride semiconductor device having excellent characteristics can be provided also in this example.

  This is presumably because the step of etching the surface of the cap layer 15 can remove the surface natural oxide film after epi growth and the surface defects during the process, which are the main factors of the gate leakage current.

  Note that since the etching rate of the silicon tetrachloride plasma used in this embodiment can be made extremely low as 1.4 nm / min, it can be easily controlled even in shallow etching as in this embodiment. Further, when the etched surface was measured by an atomic force microscope (AFM), the RMS value was 0.56 nm even after etching, and the flatness was very excellent.

  Also in this embodiment, when plasma etching or nitrogen plasma treatment is performed, new defects are generated in the cap layer 15 or the carrier supply layer 14 depending on the conditions, and the generation amount of the two-dimensional electron gas is reduced. May end up. Therefore, it is necessary to adjust the applied power, the processing time, etc. to such an extent that the two-dimensional electron gas is generated and the carrier supply layer 14 is not affected by defects or the like that reduce the two-dimensional electron gas generation amount.

  In addition, since a reaction product remains in the etching region, in order to remove the reaction product, the electrode surface is protected, and then the etching region is treated with an acid-based or alkali-based treatment liquid. Is preferably dissolved and removed. By this treatment, reaction products are removed, and the etching region surface can be cleaned.

  As described above, according to the present invention, it was confirmed that a normally-off type nitride semiconductor device having a low channel resistance and a high drain current ON / OFF ratio can be provided.

  The present invention is not limited to these examples and can be variously modified. For example, the type of the control electrode, the thickness of the cap layer and the carrier supply layer, and the composition ratio of aluminum or indium are appropriately set so that carriers do not exist in the channel directly below the control electrode and carriers exist in channels other than immediately below the control electrode. Can be selected and set.

  The nitride semiconductor layer is not limited to the GaN / AlGaN system, and the first nitride semiconductor layer (corresponding to the carrier supply layer 14 in the above embodiment) is GaN, InN, AlN, or a mixture thereof. It can be formed of a layer containing a crystal compound and containing at least aluminum. The second nitride semiconductor layer (corresponding to the cap layer 15 in the above embodiment) on which the control electrode is formed contains GaN, InN, AlN, or a mixed crystal compound thereof, and is on the first nitride semiconductor layer. By forming into a film, it can be formed with a layer that receives compressive stress. The second nitride semiconductor layer can also be formed of a p-type conductive film. A silicon carbide (SiC) substrate may be used instead of the sapphire substrate used in the examples. In that case, it is preferable to use aluminum nitride (AlN) as the buffer layer 12. A silicon (Si) substrate may be used instead of the sapphire substrate.

  The composition of the electrode that is in ohmic contact with the first nitride semiconductor layer may be appropriately selected according to the type of the nitride semiconductor layer to be used.

11: substrate, 12: buffer layer, 13: channel layer, 14: carrier supply layer, 15: cap layer, 16: two-dimensional electron gas layer, 17a: source electrode, 17b: drain electrode, 18: gate electrode, 19: Recess, 20: Plasma treatment region

Claims (2)

Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a nitride semiconductor device composed of a semiconductor layer,
A first nitride semiconductor layer made of the group III-V nitride semiconductor layer stacked on a substrate, and the group III-V nitride semiconductor layer stacked on the first nitride semiconductor layer, A second nitride semiconductor layer having a lattice constant larger than that of the first nitride semiconductor layer and receiving compressive stress from the first nitride semiconductor layer; and ohmic contact with the first nitride semiconductor layer; Two ohmic electrodes disposed apart from each other, a control electrode disposed between the ohmic electrodes and in contact with the second nitride semiconductor layer, and the first electrode exposed between the control electrode and the ohmic electrode A plasma treatment region on the surface of the nitride semiconductor layer of 2;
The nitriding is characterized in that when the voltage applied to the control electrode is 0 V, no carrier exists immediately below the control electrode, and carriers generated by forming the plasma processing region immediately below the plasma processing region exist. Semiconductor device. The group III-V nitride comprising a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and a group V element containing at least nitrogen among the group consisting of nitrogen, phosphorus and arsenic In a method for manufacturing a nitride semiconductor device comprising a semiconductor layer,
On the substrate, the first nitride semiconductor layer made of the group III-V nitride semiconductor layer and the group III-V nitride semiconductor layer, the lattice constant is larger than the first nitride semiconductor layer, Stacking a second nitride semiconductor layer that receives compressive stress from the first nitride semiconductor layer;
Forming two ohmic electrodes that are in ohmic contact with and spaced apart from the first nitride semiconductor layer;
Forming a control electrode that is in contact with the second nitride semiconductor layer between the ohmic electrodes and has no carriers immediately below when the applied voltage is 0 V;
Plasma treating the surface of the second nitride semiconductor layer exposed between the control electrode and the ohmic electrode, and generating carriers that were not present immediately before the plasma treatment immediately below the plasma treatment region. A method for manufacturing a nitride semiconductor device.

Images