JP2013030072A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller enabling processing at high-speed without any waste of H/W.SOLUTION: A memory controller 1000 controls a real memory 004 which stores a payload in a payload area and parity data in a parity area. A payload/parity area address calculation part 001 receives the ratio of the payload and the number of bits of parity data as a payload/parity ratio 104, receives the number of areas classified into the payload area as a result of classification into the payload area and parity area by approximating areas of the real memory 004 to the payload/penalty ratio as a division ratio 103, receives a memory address length 102 of the real memory 004, receives a memory address 101 of the payload, and calculates a memory address of the parity data corresponding to the payload in a parity area using them.

Description

  The present invention relates to a technique for controlling a memory device that stores a payload in a payload area and stores parity data in the parity area.

  A system is disclosed in which an ECC (Error Correcting Code) code length is variable and an error correction method optimal for a target application can be adopted (for example, Patent Document 1 and Patent Document 2).

JP 2003-131954 A JP 2008-41171 A

  As described in the background art, the ECC code length is variable, and the tradeoff between the payload protected by ECC (data corrected by ECC) and the cost (redundant / parity data amount) required for protection There has been proposed a system that can be flexibly adapted and can set an optimal trade-off point according to input data and conditions even in the same system configuration.

In Patent Document 1, a single memory is virtually divided into two areas by software (hereinafter also referred to as S / W), and the ratio of the payload area and the parity area in the single memory according to the selected ECC algorithm A method of making the variable is disclosed.
Further, in Patent Document 2, a data memory cell array and a parity memory cell array in a memory cell array are configured to correspond to a plurality of ECC code lengths, an input-side parity generation circuit that generates parity from write data, and parity from read data. The output-side parity generation circuit that generates a syndrome and the syndrome generation circuit that generates a syndrome bit indicating an error bit from the read parity bit and the generated parity bit can be switched according to the code lengths of a plurality of ECCs. It is disclosed.

Since the conventional technology is configured as described above, when performing a series of processes in S / W as in Patent Document 1, complicated calculations such as ECC calculation and address calculation for storing payload and parity are performed in S. Since it is necessary to perform the processing at / W, processing takes time.
In addition, when configured with hardware (hereinafter also referred to as H / W) as in Patent Document 2, although it can be processed at a higher speed than S / W, the area where the payload and parity are arranged is H / W. For example, when the parity may be extremely small with respect to the payload, all the memory prepared as the parity area is not used, resulting in H / W waste.

  One of the main objects of the present invention is to solve the above-mentioned problems, and it is a main object of the present invention to realize a memory control device capable of processing at high speed without waste of H / W. And

The memory control device according to the present invention includes:
A memory control device that controls a memory device that stores a payload to be error corrected in a payload area and stores parity data used for error correction of the payload in a parity area,
A payload / parity ratio input section for inputting a ratio of the number of bits of the payload to the number of bits of parity data as a payload / parity ratio;
A plurality of divided areas obtained by dividing the area of the memory device by a predetermined number equal to or greater than the total value of the number of bits of the payload and the number of bits of parity data are approximated to the payload / parity ratio, A division ratio input unit that inputs the number of divided areas classified into the payload area as a division ratio,
A memory address length input unit for inputting a memory address length of the memory device;
A payload address input unit for inputting a memory address in the payload area as a payload address;
The payload / parity ratio input by the payload / parity ratio input unit, the division ratio input by the division ratio input unit, the memory address length input by the memory address length input unit, and the payload address input unit And a parity address calculation unit that calculates a memory address in the parity area of the parity data corresponding to the payload stored in the payload address as a parity address using the payload address input by .

  According to the present invention, three parameters (payload / parity ratio, memory address length, division ratio) are changed in response to a change in the data length ratio between the payload and the parity data and a change in the size of the memory device. If the division ratio is set appropriately, H / W is not wasted. Further, since all control can be performed by H / W, high-speed processing can be realized.

FIG. 3 is a diagram illustrating a configuration example of a memory control device according to the first embodiment. FIG. 3 is a diagram showing a configuration example of a payload / parity area address calculation unit according to the first embodiment. The figure which shows the division | segmentation ratio of the payload area | region and parity area which can be expressed by 6 bits which concern on Embodiment 1. FIG. FIG. 3 shows an example of a payload area and a parity area according to the first embodiment. FIG. 3 is a timing chart at the time of writing according to the first embodiment. FIG. 4 is a timing chart at the time of reading according to the first embodiment. FIG. 3 is a timing chart at the time of read-modify-write according to the first embodiment. FIG. 3 is a diagram showing an outline of a read modify write according to the first embodiment.

Embodiment 1 FIG.
In the present embodiment, an address calculation unit for performing address calculation for storing payload and parity data in a single memory device, and a sequence control unit for controlling a control signal for reading / writing to / from the memory A memory control device including the above will be described.
More specifically, all control can be performed at high speed by performing H / W, and address calculation is performed with three parameters of memory address length, division ratio, and payload / parity ratio. On the other hand, since it can be divided into two areas at an arbitrary ratio within the range of the maximum natural number that can represent the division ratio, and payload and parity data can be stored separately in a single memory, there is no waste in H / W A memory controller that does not occur will be described.

FIG. 1 shows a configuration example of a memory control device and the like according to the first embodiment.
Reference numeral 1000 denotes a memory control device according to the present embodiment.
The memory control device 1000 is connected to an actual memory 004 that is a memory device and an ECC calculation unit 003 that calculates ECC.

In the memory control device 1000, the payload / parity area address calculation unit 001 receives the memory address 101, the memory address length 102, the division ratio 103, the payload / parity ratio 104, and the payload / parity selection signal 105 as input. Output the address 106 of the real memory 004.
The sequence control unit 002 receives the address 106, the command 107, the write data 108, and the parity data 109, and outputs a control signal, a real memory address 111, a real memory command 112, and a real memory write data 113 to the real memory 004.
Also, the real memory read data 110 is input, and the payload and parity data are buffered separately in the inside, and read data (payload) 114 and read data (parity) 115 are output.

The ECC calculation unit 003 receives the write data 108 and generates parity data 109.
Also, read data (payload) 114 and read data (parity) 115 are input, and read data 116 after ECC is output.

  As illustrated in FIG. 4, the real memory 004 is divided into a payload area and a parity area, stores the payload in the payload area, and stores parity data in the parity area.

The memory address length 102, the division ratio 103, and the payload / parity ratio 104 are basically fixed values.
These parameter values are changed in accordance with the ECC algorithm and the capacity of the real memory 004, and are not changed unless the ECC algorithm and the memory capacity are changed.
For example, it is set once when the system is started and is not changed thereafter.

Next, the detailed configuration of the payload / parity area address calculation unit 001 is shown in FIG.
In the following description, in order to simplify the description, the memory address is input by a 32-bit signal line, the division ratio is input by a 6-bit signal line, and the memory address length is input by a 20-bit signal line. .
This is for simplifying the description and does not limit the configuration.

The payload address input unit 121 inputs a bit string representing the memory address 101 and the memory address length 102, validates the memory address 101 by the number of bits indicated by the memory address length 102, and masks the rest to “0”. In other words, taking this embodiment as an example, the lower 20 bits of the 32 memory addresses are valid and the upper 12 bits are masked to “0”.
The memory address 101 is the address of the payload to be read or written (the address in the payload area of the real memory 004).

The memory address length input unit 122 inputs a bit string representing the memory address length 102.
The memory address length 102 is the address length of the real memory 004.

The division ratio input unit 123 inputs a bit string representing the division ratio 103.
Details of the division ratio 103 will be described later.

The payload / parity ratio input unit 124 inputs the payload / parity ratio 104.
The payload / parity ratio 104 represents the ratio of the data length of the payload to the data length of the parity data as a logarithm with 2 as the base.
For example, for a payload with a data length of 32 bits, if the parity data has a data length of 8 bits, the payload / parity ratio 104 is log ₂ 32/8 = “2”.

The first shift unit 125 shifts the bit string representing the memory address 101 to the right or left according to the payload / parity ratio 104.
More specifically, if the data length of the payload is longer than the data length of the parity data (payload> parity), the first shift unit 125 increases the memory address 101 by the number of bits corresponding to the value of the payload / parity ratio 104. The bit string representing is shifted to the right.
If the data length of the payload is shorter than the data length of the parity data (payload <parity), the bit string representing the memory address 101 is shifted leftward by the number of bits corresponding to the value of the payload / parity ratio 104.
For example, for a payload with a data length of 32 bits, if the parity data has a data length of 8 bits, the payload / parity ratio 104 is “2”, and the first shift unit 125 sets the bit string representing the memory address 101 to 2 Shift right by bits.
Conversely, if the parity data is 32 bits with respect to the 8-bit payload, the payload / parity ratio 104 is “−2”, and the first shift unit 125 converts the bit string representing the memory address 101 into 2 bits. Shift left.
If the payload / parity is not an integer such as “2.2”, a shift corresponding to the number of bits of the integer portion is performed.
That is, when the payload / parity ratio 104 is “2.2”, the data is shifted to the right by 2 bits.
Further, if the data length of the payload and the data length of the parity data are the same number (payload = parity), the data is not shifted in either direction.

The shift amount calculation unit 127 calculates a difference ((mn) bits) between the number of bits of the bit string having the memory address length 102 (m bits) and the number of bits of the bit string representing the division ratio 103 (n bits). Ask.
Note that m and n are both natural numbers.

  The second shift unit 126 shifts the bit string representing the division ratio 103 to the left by (mn) bits calculated by the shift amount calculation unit 127.

The adder 128 adds the bit string representing the memory address 101 after the shift calculation by the first shift unit 125 and the bit string representing the division ratio 103 after the shift calculation by the second shift unit 126.
The addition result by the second shift unit 126 is the address of the parity data corresponding to the payload specified by the memory address 101 (the address in the parity area of the real memory 004).
That is, the value output from the first shift unit 125 is the lower part of the memory address storing the parity data, and the value output from the second shift unit 126 is from the memory start address of the address storing the parity data. Indicates an offset. Therefore, by adding these, the address of the parity data can be calculated.

The selector 129 selects the address 106 to be output to the sequence control unit 002 based on the payload / parity selection signal 105.
That is, when a payload is specified by the payload / parity selection signal 105, the memory address 101 is output as the address 106 as it is.
On the other hand, when the parity is designated by the payload / parity selection signal 105, the address of the parity data generated by the adder 128 is output as the address 106.

The address 106 is the same size as the memory address 101 (32 bits in the first embodiment).
Of the 32 bits of the address 106, the address for storing the parity data is included in the memory address length (20 bits in the first embodiment).
The real memory address 111 indicates valid 20 bits (real memory address) out of 32 bits of the address 106, and in actual use, these 20 bits are connected to the address line of the real memory.
The remaining 12 bits are not connected.

  In the configuration of FIG. 2, the first shift unit 125, the second shift unit 126, the shift amount calculation unit, and the 127 adder 128 correspond to a parity address calculation unit, and the selector 129 corresponds to an address notification unit. .

Next, the division ratio 103 will be described.
The division ratio 103 represents the ratio at which the payload / parity data is stored on the real memory 004.
In other words, the division ratio 103 is obtained by approximating a plurality of divided areas obtained by dividing an area of the real memory 004 by a predetermined number equal to or greater than the sum of the number of payload bits and the number of parity data bits to the payload / parity ratio. The number of divided areas classified into the payload area as a result of the classification into the payload area and the parity area.
As a specific expression method, the memory is divided by the maximum natural number that can be expressed by a binary number, or 11_1111 (binary) = 64 (decimal) if the division ratio is 6 bits. Represents the number of regions used by.
According to this expression method, the ratio between the payload area and the parity area in the real memory is expressed by the following equation (1).
Payload area: Parity area = Payload use area number: 64-Payload use area number (1)
Therefore, for example, when the ECC algorithm requires 8-bit parity for a 32-bit payload, the division ratio is set to 11_0011 () so that the division ratio 51: 13 = 3.92: 1 is closest to this ratio. Binary number) = 51 (decimal number).

Since it is configured as described above, in the case of the present embodiment, the division ratio can be freely moved from 0 to the maximum natural number that can be expressed by the division ratio (6 bits), 2 ⁶ = 64, Even if the ECC algorithm changes and the ratio between the payload and the parity changes, it is possible to flexibly cope with it and reduce H / W waste.
FIG. 3 shows the division ratio between the payload area and the parity area that can be expressed by a division ratio of 6 bits.

  Next, an address calculation method will be described.

The memory address length 102 used for the calculation represents the address length of the real memory 004 connected to the memory control apparatus 1000. For example, if the memory has a capacity of 512 kB, it may be 19 (decimal notation), 1 MB memory. 20 (decimal notation).
The payload / parity selection signal 105 is a signal indicating which address indicating the payload / parity data area is output.
If this signal instructs to output the payload address, the memory address 101 is output as it is.
If an instruction to output a parity address is given, a parity address is generated from the memory address 101 using the payload / parity ratio 104, the division ratio 103, and the memory address length 102 as calculation parameters.

  As shown in FIG. 2, the calculation of the parity address in the first embodiment can be configured with only a logical shift and an adder using a memory address 101, a memory address length 102, a division ratio 103, and a payload / parity ratio 104. It can be realized on a small circuit scale.

As described above, the shift amount of the division ratio 103 calculated from the memory address length 102 is the difference between the n-bit bit string indicating the division ratio 103 and the memory address length 102 indicated by m bits (mn). ) Bit.
Then, the n-bit bit string indicating the division ratio 103 is shifted left by (mn) bits.
That is, the n-bit bit string indicating the division ratio 103 is shifted to the most significant bit position of the input memory address 101 calculated from the memory address length 102 indicated by m bits.
In this embodiment, since m = 20 and n = 6, the shift amount is 14 bits, and the bit string indicating the division ratio 103 is shifted left by 14 bits.
Further, as described above, the bit string representing the memory address 101 is right-shifted or left-shifted according to the payload / parity ratio 104 and the bit string representing the division ratio 103 after the left shift is added to obtain the parity address. obtain.

The sequence control unit 002 receives the address 106, the command 107, and the write data 108, and outputs a control signal real memory address 111, a real memory command 112, and a real memory write data 113 for controlling the real memory 004.
In this embodiment, the real memory command 112 includes a general control signal for memory control.
Examples of the memory control signal include a chip select signal indicating that a command to the memory is valid, a read / write signal instructing read / write, and a byte control instructing a read / write position.
These control signals can be read / written to the memory by controlling the assertion / negotiation period and order of each signal in accordance with the performance and standard / specification of the connected memory.
In this embodiment, since the payload and parity data are stored in the same memory, at least two memory accesses (payload read / write, parity read / write) are required.
In this embodiment, the payload is read / written in the first access, and the parity data is read / written in the second access.
This series of sequence control is performed by the sequence control unit 002.
In this embodiment, the payload read / write is performed for the first time and the parity data read / write is performed for the second time. However, this order may be reversed.

In addition, ECC calculation requires a fixed length of parity for a fixed length of payload according to an algorithm to be applied.
Therefore, special processing is required when it is desired to write a payload shorter or longer than a predetermined length to the memory.
For example, when an ECC algorithm that requires 8-bit (1-byte) parity is applied to a 32-bit (4-byte) payload, the first 4 bytes are written to an address as shown in FIG. After performing the above, consider the case where only the 1-byte payload at the same address is rewritten.
Since the first access (FIG. 8A) has a 4-byte payload, parity can be generated without any problem.
In the second access (FIG. 8 (b)), we want to rewrite only 1 byte of the same address, but since the parity has already been generated in a form including the remaining 3 bytes of redundant data, the remaining 3 bytes of payload is Without it, correct parity cannot be generated.
Therefore, the remaining 3-byte payload (and parity) is read prior to writing.
Then, the read 3-byte payload is merged with 8-bit write data (payload) to obtain 32 bits, and then the ECC is calculated.
Such read-modify-write processing is also performed by the sequence control unit 002.

The ECC calculation unit 003 receives the write data 108 and calculates the parity data 109 according to the ECC algorithm.
Also, read data (payload) 114 and read data (parity) 115 are input from sequence control unit 002, and if there is an error in read data (payload) 114 using read data (parity) 115, correction is performed. And output as read data 116.

With the above configuration, even if the payload algorithm or parity data ratio changes due to a change in the ECC algorithm or the actual memory size changes, three parameters (memory address length and division ratio, payload / (Parity ratio) only needs to be changed accordingly. Payload and parity data are stored in the same memory by dividing the area, and the division ratio is the maximum natural number range that can be expressed by the division ratio. Therefore, if the division ratio is set appropriately, H / W is not wasted.
Moreover, since all control is performed by H / W, it can process at high speed.
Furthermore, since the payload / parity area address calculation can be configured with only logical operations and shifters as shown in FIG. 2, the circuit scale can be reduced.

  Next, the operation at the time of writing, the operation at the time of reading, and the operation at the time of read modify writing will be described.

FIG. 5 shows a timing chart at the time of writing.
The operation at the time of writing is composed of the following (1) and (2).

(1) First, a write request (command 107) to the memory control device 1000 is input to the sequence control unit 002.
When recognizing that it is a write, the sequence control unit 002 first outputs the payload / parity selection signal 105 to the payload / parity area address calculation unit 001 to select the payload in order to write the payload data into the memory. Let them know.
Upon receiving this notification, the payload / parity area address calculation unit 001 returns the payload data write address (memory address 101 itself) to the sequence control unit 002 as the address 106.
In accordance with this address 106, the sequence control unit 002 performs a payload data write operation to the real memory 004.
(2) When the write of (1) is completed, the sequence control unit 002 next outputs a payload / parity selection signal 105 to the payload / parity area address calculation unit 001 to inform the selection of parity data.
Upon receiving this notification, the payload / parity area address calculation unit 001 generates a parity data write address according to the above-described procedure, and returns the parity data write address as the address 106 to the sequence control unit 002.
In accordance with this address 106, the sequence control unit 002 performs a parity data 109 write operation to the real memory 004.

Next, FIG. 6 shows a timing chart at the time of reading.
The operation at the time of writing is composed of the following (1), (2) and (3).

(1) First, a read request (command 107) for the memory control device 1000 is input to the sequence control unit 002.
When the sequence control unit 002 recognizes that it is a read, first, in order to read the payload data from the real memory 004, it outputs a payload / parity selection signal 105 to the payload / parity area address calculation unit 001 and outputs the payload. Tell them to choose.
Upon receiving this notification, the payload / parity area address calculating unit 001 returns the payload data read address (memory address 101 itself) to the sequence control unit 002 as the address 106.
In accordance with this address 106, the sequence control unit 002 performs a payload data read operation on the real memory 004.
(2) When the reading of (1) above is completed, the sequence control unit 002 next outputs a payload / parity selection signal 105 to the payload / parity area address calculation unit 001 to inform it to select a parity.
Upon receiving this notification, the payload / parity area address calculation unit 001 generates a parity data read address by the above-described procedure, and returns the parity data read address as the address 106 to the sequence control unit 002.
In accordance with this address 106, the sequence control unit 002 performs a parity data read operation on the real memory 004.
(3) Finally, the ECC calculation unit 003 performs ECC calculation from the read data (payload) 114 and the read data (parity) 115 and outputs the calculation result as read data 116.

Next, FIG. 7 shows a timing chart at the time of read-modify-write.
The operation during read-modify-write is composed of the following (1) to (5).

(1) The sequence control unit 002 performs the payload read operation described with reference to FIG. 6 on the payload to be merged.
(2) Similarly, the sequence control unit 002 performs the parity data read operation described with reference to FIG. 6 on the parity data of the payload to be merged.
(3) The ECC calculation unit 003 merges the write data 108 and the payload read in (1) above, and generates new parity data using the parity data read in (2) above.
(4) Next, the sequence control unit 002 performs the payload write operation described with reference to FIG. 5 on the merged payload.
(5) Similarly, the sequence control unit 002 performs the parity write operation described with reference to FIG. 5 on new parity data.

  As described above, in this embodiment, an ECC calculation unit that calculates ECC (Error Check and Correct memory), an address calculation unit that calculates a memory address for storing an ECC payload and a parity bit, and read / write to the memory A memory control device including a sequence control unit that controls a control signal for performing the above-described operation has been described.

  In addition, it has been described that the address calculation unit calculates a memory address for storing payload and parity data using the memory address length and the division ratio as parameters.

  The address calculation unit outputs a memory address, a payload / parity selection signal indicating which address of the payload / parity area is output, a bit string of n (n is a natural number) bits indicating a division ratio, and m (M is a natural number) When the memory address length indicated in bits and the payload / parity ratio are input, and the payload / parity selection signal indicates the output of the address of the payload area, the input memory address is output as it is, and the parity area When instructing the address output, the n-bit bit string indicating the division ratio is shifted to the most significant bit position of the input memory address calculated from the memory address length indicated by m bits, and the shifted n-bit bit string and , The memory address shifted right by the number of bits indicated by the payload / parity ratio. It has been described to calculate a memory address of the parity area by adding and.

  001 Payload / parity area address calculation unit, 002 sequence control unit, 003 ECC calculation unit, 004 real memory, 101 memory address, 102 memory address length, 103 division ratio, 104 payload / parity ratio, 105 payload / parity selection signal, 106 Address, 107 command, 108 write data, 109 parity data, 110 real memory read data, 111 real memory address, 112 real memory command, 113 real memory write data, 114 read data (payload), 115 read data (parity), 116 Read data, 121 Payload address input section, 122 Memory address length input section, 123 Division ratio input section, 124 Payload / parity ratio input section, 125 First shift , 126 second shift section, 127 a shift amount calculation portion, 128 an adder, 129 a selector, 1000 memory controller.

Claims (3)

A memory control device that controls a memory device that stores a payload to be error corrected in a payload area and stores parity data used for error correction of the payload in a parity area,
A payload / parity ratio input section for inputting a ratio of the number of bits of the payload to the number of bits of parity data as a payload / parity ratio;
A plurality of divided areas obtained by dividing the area of the memory device by a predetermined number equal to or greater than the total value of the number of bits of the payload and the number of bits of parity data are approximated to the payload / parity ratio, A division ratio input unit that inputs the number of divided areas classified into the payload area as a division ratio,
A memory address length input unit for inputting a memory address length of the memory device;
A payload address input unit for inputting a memory address in the payload area as a payload address;
The payload / parity ratio input by the payload / parity ratio input unit, the division ratio input by the division ratio input unit, the memory address length input by the memory address length input unit, and the payload address input unit And a parity address calculation unit that calculates a memory address in the parity area of the parity data corresponding to the payload stored in the payload address as a parity address using the payload address input by Memory controller. The split ratio input unit is
A bit string of n (n is a natural number) bits representing the division ratio is input as a division ratio bit string,
The memory address length input unit is:
A bit string of m (m is a natural number) bits representing the memory address length is input as a memory address length bit string,
The parity address calculation unit
Shifting the division ratio bit string to the left by (mn) bits, which is the difference between the bit number of the memory address length bit string and the bit number of the division ratio bit string,
If the number of bits of the payload is longer than the data length of the parity data, the payload address is shifted to the right by the number of bits corresponding to the value of the payload / parity ratio, and the number of bits of the payload is the data of the parity data. If shorter than the length, the payload address is shifted leftward by the number of bits corresponding to the value of the payload / parity ratio,
The memory control device according to claim 1, wherein the parity address is calculated by adding the shifted division ratio bit string and the shifted payload address. The memory control device further includes:
Inquires about the memory address of the payload and the memory address of the parity data, and based on the memory address notified in response to the inquiry, at least reading of the payload and parity data from the memory device and writing of the payload and parity data to the memory device A sequence controller that performs one of the following:
When the inquiry from the sequence control unit is input, and when there is an inquiry about the memory address of the payload from the sequence control unit, the payload address input by the payload address input unit is notified to the sequence control unit, and the sequence An address notifying unit for notifying the sequence control unit of a parity address calculated by the parity address calculating unit when an inquiry about a memory address of parity data is received from the control unit. 3. The memory control device according to 2.

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