JP2013029926A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To normally operate a semiconductor device even if the semiconductor device is erroneously entered into a test mode.SOLUTION: A semiconductor device comprises a test signal generation circuit 1 in which, in response to inputting a test mode entry signal that starts a test to a test circuit 2 for testing an internal circuit, an internal latch 10 is set to output from the latch 10 to the test circuit 2 a test enable signal permitting the test circuit 2 to be driven. The test signal generation circuit 1 includes a reset signal generation circuit 30 and a delay initialization circuit 40. In the case where the latch 10 is outputting the test enable signal, the reset signal generation circuit 30 delays the test enable signal to generate a reset signal for resetting the latch 10. In the case where the latch 10 is outputting the delay initialization signal, on the basis of a toggle signal supplied from the outside, the delay initialization circuit 40 outputs a delay initialization signal for initializing an operation to generate the reset signal by the reset signal generation circuit 30.

Description

  The present invention relates to a semiconductor device.

  A semiconductor device including a test signal generation circuit for entering a test mode is known (see, for example, Patent Document 1). Such a semiconductor device enters the test mode by the test signal generation circuit and shifts to a test state in which the test circuit corresponding to the test mode is operated. In such a semiconductor device, when the power is turned on, depending on the state when the power is turned on, the test mode may be erroneously entered and the test circuit may shift to the test state. A power-on reset circuit described in Patent Document 1 is known as a circuit for controlling entry to the test mode so that the test mode is not entered by mistake when the power is turned on.

Japanese Patent Laid-Open No. 5-233099

By the way, even if the semiconductor device as described above includes a power-on reset circuit, the semiconductor device may be erroneously entered into the test mode depending on the power supply waveform when the power is turned on. Therefore, the semiconductor device as described above needs to cancel (reset) the test mode using a test command or the like after the semiconductor device is started in order to reliably cancel (reset) the test mode.
However, if the semiconductor device as described above is erroneously entered into the test mode in normal use without using the test command, the test mode may not be released and may not operate normally. For example, consider a case where the semiconductor device as described above has a test mode in which the output terminal is in a Low-Z (low impedance) state, and is erroneously entered in this test mode. In this case, the semiconductor device as described above executes a test mode that is not intended by the user, and the output terminal is in the Low-Z state even when it is correctly in the Hi-Z state. There are things that cannot be done.

  Thus, in the semiconductor device as described above, there is a problem that it is difficult to operate normally if the test mode is erroneously entered.

  The present invention sets the internal latch in response to the input of the test mode entry signal for starting the test to the test circuit for testing the internal circuit, thereby allowing the test circuit to A test signal generation circuit for outputting a test enable signal for permitting driving from the latch, and the test signal generation circuit delays the test enable signal when the latch outputs the test enable signal; A reset signal generation circuit for generating a reset signal for resetting the latch; and, when the latch outputs the test enable signal, the reset by the reset signal generation circuit based on a toggle signal supplied from the outside Delay initial that outputs a delay initialization signal that initializes the signal generation operation Is a semiconductor device characterized in that it comprises a circuit.

  According to the present invention, in the semiconductor device, when the latch outputs the test enable signal, the reset signal generation circuit delays the test enable signal and generates a reset signal for resetting the latch. Further, the delay initialization circuit initializes the operation of generating the reset signal by the reset signal generation circuit based on the toggle signal supplied from the outside when the latch outputs the test enable signal. Output a signal. Thereby, even if the semiconductor device is erroneously entered into the test mode, the reset signal generated by delaying the test enable signal resets the latch in the period when the toggle signal is not supplied. Therefore, even if the semiconductor device is erroneously entered into the test mode, it can operate normally.

1 is a block diagram illustrating a semiconductor device according to an embodiment. 2 is a block diagram showing a test signal generation circuit and a test circuit 2 according to the present embodiment. FIG. It is a block diagram which shows the Delay circuit in this embodiment. 6 is a time chart illustrating an example of the operation of the semiconductor device according to the present embodiment. 6 is a time chart showing an operation of the test signal generation circuit in the present embodiment when the power is turned on. 6 is a time chart showing an operation in a test mode of the test signal generation circuit in the present embodiment. It is a time chart which shows operation | movement of the entry signal generation circuit in this embodiment.

Hereinafter, a semiconductor device 100 according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic block diagram showing the semiconductor device 100 according to the present embodiment.
An example in which the semiconductor device 100 is an SDRAM (Synchronous Dynamic Random Access Memory) that operates in synchronization with a clock signal supplied from the outside will be described.

  In FIG. 1, a semiconductor device 100 includes a command input circuit 81, a command decoder 82, an address input circuit 83, an address latch circuit 84, a mode register 85, a column system control circuit 86, a row system control circuit 87, a row decoder 88, and a column decoder. 89, a memory cell array 90, a sense circuit 91, a data amplifier 92, a clock input circuit 93, a DLL circuit 94, a data input / output circuit 110, a test signal generation circuit 1, and a test circuit 2.

  The semiconductor device 100 also includes clock terminals 71a and 71b, a clock enable terminal 71c, command terminals 72a to 72d, an address terminal 73, and a data input / output terminal 74 as external terminals (pads on the semiconductor chip). In addition, a power supply terminal, a data strobe terminal, a reset terminal, and the like are also provided, but these are not shown.

The clock terminals 71 a and 71 b are terminals to which external clock signals CK and CKN are supplied, respectively. The supplied external clock signals CK and CKN are supplied to the clock input circuit 93. The external clock signal CKN is an inverted signal of the external clock signal CK, and the external clock signals CK and CKN are complementary signals.
The clock input circuit 93 generates a single-phase internal clock signal PreCLK based on the external clock signals CK and CKN, and supplies this to the DLL circuit 94. The DLL circuit 94 generates a phase-controlled internal clock LCLK based on the internal clock signal PreCLK, and supplies it to the data input / output circuit 110.

  The command terminals 72a to 72d are terminals to which a chip select signal CSN, a row address strobe signal RASN, a column address strobe signal CASN, and a write enable signal WEN are supplied, respectively. The command signal CMD is configured by a combination of signals input to these command terminals 72a to 72d. The command signal CMD is input to the command input circuit 81. The command input circuit 81 outputs the supplied command signal CMD to the command decoder 82. The command decoder 82 is a circuit that generates various internal commands ICMD by holding, decoding, and counting command signals. The command decoder 82 supplies the generated internal command ICMD to the column system control circuit 86, the row system control circuit 87, and the mode register 85.

The address terminal 73 is a terminal to which an address signal ADD is supplied and is connected to the address input circuit 83. The address input circuit 83 outputs an address signal ADD supplied to the address terminal 73 to the address latch circuit 84. The address latch circuit 84 supplies the row address of the latched address signal ADD to the row system control circuit 87 and the column address to the column system control circuit 86. If the entry is made in the mode register set, the address latch circuit 84 supplies the address signal ADD to the mode register 85, whereby the contents of the mode register 85 are updated.
The mode register 85 outputs, for example, a request signal MRW # 41 and a request signal MRW # 42, which will be described later, generated based on the address signal ADD and the command signal CMD.

  The row control circuit 87 supplies the row address supplied from the address latch circuit 84 to the row decoder 88. The row decoder 88 is a circuit that selects one of the word lines WL included in the memory cell array 90. In the memory cell array 90, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections (in FIG. 1, one word line WL, one line Only the bit line BL and one memory cell MC are shown). The bit line BL is connected to the corresponding sense amplifier SA in the sense circuit 91.

  The column control circuit 86 supplies the column address supplied from the address latch circuit 84 to the column decoder 89. The column decoder 89 is a circuit that selects any one of the sense amplifiers SA included in the sense circuit 91. The sense amplifier SA selected by the column decoder 89 is connected to the data amplifier 92. The data amplifier 92 further amplifies the read data RD amplified by the sense amplifier SA during the read operation, and supplies the read data RD amplified through the read / write bus RWBS to the data input / output circuit 110. On the other hand, the data amplifier 92 amplifies the write data supplied from the data input / output circuit 110 via the read / write bus RWBS during the write operation, and supplies the amplified write data to the sense amplifier SA.

The data input / output terminal 74 is a terminal for outputting read data and inputting write data, and is connected to the data input / output circuit 110. Here, the input / output signal DQ is a signal input / output at the data input / output terminal 74.
Although only one data input / output terminal 74 is shown in FIG. 1, a plurality of data input / output terminals 74 may be provided. Here, an example in which the data input / output terminal 74 inputs / outputs an input / output signal DQ that is a signal having a plurality of bit widths will be described.

  The clock enable terminal 71 c is a terminal to which a clock enable signal CKE is supplied, and the supplied clock enable signal CKE is supplied to the test circuit 2 and the data input / output circuit 110. The clock enable signal CKE is a signal that determines whether the clock is valid or invalid with respect to the input / output signal DQ.

The data input / output circuit 110 is a circuit that controls the input / output signal DQ, and includes an output circuit 111 and an input circuit 112.
The output circuit 111 outputs the read data RD supplied from the data amplifier 92 to the data input / output terminal 74, or sets the data input / output terminal 74 to the Hi-Z state (high impedance state). The output circuit 111 puts the data input / output terminal 74 in a Low-Z (low impedance) state in the CA training test mode. The CA training test mode will be described later in detail.
The input circuit 112 takes in write data to be written to the memory cell array 90 from the outside via the data input / output terminal 74.

The test signal generation circuit 1 is supplied with the request signal MRW # 41 from the mode register 85, for example, when starting a CA training test. The test signal generation circuit 1 outputs a test enable signal TSTEN indicating that the driving of the test circuit 2 is permitted to the test circuit 2 based on the request signal MRW # 41 supplied from the mode register 85.
The test signal generation circuit 1 is supplied with the request signal MRW # 42 from the mode register 85, for example, when the CA training test is completed. The test signal generation circuit 1 stops the output of the test enable signal TSTEN based on the request signal MRW # 42 supplied from the mode register 85. Here, the test enable signal TSTEN becomes, for example, L level (low level) when the drive of the test circuit 2 is permitted, and becomes H level (high level) when the drive of the test circuit 2 is prohibited. Further, the request signal MRW # 41 and the request signal MRW # 42 are valid when they are at the H level, and are invalid when they are at the L level.
That is, for example, when the request signal MRW # 41 becomes H level, the test signal generation circuit 1 causes the test enable signal TSTEN to transition from H level to L level. For example, when the request signal MRW # 42 becomes H level, the test signal generation circuit 1 changes the test enable signal TSTEN from L level to H level.

  Further, the test signal generation circuit 1 determines that the test enable signal TSTEN is at the L level and the chip select signal CSN (toggle signal) input from the outside is not toggled for a preset period (first period). The test enable signal TSTEN is changed from L level to H level. The details of the test signal generation circuit 1 will be described later with reference to FIG.

  The test circuit 2 is a test circuit for performing a CA training test. The test circuit 2 sets the output of the output circuit 111 to the Hi-Z state or the Low-Z state based on the test enable signal TSTEN output from the test signal generation circuit 1 and the clock enable signal CKE input from the outside. Control. That is, the test circuit 2 generates a signal ODIS (Output Disable signal) based on the test enable signal TSTEN and the clock enable signal CKE, and supplies the generated signal ODIS to the output circuit 111. The details of the test signal generation circuit 1 will be described later with reference to FIG.

Next, detailed configurations of the test signal generation circuit 1 and the test circuit 2 will be described.
FIG. 2 is a block diagram showing the test signal generation circuit 1 and the test circuit 2.
In this figure, the test signal generation circuit 1 includes a latch 10, a reset signal generation circuit 30, a delay initialization circuit 40, an entry signal generation circuit 50, and a release signal generation circuit 60.

  The entry signal generation circuit 50 generates a pulse signal based on the request signal MRW # 41 that starts the test supplied from the mode register 85, and outputs the generated pulse signal to the latch 10 as a test mode entry signal. That is, the entry signal generation circuit 50 performs an AND operation on the request signal MRW # 41 and a signal obtained by logically inverting the request signal MRW # 41 for starting the test by delaying a predetermined period (second period). To generate a pulse signal and output the generated pulse signal as a test mode entry signal. The entry signal generation circuit 50 includes inverter circuits 51 to 53 and 55 and a NAND circuit (negative AND operation circuit) 54.

  Each of the inverter circuits 51 to 53 is a logic inverting circuit that outputs a signal obtained by logically inverting the signal input to the input terminal. These inverter circuits 51 to 53 are connected in series. Inverter circuits 51-53 each output an output signal with a predetermined delay time with respect to the signal input to the input terminal. Here, the inverter circuit 51 has an input terminal connected to the signal line of the request signal MRW # 41, and the inverter circuit 53 has an output terminal connected to the node N1. The inverter circuit 53 outputs a delayed signal obtained by logically inverting the request signal MRW # 41 after being delayed for a preset period (second period). Here, the delay of the preset period corresponds to the total delay amount by the inverter circuits 51 to 53.

  The NAND circuit 54 is a NAND operation circuit, and one input terminal is connected to the node N1, and the other input terminal is connected to the signal line of the request signal MRW # 41. The inverter circuit 55 is a logic inversion circuit, and an output terminal is connected to the node N2. In the NAND circuit 54 and the inverter circuit 55, the output terminal of the NAND circuit 54 is connected to the input terminal of the inverter circuit 55, and functions as an AND operation circuit. The NAND circuit 54 and the inverter circuit 55 generate a pulse signal by the logical product operation of the delay signal output from the inverter circuit 53 and the request signal MRW # 41, and output the generated pulse signal as a test mode entry signal. To do. Here, the inverter circuit 55 outputs a pulse signal having a pulse width corresponding to the delay of the above-described preset period (second period) generated by the inverter circuits 51 to 53. For example, the pulse signal is set to the H level during the pulse width corresponding to the delay of the preset period described above.

  The cancellation signal generation circuit 60 generates a pulse signal based on the request signal MRW # 42 for starting the test supplied from the mode register 85, and outputs the generated pulse signal to the latch 10 as a test mode cancellation signal. That is, the release signal generation circuit 60 performs an AND operation on the request signal MRW # 42 and a signal obtained by logically inverting the request signal MRW # 42 for ending the test by delaying a predetermined period (third period). To generate a pulse signal and output the generated pulse signal as a test mode release signal. The release signal generation circuit 60 includes inverter circuits 61 to 63 and 65 and a NAND circuit 64.

  Each of the inverter circuits 61 to 63 is a logic inversion circuit that outputs a signal obtained by logically inverting the signal input to the input terminal. These inverter circuits 61 to 63 are connected in series. Further, the inverter circuits 61 to 63 each output an output signal with a predetermined delay time with respect to the signal input to the input terminal. Here, the inverter circuit 61 has an input terminal connected to the signal line of the request signal MRW # 42, and the inverter circuit 63 has an output terminal connected to the node N3. Inverter circuit 63 outputs a delayed signal obtained by logically inverting the request signal MRW # 42 after being delayed for a preset period (third period). Here, the delay of the preset period corresponds to the total delay amount by the inverter circuits 61 to 63.

  The NAND circuit 64 is a NAND operation circuit, and one input terminal is connected to the node N3 and the other input terminal is connected to the signal line of the request signal MRW # 42. The inverter circuit 65 is a logic inversion circuit, and an output terminal is connected to the node N4. In the NAND circuit 64 and the inverter circuit 65, the output terminal of the NAND circuit 64 is connected to the input terminal of the inverter circuit 65, and functions as an AND operation circuit. The NAND circuit 64 and the inverter circuit 65 perform a logical product operation of the delay signal output from the inverter circuit 63 and the request signal MRW # 42, and generate a pulse signal as a test mode release signal. Here, the inverter circuit 65 outputs a pulse signal having a pulse width corresponding to the delay of the above-described preset period (third period) generated by the inverter circuits 61 to 63. For example, the pulse signal is set to the H level during the pulse width corresponding to the delay of the preset period described above.

The latch 10 is set by a test mode entry signal output from the entry signal generation circuit 50 or a delay initialization signal DLYINIT output from a delay initialization circuit 40 described later. The latch 10 is reset (released) by a test mode release signal output from the release signal generation circuit 60 or a reset signal output from a reset signal generation circuit 30 described later. Here, in the latch 10, “set” means that the test enable signal TSTEN is set to L level, and “reset” (release) means that the test enable signal TSTEN is set to H level.
The latch 10 includes NOR circuits (NOR operation circuits) 11 and 12.

  The NOR circuits 11 and 12 are, for example, a three-input NAND circuit, and each output terminal functions as an SR (Set-Reset) latch connected to one of the input terminals of each other. To do. The NOR circuit 11 has two input terminals of the three inputs connected to the node N2 and the node N8, respectively, and an output terminal connected to the node N5 and the input terminal of the NOR circuit 12. In the NOR circuit 12, two of the three inputs are connected to a node N 4 and an output signal line of a reset signal generation circuit 30 described later, and an output terminal is connected to an input terminal of the NOR circuit 11. . The NOR circuit 11 outputs a test enable signal TSTEN to the test circuit 2.

When the latch 10 outputs the test enable signal TSTEN, the reset signal generation circuit 30 delays the test enable signal TSTEN and generates a reset signal TRST that resets the latch 10. That is, when the test enable signal TSTEN is at the L level, the reset signal generation circuit 30 generates the reset signal TRST that is logically inverted by delaying the test enable signal TSTEN for a preset period (first period). . The reset signal generation circuit 30 outputs the generated reset signal TRST to the latch 10. Here, when the reset signal TRST becomes H level, the latch 10 is reset.
The reset signal generation circuit 30 initializes an operation for generating the reset signal TRST based on a delay initialization signal DLYINIT output from a delay initialization circuit 40 described later. For example, the reset signal generation circuit 30 initializes the operation of generating the reset signal TRST when the delay initialization signal DLYINIT becomes H level. That is, the reset signal generation circuit 30 is reset when the test enable signal TSTEN becomes L level and when the delay initialization signal DLYINIT is maintained at L level for a preset period (first period). Signal TRST is set to H level.
The reset signal generation circuit 30 includes a delay circuit 31 and an inverter circuit 32.

The Delay circuit 31 is a delay circuit having a delay initialization function based on the delay initialization signal DLYINIT. The delay circuit 31 outputs a signal obtained by delaying the test enable signal TSTEN for a preset period (first period) when the test enable signal TSTEN is at the L level. Details of the delay circuit 31 will be described later with reference to FIG.
The inverter circuit 32 logically inverts the signal output from the delay circuit 31 and outputs the inverted signal to the NOR circuit 12 of the latch 10 as the reset signal TRST.

When the latch 10 outputs the test enable signal TSTEN, the delay initialization circuit 40 generates the reset signal TRST by the reset signal generation circuit 30 based on the toggle signal (chip select signal CSN) supplied from the outside. A delay initialization signal DLYINIT for initializing the operation to be performed is output. That is, when the test enable signal TSTEN is at L level, the delay initialization circuit 40 sets the delay initialization signal DLYINIT to H level based on the chip select signal CSN. The delay initialization signal DLYINIT is output to the delay circuit 31 of the reset signal generation circuit 30 via the node N8.
The delay initialization circuit 40 includes inverter circuits 42 to 44, 46, a NAND circuit 45, and a NOR circuit 41.

The NOR circuit 41 has two input terminals connected to the signal line of the chip select signal CSN and the node N5, respectively, and an output terminal connected to the node N6. The NOR circuit 41 outputs a signal obtained by performing a NOR operation on the chip select signal CSN supplied from the command terminal 72a and the test enable signal TSTEN.
The inverter circuits 42 to 44 and 46 and the NAND circuit 45 are the same circuits as the entry signal generation circuit 50 and the release signal generation circuit 60 described above. The inverter circuits 42 to 44 are connected in series, the input terminal of the inverter circuit 42 is connected to the node N6, and the output terminal of the inverter circuit 44 is connected to the node N7. The inverter circuit 44 outputs a delayed signal obtained by logically inverting the output signal of the NOR circuit 41 after being delayed for a preset period (fourth period). Here, the delay of the preset period corresponds to the total delay amount by the inverter circuits 42 to 44.

NAND circuit 45 has an output terminal connected to the input terminal of inverter circuit 46, and inverter circuit 65 has an output terminal connected to node N8.
The NAND circuit 45 and the inverter circuit 46 perform an AND operation on the signal output from the inverter circuit 44 and the output signal of the NOR circuit 41, and generate a pulse signal as a delay initialization signal DLYINIT. Here, the inverter circuit 46 outputs a pulse signal having a pulse width corresponding to the delay of the above-described preset period (fourth period) generated by the inverter circuits 42 to 44. Note that this pulse signal is set to the H level by, for example, the toggle of the chip select signal CSN (toggle signal) for a pulse width corresponding to the delay of the preset period described above.

  That is, the delay initialization circuit 40 performs a negative OR operation between the chip select signal CSN (toggle signal) and the test enable signal TSTEN. The delay initialization circuit 40 includes a signal generated by the negative OR operation and a signal obtained by logically inverting the signal generated by the negative OR operation by delaying a predetermined period (fourth period). A pulse signal is generated by a logical product operation, and the generated pulse signal is output as a delay initialization signal.

  As described above, when the test mode entry signal for starting the test is input to the test circuit 2 for testing the internal circuit, the test signal generation circuit 1 sets the internal latch 10 by the test mode entry signal. The test signal generation circuit 1 outputs from the latch 10 a test enable signal TSTEN indicating that the test circuit 2 is permitted to drive the test circuit 2. In other words, the test signal generation circuit 1 sets the internal latch 10 in response to the input of the test mode entry signal for starting the test to the test circuit 2 that tests the internal circuit, whereby the test circuit 2 On the other hand, a test enable signal permitting driving of the test circuit 2 is output from the latch 10.

The test circuit 2 is activated (driven) when executing the CA training test, and controls the output signal Dout of the output circuit 111 to the Low-Z state when the test enable signal TSTEN is at the L level. To do. Here, the output signal Dout is an output signal in the input / output signal DQ.
For example, when the test enable signal TSTEN becomes the L level (in the case of the CA training test mode), the test circuit 2 sets the signal ODIS to the L level. Further, the test circuit 2 sets the signal ODIS to the H level or the L level according to the logic level of the clock enable signal CKE when the test enable signal TSTEN becomes the H level (in the normal operation). In this case, for example, the test circuit 2 sets the signal ODIS to the H level when the clock enable signal CKE becomes the L level, and sets the signal ODIS to the L level when the clock enable signal CKE becomes the H level. .

The output circuit 111 sets the output signal Dout to the Hi-Z state when the signal ODIS becomes the H level, and sets the output signal Dout to the Low-Z state when the signal ODIS becomes the L level.
The test circuit 2 includes inverter circuits 21 and 23 and a NAND circuit 22.

The inverter circuit 21 has an input terminal connected to the signal line of the clock enable signal CKE and an output terminal connected to one input terminal of the NAND circuit 22.
The other input terminal of the NAND circuit 22 is connected to the node N5 which is a signal line of the test enable signal TSTEN, and the output terminal is connected to the input terminal of the inverter circuit 23. The NAND circuit 22 and the inverter circuit 23 function as an AND operation circuit, and the output of the inverter circuit 23 is supplied to the output circuit 111 as a signal ODIS.

Next, a detailed configuration of the above-described delay circuit 31 will be described.
FIG. 3 is a block diagram showing an example of the configuration of the delay circuit 31 in the present embodiment.
In this figure, the delay circuit 31 includes a delay circuit unit 70, a switch unit 80, and an inverter circuit 316.

  The delay circuit unit 70 delays the test enable signal TSTEN for a preset period (first period). For example, the delay circuit unit 70 logically inverts the test enable signal TSTEN and delays it for a preset period (first period). The delay circuit unit 70 outputs an output voltage to be output to the output signal so as to reach a predetermined threshold voltage (threshold voltage Vth) from the initial voltage over a preset period (first period DLY1). Change. In the present embodiment, the delay circuit unit 70 includes P-type channel metal oxide semiconductor field effect transistors (PMOS transistors) 312 and 313 and N-type channel metal oxide semiconductor field effect transistors (NMOS transistors) 314. The PMOS transistor 312 has a source terminal connected to the node N9, a gate terminal connected to the node N5, and a drain terminal connected to the node N10. The PMOS transistor 313 has a source terminal connected to the node N10, a gate terminal connected to the node N5, and a drain terminal connected to the node N11.

  The PMOS transistors 312 and 313 are connected in series, and become conductive when the test enable signal TSTEN becomes L level. The PMOS transistors 312 and 313 are turned off when the test enable signal TSTEN becomes H level.

  The PMOS transistors 312 and 313 supply current to the node N11 when the test enable signal TSTEN and the delay initialization signal DLYINIT are both at the L level. Here, when supplying current to the node N11, the PMOS transistors 312 and 313 generate gate delay (channel length) which is a transistor constant so as to generate the delay of the preset period (first period) described above. ) L and gate width (channel width) W are set. That is, the PMOS transistors 312 and 313 have a wider gate length (channel length) L and a wider gate width (channel length) than a normal transistor so as to generate the delay of the preset period (first period) described above. The channel width (W) is set narrow.

  Thus, the PMOS transistors 312 and 313 limit the current supplied to the node N11 when the test enable signal TSTEN becomes L level. Therefore, the voltage of the node N11 is equal to the threshold voltage (threshold voltage Vth) of the inverter circuit 316 over the preset period (first period) described above when the test enable signal TSTEN becomes L level. To reach.

  The NMOS transistor 314 has a source terminal connected to the ground power supply line, a gate terminal connected to the node N5, and a drain terminal connected to the node N11. Thereby, the NMOS transistor 314 becomes non-conductive when the test enable signal TSTEN becomes L level, and becomes conductive when the test enable signal TSTEN becomes H level. That is, the NMOS transistor 314 sets the voltage of the node N11 to L level when the test enable signal TSTEN becomes H level.

The switch unit 80 initializes the output of the delay circuit unit 70 based on the delay initialization signal DLYINIT output from the delay initialization circuit 40. That is, the switch unit 80 returns the output voltage of the delay circuit unit 70 to the initial voltage (the potential of the ground power supply line) based on the delay initialization signal DLYINIT output from the delay initialization circuit 40. Here, to initialize the output of the delay circuit unit 70 is to set the output of the delay circuit unit 70 to the potential of the ground power supply line. That is, the switch unit 80 sets the voltage at the node N11 to L level when the delay initialization signal DLYINIT becomes H level. Further, the switch unit 80 supplies current from the drive voltage power supply line to the PMOS transistors 312 and 313 of the delay circuit unit 70 when the delay initialization signal DLYINIT becomes L level.
The switch unit 80 includes a PMOS transistor 311 and an NMOS transistor 315.

The PMOS transistor 311 has a source terminal connected to the drive voltage power supply line, a gate terminal connected to the node N8 which is a signal line of the delayed initialization signal DLYINIT, and a drain terminal connected to the node N9. The PMOS transistor 311 becomes conductive when the delay initialization signal DLYINIT becomes L level, and becomes non-conductive when the delay initialization signal DLYINIT becomes H level.
The NMOS transistor 315 has a source terminal connected to the ground power supply line, a gate terminal connected to the node N8 which is a signal line of the delay initialization signal DLYINIT, and a drain terminal connected to the node N11. The NMOS transistor 315 becomes non-conductive when the delay initialization signal DLYINIT becomes L level, and becomes conductive when the delay initialization signal DLYINIT becomes H level. Thus, when the delay initialization signal DLYINIT becomes H level, the NMOS transistor 315 sets the voltage of the node N11 to L level and initializes the output of the delay circuit unit 70.

  The inverter circuit 316 has an input terminal connected to the node N11 and an output terminal connected to the input terminal of the inverter circuit 31. The inverter circuit 316 outputs a signal obtained by logically inverting the output signal of the delay circuit unit 70 to the inverter circuit 32 based on the threshold voltage (threshold voltage Vth) described above.

Next, the operation of the semiconductor device 100 in this embodiment will be described.
As an example, an outline of an operation when the semiconductor device 100 executes a CA training test will be described.

FIG. 4 is a time chart showing the operation of the CA training test of the semiconductor device 100 in this embodiment.
In this figure, the vertical axis indicates, in order from the top, the clock signal CK, the signal CA indicating a part of the address signal ADD, the chip select signal CSN, the clock enable signal CKE, the even bit signal (EvenDQ) of the input / output signal DQ, and the odd number. A bit signal (OddDQ) is shown. The horizontal axis indicates time t.

  First, when the CA training test is executed, the semiconductor device 100 receives the command signal CMD for entering the test mode from the outside, and transitions from the normal operation mode to the CA training test mode. Here, the normal operation mode is an operation mode in normal use that does not use the test mode.

At time T1, the semiconductor device 100 receives a command signal CMD for entering the CA training test mode from the outside. Here, “MRW # 41” is input to signal CA, and chip select signal CSN is set to L level.
As a result, the signal corresponding to “MRW # 41” in the mode register 85 is updated, and the mode register 85 supplies the test signal generation circuit 1 with the request signal MRW # 41 for starting the CA training test.
The test signal generation circuit 1 sets an internal latch by a test mode entry signal generated based on the request signal MRW # 41 and outputs a test enable signal TSTEN to the test circuit 2. Accordingly, the test circuit 2 sets the signal ODIS to the L level and controls the input / output signal DQ, which is the output of the output circuit 111, to the Low-Z state.

  Next, when the clock enable signal CKE and the chip select signal CSN are input to the L level and data is input to the signal CA, the semiconductor device 100 inputs the data corresponding to the input data in the Low-Z state. Output to output signal DQ (EvenDQ, OddDQ). Thereby, the CA training test is executed on the semiconductor device 100.

For example, when data “CAxR” and “CAxR #” are input to the signal CA at times T2 and T3, the semiconductor device 100 outputs the data “CAxR” and “CAxR #” to the input / output signals at time T4. Output to EvenDQ and OddDQ.
For example, when data “CAyR” and “CAyR #” are input to the signal CA at times T5 and T6, the semiconductor device 100 inputs the data “CAyR” and “CAyR #” at time T7. Output to the output signals EvenDQ and OddDQ.

  Next, when the CA training test is finished, the semiconductor device 100 receives a command signal CMD for canceling the test mode from the outside, and transitions from the CA training test mode to the normal operation mode.

At time T8, semiconductor device 100 receives externally a command signal CMD for canceling the CA training test mode. Here, “MRW # 42” is input to signal CA, and chip select signal CSN is set to L level.
As a result, the signal corresponding to “MRW # 42” in the mode register 85 is updated, and the mode register 85 supplies the test signal generation circuit 1 with a request signal MRW # 42 for ending the CA training test.
The test signal generation circuit 1 resets the internal latch by the test mode entry signal generated based on the request signal MRW # 42, and cancels the CA training test mode. Thereby, the semiconductor device 100 sets the input / output signals EvenDQ and OddDQ to the Hi-Z state (here, don't care) at time T9.

Next, the operation of the test signal generation circuit 1 in this embodiment will be described.
FIG. 5 is a time chart showing the operation of the test signal generation circuit 1 according to this embodiment when the power is turned on. Here, an example will be described in which, when the power is turned on, the CA training test mode is erroneously entered.
In this figure, the vertical axis indicates the power supply voltage Power, the clock enable signal CKE, the chip select signal CSN, the signal CA, the test enable signal TSTEN, the delay initialization signal DLYINIT, and the node N11 in the delay circuit 31 in order from the top. A signal, a reset signal TRST, a signal ODIS, and an output signal Dout of the output circuit 111 are shown. The horizontal axis indicates time t.

When the power supply voltage Power is supplied to the semiconductor device 100 and it is erroneously entered into the CA training test mode, the internal test enable signal TSTEN of the semiconductor device 100 is in the L level state. That is, in this state (time T11), the latch 10 of the test signal generation circuit 1 outputs the L level to the test enable signal TSTEN. Therefore, the test circuit 2 outputs L level to the signal ODIS, and the output circuit 111 sets the output signal Dout to the Low-Z state.
At time T11, the test signal generation circuit 1 receives the L level as the clock enable signal CKE and the H level as the chip select signal CSN.

  Since the test enable signal TSTEN is at the L level, the delay circuit 31 of the reset signal generation circuit 30 starts generating a delayed signal of the test enable signal TSTEN. As a result, the delay circuit unit 70 of the delay circuit 31 increases the voltage of the node N11.

  Next, at time T12 when the above-described preset period (first period DLY1) has elapsed from time T11, the voltage at the node N11 reaches the threshold voltage Vth of the inverter circuit 316, and the reset signal generation circuit 30 The reset signal TRST is changed from L level to H level.

  Therefore, at time T12, the latch 10 is reset, and the test signal generation circuit 1 changes the test enable signal TSTEN from the L level to the H level. Therefore, the test circuit 2 changes the signal ODIS from the L level to the H level (time T13), and the output circuit 111 sets the output signal Dout to the Hi-Z state (time T14).

As described above, in the semiconductor device 100, the test mode of the CA training that is erroneously entered is automatically canceled, and the test mode is changed to the normal operation mode. That is, after time T13, the semiconductor device 100 operates in the normal operation mode.
For example, when the clock enable signal CKE transitions from the L level to the H level at time T15, the output circuit 111 changes the output signal Dout from the Hi-Z state to the Low-Z state as an operation in the normal operation mode. .

  FIG. 6 is a time chart showing the operation of the test signal generation circuit 1 in the present embodiment in the test mode. Here, as an example of the test mode, an example in the case of entering the CA training test mode will be described.

  In this figure, the vertical axis indicates the power supply voltage Power, the clock enable signal CKE, the chip select signal CSN, the signal CA, the request signal MRW # 41, the test mode entry signal, the test enable signal TSTEN, and the delay initialization in order from the top. The signal DLYINIT, the signal at the node N11 in the delay circuit 31, the reset signal TRST, the signal ODIS, and the output signal Dout of the output circuit 111 are shown. The horizontal axis indicates time t.

  At time T21, the semiconductor device 100 receives the command signal CMD for entering the CA training test mode from the outside. Note that at time T21, the test signal generation circuit 1 receives the H level as the clock enable signal CKE.

Here, “MRW # 41” is input to signal CA, and chip select signal CSN is set to L level. Thereby, mode register 85 outputs request signal MRW # 41 to test signal generation circuit 1. That is, mode register 85 changes request signal MRW # 41 from the L level to the H level. The entry signal generation circuit 50 of the test signal generation circuit 1 generates a pulse signal when the request signal MRW # 41 transitions from L level to H level, and outputs the generated pulse signal to the latch 10 as a test mode entry signal. .
As a result, the latch 10 is set, and the latch 10 changes the test enable signal TSTEN from the H level to the L level. The test circuit 2 maintains the signal ODIS at the L level when the test enable signal TSTEN transitions from the H level to the L level, and the output circuit 111 maintains the output signal Dout in the Low-Z state.

  Further, when the test enable signal TSTEN becomes L level, the delay initialization circuit 40 outputs a pulse signal to the node N8 as the delay initialization signal DLYINIT. As a result, the reset signal generation circuit 30 initializes the delay operation and initializes the output of the delay circuit unit 70. That is, when the delay initialization signal DLYINIT is set to the H level by the pulse signal, the PMOS transistor 311 of the delay circuit 31 is turned off and the NMOS transistor 315 is turned on. As a result, the supply of current to the delay circuit unit 70 is stopped, and the NMOS transistor 315 discharges the charge of the node N11 to the ground power supply line, and initializes the output of the delay circuit unit 70. That is, the NMOS transistor 315 returns the output voltage of the delay circuit unit 70, which is the voltage of the node N11, to the initial voltage (the potential of the ground power supply line).

  Further, when the delay initialization signal DLYINIT is set to L level by the pulse signal, the PMOS transistor 311 of the delay circuit 31 is turned on and the NMOS transistor 315 is turned off. As a result, a current is supplied to the delay circuit unit 70. Here, since the test enable signal TSTEN is at the L level, in the delay circuit unit 70, the PMOS transistors 312 and 313 are in a conductive state and the NMOS transistor 314 is in a non-conductive state. Therefore, the node N11 that is the output of the delay circuit unit 70 is charged by the PMOS transistors 312 and 313, and the voltage rises.

  Next, at time T22, the clock enable signal CKE transitions from the H level to the L level. In this case, since the test enable signal TSTEN in the CA training test mode is at the L level in the semiconductor device 100, the output circuit 111 maintains the output signal Dout in the Low-Z state.

  Next, when the chip select signal CSN transitions from the H level to the L level at time T23, the delay initialization circuit 40 of the test signal generation circuit 1 outputs a pulse signal to the node N8 as the delay initialization signal DLYINIT. . The reset signal generation circuit 30 initializes the delay operation by the delay initialization signal DLYINIT, and initializes the output of the delay circuit unit 70. Thereby, the reset signal generation circuit 30 maintains the reset signal TRST at the L level, and the latch 10 maintains the test enable signal TSTEN at the L level. Since the delay initialization signal DLYINIT is supplied to the latch 10 as a signal for setting the latch 10, the latch 10 is reset based on the delay initialization signal DLYINIT, and the test enable signal TSTEN is maintained at the L level. To do.

  Next, in a state where the chip select signal CSN is at the L level, data “CAxR” and “CAxR #” are input to the signal CA. In this case, the semiconductor device 100 outputs data corresponding to the data “CAxR” and “CAxR #” to the output signal Dout of the output circuit 111 at a time T24 delayed by a period DLY2 from the time T23. The chip select signal CSN transitions from the L level to the H level after the data “CAxR” and “CAxR #” are input to the signal CA. That is, here, the chip select signal CSN is a toggle signal.

  Similarly, when chip select signal CSN transitions from H level to L level at time T25, delay initialization circuit 40 again outputs a pulse signal to node N8 as delay initialization signal DLYINIT. The reset signal generation circuit 30 initializes the delay operation by the delay initialization signal DLYINIT, and initializes the output of the delay circuit unit 70. Thereby, the reset signal generation circuit 30 maintains the reset signal TRST at the L level, and the latch 10 maintains the test enable signal TSTEN at the L level.

  Next, when the chip select signal CSN is not toggled during a preset period (first period DLY1), the voltage at the node N11 reaches the threshold voltage Vth of the inverter circuit 316 at time T26. Thereby, the reset signal generation circuit 30 changes the reset signal TRST from the L level to the H level to reset the latch 10. The test signal generation circuit 1 changes the test enable signal TSTEN from L level to H level. That is, at time T26, the semiconductor device 100 is released from the CA training test mode. Therefore, the test circuit 2 outputs the H level to the signal ODIS, and the output circuit 111 sets the output signal Dout to the Hi-Z state. Here, the period P1 from the time T21 to the time T26 is a period of the CA training test mode.

Next, an operation in which the entry signal generation circuit 50 generates a pulse signal as a test mode entry signal will be described.
FIG. 7 is a time chart showing the operation of the entry signal generation circuit 50 in the present embodiment.
In this figure, the vertical axis indicates, in order from the top, the request signal MRW # 41, the signal at the node N1, and the signal at the node N2 (test mode entry signal). The horizontal axis indicates time t.

  When the request signal MRW # 41 transits from the L level to the H level at time T31, the NAND circuit 54 and the inverter circuit 55 of the entry signal generation circuit 50 AND the request signal MRW # 41 and the signal at the node N1. Calculate. Here, inverter circuit 55 changes the test mode entry signal, which is a signal at node N2, from L level to H level.

Since the inverter circuits 51 to 53 output the output signal with a predetermined delay time delayed with respect to the signals input to the input terminals, the inverter circuit 53 sets the request signal MRW # 41 in advance at time T32. A delayed signal that is logically inverted and delayed for a predetermined period (second period DLY3). That is, inverter circuit 53 causes the signal at node N1 to transition from the H level to the L level at time T32. As a result, the output of NAND circuit 54 is logically inverted, and inverter circuit 55 causes the test mode entry signal, which is a signal at node N2, to transition from the H level to the L level.
In this way, the entry signal generation circuit 50 generates a pulse signal having a pulse width of a preset period (second period DLY3) when the request signal MRW # 41 transitions from the L level to the H level. And output as a test mode entry signal to the node N2.

  The release signal generation circuit 60, the inverter circuits 42 to 44 and 46 of the delay initialization circuit 40, and the NAND circuit 45 have the same circuit configuration as the entry signal generation circuit 50, and the same operation as the entry signal generation circuit 50. Thus, a pulse signal is generated.

  As described above, in the semiconductor device 100 according to the present embodiment, when the test signal generation circuit 1 receives the test mode entry signal that starts the test for the test circuit 2 that tests the internal circuit, The internal latch 10 is set by the entry signal. The test signal generation circuit 1 outputs from the latch 10 a test enable signal TSTEN that allows the test circuit 2 to drive the test circuit 2. The test signal generation circuit 1 includes a reset signal generation circuit 30 and a delay initialization circuit 40. When the latch 10 outputs the test enable signal TSTEN, the reset signal generation circuit 30 delays the test enable signal TSTEN and generates a reset signal TRST that resets the latch 10. When the latch 10 outputs the test enable signal TSTEN, the delay initialization circuit 40 generates the reset signal TRST by the reset signal generation circuit 30 based on the toggle signal (chip select signal CSN) supplied from the outside. A delay initialization signal DLYINIT for initializing the operation to be performed is output.

Thus, even if the semiconductor device 100 is erroneously entered into the test mode, the reset signal TRST generated by delaying the test enable signal TSTEN by the reset signal generation circuit 30 is latched in the period when the toggle signal is not supplied. Reset (cancel). Therefore, even if the semiconductor device 100 is erroneously entered into the test mode, the test mode is automatically reset (released), and thus can operate normally.
In the operation in the test mode, the delay initialization circuit 40 generates the reset signal TRST by the reset signal generation circuit 30 by toggling the chip select signal CSN within a preset period (first period DLY1). Initialize the operation to be generated. Therefore, the semiconductor device 100 can prevent the test mode from being automatically reset (released), and can normally execute the test mode operation.

In the present embodiment, the reset signal generation circuit 30 includes a delay circuit unit 70 and a switch unit 80. The delay circuit unit 70 delays the test enable signal TSTEN for a preset period (first period DLY1), and the switch unit 80 delays based on the delay initialization signal DLYINIT output from the delay initialization circuit 40. The output of the circuit unit 70 is initialized. For example, the delay circuit unit 70 outputs the output signal so as to reach a predetermined threshold voltage (threshold voltage Vth) from the initial voltage over a preset period (first period DLY1). Change the voltage. The switch unit 80 returns the output voltage of the delay circuit unit 70 to the initial voltage based on the delay initialization signal DLYINIT output from the delay initialization circuit 40.
Thereby, for example, the reset signal generation circuit 30 appropriately executes a process of automatically resetting (releasing) the test mode when the chip select signal CSN is not toggled for a preset period (first period DLY1). To do. Further, the reset signal generation circuit 30 appropriately executes the process of continuing the test mode when the chip select signal CSN is toggled within the first period DLY1. That is, the semiconductor device 100 appropriately executes a process for automatically resetting (releasing) the test mode in a normal operation and a process for continuing the test mode in a test operation for executing a test with a simple configuration. Can do.

In this embodiment, the delay initialization circuit 40 outputs a pulse signal generated based on the chip select signal CSN (toggle signal) and the test enable signal TSTEN as the delay initialization signal. That is, the delay initialization circuit 40 performs a negative OR operation between the chip select signal CSN (toggle signal) and the test enable signal TSTEN. The delay initialization circuit 40 includes a signal generated by the negative OR operation and a signal obtained by logically inverting the signal generated by the negative OR operation by delaying a predetermined period (fourth period). A pulse signal is generated by a logical product operation, and the generated pulse signal is output as a delay initialization signal DLYINIT.
As a result, the delay initialization circuit 40 generates the delay initialization signal DLYINIT when the test enable signal TSTEN is output (when it becomes L level), and the test enable signal TSTEN is not output ( The delay initialization signal DLYINIT is not generated when the signal becomes H level. That is, the semiconductor device 100 activates the delay initialization circuit 40 in the test mode and deactivates the delay initialization circuit 40 in the normal operation.
Therefore, the semiconductor device 100 can reduce power consumption by deactivating the delay initialization circuit 40 that is not necessary in normal operation.

In the present embodiment, the delay initialization signal DLYINIT is used as a signal for setting the latch 10. In this case, the semiconductor device 100 can reduce the possibility of being erroneously entered into the test mode by deactivating the delay initialization circuit 40 in a normal operation.
Further, the delay initialization circuit 40 can generate a pulse signal with a simple configuration by using the delay signal.

Further, in the present embodiment, the latch 10 is set by the test mode entry signal or the delay initialization signal DLYINIT, and is reset by the test mode cancel signal for resetting the test circuit 2 or the reset signal TRST.
Since the latch 10 is set by the delay initialization signal DLYINIT, the semiconductor device 100 reliably maintains the test mode by toggling the chip select signal CSN within a preset period (first period DLY1). can do. Further, since the latch 10 is reset by the test mode release signal, the semiconductor device 100 can release the test mode by, for example, an external command process.

In the present embodiment, the test signal generation circuit 1 includes an entry signal generation circuit 50 and a release signal generation circuit 60. The entry signal generation circuit 50 calculates the logic of a signal obtained by logically inverting the request signal MRW # 41 for starting the test by delaying a predetermined period (second period) and the request signal MRW # 41 for starting the test. Perform product operation. Then, the entry signal generation circuit 50 outputs the pulse signal generated by the logical product operation as a test mode entry signal. Further, the release signal generation circuit 60 delays the request signal MRW # 42 for ending the test by a predetermined period (third period) and logically inverts the request signal MRW # 42 for ending the test. Perform the logical AND operation. Then, the release signal generation circuit 60 outputs the pulse signal generated by the logical product operation as a test mode release signal.
Thereby, the test signal generation circuit 1 can generate a pulse signal as a test mode entry signal and a test mode release signal with a simple configuration.

In addition, this invention is not limited to said embodiment, It can change in the range which does not deviate from the meaning of this invention.
In the above embodiment, the test signal generation circuit 1 has been described as entering the test mode of CA training. However, the test signal generating circuit 1 may enter other test modes. Further, the semiconductor device 100 may include a plurality of test signal generation circuits 1 according to the number of test modes.
Further, in the above embodiment, the delay initialization circuit 40, the entry signal generation circuit 50, and the release signal generation circuit 60 generate a pulse signal by the delay of three inverter circuits connected in series. Although described, the present invention is not limited to this. The number of inverter circuits connected in series may be changed according to the pulse width necessary for setting or resetting the latch 10 and the delay amount of the inverter circuit.

In the above embodiment, the semiconductor device 100 is an SDRAM. However, the semiconductor device 100 may be applied to other semiconductor devices.
For example, in general semiconductor devices such as CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), ASSP (Application Specific Standard Product), and memory (Memory), The test signal generation circuit 1 can be applied. Examples of the product form of the semiconductor device to which the present invention is applied include SOC (system on chip), MCP (multichip package), POP (package on package), and the like. The present invention can be applied to a semiconductor device having any of these product forms and package forms.

In the above-described embodiment, the transistor may be a field effect transistor (FET), and in addition to a MOS (Metal Oxide Semiconductor), an MIS (Metal-Insulator Semiconductor), a TFT (Thin Film Transistor), and the like. It can be applied to various FETs. Furthermore, some bipolar transistors may be included in the device.
Further, the NMOS transistor is a typical example of a first conductivity type transistor, and the PMOS transistor is a typical example of a second conductivity type transistor.

  DESCRIPTION OF SYMBOLS 1 ... Test signal generation circuit, 2 ... Test circuit. DESCRIPTION OF SYMBOLS 10 ... Latch, 11, 12, 41 ... NOR circuit 21, 23, 32, 42, 43, 44, 46, 51, 52, 53, 55, 61, 62, 63, 65, 316 ... Inverter circuit, 22, 45, 54, 64 ... NAND circuit, 30 ... reset signal generation circuit, 31 ... Delay circuit, 40 ... delay initialization circuit, 50 ... entry signal generation circuit, 60 ... release signal generation circuit, 70 ... delay circuit unit, 80 ... Switch unit, 71a, 71b ... clock terminal, 71c ... clock enable terminal, 72a, 72b, 72c, 72d ... command terminal, 73 ... address terminal, 74 ... data input / output terminal, 81 ... command input circuit, 82 ... coder with command 83 ... Address input circuit, 84 ... Address latch circuit, 85 ... Mode register, 86 ... Column system control circuit, 87 ... Row system control Circuit: 88 ... Row decoder, 89 ... Column decoder, 90 ... Memory cell array, 91 ... Sense circuit, 92 ... Data amplifier, 93 ... Clock input circuit, 94 ... DLL circuit, 100 ... Semiconductor device, 110 ... I / O circuit, 111 ... Output circuit, 112 ... Input circuit, 311, 312, 313 ... PMOS transistor, 314, 315 ... NMOS transistor

Claims (7)

The test circuit is allowed to drive the test circuit by setting an internal latch in response to the input of the test mode entry signal for starting the test to the test circuit for testing the internal circuit. A test signal generation circuit for outputting a test enable signal from the latch;
The test signal generation circuit includes:
A reset signal generating circuit for generating a reset signal for delaying the test enable signal and resetting the latch when the latch outputs the test enable signal;
When the latch outputs the test enable signal, a delay initialization signal for initializing an operation of generating the reset signal by the reset signal generation circuit is output based on a toggle signal supplied from the outside. A delay initialization circuit;
A semiconductor device comprising: The reset signal generation circuit includes:
A delay circuit unit for delaying the test enable signal for a preset period;
A switch unit that initializes the output of the delay circuit unit based on the delay initialization signal output from the delay initialization circuit;
The semiconductor device according to claim 1, comprising: The delay circuit unit changes an output voltage to be output to an output signal so as to reach a predetermined threshold voltage from an initial voltage over the preset period,
The semiconductor device according to claim 2, wherein the switch unit returns the output voltage to the initial voltage based on the delay initialization signal output from the delay initialization circuit. The delay initialization circuit includes:
The semiconductor device according to claim 3, wherein a pulse signal generated based on the toggle signal and the test enable signal is output as the delay initialization signal. The delay initialization circuit includes:
Logical AND operation of a signal generated by a negative OR operation of the toggle signal and the test enable signal and a signal obtained by logically inverting the signal generated by the negative OR operation by delaying a preset period. 5. The semiconductor device according to claim 4, wherein a pulse signal is generated according to claim 1 and the generated pulse signal is output as the delay initialization signal. The latch is
6. The test mode entry signal or the delay initialization signal is set, and the test circuit is reset by a test mode release signal or the reset signal for ending the test. Semiconductor device. The test signal generation circuit includes:
Entry signal for outputting a pulse signal generated by a logical product operation of a signal obtained by logically inverting a request signal for starting a test by delaying a predetermined period and the request signal for starting the test as the test mode entry signal A generation circuit;
A release signal for outputting a pulse signal generated by a logical product operation of a signal obtained by logically inverting the request signal for ending the test for a predetermined period and a request signal for ending the test as the test mode release signal A generation circuit;
The semiconductor device according to claim 6, comprising:

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