JP2013025539A - Monitoring system and monitoring method for multi-cpu system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a monitoring system and monitoring method of a multi-CPU system for discriminating the classification of a failure.SOLUTION: A monitoring system 1 of a multi-CPU system having a plurality of CPU terminals (CPU1, CPU2, through CPUn+1) connected via a serial bus 2 includes a bus 3 for failure discrimination connected to the plurality of CPU terminals (CPU1, CPU2, through CPUn+1). When any response signal to a first response request signal transmitted from one CPU terminal (CPU1) via the serial bus 2 to the other CPU terminal (CPU2) is not received, a second response request signal is transmitted from one CPU terminal (CPU1) via the bus 3 for failure discrimination to the other CPU terminal (CPU2), and the classification of the failure of the other CPU terminal (CPU2) is discriminated on the basis of the presence/absence of the reception of a response signal to the second response request signal.

Description

  The present invention relates to a monitoring system and a monitoring method for a multi-CPU system.

2. Description of the Related Art Conventionally, for example, in bank online systems, a distributed processing system in which information processing is shared by a plurality of CPU terminals is used for risk distribution and data processing efficiency.
In such a system configuration, if any one of the CPU terminals fails, it causes a functional failure of the entire system. Therefore, it is necessary to monitor the operation of each CPU terminal.

  As this monitoring method, for example, as shown in FIG. 3, there is a method of determining whether or not the state of another CPU terminal is normal by transmitting and receiving signals between the CPU terminals via a serial bus. (For example, refer to Patent Document 1).

Japanese Patent No. 4126849

However, with the above technology, it is possible to determine whether or not a failure has occurred, but it is not possible to specify the type of failure, and whether there is a failure in the communication function of each CPU terminal or a failure has occurred in other parts. It was not possible to determine whether it was.
Therefore, in the above technique, even when a failure occurs in the communication function, the entire CPU is dealt with by resetting the entire CPU.

  An object of the present invention is to provide a monitoring system and a monitoring method for a multi-CPU system that can determine the type of failure in more detail.

  A monitoring system for a multi-CPU system according to the present invention is a monitoring system for a multi-CPU system having a plurality of CPU terminals connected by a serial bus, and includes a failure determination bus connected to the plurality of CPU terminals. And when one CPU terminal does not receive a response signal to the first response request signal transmitted to another CPU terminal via the serial bus, the one CPU terminal via the fault determination bus A second response request signal is transmitted to the other CPU terminal, and a failure type of the other CPU terminal is determined based on whether or not a response signal is received in response to the second response request signal.

  According to a preferred embodiment of the present invention, the serial bus is a synchronous serial interface, and the failure determination bus is an asynchronous serial interface.

  The monitoring method for a multi-CPU system according to the present invention also includes receiving a response signal for a first response request signal transmitted from one CPU terminal to another CPU terminal of a plurality of CPU terminals connected via a serial bus. Determining whether or not a fault has occurred in the other CPU terminal based on the presence or absence of the fault, and a fault determination bus to which the plurality of terminals are connected when it is determined that a fault has occurred in the other CPU terminal. Transmitting a second response request signal from the one CPU terminal to the other CPU terminal via the terminal, and determining a failure type of the other CPU terminal based on whether or not the response signal is received; , Including.

  According to the present invention, it is possible to determine not only the occurrence of a failure but also the type of failure in more detail.

It is a block diagram which shows an example of the monitoring system of the multi CPU system of this invention. It is a figure for demonstrating operation | movement of the monitoring system of the multi CPU system of this invention. It is a block diagram which shows the conventional multi CPU system.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
As shown in FIG. 1, in a monitoring system 1 of a multi-CPU system of the present invention, a plurality of CPU terminals CPU1, CPU2,..., CPUn + 1 are connected via a serial bus 2 and a fault determination bus 3.

The serial bus 2 is an interface for performing serial communication between CPU terminals, and is a synchronous serial bus in the illustrated example.
Each of the CPU terminals CPU1, CPU2,..., CPUn + 1 transmits / receives a signal to / from another CPU terminal via the serial bus 2, and monitors the occurrence of a failure in the other CPU terminal.

  The failure determination bus 3 is an interface used to determine the type of failure when it is determined that a failure has occurred by monitoring whether or not a failure has occurred between CPU terminals via the serial bus 2. Then, it is an asynchronous serial bus.

The operation of the multi-CPU system monitoring system according to the present invention will be described below.
First, one CPU terminal performs serial communication with another CPU terminal via the serial bus 2 and transmits a response request signal to the other CPU terminal. When the response signal is received within a predetermined time, it is determined that the other CPU terminal is normal.
On the other hand, if one CPU terminal does not receive a response signal via the serial bus 2 within a predetermined time, it determines that a failure has occurred in another CPU terminal.

  Specifically, the monitoring CPU terminal transmits a first response request signal to the monitored CPU terminal and starts a timer in synchronization with the transmission. When a response signal is received from the monitored CPU terminal before the time measured by the timer reaches the predetermined monitoring time T1, the CPU terminal determines that the CPU terminal is normal and resets the timer. On the other hand, if a response signal from the monitored CPU terminal is not received even when the measured time of the timer reaches the monitoring time T1, it is determined that a failure has occurred in the CPU terminal, and the timer is reset.

  In this way, when one CPU terminal monitors another CPU terminal via the serial bus 2 and reception of a response signal is confirmed within a predetermined monitoring time, the other CPU terminal Can confirm that it is working properly.

  On the other hand, as shown in FIG. 2, in response to the first response request signal from, for example, the CPU 1 to the CPU 2 by communication via the serial bus 2, no response signal is received within a predetermined monitoring time T1, and the CPU 2 If it is determined that a failure has occurred, a second response request signal is transmitted from the CPU 1 to the CPU 2 via the failure determination bus 3, and T2 within a predetermined monitoring time (even if the same as T1) The presence or absence of a response signal from the CPU 2 is confirmed.

Thus, when a response signal is received from the CPU 2 within a predetermined monitoring time T2 through communication via the failure determination bus 3, it is determined that there is a failure in the communication function of the CPU 2.
In this case, only the communication function of the CPU 2 may be reset. Therefore, the influence on the entire multi-CPU system can be reduced as compared with the case where the entire CPU 2 is reset.

On the other hand, even in communication via the failure determination bus 3, if there is no response signal from the CPU 2 within the predetermined monitoring time T2, it is determined that a failure has occurred in a portion other than the communication function of the CPU 2. .
In this case, the function of the CPU 2 can be restored normally by resetting the entire CPU 2.

  Here, it is preferable that the serial bus 2 and the failure determination bus 3 have different communication methods. In particular, the serial bus 2 is a synchronous serial interface, and the failure determination bus 3 is an asynchronous serial interface. It is preferable.

  This is considered to be a failure depending on the communication method when a failure occurs in the communication function of the CPU terminal. In such a case, by changing the communication method of the failure determination bus, This is because it is possible to avoid the occurrence of a failure due to the same cause in communication via the failure determination bus and to more reliably determine that the failure occurrence location is the communication function.

For example, in the example shown in FIG. 1, since the serial bus 2 is a synchronous serial bus, noise or the like may affect the clock system used for synchronous communication, and jitter may occur.
In such a case, when the failure determination bus 3 is a similar communication system, that is, a synchronous serial bus, the communication with the CPU terminal where the failure has occurred is not successful due to the noise similarly. In this case, there is a possibility of erroneously determining that a failure has occurred in the entire CPU terminal even though a failure has occurred in the communication function.
Therefore, by making the failure determination bus 3 an asynchronous bus, it is possible to avoid the same cause of the failure from affecting the communication via the failure determination bus 3.

As described above, according to the present embodiment, when it is determined that a failure has occurred in the CPU terminal, the CPU terminal that has been determined to have failed by communicating via the failure determination bus. It is possible to determine whether a failure has occurred in the communication function or whether a failure has occurred elsewhere.
Therefore, since only the location where the failure of the CPU terminal has occurred can be reset, the influence of the failure recovery operation on the entire multi-CPU system can be minimized.

  In addition, this invention is not limited to the said embodiment, A various change is possible in the range which does not deviate from the meaning of invention. For example, the failure determination bus is not limited to a serial bus, but may be a parallel bus.

1 Multi-CPU system monitoring system 2 Serial bus 3 Fault determination bus

Claims (3)

A multi-CPU system monitoring system comprising a plurality of CPU terminals connected by a serial bus,
A fault determination bus connected to the plurality of CPU terminals;
When one CPU terminal does not receive a response signal to the first response request signal transmitted to the other CPU terminal via the serial bus, the other CPU terminal via the fault determination bus from the one CPU terminal. A multi-CPU system monitoring system that transmits a second response request signal to the CPU terminal of the CPU and determines the type of failure of the other CPU terminal based on whether or not a response signal is received in response to the second response request signal .   The multi-CPU system monitoring system according to claim 1, wherein the serial bus is a synchronous serial interface, and the failure determination bus is an asynchronous serial interface. Occurrence of a failure in the other CPU terminal based on whether or not a response signal is received in response to the first response request signal transmitted from one CPU terminal to another CPU terminal of a plurality of CPU terminals connected via a serial bus Determining the presence or absence of
When it is determined that a failure has occurred in the other CPU terminal, a second response request signal is sent from the one CPU terminal to the other CPU terminal via a failure determination bus to which the plurality of terminals are connected. Transmitting and determining the type of failure of the other CPU terminal based on whether or not the response signal is received;
A method for monitoring a multi-CPU system, including:

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