JP2013021641A - Transceiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transceiver capable of achieving a low cost communication system.SOLUTION: When a fall edge of a signal on a bus communication path is extracted before a count value reaches an upper limit value (S103: YES), a pulse width is determined from a present count value (period count value corresponding to one period of a clock component included in the signal on the bus communication path) (S105), and a clock having the pulse width is output as a bus clock (S106). On the other hand, when the count value reaches the upper limit value before the fall edge of the signal on the bus communication path is extracted (S104: YES), each time a count value reaches an up-to-date period count value obtained in the past (S112: YES), the pulse width is determined from the present count value (up-to-date period count value obtained in the past) (S113), and a clock having the pulse width is output as an alternative clock (S114).

Description

  The present invention relates to a transceiver capable of receiving a signal encoded using a transmission line code including a clock component via a bus communication line.

Conventionally, as a communication system mounted on a vehicle, one using a bus communication path such as CAN or LIN is known (see Non-Patent Document 1).
In order to perform efficient communication in this type of communication system, it is desirable to synchronize the operations of the transceivers provided in the respective nodes for transmitting and receiving signals via the bus communication path.

  As one of the techniques for realizing such synchronization, any one node transmits a signal encoded using a transmission path code including a clock component to a bus communication path, and the other nodes perform bus communication. By extracting the clock component from the signal on the road and processing (dividing etc.) the free-running clock generated by the own transceiver, a bus clock synchronized with the extracted clock component is generated, and the transceiver is in accordance with the bus clock. Is known to operate.

Michio Sato "In-vehicle network system thorough commentary" CQ Publishing Co., Ltd., issued December 1, 2005

  By the way, in each node, a signal processing unit (CPU or sequencer) that executes communication via a communication path using a transceiver normally operates according to an operation clock generated using an oscillator. That is, it is necessary to provide an oscillator for each node, which is a factor that hinders cost reduction of the communication system.

  In order to solve the above problems, an object of the present invention is to provide a transceiver that can reduce the cost of a communication system.

  In the transceiver of the present invention that achieves the above object, the clock generation means generates a counting clock having a higher frequency than the clock component included in the signal on the bus communication path. Further, the edge extracting means extracts an edge of a signal on the bus communication path, which is an edge of interest generated at a clock component period. Then, the counting means counts an edge interval, which is an interval from the time when the edge of interest is extracted by the edge extraction means until the next edge of interest is extracted, using the counting clock, and the clock generation means By dividing the clock, a bus clock synchronized with the clock component is generated.

  Specifically, the upper limit detection unit detects that the count value by the counting unit has reached a predetermined upper limit value, and the clock generation unit detects that the count value has reached the upper limit value by the upper limit detection unit. If the target edge is extracted by the edge extraction unit before, a bus clock having a period corresponding to the count value of the edge interval up to the target edge is generated.

  In particular, in the transceiver according to claim 1, when the clock generation unit detects that the count value reaches the upper limit value by the upper limit detection unit before the edge extraction unit extracts the target edge. Until the edge of interest is extracted by the edge extraction means, an alternative clock having a period corresponding to the alternative count value as one cycle is generated instead of the bus clock.

  According to such a transceiver according to claim 1, in a situation where a signal including a clock component is supplied via a bus communication path, a node including the transceiver uses the transceiver to change the communication path. It is possible to operate the signal processing unit that executes communication via the bus clock. Even in the situation where the supply of the signal including the clock component is stopped, the signal processing unit can be operated using an alternative clock having a period corresponding to the alternative count value as one cycle. Therefore, in a communication system, it is possible to configure a node that receives a signal including a clock component without using an oscillator for generating an operation clock of the signal processing unit. As a result, the cost of the communication system can be reduced. Can be achieved.

  Here, as described in claim 2, the alternative count value may be a value determined based on the count value of the edge interval to the target edge extracted in the past. In this way, even in a situation where the supply of the signal including the clock component is stopped, an alternative clock having the same cycle as the bus clock before the supply is stopped can be generated.

  On the other hand, in the transceiver according to claim 3, when the clock generation unit detects that the count value reaches the upper limit value by the upper limit detection unit before the edge of interest is extracted by the edge extraction unit, An alternative clock having a period corresponding to the upper limit as one cycle is generated.

  Such a transceiver according to claim 3 can also reduce the cost of the communication system for the same reason as that of the transceiver according to claim 1 described above. In particular, according to the transceiver of the third aspect, since it is not necessary to distinguish between a situation in which a signal including a clock component is supplied and a situation in which the supply is stopped, the processing load can be reduced.

  By the way, in a communication system using the transceiver of the present invention, there are a node that supplies a signal including a clock component and a node that receives the signal. However, it is preferable that the transceivers have the same configuration.

  Therefore, in the transceiver according to claim 4, the clock generation means is configured to be switchable to a plurality of operation modes, and the plurality of operation modes include a clock component based on a clock component included in a signal on the bus communication path. And a second mode in which a clock component synchronized with the reference clock is generated based on a reference clock with higher accuracy than the counting clock.

  According to such a transceiver, in a communication system, it can be used for both a node that supplies a signal including a clock component and a node that receives the signal.

The block diagram which shows schematic structure of a vehicle-mounted communication system. (A) is a structure of the transmission line code | cord | chord used on a bus communication path, (b) is a structure of the flame | frame transmitted / received via a bus communication path, (c) is explanatory drawing which shows the structure of the block data which UART transmits / receives. The block diagram which shows the structure of a master node and a slave node. The flowchart of the process performed with the slave transceiver of 1st Embodiment. The flowchart of the process performed with the slave transceiver of 2nd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
<Overall configuration>
FIG. 1 shows an electronic control device (body ECU) that is mounted on a vehicle and realizes a body-related application, and related devices (lights) that are provided for detecting the state of the vehicle and controlling the state of the vehicle. 1 is a block diagram showing a schematic configuration of a communication system 1 in which nodes 3 including sensors, etc.) are connected to each other via a bus-like communication path (hereinafter referred to as “bus communication path”) 5.

  As shown in FIG. 1, among the nodes 3 constituting the communication system 1, the body system ECU includes a body wiper ECU, a seat ECU, a slide door ECU, a mirror ECU, a back door ECU, a tilt tele (electric steering position adjustment device). ) ECU etc. On the other hand, related equipment includes light SW, wiper SW, light sensor, rain sensor and the like.

<Bus communication path>
The bus communication path 5 is configured such that when a high level signal and a low level signal are simultaneously output from different nodes 3, the signal level on the bus communication path 5 becomes a low level. To achieve bus arbitration.

Here, FIG. 2A is an explanatory diagram showing transmission path codes used in the bus communication path 5.
As shown in FIG. 2A, in the bus communication path 5, a PWM code in which the signal level changes from a low level to a high level in the middle of a bit is used as a transmission path code, which is recessive (corresponding to 1 in this embodiment). ) And a dominant signal (corresponding to 0 in this embodiment) are expressed by two types of duty ratios.

  Specifically, the dominant is set so that the ratio of the low level is longer than the recessive (in this embodiment, the recessive is a 1/3 period of 1 bit and the dominant is a 2/3 period of 1 bit). When the recessive and the dominant collide with each other on the bus communication path 5, the dominant wins the arbitration.

  In the communication system 1, a so-called CSMA / CA access control method is used in which the node 3 that has lost the arbitration immediately stops transmission, and only the node 3 that has won the arbitration continues transmission.

  In the communication system 1, one of the nodes 3 (in this embodiment, the body wiper ECU 3 and hereinafter also referred to as “master 3a”) operates as a clock master. The transceiver 20 of the master 3a continues to output recessive to the bus communication path 5 even when the transmission data TXD is not supplied from the microcomputer 10, so that the node 3 other than the master 3a (hereinafter also referred to as "slave 3b"). A signal including a clock component necessary for reproducing the bus clock BCK is supplied. In the bus communication path 5, a period in which recessive continues for more than a preset allowable bit (11 bits in this embodiment) is called IFS (Inter Frame Space), and a state in which IFS is detected is in an idle state. That's it.

FIG. 2B is an explanatory diagram showing a configuration of a frame used for communication between the nodes 3.
As shown in FIG. 2B, the frame includes a header for designating data permitted to be transmitted and a variable length response for transmitting the data designated by the header.

  Among these, the header is made up of an identifier (ID) of data that is permitted to be transmitted, and is set so that the smaller the ID value, the longer the bus arbitration is won. On the other hand, the response includes at least size information indicating the size of the data (response) and a CRC code for checking the presence / absence of an error in addition to the data.

<Common to all nodes>
In the communication system 1, the master 3a transmits a header to sequentially specify data to be permitted to be transmitted (and thus the slave 3b that is the data transmission source), and the slave 3b that is the data transmission source specified by the header Polling for transmitting a response (data) (hereinafter also referred to as “periodic communication”) and event communication in which the slave 3b autonomously controls communication regardless of an instruction from the master 3a.

Hereinafter, the configurations of the master 3a and the slave 3b will be described with reference to the block diagram shown in FIG.
<Master>
The master 3 a is a microcomputer (microcomputer) 10 as a signal processing unit that executes various processes assigned to the node 3 based on information obtained by communication with other nodes 3 via the bus communication path 5. The transmission data TXD of the NRZ code supplied from the microcomputer 10 is encoded into the transmission data of the PWM code and output to the bus communication path 5, and the reception data of the PWM code fetched from the bus communication path 5 is received as the reception data RXD of the NRZ code. And a transceiver 20 for decoding and supplying to the microcomputer 10.

<< Signal processing section >>
The microcomputer 10 is composed mainly of a CPU, ROM, RAM, IO port, and the like, and further, a UART (Universal Asynchronous Receiver Transmitter) 11 for realizing asynchronous communication (asynchronous) serial communication. An oscillator 12 is provided that generates an internal clock CK that is set to the same speed (20 Kbps in the present embodiment) as the operation speed for operating the microcomputer 10 and the communication speed of the UART 11 and is supplied to the transceiver 20. As the oscillator 12, a high-accuracy one that oscillates at a stable frequency (for example, a crystal oscillator) is used.

Further, the microcomputer 10 is configured to supply a mode signal representing the master mode to the transceiver 20 as the mode signal M / S representing the operation mode of the own node.
Here, FIG. 2C is an explanatory diagram showing a configuration of data TXD and RXD transmitted and received by the UART 11. As shown in the figure, the UART 11 has a 1-bit start bit (low level) indicating the start of data, a stop bit (high level) indicating the end of data, and 8 bits sandwiched between these start bits and stop bits. A total of 10-bit block data composed of bit data is transmitted and received as a unit. However, the 8-bit data as the main part is set so that the LSB (least significant bit) is the head and the MSB (most significant bit) is the end.

  The header constituting the above-mentioned frame (see FIG. 2B) is composed of a single block data, and 7 bits are used as an ID among 8 bits data excluding a start bit and a stop bit. One bit is used as a parity bit. The response is composed of one or a plurality of block data, and size information is set in the first block.

<< Transceiver >>
Returning to FIG. 3, the transceiver 20 includes an oscillation circuit 21, a reproduction circuit 22, a counter 23, and a determination circuit 24.

  The oscillation circuit 21 is a simple circuit including a ring oscillator configured by connecting a plurality of inverters in a ring shape, and generates a counting clock CCK. The count clock CCK is set to have a sufficiently high frequency (several tens to several hundred times) with respect to the frequency of the internal clock CK (the frequency of the clock component included in the signal on the bus communication path 5). Yes.

  Further, the reproduction circuit 22 is switched to one of a master mode that is an operation mode as a clock master and a slave mode that is an operation mode as a slave in accordance with a mode signal M / S supplied from the microcomputer 10. . In the transceiver 20 mounted on the master 3a, the reproduction circuit 22 is switched to the master mode. Then, the reproduction circuit 22 in the master mode extracts the falling edge of the internal clock CK supplied from the microcomputer 10.

  The counter 23 determines the edge interval, which is an interval (one cycle of the clock component) from the time when the reproducing circuit 22 extracts the falling edge of the internal clock CK to the time when the next falling edge is extracted. Use to count.

  The determination circuit 24 determines whether or not the supply of the signal including the clock component from the master 3a is stopped by determining whether or not the count value by the counter 23 has reached a preset upper limit value. .

  The reproduction circuit 22 in the master mode synchronizes with the internal clock CK supplied from the microcomputer 10 by dividing the count clock CCK generated by the oscillation circuit 21 based on the count value obtained by the counter 23. Generated timing signals. In the reproduction circuit 22, the transmission data TXD is encoded according to the generated timing signal, and a signal including a clock component synchronized with the internal clock CK is supplied to the bus communication path 5.

<Slave>
The slave 3b includes a sequencer 30 as a signal processing unit that executes various processes assigned to the node 3 based on information obtained by communication with the other node 3 via the bus communication path 5, and the sequencer 30. A transceiver 20 is provided that outputs transmission data obtained by encoding supplied transmission data TXD with a PWM code to the bus communication path 5 and supplies received data RXD received on the bus communication path 5 to the sequencer 30. . The transceiver 20 of the slave 3b has the same configuration as that used for the master 3a.

<< Signal processing section >>
The sequencer 30 has a function corresponding to the UART 11 and the like, and the basic function is the same as that of the microcomputer 10, but does not have an oscillator for generating an operation clock, and operates with a clock supplied from the transceiver 20. . Further, the sequencer 30 is configured to supply a mode signal representing the slave mode to the transceiver 20 as the mode signal M / S representing the operation mode of the own node.

<< Transceiver >>
The transceiver 20 has the same configuration as that used for the master 3a. However, in the transceiver 20 mounted on the slave 3b, the reproduction circuit 22 is switched to the slave mode. Then, the reproduction circuit 22 in the slave mode extracts a falling edge that is an edge of a signal on the bus communication path 5 and is generated at a cycle of the clock component.

  Therefore, the counter 23 is an edge interval that is an interval (the length of one cycle) from when the reproducing circuit 22 extracts the falling edge of the signal on the bus communication path 5 until the next falling edge is extracted. Are counted using the count clock CCK.

  Then, the slave mode reproduction circuit 22 divides the count clock CCK generated by the oscillation circuit 21 based on the count value obtained by the counter 23 to thereby generate a clock included in the signal on the bus communication path 5. A bus clock BCK synchronized with the component is generated.

That is, in the slave mode, the signal to be synchronized is not the internal clock CK but the clock component included in the signal on the bus communication path 5.
As described above, the transceiver 20 of the slave 3b extracts the falling edge that is the bit boundary of the received data of the PWM code fetched from the bus communication path 5 as the clock component, and generates the bus clock BCK synchronized with the clock component. The transmission data TXD is encoded and the reception data RX is decoded according to the bus clock BCK, thereby realizing communication via the bus communication path 5.

<< Transceiver processing >>
Next, processing repeatedly executed by the transceiver 20 of the slave 3b will be described using the flowchart of FIG.

  First, the counter 23 resets the count value (S101), and starts counting using the count clock CCK (S102). Thereafter, while the reproduction circuit 22 does not extract the falling edge of the signal on the bus communication path 5 (S103: NO) and the determination circuit 24 does not determine that the count value has reached the upper limit value (S104: NO), The count is continued (S102).

  If the falling edge of the signal on the bus communication path 5 is extracted by the reproduction circuit 22 before the determination circuit 24 determines that the count value has reached the upper limit value (S103: YES), the current count The pulse width is determined from the value (S105), and the clock having the determined pulse width is output from the reproduction circuit 22 as the bus clock BCK (S106). This count value is a value corresponding to one cycle of the clock component supplied from the master 3a (hereinafter referred to as “cycle count value”). In this embodiment, the latest value is used for the determination process (S112) described later. The cycle count value is stored in the determination circuit 24.

  Thereafter, the counter 23 resets the count value (S101), and the same processing is repeated. That is, in a situation where a signal including a clock component is supplied from the master 3a, the falling edge is extracted before the count value reaches the upper limit value, and is synchronized with the clock component included in the signal on the bus communication path 5. The bus clock BCK is generated and output by the reproduction circuit 22 (S101 to S106).

  On the other hand, if the determination circuit 24 determines that the count value has reached the upper limit value before the reproduction circuit 22 extracts the falling edge of the signal on the bus communication path 5 (S104: YES), the current count A pulse width is determined from the value (upper limit value) (S107), and a clock having the determined pulse width is output as an alternative clock ACK (S108). Then, the counter 23 resets the count value (S109), and starts counting using the count clock CCK (S110). Thereafter, the falling edge of the signal on the bus communication path 5 is not extracted by the reproduction circuit 22 (S111: NO), and the determination circuit 24 does not determine that the count value has reached the latest cycle count value obtained in the past. During this time (S112: NO), the count is continued (S110).

  If the determination circuit 24 determines that the count value has reached the latest cycle count value obtained in the past before the falling edge of the signal on the bus communication path 5 is extracted by the reproduction circuit 22 (S112: YES), the pulse width is determined from the current count value (the latest cycle count value obtained in the past) (S113), and the clock having the determined pulse width is output as the alternative clock ACK (S114).

  That is, in the situation where the supply of the signal including the clock component from the master 3a is stopped, the falling edge is not extracted, so that a period corresponding to the latest cycle count value obtained in the past is used instead of the bus clock BCK. An alternative clock ACK for one cycle is generated and output by the reproduction circuit 22 (S109 to S114).

  On the other hand, when the falling edge of the signal on the bus communication path 5 is extracted by the reproduction circuit 22, that is, when the supply of the signal including the clock component from the master 3a is resumed (S111: YES), the bus The process returns to the process of generating the clock BCK (S101 to S106).

<Effect>
As described above, the transceiver 20 of the slave 3b can operate the sequencer 30 using the bus clock BCK in a situation where a signal including a clock component is supplied from the master 3a. Even in the situation where the supply of the signal including the clock component is stopped, the sequencer 30 can be operated using the alternative clock ACK. Therefore, the slave 3b can be configured using the oscillator-less sequencer 30, and as a result, the cost of the communication system 1 can be reduced.

  Moreover, since the alternative clock ACK is generated based on the latest cycle count value obtained in the past, the bus clock BCK before the supply is stopped even in the situation where the supply of the signal including the clock component is stopped. It is possible to generate an alternative clock ACK having the same period as in FIG.

  In addition, the reproduction circuit 22 of the transceiver 20 is supplied via the bus communication path 5 and a master mode for generating a clock component included in a signal supplied via the bus communication path 5 based on the internal clock CK. It is configured to be switchable to a slave mode that generates a bus clock BCK based on a clock component included in the signal. For this reason, the transceiver 20 common to the master 3a and the slave 3b can be used.

  In this embodiment, the oscillation circuit 21 corresponds to a clock generation unit, the reproduction circuit 22 corresponds to an edge extraction unit and a clock generation unit, the counter 23 corresponds to a count unit, and the determination circuit 24 serves as an upper limit detection unit. Equivalent to.

[Second Embodiment]
The basic configuration of the second embodiment is the same as that of the first embodiment, but the processing executed by the transceiver 20 of the slave 3b is different. Specifically, in the transceiver 20 of the slave 3b of the second embodiment, the process shown in FIG. 5 is executed instead of the process shown in FIG.

Here, processing repeatedly executed by the transceiver 20 of the slave 3b will be described with reference to the flowchart of FIG.
First, the counter 23 resets the count value (S201), and starts counting using the count clock CCK (S202). Thereafter, while the reproduction circuit 22 does not extract the falling edge of the signal on the bus communication path 5 (S203: NO) and the determination circuit 24 does not determine that the count value has reached the upper limit value (S204: NO), The count is continued (S202).

  If the falling edge of the signal on the bus communication path 5 is extracted by the reproduction circuit 22 before the determination circuit 24 determines that the count value has reached the upper limit value (S203: YES), the current count The pulse width is determined from the value (cycle count value) (S205), and the clock having the determined pulse width is output from the reproduction circuit 22 as the bus clock BCK (S206).

  Thereafter, the counter 23 resets the count value (S201), and the same processing is repeated. That is, in a situation where a signal including a clock component is supplied from the master 3a, the falling edge is extracted before the count value reaches the upper limit value, and is synchronized with the clock component included in the signal on the bus communication path 5. The bus clock BCK is generated and output by the reproduction circuit 22 (S201 to S206).

  On the other hand, if the determination circuit 24 determines that the count value has reached the upper limit before the reproduction circuit 22 extracts the falling edge of the signal on the bus communication path 5 (S204: YES), the current count A pulse width is determined from the value (upper limit value) (S205), and a clock having the determined pulse width is output as an alternative clock ACK (S206). Thereafter, the counter 23 resets the count value (S201), and the same processing is repeated. In other words, in the situation where the supply of the signal including the clock component from the master 3a is stopped, the falling edge is not extracted, so that instead of the bus clock BCK, an alternative clock ACK having a period corresponding to the upper limit value as one cycle is generated. Generated by the reproduction circuit 22 and output.

<Effect>
The cost reduction of the communication system 1 is also realized by the process of the second embodiment for the same reason as the first embodiment. In particular, according to the second embodiment, since the period until the count value reaches the upper limit is set as one cycle of the alternative clock ACK as it is, processing in a situation where a signal including a clock component is supplied from the master 3a. Therefore, it is not necessary to distinguish the processing in the situation where the supply is stopped, and the processing load can be reduced.

[Other Embodiments]
As mentioned above, although embodiment of this invention was described, it cannot be overemphasized that this invention can take a various form, without being limited to the said embodiment.

  For example, in the first embodiment, the alternative clock ACK is generated based on one cycle count value obtained in the past, but instead of this, a value using a plurality of cycle count values obtained in the past ( The alternative clock ACK may be generated based on the average value.

  In each of the above embodiments, in the slave 3b, the example in which the signal processing unit (the sequencer 30 in the above example) is configured separately from the transceiver is shown, but instead, the signal processing unit is incorporated in the transceiver. It is good also as a structure.

  DESCRIPTION OF SYMBOLS 1 ... Communication system 3 ... Node 3a ... Master 3b ... Slave 5 ... Bus communication path 10 ... Microcomputer 12 ... Oscillator 20 ... Transceiver 21 ... Oscillator circuit 21 22 ... Reproduction circuit 23 ... Counter 24 ... Judgment circuit 30 ... Sequencer

Claims (4)

A transceiver capable of receiving a signal encoded using a transmission path code including a clock component via a bus communication path,
Clock generating means for generating a counting clock having a frequency higher than that of the clock component;
Edge extraction means for extracting an edge of interest on the edge of the signal on the bus communication path and occurring in the period of the clock component;
Counting means for counting an edge interval, which is an interval from when the target edge is extracted by the edge extracting unit to when the next target edge is extracted, using the counting clock;
Clock generation means for generating a bus clock synchronized with the clock component by dividing the counting clock;
Upper limit detection means for detecting that the count value by the counting means has reached a predetermined upper limit;
With
The clock generation means includes
If the target edge is extracted by the edge extraction unit before the upper limit detection unit detects that the count value has reached the upper limit value, the count value of the edge interval up to the target edge is obtained. Generating the bus clock with a period corresponding to one cycle;
If the upper limit detection unit detects that the count value has reached the upper limit before the edge extraction unit extracts the target edge, the edge extraction unit extracts the target edge. Until this time, in place of the bus clock, a substitute clock having a period corresponding to the substitute count value as one cycle is generated. The transceiver of claim 1, comprising:
The transceiver is characterized in that the alternative count value is determined based on a count value of the edge interval to the edge of interest extracted in the past. A transceiver capable of receiving a signal encoded using a transmission path code including a clock component via a bus communication path,
Clock generating means for generating a counting clock having a frequency higher than that of the clock component;
Edge extraction means for extracting an edge of interest on the edge of the signal on the bus communication path and occurring in the period of the clock component;
Counting means for counting an edge interval, which is an interval from when the target edge is extracted by the edge extracting unit to when the next target edge is extracted, using the counting clock;
Clock generation means for generating a bus clock synchronized with the clock component by dividing the counting clock;
Upper limit detection means for detecting that the count value by the counting means has reached a predetermined upper limit;
With
The clock generation means includes
If the target edge is extracted by the edge extraction unit before the upper limit detection unit detects that the count value has reached the upper limit value, the count value of the edge interval up to the target edge is obtained. Generating the bus clock with a period corresponding to one cycle;
If the upper limit detection unit detects that the count value has reached the upper limit before the edge extraction unit extracts the target edge, the period corresponding to the upper limit is set as one cycle. A transceiver that generates an alternative clock. A transceiver according to any one of claims 1 to 3, comprising:
The clock generation means is configured to be switchable to a plurality of operation modes, and the plurality of operation modes include:
A first mode for generating the bus clock synchronized with the clock component based on the clock component included in the signal on the bus communication path;
A second mode for generating the clock component synchronized with the reference clock based on a reference clock with higher accuracy than the counting clock;
A transceiver characterized in that is included.

Images