JP5598441B2 - Communication device - Google Patents

Description

  The present invention relates to a communication apparatus that is connected to a common bus communication path and communicates with each other via the bus communication path.

  Conventionally, a CSMA / CA CAN (Controller Area Network) protocol is known as a communication protocol widely used for a local area network (LAN), particularly an in-vehicle LAN (see Patent Document 1).

  An identification code (ID) for identifying what kind of message is assigned to the subsequent data area is included in the head part of the frame defined by the CAN protocol, and constitutes a communication system. The communication device that performs identification identifies the type of the received frame based on the ID included in the frame.

  In addition, since a plurality of communication devices communicate via a common bus communication path, a communication apparatus having a frame to be transmitted immediately starts transmitting a frame unless the bus communication path is in use. If the bus is in use, frame transmission starts after the bus communication path is released (frame transmission is completed). For this reason, if there are a plurality of communication devices having a frame to be transmitted, the plurality of communication devices may start transmitting frames at the same time. In this case, a frame collision occurs on the bus communication path. When such a frame collision occurs, the CAN protocol stipulates that an arbitration process for determining which frame is preferentially processed is performed using the above-described ID.

  Incidentally, information called ACK is returned as information for determining the normal arrival of a frame from the transmitting communication device to the receiving communication device. Specifically, in the CAN protocol, ACK information indicating that a frame has been normally received is assigned to a specific bit (ACK slot) of the frame, for example. At this time, since the communication device on the transmission side compares the signal level of the frame with the signal level on the bus communication channel for each bit during frame transmission, if the frame is not normally received, ACK information can be returned to the communication device on the transmission side by rewriting the specific bit of the frame.

JP 2006-287738 A

  However, when communication is performed using a signal processing unit having a general-purpose asynchronous transmission / reception circuit, the general-purpose asynchronous transmission / reception circuit is so-called start-stop synchronization, and therefore ACK information cannot be returned in the same manner as the CAN protocol. In order to realize this, it is necessary to provide the transceiver interposed between the microcomputer and the bus communication path with a function of returning ACK, and as a result, the scale of the transceiver increases.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to perform frame communication without increasing the scale of a transceiver when performing communication using a signal processing unit having a general-purpose asynchronous transmission / reception circuit. It is to provide a communication device capable of notifying the arrival of.

Communication apparatus has been made in order to achieve the object described above, are connected to a common bus communication line, and performs communication with each other via the bus communication line.
The communication apparatus of the present invention includes a signal processing unit and a transceiver. The signal processing unit has a general-purpose asynchronous transmission / reception circuit. The transceiver outputs a frame from the general-purpose asynchronous transmission / reception circuit to the bus communication path and outputs a frame received via the bus communication path to the general-purpose asynchronous transmission / reception circuit.

  Here, particularly in the present invention, the reception side processing is executed by the signal processing unit. In this reception side processing, the reception information is stored so that the reception information based on the frame received via the bus communication path is included in the response at the time of frame transmission.

  That is, since the reception information based on the received frame is stored in the signal processing unit, if this reception information is included in the response at the time of frame transmission, the information of the frame received in the past is transmitted to other communication devices. You can be notified. In this way, when communication is performed using a signal processing unit having a general-purpose asynchronous transmission / reception circuit, arrival of a frame can be notified without increasing the size of the transceiver.

  Note that the signal processing unit may be configured by a microcomputer, or may be configured by a sequencer having at least a function corresponding to a general-purpose asynchronous transmission / reception circuit, for example, if the communication device operates as a slave.

In receiving side processing, the received information is considered to store the received information in the specified byte data constituting the response to include the response at the time of frame transmission. In this way, when the frame is transmitted, the designated byte of the data constituting the response becomes the reception information, so that the arrival of the frame can be notified relatively easily.

Receiving information, it is considered to be information based on the ID value included in the header of the received frame. At this time, in the receiving process, the calculation result of the past received information and the ID value of the received frame is stored as new received information. In this way, since the reception information is updated with the ID value of the received frame, it is possible to grasp the reception status of the past frame. That is, there is a high possibility that it can be determined based on the received information which frame has been received among frames transmitted in the past.

Specifically, the operation result of the received information, it is considered to be a logical sum of the ID value of the received frame and the reception information in the past. In this way, since the frame ID value is added as the reception information, it is possible to grasp the reception status of the past frame.

Receiving information, it is conceivable that a number of frames received. At this time, in the receiving side processing, when receiving the frame, the past received information is incremented and stored as new received information. In this way, since the reception information corresponds to the number of received frames, it is possible to grasp the reception status of past frames. That is, it can be determined based on the reception information whether or not all frames have been received from the start of counting to the present.

In the above configuration, in the receiving side processing, based on the ID value included in the header of the frame received via the bus communication line, it is also possible to store the received information only about the particular frame. For example, only the number of frames having an ID value in a predetermined range is counted and used as reception information. In this way, it is possible to notify the arrival of a specific frame.

Further, in the receiving side processing, during the establishment of a predetermined condition, it is also possible to clear the received information. “When the predetermined condition is satisfied” is considered to be a timing at which a certain period of time has elapsed, a certain number of frames have been transmitted, or the received information stored does not overflow (overflow). “Clearing received information” means resetting received information. As an example, “clearing received information” can be considered. In this way, the reception status of the past frame can be grasped from the timing of clearing the reception information.

It is a block diagram which shows schematic structure of a communication system. (A) is explanatory drawing which shows the structure of the transmission-line code | cord | chord used on a bus channel, (b) is explanatory drawing which shows the structure of the flame | frame transmitted / received via a bus channel, (c) is UART. It is explanatory drawing which shows the structure of the block data which transmits / receives. It is a flowchart which shows the receiving side process which a signal processing part performs. It is explanatory drawing for showing the effect by receiving side processing. It is a flowchart which shows the receiving side process in 2nd Embodiment. It is explanatory drawing for demonstrating the effect by the receiving side process of 2nd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a communication system mounted on a vehicle.

The communication system includes a plurality of communication devices (hereinafter referred to as “ECUs”) 10. These ECUs 10 are connected to each other via a bus communication path 40.
The ECU 10 constituting the communication system may be a body system ECU, for example. Specifically, there are a body wiper ECU, a seat ECU, a slide door ECU, a mirror ECU, a back door ECU, a light ECU, a tilt tele (electric steering position adjustment device) ECU, and the like. In addition, although the aspect in which ECU10 was mutually connected was shown here, it is also considered that light SW, wiper SW, a light sensor, a rain sensor, etc. as a related apparatus are connected as a communication apparatus with body system ECU.

  The bus communication path 40 is configured such that when a high level signal and a low level signal are simultaneously output from different ECUs 10, the signal level on the bus communication path 40 becomes low level. Realize bus arbitration.

Here, FIG. 2A is an explanatory diagram showing transmission path codes used in the bus communication path 40.
As shown in FIG. 2A, in the bus communication path 40, a PWM code whose signal level changes from a low level to a high level in the middle of a bit is used as a transmission path code. ) And recessive (corresponding to 1 in the present embodiment) are expressed by two types of duty ratios.

  Specifically, the dominant is set so that the ratio of the low level is longer than the recessive (in this embodiment, the dominant is a 2/3 period of 1 bit and the recessive is a 1/3 period of 1 bit) When a dominant and recessive collision occurs on the bus communication path 40, the dominant wins arbitration.

  In the communication system, a so-called CSMA / CA access control method is used in which the ECU 10 that has lost the arbitration immediately stops transmission, and only the ECU 10 that has won the arbitration continues the transmission.

FIG. 2B is an explanatory diagram showing the configuration of the ram used for communication between the ECUs 10.
As shown in FIG. 2B, the frame includes a header for designating data permitted to be transmitted and a variable length response for transmitting the data designated by the header.

  Among these, the header includes an identifier (ID), and is set so that the smaller the ID value, the longer the bus arbitration is won. On the other hand, the response includes at least size information indicating the size of the data (response) and a CRC code for checking the presence / absence of an error in addition to the data.

  In addition, one of the ECUs 10 is a master and the other ECU 10 is a slave, and the master transmits the header, thereby sequentially specifying data to be allowed to be transmitted (and consequently the slave that is the data transmission source), and is specified by the header. Polling (periodic communication) in which a slave serving as a data transmission source transmits a response (data) and event communication in which the slave autonomously controls communication regardless of an instruction from the master.

Next, the configuration of the ECU 10 will be described.
As shown in FIG. 1, the ECU 10 includes a microcomputer 20 and a transceiver 30.

  The microcomputer 20 executes various processes assigned to the own ECU 10 based on information obtained by communication with the other ECU 10 via the bus communication path 40. Therefore, the microcomputer 20 is configured around a known microcomputer including a CPU, a ROM, a RAM, an I / O port, and the like.

  The microcomputer 20 has a UART (Universal Asynchronous Receiver Transmitter) 21 and an oscillator 22. This UART 21 implements asynchronous serial communication. The oscillator 22 generates an operation clock for operating the microcomputer 20 and an internal clock supplied to the transceiver 30. This internal clock is set to the same speed as the communication speed of the UART 21 (in this embodiment, 20 Kbps).

  However, the slave node is not necessarily configured by the microcomputer 20, and may be configured by a sequencer having at least a function corresponding to the UART 11 and an oscillation circuit that generates an operation clock for operating the sequencer.

  FIG. 2C is an explanatory diagram showing a configuration of data transmitted / received by the UART 21. As shown in FIG. 2C, the UART 21 is sandwiched between a start bit (low level) indicating the start of data, a stop bit (high level) indicating the end of data, and the start bit and stop bit. A total 10-bit block unit data composed of the 8-bit data is transmitted and received.

  The header constituting the above-mentioned frame (see FIG. 2B) is composed of a single block data, and 7 bits are used as an ID among 8 bits data excluding the start bit and stop bit. One bit is used as a parity bit. The response is composed of one or a plurality of block data, and size information is set in the first block. In this embodiment, ID information is stored in a designated byte of response data. For example, it is assumed that ID information is stored in the last byte of data.

  On the other hand, the transceiver 30 encodes the transmission data supplied from the microcomputer 20 and outputs the encoded data to the bus communication path 40, and also decodes the received data of the PWM code fetched from the bus communication path 40 and supplies it to the microcomputer 20.

Next, the receiving side process executed by the microcomputer 20 of the ECU 10 will be described with reference to FIG. This reception side process is executed when receiving transmission data from the other ECU 10.
In first S100, it is determined whether or not frame reception is completed. If it is determined that the reception of the frame is completed (S100: YES), the process proceeds to S110. On the other hand, while the reception of the frame is not completed (S100: NO), the determination process of S100 is repeated.

  In S110, it is determined whether a condition for clearing the reception ID register is satisfied. The reception ID register is a register provided in the microcomputer 20 for storing reception information. The reception ID register may be periodically cleared, may be cleared when a certain number of frames are transmitted, or may be cleared so that the register does not overflow. If it is determined that the condition for clearing the reception ID register is satisfied (S110: YES), the reception ID register is cleared to “0x00” in S130, and then the process proceeds to S140. On the other hand, if it is determined that the clear condition of the reception ID register is not satisfied (S110: NO), the received ID is added to the reception ID register in S120, and then the process proceeds to S140. Specifically, the logical sum (OR) of the value of the reception ID register and the value of the reception ID is taken, and the logical sum is stored in the reception ID register.

  In S140, the value of the reception ID register is stored at the designated position of the data. In this process, the value of the reception ID register is stored in the designated byte of the response data. In the present embodiment, it is assumed that the value of the reception ID register is stored in the last byte of data. Thus, at the time of frame transmission, the value of the reception ID register is stored in the last byte of the response data and transmitted.

  Specifically, as shown in FIG. 4, it is assumed that a frame including a header having an ID “0x10” and a response is transmitted first. At this time, a response in which the value “0x00” of the reception ID register is stored in the last byte of the data is transmitted (symbol A in the figure).

  The ECU 10 that has received this frame (S100: YES) adds the received ID “0x10” to the value “0x00” of the reception ID register if the clear condition of the reception ID register is not satisfied (S110: NO) ( S120). Therefore, the value of the reception ID register is “0x10”, and “0x10” is stored in the designated position of the data (S140).

  As a result, when the ECU 10 next transmits a frame including the header of ID “0x15” and the response, the last byte of the response data is “0x10” (symbol B in the figure).

  Similarly, the ECU 10 that has received this frame adds the received ID “0x15” to the value “0x10” of the reception ID register (S120). In this case, since the OR of the binary number “00010000” and the binary number “00010101” is taken, the binary number becomes “00010101”. That is, the hexadecimal number is “0x15”.

  As a result, when the ECU 10 next transmits a frame composed of the header having the ID “0x20” and the response, the last byte of the response data is “0x15” (symbol C in the figure).

  As described in detail above, according to the present embodiment, reception of a frame is determined (S100 in FIG. 3), and when reception of the frame is completed (S100: YES), the received ID is added to the reception ID register. (S120), the value of the reception ID register is stored in the designated position of the data (S140). Thus, when communication is performed using the microcomputer 20 having the general-purpose asynchronous transmission / reception circuit, the arrival of the frame can be notified without increasing the scale of the transceiver 30.

  In particular, by storing the value of the reception ID register at the data specified position in the processing on the receiving side (S140 in FIG. 3), the data specified position constituting the response becomes reception information at the time of frame transmission, and the arrival of the frame is relatively Can be easily notified.

  In this embodiment, the received ID is added to the received ID register (S120 in FIG. 3), specifically, the logical sum of the received ID register value and the received ID value is received as received information. Store in ID register. This increases the possibility that it can be determined based on the received information which frame has been received among frames transmitted in the past. As a result, it is possible to grasp the reception status of past frames.

  Furthermore, in this embodiment, it is determined whether or not the clear condition of the reception ID register is satisfied (S110 in FIG. 3). If the clear condition is satisfied (S110: YES), the reception ID register is cleared. Then, “0x00” is set (S130). Thereby, the reception status of the past frame can be grasped from the timing of clearing the reception ID register.

  In this embodiment, the ECU 10 constitutes a “communication device”, the UART 21 constitutes a “general purpose asynchronous transmission / reception circuit”, the microcomputer 20 constitutes a “signal processing unit”, the transceiver 30 constitutes a “transceiver”, The bus communication path 40 constitutes a “bus communication path”. Further, the reception side processing shown in FIG. 3 corresponds to “reception side processing”.

[Second Embodiment]
In the first embodiment, the received ID is added to the reception ID register. In contrast, the second embodiment is characterized in that the number of frame receptions is stored. Therefore, what is different from the first embodiment is a part of the processing on the receiving side.

Then, the receiving side process executed by the microcomputer 20 of the ECU 10 will be described with reference to FIG. This reception side process is executed when receiving transmission data from the other ECU 10.
In first S200, it is determined whether or not the frame reception is completed. Here, when it is determined that the reception of the frame is completed (S200: YES), the process proceeds to S210. On the other hand, while the reception of the frame is not completed (S200: NO), the determination process of S200 is repeated.

  In S210, it is determined whether a clear condition of the reception ID register is satisfied. The reception ID register is a register provided in the microcomputer 20 for storing ID information. The reception ID register may be periodically cleared, may be cleared when a certain number of frames are transmitted, or may be cleared so that the register does not overflow. If it is determined that the condition for clearing the reception ID register is satisfied (S210: YES), the reception ID register is cleared to “0x00” in S230, and then the process proceeds to S240. On the other hand, when it is determined that the condition for clearing the reception ID register is not satisfied (S210: NO), the reception ID register is incremented in S220, and then the process proceeds to S240.

  In S240, the value of the reception ID register is stored at the designated position of the data. In this process, the value of the reception ID register is stored in the designated byte of the response data. In the present embodiment, it is assumed that the value of the reception ID register is stored in the last byte of data. Thus, at the time of frame transmission, the value of the reception ID register is stored in the designated byte of the response data and transmitted.

  Specifically, as shown in FIG. 6, it is assumed that a frame including a header having an ID “0x10” and a response is transmitted first. At this time, a response in which the value “0x00” of the reception ID register is stored in the last byte of the data is transmitted (symbol A in the figure).

  Upon receiving this frame (S200: YES), if the clear condition of the reception ID register is not satisfied (S210: NO), the value “0x00” of the reception ID register is incremented to “0x01” (S220). ). Therefore, the value of the reception ID register becomes “0x01”, and “0x01” is stored at the designated position of the data (S240).

  As a result, when the ECU 10 next transmits a frame composed of the header of ID “0x15” and the response, the last byte of the response data is “0x01” (symbol B in the figure).

Similarly, the ECU 10 receiving this frame increments the value “0x01” of the reception ID register to “0x02” (S220).
As a result, when the ECU 10 next transmits a frame including the header of ID “0x20” and the response, the last byte of the response data is “0x02” (symbol C in the figure).

  As described above in detail, according to the present embodiment, reception of a frame is determined (S200 in FIG. 5), and when reception of the frame is completed (S200: YES), the value of the reception ID register is incremented (S220). ), The value of the reception ID register is stored in the designated position of the data (S240). Thus, when communication is performed using the microcomputer 20 having the general-purpose asynchronous transmission / reception circuit, the arrival of the frame can be notified without increasing the scale of the transceiver 30.

  In particular, by storing the value of the reception ID register at the data specified position in the reception side processing (S240 in FIG. 5), the data specified position constituting the response becomes reception information at the time of frame transmission, and the arrival of the frame is relatively Can be easily notified.

  In this embodiment, by incrementing the value of the reception ID register (S220 in FIG. 5), the number of received frames is stored in the reception ID register as reception information. Thereby, it can be determined based on the reception information whether or not all frames are received from the start of counting until the present. As a result, it is possible to grasp the reception status of past frames.

  Furthermore, in this embodiment, it is determined whether or not a clear condition for the reception ID register is satisfied (S210 in FIG. 5). If the clear condition is satisfied (S210: YES), the reception ID register is cleared. Then, “0x00” is set (S230). Thereby, the reception status of the past frame can be grasped from the timing of clearing the reception ID register.

  In this embodiment, the ECU 10 constitutes a “communication device”, the UART 21 constitutes a “general purpose asynchronous transmission / reception circuit”, the microcomputer 20 constitutes a “signal processing unit”, the transceiver 30 constitutes a “transceiver”, The bus communication path 40 constitutes a “bus communication path”. Further, the reception side processing shown in FIG. 5 corresponds to “reception side processing”.

As described above, the present invention is not limited to the above-described embodiments, and can be implemented in various forms without departing from the scope of the invention.
(A) In the above embodiment, reception information is created for all received frames. However, reception information may be stored only for specific frames. For example, only for frames having ID values in a predetermined range, the ID received in S120 in FIG. 3 is added, or the reception ID register is incremented in S220 in FIG. In this way, it is possible to notify the arrival of a specific frame.

  (B) In the above embodiment, only when the clear condition is not satisfied (S110: NO in FIG. 3, S210: NO in FIG. 5), the reception ID is added (S120 in FIG. 3), The reception ID register is incremented (S220 in FIG. 5).

  On the other hand, when the clear condition is satisfied (S110 in FIG. 3: YES, S210: YES in FIG. 5), the reception ID register is cleared (S130 in FIG. 3, S230 in FIG. 5) and then received. ID addition (S120 in FIG. 3) or reception ID register increment (S220 in FIG. 5) may be executed, and then the process may proceed to S140 in FIG. 3 or S240 in FIG.

  (C) In the first embodiment, the reception information is obtained by taking the logical sum of the value of the reception ID register and the received ID value, but the result of another calculation may be used as the reception information. For example, the received ID value may be simply added to the reception ID register.

  (D) The communication system shown in FIG. 1 may be configured such that only the microcomputer 20 of the specific ECU 10 can execute the receiving side process. In this case, only the specific ECU 10 stores the reception information and transmits a frame in which the reception information is included in the data.

  10: communication device (ECU), 20: microcomputer, 21: UART (general purpose asynchronous transmission / reception circuit), 22: oscillator, 30: transceiver, 40: bus communication path

Claims (7)

A communication device connected to a common bus communication path and communicating with each other via the bus communication path,
A signal processing unit having a general-purpose asynchronous transceiver circuit;
A transceiver that outputs a frame received from the general-purpose asynchronous transmission / reception circuit to the bus communication path and outputs a frame received via the bus communication path to the general-purpose asynchronous transmission / reception circuit,
The signal processing unit is capable of executing a reception-side process for storing the reception information so that reception information based on a frame received via the bus communication path is included in a response at the time of frame transmission ,
The received frame that is the basis of the reception information is a frame that uses the communication device connected to the bus communication path and another communication device as a response transmission source.
Communication and wherein the. The communication device according to claim 1,
In the reception side process, the reception information is stored in a designated byte of data constituting the response so that the reception information is included in a response at the time of frame transmission. The communication device according to claim 1 or 2,
The reception information is information based on an ID value included in the header of the received frame;
In the receiving side process, a calculation result of past received information and an ID value of a received frame is stored as new received information. The communication device according to claim 3.
The calculation result is a logical sum of past received information and an ID value of a received frame. The communication device according to claim 1 or 2,
The received information is the number of received frames,
In the receiving side process, when a frame is received, past received information is incremented and stored as new received information. In the communication apparatus as described in any one of Claims 1-5,
The reception apparatus stores the reception information only for a specific frame based on an ID value included in a header of the frame among frames received via the bus communication path. In the communication apparatus as described in any one of Claims 1-6,
In the reception side process, the reception information is cleared when a predetermined condition is satisfied.

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