JP2013020215A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device with excellent display quality.SOLUTION: A liquid crystal display device comprises: a first switching element disposed in a first color pixel; a second switching element disposed in a second color pixel; a third switching element disposed in a third color pixel; a light-blocking layer facing the first switching element, the second switching element, and the third switching element; a first color filter disposed in the first color pixel and stacked on the light-blocking layer at a position facing the first switching element; a third color filter disposed in the third color pixel and stacked on the light-blocking layer at a position facing the second switching element and the third switching element; and a second color filter disposed in the second color pixel, overlapping with the first color filter at a position facing the first switching element, and overlapping with the third color filter at a position facing the second switching element and the third switching element.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  Liquid crystal display devices are utilized in various fields as display devices for OA equipment such as personal computers and televisions, taking advantage of features such as light weight, thinness, and low power consumption. In recent years, liquid crystal display devices are also used as mobile terminal devices such as mobile phones, display devices such as car navigation devices and game machines.

  In such a liquid crystal display device, when the counter substrate includes a light shielding layer made of a metal material such as chromium (Cr), light from the backlight is reflected by the light shielding layer and enters the thin film transistor (TFT) of the array substrate. There are things to do. In the case where the thin film transistor is a bottom gate type, the light leakage current of the thin film transistor may become a problem because the reflected light from the light shielding layer enters the semiconductor layer.

  In recent years, backlights tend to have higher brightness, and there is a demand for improvement in display problems (flicker, crosstalk, etc.) due to light leakage current.

JP 2002-90748 A

  An object of the present embodiment is to provide a liquid crystal display device with good display quality.

According to this embodiment,
A first substrate comprising: a first switching element disposed in a first color pixel; a second switching element disposed in a second color pixel; and a third switching element disposed in a third color pixel; A light shielding layer facing the first switching element, the second switching element, and the third switching element, and a layer disposed on the first color pixel and stacked on the light shielding layer at a position facing the first switching element. A first color filter, a third color filter disposed on the third color pixel and stacked on the light shielding layer at a position facing the second switching element and the third switching element, and a second color pixel And overlapping the first color filter at a position facing the first switching element, and the second switching element and the third switching element. A second substrate provided with a second color filter overlapping the third color filter at a position facing the element, and a liquid crystal layer held between the first substrate and the second substrate. A liquid crystal display device is provided.

According to this embodiment,
A first switching element; a first pixel electrode electrically connected to the first switching element; a second switching element; a second pixel electrode electrically connected to the second switching element; A first substrate comprising a switching element and a third pixel electrode electrically connected to the third switching element; a) the first switching element, the second switching element, and the third switching A first opening facing the first pixel electrode, a second opening facing the second pixel electrode, and a third opening facing the third pixel electrode. B) a first color filter disposed in the first opening and stacked on the light shielding layer at a position facing the first switching element; and c) disposed in the third opening. And a third color filter stacked on the light shielding layer at a position facing the second switching element and the third switching element; and d) the first switching element disposed in the second opening and the first switching element. A second color filter that overlaps the first color filter at a position facing it and that overlaps the third color filter at a position facing the second switching element and the third switching element; e) the first pixel electrode; A second substrate having a second pixel electrode and a common electrode facing the third pixel electrode, and a liquid crystal layer held between the first substrate and the second substrate. A liquid crystal display device is provided.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment. FIG. 2 is a plan view schematically showing the configuration of the array substrate shown in FIG. FIG. 3 is a plan view schematically showing a configuration of a counter substrate that can be combined with the array substrate shown in FIG. FIG. 4 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel when cut along line AA shown in FIG. FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of a liquid crystal display panel to which a counter substrate having another configuration is applied.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN has a substantially rectangular flat plate shape, an array substrate AR that is a first substrate, a counter substrate CT that is a second substrate disposed to face the array substrate AR, and the array substrate AR. And a liquid crystal layer LQ held between the substrate CT. The array substrate AR and the counter substrate CT are bonded together by a seal material SE.

  Such a liquid crystal display panel LPN is provided with an active area ACT for displaying an image on the inner side surrounded by the seal material SE. The active area ACT is formed, for example, in a quadrangular shape (in particular, a rectangular shape) and includes a plurality of color pixels PX arranged in an m × n matrix (where m and n are positive integers). is there). Note that the color pixel PX includes a red pixel that displays red, a green pixel that displays green, a blue pixel that displays blue, and the like.

  In the active area ACT, the liquid crystal display panel LPN includes a plurality of gate lines G (G1 to Gn), a plurality of auxiliary capacitance lines C (C1 to Cn), a plurality of source lines S (S1 to Sm), and the like. For example, the gate line G and the auxiliary capacitance line C extend substantially linearly along the first direction X. These gate lines G and storage capacitor lines C are alternately arranged in parallel along a second direction Y that intersects the first direction X. Here, the first direction X and the second direction Y are substantially orthogonal to each other. The source line S intersects with the gate line G and the auxiliary capacitance line C. The source line S extends substantially linearly along the second direction Y. Note that the gate wiring G, the auxiliary capacitance line C, and the source wiring S do not necessarily extend linearly, and some of them may be bent.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. At least a part of the gate driver GD and the source driver SD is formed on, for example, the array substrate AR, and is connected to the driving IC chip 2 with a built-in controller.

  Each color pixel PX in the active area ACT includes a switching element SW, a pixel electrode PE, a common electrode CE, and the like. The switching element SW and the pixel electrode PE are provided on the array substrate AR. The common electrode CE may be provided on the array substrate AR, or may be provided on the counter substrate CT. The storage capacitor Cs is formed, for example, between the storage capacitor line C and the electrode having the same potential as the pixel electrode PE. The auxiliary capacitance line C is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is applied.

  The switching element SW is electrically connected to the gate line G and the source line S. The switching element SW is constituted by, for example, a bottom gate type thin film transistor (TFT). The semiconductor layer of such a switching element SW is made of amorphous silicon, for example.

  The gate electrode WG of the switching element SW is electrically connected to the gate line G (or the gate electrode WG is formed integrally with the gate line G). The source electrode WS of the switching element SW is electrically connected to the source line S (or the source electrode WS is formed integrally with the source line S). The drain electrode WD of the switching element SW is electrically connected to the pixel electrode PE.

  The pixel electrode PE is disposed in each color pixel PX and is electrically connected to the switching element SW. The common electrode CE is disposed in common with respect to the pixel electrodes PE of the plurality of color pixels PX. The pixel electrode PE and the common electrode CE are formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

  The array substrate AR includes a power supply unit VS for applying a voltage (for example, a common potential) to the common electrode CE. For example, the power supply unit VS is formed outside the active area ACT. The common electrode CE is drawn out of the active area ACT and is electrically connected to the power supply unit VS via a conductive member (not shown).

  FIG. 2 is a plan view schematically showing the configuration of the array substrate AR shown in FIG.

  In the active area ACT in the figure, the gate wiring G extends along the first direction X, and the source wirings S1 to S3 extend along the second direction Y, respectively. In the active area ACT, the first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 are arranged in order from the left side to the right side in the drawing along the first direction X, and the unit pixel UP is displayed. It is composed. Such unit pixels UP are repeatedly arranged along the first direction X. That is, the third color pixel PX3 of the other adjacent unit pixel UP is located on the left side of the first color pixel PX1 in the drawing, and the other adjacent unit pixel UP is located on the right side of the third color pixel PX3. The first color pixel PX1 is located.

  The first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 are color pixels that display different colors. For example, the first color pixel PX1 is a red pixel that displays red, the second color pixel PX2 is a green pixel that displays green, and the third color pixel PX3 is a blue pixel that displays blue. It is not limited to.

  In the first color pixel PX1, a first switching element SW1 electrically connected to the gate line G and the source line S1, and a first pixel electrode PE1 electrically connected to the first switching element SW1 are arranged. ing.

  In the second color pixel PX2, a second switching element SW2 electrically connected to the gate line G and the source line S2 and a second pixel electrode PE2 electrically connected to the second switching element SW2 are arranged. ing.

  In the third color pixel PX3, a third switching element SW3 electrically connected to the gate line G and the source line S3 and a third pixel electrode PE3 electrically connected to the third switching element SW3 are arranged. ing.

  The source line S1 is located between the first pixel electrode PE1 and the second pixel electrode PE2. The source line S2 is located between the second pixel electrode PE2 and the third pixel electrode PE3.

  The first switching element SW1, the second switching element SW2, and the third switching element SW3 are located on the same straight line, and are arranged in this order along the first direction X in the illustrated example. However, the first switching element SW1 is located on the side close to the source line S1. The second switching element SW2 is located between the source line S1 and the source line S2, but is located closer to the source line S2 than the source line S1. The third switching element SW3 is located between the source line S2 and the source line S3, but is located closer to the source line S3 than the source line S2.

  Here, the first switching element SW1 will be described in more detail. The second switching element SW2 and the third switching element SW3 have substantially the same structure as the first switching element SW1 except that the connected source wirings are different.

  That is, in the first switching element SW1, the gate electrode WG is a part of the gate line G. The semiconductor layer SC is located above the gate wiring G. The source electrode WS extends from the source line S1 and is in contact with the semiconductor layer SC. The drain electrode WD contacts the semiconductor layer SC and extends toward the first pixel electrode PE1. The first pixel electrode PE1 is electrically connected to the drain electrode WD via the contact hole CH.

  FIG. 3 is a plan view schematically showing the configuration of the counter substrate CT that can be combined with the array substrate AR shown in FIG. The configuration on the array substrate side such as the switching element SW and the pixel electrode PE of each color pixel is indicated by a broken line.

  The counter substrate CT includes a light shielding layer BM, a first color filter CF1, a second color filter CF2, a third color filter CF3, a common electrode CE, and the like.

  The light shielding layer BM is formed in a lattice shape. More specifically, the light shielding layer BM extends along the first direction X, and extends to the first switching element SW1, the second switching element SW2, and the third switching element SW3 arranged along the first direction X. Opposed to each other. That is, the light shielding layer BM extending along the first direction X is located immediately above the gate line G. Further, the light shielding layer BM extends along the second direction Y, and is located immediately above the source line S1, the source line S2, and the source line S3.

  Such a light shielding layer BM includes a first opening AP1 facing the first pixel electrode PE1, a second opening AP2 facing the second pixel electrode PE2, and a third opening facing the third pixel electrode PE3. It has AP3. The first opening AP1, the second opening AP2, and the third opening AP3 are formed in, for example, a rectangular shape whose length along the second direction Y is longer than the length along the first direction X. Has been.

  The first color filter CF1 is disposed in the first color pixel PX1, and is stacked on the light shielding layer BM at a position facing the first switching element SW1. That is, the first color filter CF1 is disposed in the first opening AP1 and is located above the first pixel electrode PE1. Such a first color filter CF1 is formed in a strip shape extending along the second direction Y. When the first color pixel PX1 is a red pixel, the first color filter CF1 is a red color filter formed of a resin material colored in red.

  The third color filter CF3 is disposed in the third color pixel PX3, and is stacked on the light shielding layer BM at a position facing the second switching element SW2 and the third switching element SW3. That is, the third color filter CF3 is disposed in the third opening AP3 and is located above the third pixel electrode PE3. The third color filter CF3 is formed in a strip shape extending substantially along the second direction Y, but a part thereof is a switching element close to the third color pixel PX3, that is, the second switching element SW2. It protrudes toward the second color pixel PX2 so as to face each other. When the third color pixel PX3 is a blue pixel, the third color filter CF3 is a blue color filter formed of a resin material colored in blue.

  The second color filter CF2 is disposed in the second color pixel PX2, overlaps the first color filter CF1 at a position facing the first switching element SW1, and faces the second switching element SW2 and the third switching element SW3. It overlaps with the third color filter CF3 at the position. That is, the second color filter CF2 is disposed in the second opening AP2 and is located above the second pixel electrode PE2. Such a second color filter CF2 is formed in a strip shape extending substantially along the second direction Y, but the first color filter CF2 is partly opposed to the first switching element SW1 and the third switching element SW3. Projecting to the pixel PX1 side and the third color pixel PX3 side, respectively. In the illustrated example, the second color filter CF2 is formed in a strip shape extending along the first direction X, and faces each of the first switching element SW1, the second switching element SW2, and the third switching element SW3. . When the second color pixel PX2 is a green pixel, the second color filter CF2 is a green color filter formed of a resin material colored in green.

  The edges of the adjacent first color filter CF1 and second color filter CF2 are separated from each other and are located immediately above the source line S1. Further, the edges of the adjacent second color filter CF2 and third color filter CF3 are separated from each other and are located immediately above the source line S2.

  As described above, in the counter substrate CT, not only the light shielding layer BM but also two kinds of color filters are stacked at the positions facing the first switching element SW1, the second switching element SW2, and the third switching element SW3. Has been.

  The common electrode CE is formed over substantially the entire surface of the counter substrate CT, and faces the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

  The columnar spacer SP is disposed in a color pixel that displays a color with the lowest transmittance. In the illustrated example, the columnar spacer SP is disposed in a third color pixel PX3 that displays blue. More specifically, the columnar spacer SP is disposed at a position facing the second switching element SW2 and the third switching element SW3 in a region where the second color filter CF2 and the third color filter CF3 overlap. ing. That is, the second switching element SW2, the source line S2, the columnar spacer SP, and the third switching element SW3 are arranged in this order along the first direction X.

  4 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel LPN when cut along the line AA shown in FIG.

  A backlight BL is disposed on the back side of the array substrate AR constituting the liquid crystal display panel LPN. As the backlight BL, various forms are applicable, and any of those using a light emitting diode (LED) or a cold cathode tube (CCFL) as a light source can be applied. The description of the structure is omitted.

  The array substrate AR is formed using a first insulating substrate 10 having light transparency. The array substrate AR includes a gate line G, a source line S1, a source line S2, a first switching element SW1, a second switching element SW2, a third switching element SW3, a first pixel electrode PE1, a second pixel electrode, and a third pixel. An electrode, a first alignment film AL1, and the like are provided.

  The gate wiring G is disposed on the inner surface 10 </ b> A facing the counter substrate CT of the first insulating substrate 10, and is covered with the first insulating film 11. The gate line G includes the gate electrodes WG of the first switching element SW1, the second switching element SW2, and the third switching element SW3.

  Focusing on the first switching element SW1, the semiconductor layer SC is formed on the first insulating film 11 and is located immediately above the gate electrode WG which is a part of the gate wiring G. The source electrode WS is a part of the source wiring S1 and is in contact with the semiconductor layer SC. The drain electrode WD is in contact with the carrier layer SC. The description of the structures of the second switching element SW2 and the third switching element SW3 is omitted. The first switching element SW1, the second switching element SW2, and the third switching element SW3 are covered with the second insulating film 12.

  The source line S1, the source line S2, and the source line S3 are each formed on the first insulating film 11 and covered with the second insulating film 12.

  The first pixel electrode PE1 is formed on the second insulating film 12. The first pixel electrode PE1 is electrically connected to the drain electrode WD of the first switching element SW1 through a contact hole CH formed in the second insulating film 12. Although not shown, the second pixel electrode PE2 and the third pixel electrode PE3 are electrically connected to the drain electrode of the second switching element SW2 and the drain electrode of the third switching element SW3, respectively.

  The first alignment film AL1 is disposed on the surface of the array substrate AR that faces the counter substrate CT, and extends over substantially the entire active area ACT. The first alignment film AL1 covers the first pixel electrode PE1 and the like, and is also disposed on the second insulating film 12.

  The counter substrate CT is formed by using a second insulating substrate 20 having optical transparency. The counter substrate CT includes a light shielding layer BM, a first color filter CF1, a second color filter CF2, a third color filter CF3, a common electrode CE, a second alignment film AL2, and the like.

  The light shielding layer BM is disposed so as to face wiring portions such as the source wiring S1, the source wiring S2, the source wiring S3, the gate wiring G, the first switching element SW1, the second switching element SW2, and the third switching element SW3. Yes. The light shielding layer BM is disposed on the inner surface 20A of the second insulating substrate 20 facing the array substrate AR. Such a light shielding layer BM is made of, for example, a metal material such as chromium (Cr).

  The first color filter CF1 is stacked on the side of the light shielding layer BM that faces the array substrate AR just above the first switching element SW1. The first color filter CF1 is disposed on the inner surface 20A of the second insulating substrate 20 immediately above the first pixel electrode PE1.

  In the cross section shown in the drawing, the third color filter CF3 is stacked on the side facing the array substrate AR of the light shielding layer BM immediately above the second switching element SW2 and the third switching element SW3. The third color filter CF3 is separated from the first color filter CF1.

  In the illustrated cross section, the second color filter CF2 is stacked on the side of the first color filter CF1 facing the array substrate AR immediately above the first switching element SW1. The second color filter CF2 is stacked on the side of the third color filter CF3 facing the array substrate AR just above the second switching element SW2 and the third switching element SW3. Further, the second color filter CF2 is stacked on the light shielding layer BM exposed from between the first color filter CF1 and the third color filter CF3. Such a second color filter CF2 is continuously formed so as to connect positions immediately above the first switching element SW1, the second switching element SW, and the third switching element SW3.

  The common electrode CE is formed on the side of the second color filter CF2 that faces the array substrate AR. The common electrode CE is opposed to the second pixel electrode and the third pixel electrode as well as the illustrated first pixel electrode PE1. The second alignment film AL2 is disposed on the surface of the counter substrate CT facing the array substrate AR, and extends over substantially the entire active area ACT. The second alignment film AL2 covers the common electrode CE and the like.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, between the array substrate AR and the counter substrate CT, for example, a columnar spacer SP integrally formed on one substrate by a resin material is disposed, and a predetermined cell gap, for example, a cell gap of 2 to 7 μm is disposed. Is formed. The array substrate AR and the counter substrate CT are bonded together in a state where a predetermined cell gap is formed.

  In the illustrated example, the columnar spacer SP is provided on the counter substrate CT, is formed on the side of the common electrode CE facing the array substrate AR, and is covered with the second alignment film AL2. Such a columnar spacer SP supports the array substrate AR at a position between the second switching element SW2 and the third switching element SW3, and forms a cell gap.

  The liquid crystal layer LQ is held in a cell gap formed between the array substrate AR and the counter substrate CT, and is disposed between the first alignment film AL1 and the second alignment film AL2.

  On the outer surface of the array substrate AR, that is, the outer surface 10B of the first insulating substrate 10 constituting the array substrate AR, the first optical element OD1 including the first polarizing plate PL1 is attached with an adhesive or the like. The first optical element OD1 is located on the side facing the backlight 4 of the liquid crystal display panel LPN, and controls the polarization state of incident light incident on the liquid crystal display panel LPN from the backlight 4.

  On the outer surface of the counter substrate CT, that is, the outer surface 20B of the second insulating substrate 20 constituting the counter substrate CT, the second optical element OD2 including the second polarizing plate PL2 and the like is attached with an adhesive or the like. The second optical element OD2 is located on the display surface side of the liquid crystal display panel LPN, and controls the polarization state of the outgoing light emitted from the liquid crystal display panel LPN.

  The counter substrate CT having the above configuration is manufactured as follows, for example.

  That is, after the second insulating substrate 20 is prepared and the light shielding layer BM is formed on the inner surface 20A, the first color filter CF1 and the third color filter CF3 are formed, and then the second color filter CF2 is formed, and the common electrode After forming the CE, the columnar spacer SP is formed, and the second alignment film AL2 is formed. Accordingly, the second color filter CF2 is connected to the first color filter CF1, the third color filter CF3, and the common electrode CE at a position facing the first switching element SW1, the second switching element SW2, and the third switching element SW3. Between.

  According to the present embodiment, at least two types of color filters CF are stacked on the side of the light shielding layer BM facing the array substrate AR at a position facing the switching element SW. For this reason, it becomes possible to suppress the reflection of the backlight light at the light shielding layer BM, and it is possible to reduce the reflected light from the light shielding layer BM toward the switching element SW. For this reason, even when the switching element SW is formed of a bottom-gate thin film transistor, the light leakage current can be reduced. Therefore, display defects (flicker, crosstalk, etc.) due to light leakage current can be improved, and a liquid crystal display device with good display quality can be provided.

  Further, when the light shielding layer BM is formed of a metal material, it is possible to obtain a high optical density with a thin film thickness as compared with the case where the light shielding layer BM is formed of a resin material, and to reduce the level difference of the light shielding layer BM. Is possible. On the other hand, the light shielding layer BM formed of a metal material may have a higher reflectance than the light shielding layer formed of a resin material. For this reason, as a countermeasure against the reflection of the backlight light at the light shielding layer BM, a configuration in which the above-described plural types of color filters CF are stacked is extremely effective.

  In addition, according to the present embodiment, the columnar spacer SP for forming a cell gap between the array substrate AR and the counter substrate CT is on the same straight line in the region where two types of color filters are stacked. It arrange | positions in the position which opposes between the two switching elements located in a line. For this reason, the columnar spacer SP can be disposed on a flat surface having almost no step. Therefore, the top positions of the columnar spacers SP (surfaces supporting the array substrate AR) can be aligned, and a uniform cell gap can be formed. As a result, it is possible to improve display defects caused by nonuniform cell gaps.

  Note that the columnar spacer SP may be formed on the second insulating film 12 of the array substrate AR. In this case, for example, the columnar spacer SP is located between the second switching element SW2 and the third switching element SW3, and the second collar The counter substrate CT is supported immediately below the region where the filter CF2 and the third color filter CF3 overlap. Even in such a case, since the surface on the counter substrate CT side supported by the columnar spacers SP is flattened, a uniform cell gap can be formed.

  In addition, according to the present embodiment, the columnar spacers SP are arranged in color pixels that display the color with the lowest transmittance (for example, color pixels that display blue). For this reason, when alignment processing is performed on the alignment film, even if a defect in the alignment processing occurs due to the influence of the columnar spacers SP, it is difficult to be visually recognized during display, and deterioration of display quality can be suppressed. It becomes.

  Next, another configuration example of this embodiment will be described. In addition, about the same structure as the structure demonstrated in said example, the same referential mark is attached | subjected and detailed description is abbreviate | omitted.

  FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of a liquid crystal display panel LPN to which a counter substrate CT having another configuration is applied.

  Compared to the configuration shown in FIG. 4, the configuration shown here is such that the second color filter CF2 is opposed to the first switching device SW1, the second switching device SW2, and the third switching device SW3. The difference is that the light shielding layer BM is disposed between the first color filter CF1 and the third color filter CF3.

  The counter substrate CT having the above configuration is manufactured as follows, for example.

  That is, the second insulating substrate 20 is prepared, the light shielding layer BM is formed on the inner surface 20A, the second color filter CF2 is formed, and then the first color filter CF1 and the third color filter CF3 are formed. After forming the CE, the columnar spacer SP is formed, and the second alignment film AL2 is formed.

  Even when such a counter substrate CT is applied, the same effect as that obtained when the counter substrate CT shown in FIG. 4 is applied can be obtained.

  As described above, according to this embodiment, it is possible to provide a liquid crystal display device with good display quality.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device LPN ... Liquid crystal display panel AR ... Array substrate CT ... Opposite substrate LQ ... Liquid crystal layer PE ... Pixel electrode CE ... Common electrode SW1 ... First switching element SW2 ... Second switching element SW3 ... Third switching element CF1 ... 1st color filter CF2 ... 2nd color filter CF3 ... 3rd color filter SP ... Columnar spacer

Claims (10)

A first substrate comprising: a first switching element disposed in a first color pixel; a second switching element disposed in a second color pixel; and a third switching element disposed in a third color pixel;
A light shielding layer facing the first switching element, the second switching element, and the third switching element, and a layer disposed on the first color pixel and stacked on the light shielding layer at a position facing the first switching element. A first color filter, a third color filter disposed on the third color pixel and stacked on the light shielding layer at a position facing the second switching element and the third switching element, and a second color pixel And a second color filter that overlaps the first color filter at a position facing the first switching element and that overlaps the third color filter at a position facing the second switching element and the third switching element. A second substrate comprising:
A liquid crystal layer held between the first substrate and the second substrate;
A liquid crystal display device comprising: The first switching element, the second switching element, and the third switching element are located on the same straight line,
2. The liquid crystal display device according to claim 1, wherein the second color filter is formed in a strip shape facing each of the first switching element, the second switching element, and the third switching element. .   The liquid crystal display device according to claim 1, wherein the first switching element, the second switching element, and the third switching element are bottom-gate thin film transistors.   4. The liquid crystal display device according to claim 1, further comprising a columnar spacer that forms a cell gap between the second substrate and the first substrate. 5.   5. The columnar spacer according to claim 4, wherein the columnar spacer is disposed in a color pixel that displays a color having the lowest transmittance among the first color pixel, the second color pixel, and the third color pixel. Liquid crystal display device.   The columnar spacer is disposed at a position facing the second switching element and the third switching element in a region where the second color filter and the third color filter overlap each other. The liquid crystal display device according to claim 4 or 5.   The liquid crystal display device according to claim 1, wherein the light shielding layer is made of a metal material. A first switching element; a first pixel electrode electrically connected to the first switching element; a second switching element; a second pixel electrode electrically connected to the second switching element; A first substrate comprising a switching element and a third pixel electrode electrically connected to the third switching element;
a) A first opening disposed opposite to the first switching element, the second switching element, and the third switching element, and opposed to the first pixel electrode, and opposed to the second pixel electrode. A light shielding layer having a second opening and a third opening facing the third pixel electrode; and b) the light shielding layer disposed in the first opening and facing the first switching element. C) a third color filter disposed in the third opening and disposed on the light shielding layer at a position facing the second switching element and the third switching element. D) is disposed in the second opening and overlaps the first color filter at a position facing the first switching element, and the second switching element and the second switching element, A second color filter that overlaps the third color filter at a position facing the three switching elements; and e) the first pixel electrode, the second pixel electrode, and a common electrode facing the third pixel electrode. A second substrate provided;
A liquid crystal layer held between the first substrate and the second substrate;
A liquid crystal display device comprising:   The second color filter is located between the first color filter, the third color filter, and the common electrode at a position facing the first switching element, the second switching element, and the third switching element. 9. A liquid crystal display device according to claim 8, wherein   The second color filter is located between the light shielding layer, the first color filter, and the third color filter at a position facing the first switching element, the second switching element, and the third switching element. 9. A liquid crystal display device according to claim 8, wherein

Images