JP2013012114A - Storage device, communication system and control method for storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simply-structured storage device without a circuit configuration such as a terminal, wiring, etc. for connecting a reset signal line, and provide a cartridge, a communication system and a control method for the storage device.SOLUTION: A storage device 20 starts data communications synchronized with a clock signal SCK after receiving input of the clock signal SCK and a data signal SDA and being initialized through resetting. The storage device 20 comprises a reset processing unit 27 that: determines whether or not multiple level changes occur in the data signal SDA in a period when the clock signal SCK maintains a high level; and resets the storage device 20 when the level changes occur.

Description

  The present invention relates to a storage device that performs data communication with a host computer, a cartridge, a communication system, and a storage device control method.

  A system is known in which communication between a storage device and a host computer that controls the storage device is performed using three lines of a clock signal line, a data signal line, and a reset signal line (for example, Patent Documents). 1).

  In the system described in Patent Document 1, communication between a storage device provided in an ink cartridge of an ink jet printer and a host computer provided on the main body side of the printer is performed using three lines of a clock signal line, a data signal line, and a reset signal line. Is what you do. In this system, when accessing the storage device from the host computer, the host computer sends a reset signal to the storage device via the reset signal line. When the storage device receives the reset signal, the storage device executes a reset. For example, the storage device is initialized by clearing a register provided in the storage device. After the storage device is initialized, data communication synchronized with the clock signal is started between the storage device and the host computer, and this data communication allows the host computer to access the memory array of the storage device. ing.

Japanese Patent Laid-Open No. 2002-14870

  However, since the system described in Patent Document 1 needs to mount three signal lines, a clock signal line, a data signal line, and a reset signal line, circuit configurations such as wiring and terminals on the storage device and host computer side are required. There was a problem of increasing complexity. For this reason, an increase in design man-hours for circuit design and an increase in product cost have been brought about.

  Further, for example, when a plurality of ink cartridges are attached to one printer, such as an ink jet printer in which different ink cartridges are attached for each ink color, a plurality of storage devices are provided for one host computer. System. In this system, when a clock signal line, a data signal line, and a reset signal line are wired to each storage device, the circuit configuration becomes more complicated.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A storage device including a first terminal to which a clock signal is input, a second terminal to which a data signal is input, and a storage unit, and controls data communication using the clock signal and the data signal And a communication control unit that starts data communication for accessing the storage unit by the data signal synchronized with the clock signal after being initialized by reset, and the period during which the clock signal maintains the predetermined level. A storage device comprising: a reset execution unit that causes the communication control unit to execute the reset when a level change occurs a plurality of times in a data signal.

  According to this configuration, reset is executed when a level change occurs in the data signal a plurality of times during a period in which the clock signal maintains a predetermined level, and data communication for accessing the storage unit of the storage device after the reset is performed. Be started. Therefore, the storage unit of the storage device can be accessed by the clock signal and the data signal. Compared to the storage device described in Patent Document 1, a circuit configuration such as a terminal and wiring for connecting the reset signal line is provided. A storage device with a simple configuration can be obtained. In addition, since the circuit configuration can be simplified, the number of design steps for the storage device can be reduced, and the product cost can be reduced.

  Application Example 2 In the storage device, the reset execution unit causes the data signal to undergo multiple level changes in a period during which the clock signal is maintained at the predetermined level after the clock signal is changed to the predetermined level. In this case, the storage control device causes the communication control unit to execute the reset.

  According to this configuration, it is possible to more accurately determine the timing for executing the reset using the level change in which the clock signal is changed to a predetermined level.

  Application Example 3 In the storage device, the storage unit stores first identification information, and the communication control unit compares the first identification information with second identification information input by the data signal. Then, when the first identification information and the second identification information match, access to the storage unit in the data communication is permitted.

  According to this configuration, when the first identification information stored in the storage unit matches the second identification information input by the data signal, access to the storage unit by data communication is permitted. Access to the department can be managed appropriately.

  Application Example 4 The storage device includes a count unit that counts the number of times the level of the data signal has changed after the data communication is started, and the communication control unit is based on a count value of the count unit. A storage device that acquires the second identification information.

  According to this configuration, after starting data communication, the second identification information is acquired according to the number of times the level of the data signal has changed, and access to the storage unit is permitted by the first identification information and the second identification information. The Therefore, it is possible to appropriately manage access to the storage unit.

  Application Example 5 In the storage device, the storage device includes a count unit that counts the number of times the level of the data signal has changed in a period in which the clock signal maintains the predetermined level, and the communication control unit includes: A storage device that acquires the second identification information based on a count value.

  According to this configuration, the second identification information is acquired according to the number of times the level has changed during the period in which the clock signal maintains a predetermined level, and the storage unit is accessed by the first identification information and the second identification information. Allowed. Therefore, it is possible to appropriately manage access to the storage unit.

  Application Example 6 A cartridge including a storage device having a first terminal to which a clock signal is input, a second terminal to which a data signal is input, and a storage unit, the storage device including the clock signal and A communication control unit for controlling data communication by the data signal and starting data communication for accessing the storage unit by the data signal synchronized with the clock signal after being initialized by reset; and the clock signal is the predetermined signal And a reset execution unit that causes the communication control unit to execute the reset when a level change occurs a plurality of times in the data signal in a period in which the level is maintained.

  According to this configuration, a cartridge having a simple configuration without a circuit configuration such as a terminal and wiring for connecting the reset signal line can be realized.

  Application Example 7 A communication system in which a storage device having a storage unit and a host device are connected via a clock signal line and a data signal line, wherein the storage device includes a clock signal and the data of the clock signal line A communication control unit that controls data communication by a data signal of a signal line and starts data communication to access the storage unit by the data signal synchronized with the clock signal after being initialized by reset; and the clock signal A communication system, comprising: a reset execution unit that causes the communication control unit to execute the reset when a level change occurs a plurality of times in the data signal in a period in which the predetermined level is maintained.

  According to this configuration, it is possible to realize a communication system having a simple configuration in which there is no circuit configuration such as a terminal or wiring for connecting a reset signal line between the storage device or the host device or between the storage device and the host device. it can.

  Application Example 8 A method of controlling a storage device having a first terminal to which a clock signal is input, a second terminal to which a data signal is input, and a storage unit, wherein the clock signal has the predetermined level. The storage unit is accessed by the step of executing a reset when the data signal has undergone a plurality of level changes in the maintaining period, and the data signal synchronized with the clock signal after being initialized by the reset And a step of starting data communication.

  In this way, a storage device that is configured to be accessible by data communication after being initialized by reset can be accessed by using the clock signal and the data signal without using the reset signal.

1 is a block diagram showing a schematic configuration of a communication system according to a first embodiment. It is a general-view perspective view of an ink cartridge. It is the block diagram which showed the structure of the host computer. It is the block diagram which showed the data structure of the data sequence. It is the block diagram which showed the circuit structure inside a memory | storage device. 3 is a timing chart showing an example of a clock signal and a data signal. It is the block diagram which showed the structure of the reset process unit. It is the flowchart which showed the procedure of the process performed by the process performed by a host computer, and a memory | storage device. 6 is a timing chart showing an example of a clock signal and a data signal in the second embodiment. It is the block diagram which showed the structure of the reset process unit. 10 is a timing chart illustrating an example of a clock signal and a data signal according to the third embodiment. It is the flowchart which showed the procedure of the process performed by the process performed by a host computer, and a memory | storage device. It is explanatory drawing explaining a 1st modification.

(First embodiment)
Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, a communication system provided in an inkjet printer will be described as an example of the communication system.

  FIG. 1 is a diagram illustrating a schematic configuration of a communication system according to the first embodiment. As shown in FIG. 1, the communication system 1 includes a plurality of storage devices 20 (20 a to 20 d) and a host computer 10 as a host device of the storage device 20. As shown in FIG. 2, the storage device 20 is provided in each of the four color ink cartridges C1 to C4. For example, the storage device 20a is stored in the ink cartridge C1 containing cyan ink, the storage device 20b is stored in the ink cartridge C2 storing magenta ink, the storage device 20c is stored in the ink cartridge C3 storing yellow ink, and the black ink. Is stored in the ink cartridge C4. However, the number of storage devices 20 and the type of cartridge are not limited thereto. Examples of the host computer 10 include a printer controller arranged on the main body side of the ink jet printer.

  The storage device 20 (20a to 20d) is disposed on a memory module substrate provided in the ink cartridge C, and has a clock signal terminal (first terminal) CT and a data signal terminal (second terminal) DT. A clock signal line CL is connected to the clock signal terminal CT, and the clock signal line CL is connected to the host computer 10 via the clock bus CB. On the other hand, a data signal line DL is connected to the data signal terminal DT, and the data signal line DL is connected to the host computer 10 via the data bus DB.

  FIG. 3 is a diagram showing the configuration of the host computer 10. As shown in FIG. 3, the host computer 10 is a control device including a clock signal generation circuit 11, a power supply circuit 12, a power supply compensation circuit 13, a data storage circuit 14, and a control circuit 15 that controls each circuit. In addition to printing control, the host computer 10 controls access to the storage devices 20a to 20d, obtains data such as ink consumption and the mounting time of the ink cartridge C from the storage device 20, and stores them in the data storage circuit 14 and the like. I do.

  The power supply compensation circuit 13 supplies power to the storage device 20 for a predetermined period (for example, 0.3 s) even when power supply is interrupted. As a result, even if the power supply during data writing is cut off due to a power failure or the power plug being removed, the writing of data that should be prioritized for writing can be completed during the predetermined period. As the power supply compensation circuit 13, for example, a capacitor is used.

  The control circuit 15 controls the power supply circuit 12 to control the output of the positive power supply. The host computer 10 does not always supply power to the storage devices 20a to 20d, and supplies positive power to the storage devices 20a to 20d only when an access request to the storage devices 20a to 20d is generated. To do.

  The clock signal generation circuit 11 generates a clock signal SCK. The generated clock signal SCK is supplied to each of the storage devices 20a to 20d via the clock signal line CL.

  The control circuit 15 controls data communication with the storage device 20. When the data communication with the storage device 20 is performed, the control circuit 15 transmits a data string according to a predetermined format.

  Next, a data structure of a data string used in data communication between the host computer 10 and the storage device 20 will be described. FIG. 4 shows the data structure of the data string. As shown in FIG. 4, the data string 100 includes ID data (second identification information) 110, a read / write command 120, processing data 130, and ACK data 140. The ID data 110 is, for example, 3-bit data, and is used to designate a storage device 20 to be read or written from among the storage devices 20a to 20d of a plurality of ink cartridges mounted on the printer. Identification information. The read / write command 120 is a command for specifying a processing type of reading or writing with respect to the storage device 20. The processing data 130 is data that is a target of processing specified by the read / write command 120. Note that the read / write command 120 and the processing data 130 are paired, and the data string 100 repeatedly includes a set including the read / write command 120 and the processing data 130. The ACK data 140 is added to the end of the data string 100 transmitted from the storage device 20 to the host computer 10 and indicates that the processing according to the data string 100 transmitted by the host computer 10 has been normally performed. The host computer 10 sequentially sends the data constituting the above-described data string 100 to the storage device 20 by the data signal SDA in synchronization with the clock signal SCK. Thereby, data communication synchronized with the clock signal SCK is performed between the host computer 10 and the storage device 20.

  The control circuit 15 accesses the storage devices 20a to 20d through data communication in accordance with the data string 100 described above when the ink jet printer is turned on, the ink cartridge is replaced, the print job is finished, the ink jet printer is turned off, and the like. Run.

  Here, when accessing the storage device 20 from the host computer 10, the host computer 10 needs to cause the storage device 20 to perform a reset prior to access by data communication. That is, the storage device 20 is configured to be accessible by data communication synchronized with the clock signal SCK after being initialized by reset. Although details will be described later, in order to start data communication with the storage device 20, the storage device 20 is dealt with against a new access by initializing a register or the like provided in the storage device 20 by reset. This is because it needs to be in a possible state. For this reason, the control circuit 15 stores the storage device 20 when the host computer 10 accesses the storage device 20 such as when the inkjet printer is turned on, when the ink cartridge is replaced, when a print job is completed, or when the inkjet printer is turned off. Request reset.

  Next, the internal configuration of the storage device 20 will be described. FIG. 5 is a block diagram showing a circuit configuration inside the storage device 20. Hereinafter, the internal configuration of one storage device 20 will be described as an example, but the internal configuration of each of the storage devices 20a to 20d is the same except for the data stored in the memory array.

  As shown in FIG. 5, the storage device 20 includes a memory array 21, an address counter 22, a memory controller 23, an ID comparator 24, an operation code decoder 25, an I / O controller 26, and a reset processing unit 27. And. In the configuration of the storage device 20, the address counter 22, the ID comparator 24, the operation code decoder 25, and the I / O controller 26 correspond to the communication control unit 30 that controls data communication for accessing the memory array 21.

  The memory array 21 is a memory such as an EEPROM or a flash ROM that retains the storage content in a nonvolatile manner and can rewrite the storage content, and is a storage unit of the storage device 20. The memory array 21 has a storage area of a predetermined capacity, for example, 256 bits, and is configured to be accessible sequentially from the head address, that is, sequentially accessible. In the storage area of 3 bits from the head, identification data (first identification information) 210 determined in advance according to the type of ink cartridge C or the type of ink contained in the ink cartridge C is stored. The storage area of the fourth bit from the beginning is an invalid area. In the present embodiment, the identification data 210 is stored in the memory array 200 itself of the storage device 20, but the identification data 210 may be stored in a storage element provided separately from the memory array 200.

  The address counter 22 is a circuit that increments the count value in synchronization with the clock signal SCK, and is connected to the clock signal terminal CT, the memory array 21, and the reset processing unit 27. The count value of the address counter 22 is associated with the storage area position (address) of the memory array 21, and the write position or read position in the memory array 21 can be designated by the count value of the address counter 22.

  Further, when the reset signal RST from the reset processing unit 27 is input, the address counter 22 performs initialization by resetting the count value to an initial value. Here, the initial value may be any value as long as it is associated with the head position of the memory array 21. For example, “0” is used as the initial value.

  The memory controller 23 is connected to the memory array 21, the address counter 22 and the I / O controller 26. Under the control of the I / O controller 26, the area of the address designated by the address counter 22 in the storage area of the memory array 21. Write / read information to / from. Specifically, processing for reading information from the memory array 21 and transferring it to the I / O controller 26, processing for receiving information to be written from the I / O controller 26 and writing it to the storage area of the memory array 21, and the like are performed.

  The ID comparator 24 is connected to the clock signal terminal CT, the data signal terminal DT, the I / O controller 26 and the operation code decoder 25, and the ID data included in the data string 100 input via the data signal terminal DT. 110 and the identification data 210 stored in the memory array 21 are compared to determine whether they match. The ID comparator 24 also stores a 3-bit first register 240 that stores the ID data 110 input from the host computer 10 and identification data 210 acquired from the memory array 21 via the I / O controller 26. And a second register 241. The ID comparator 24 permits access from the host computer 10 to the memory array 21 when the ID data 110 stored in the first register 240 matches the identification data 210 stored in the second register 241. An access permission signal EN to that effect is sent to the operation code decoder 25.

  The ID comparator 24 is initialized by receiving the reset signal RST from the reset processing unit 27. The initialization of the ID comparator 24 is performed by clearing information stored in the first register 240 and the second register 241. After initialization, the ID comparator 24 waits for input of new ID data 110. When the data string 100 is sent from the host computer 10 in this state, the ID data 110 included in the data string 100 is acquired. It is configured to store in the first register 240. Further, the ID comparator 24 acquires the identification data 210 from the memory array 21 via the I / O controller 26 at a predetermined timing such as after the ID data 110 is stored in the first register 240, and the second register 241. To store.

  The operation code decoder 25 is connected to the clock signal terminal CT, the data signal terminal DT, the ID comparator 24, and the I / O controller 26, and acquires the read / write command 120 from the data string 100 sent from the host computer 10. To do. When the access permission signal EN is input from the ID comparator 24, the operation code decoder 25 analyzes the acquired read / write command 120 and sends a write processing request or a read processing request to the I / O controller according to the analysis result. 26.

  The I / O controller 26 is connected to the clock signal terminal CT, the data signal terminal DT, the memory controller 23, the operation code decoder 25, and the reset processing unit 27, and transfers data to the memory array 21 in accordance with a request from the operation code decoder 25. The direction and the data transfer direction for the data signal terminal DT are switched and controlled.

  Further, the I / O controller 26 performs initialization in response to the input of the reset signal RST from the reset processing unit 27. The initialization of the I / O controller 26 sets the data transfer direction with respect to the memory array 21 to the read direction, and sets the signal line connected to the data signal terminal DT to high impedance, thereby transferring data to the data signal terminal DT. This is done by banning. The initialized state is maintained until a write processing request or a read processing request is input from the operation code decoder 25. Therefore, the data of the first 4 bits of the data string 100 (that is, the ID data 110 and the read / write command 120) input via the data signal terminal DT after the reset signal RST is input is written to the memory array 21. There is no. On the other hand, the data stored in the first 4 bits of the memory array 21 (the 4th bit is invalid data) is read-only and sent to the ID comparator 24.

  Here, as described above, in the communication system 1 according to the present embodiment, when the storage device 20 is accessed from the host computer 10, the information stored in the first register 240 of the storage device 20 is cleared prior to the access. Therefore, it is necessary to keep the ID comparator 24 waiting for input of the ID data 110. Therefore, when the host computer 10 newly accesses the storage device 20 and reads or writes information from or to the memory array 21, the host computer 10 resets to the storage device 20 prior to access by data communication. And the storage device 20 needs to be initialized.

  However, in the communication system 1 configured as described above, since the reset signal line is not provided between the host computer 10 and the storage device 20 as in the system described in Patent Document 1, the host computer is connected via the reset signal line. The reset signal cannot be sent from the memory 10 to the storage device 20.

  Therefore, in the communication system 1 according to the present embodiment, when the host computer 10 starts to access the storage device 20, the clock signal level (high / low) and the data signal level (high / low) are A combination of level changes not synchronized with the clock signal SCK is used as a reset request.

  FIG. 6 is a timing chart showing an example of a combination of a clock signal and a data signal corresponding to the reset request. As shown in FIG. 6, in the present embodiment, as a combination of signals corresponding to the reset request, during the period (time T1 to T4) in which the clock signal SCK is raised and maintained high, the data signal SDA is By raising from low to high (time T2) and falling to low (time T3), a plurality of level changes are caused. This series of level change combinations is used as a reset request. That is, between the host computer 10 and the storage device 20, it is predetermined that the level changes of the clock signal SCK and the data signal SDA shown at times T1 to T4 in FIG. 6 correspond to the reset request. When the host computer 10 starts access to the storage device 20, the host computer 10 causes the clock signal SCK and the data signal SDA to change the level described above prior to data communication, so that the host computer 10 accesses the storage device 20. Request a reset. Thereby, even if the signal line for the reset signal is not connected between the host computer 10 and the storage device 20, the host computer 10 requests the storage device 20 to be reset.

  After causing the clock signal SCK and the data signal SDA to change the level corresponding to the reset request, the host computer 10 performs data communication using the data signal SDA in synchronization with the clock signal SCK (after time T5 in FIG. 6). Since the format of data transmitted from the host computer 10 to the storage device 20 follows the data string 100 described above, the data string 100 is configured in synchronization with the rising edge of the clock signal SCK after data communication is started at time T5 in FIG. The host computer 10 accesses the memory array 21 of the storage device 20 by transmitting data sequentially from the top ID data 110 among the data to be processed. The method of synchronizing the clock signal SCK in data communication is not limited to the method of synchronizing with the rising timing of the clock signal SCK, but is synchronized with the falling timing of the clock signal or both the rising and falling timing. You may make it make it.

  In addition, the storage device 20 includes a reset processing unit 27 in order to perform processing for causing the storage device 20 to perform a reset in response to the above-described reset request. The reset processing unit 27 is connected to the clock signal terminal CT, the data signal terminal DT, the address counter 22, the ID comparator 24, and the I / O controller 26. As shown in FIG. A reset execution unit 271.

  The reset request determination unit 270 monitors the clock signal SCK and the data signal SDA and determines whether or not a level change corresponding to the above-described reset request has occurred. The reset execution unit 271 determines the address counter 22, the ID comparator 24, and the I / O controller when the level change corresponding to the reset request has occurred in the clock signal SCK and the data signal SDA as determined by the reset request determination unit 270. A reset signal RST is sent to 26. This causes the components of the address counter 22, ID comparator 24, and I / O controller 26 to be reset.

  Next, the operation of the communication system 1 will be described in detail. FIG. 8 is a flowchart showing a procedure of processing performed by the host computer 10 and processing performed by the storage device 20. Hereinafter, description will be given according to the signal waveform example shown in FIG. 6 and the flowchart of FIG.

  The process of FIG. 8 is started when the ink jet printer is turned on, when the ink cartridge is replaced, when the print job is finished, when the power of the ink jet printer is shut off, and the like. When the processing is started, the host computer 10 requests the storage device 20 to reset the clock signal SCK and the data signal SDA by a combination corresponding to the reset request shown in FIG. That is, the control circuit 15 of the host computer 10 controls the clock signal generation circuit 11 to raise the level of the clock signal SCK from low to high (time T1, step S10). After rising the clock signal SCK, the control circuit 15 changes the data signal SDA from low to high and then to low (time T2, T3, step S11), and then changes the level of the clock signal SCK from high to low. (Time T4, Step S12). Note that the period (time T1 to T4) from when the clock signal SCK rises to high and returns to low is used in normal data communication so that the level change of the data signal SDA can be reliably detected on the storage device 20 side. It is preferable that the period be longer than one clock.

  On the other hand, on the storage device 20 side, the reset request determination unit 270 monitors the clock signal SCK and the data signal SDA, detects the rising edge of the clock signal SCK (time T1, step S20), and then from the data signal SDA. When a level change corresponding to the reset request, that is, a low level change, a high level change, or a low level change is detected (time T2, T3, step S21), a series of level changes detected in steps S20 and S21 are detected. It is determined that this is a reset request from. In this case, the reset execution unit 271 resets the storage device 20 by sending a reset signal RST (step S22). However, in the process of FIG. 8, the storage device 20 is reset after detecting the low, high, and low level changes of the data signal SDA, but the rising edge of the clock signal SCK and the low, high, and low level changes of the data signal SDA. Then, after detecting the falling edge of the clock signal SCK, the storage device 20 may be reset.

  To reset the storage device 20, the reset execution unit 271 sends a reset signal RST to each component of the communication control unit 30, that is, the address counter 22, the ID comparator 24, and the I / O controller 26 to perform initialization. This is done by executing. By this reset, the address counter 22 clears the count value, and the ID comparator 24 clears the first register 240 and the second register 241. The I / O controller 26 sets the data transfer direction with respect to the memory array 21 to the read direction, and prohibits data transfer by setting the signal line connected to the data signal terminal DT to high impedance.

  If the reset request determination unit 270 detects the falling edge of the clock signal SCK after detecting the rising edge of the clock signal SCK but before the data signal SDA changes in level of low, high, or low, This is a level change that can occur in normal data communication synchronized with the clock signal SCK, and is not a level change corresponding to the above-described reset request, so that no reset is performed.

  When the storage device 20 is reset, data communication according to the data string 100 is started between the host computer 10 and the storage device 20. The host computer 10 transmits the ID data 110 by data communication of the data signal SDA synchronized with the clock signal SCK (step S13). The storage device 20 receives the ID data 110 from the host computer 10, and the ID comparator 24 stores the ID data 110 in the first register 240 (step S23).

  Next, the ID comparator 24 acquires the identification data 210 stored in the memory array 21 via the I / O controller 26, stores it in the second register 241, and stores the ID data 110 stored in the first register 240. Then, it is determined whether or not the identification data 210 stored in the second register 241 matches (step S24). If the ID data 110 and the identification data 210 match (step S24: Yes), data communication according to the data string 100 is performed between the host computer 10 and the storage device 20, and access control to the memory array 21 is performed. Is done. More specifically, the host computer 10 performs data communication with the storage device 20 by sequentially transmitting a read / write command 120, processing data 130, and ACK data 140 in accordance with the data string 100 (step S14). On the storage device 20 side, the operation code decoder 25 and the I / O controller 26 perform processing according to the received read / write command 120, processing data 130, and ACK data 140, so that the host computer 10 transfers to the memory array 21. Access such as writing and reading of the information is controlled (step S25). Then, when the operation code decoder 25 of the storage device 20 interprets the ACK data 140 included in the transmitted data string 100, it is determined that the access from the host computer 10 to the memory array 21 is completed, and the processing of FIG. Ends.

  If it is determined in step S24 that the ID data 110 and the identification data 210 do not match (step S24: No), access from the host computer 10 to the memory array 21 is prohibited, and the process of FIG. finish.

  According to the first embodiment described above, the storage device 20 starts data communication with the host computer 10 after being initialized by reset, and the host computer 10 accesses the memory array 21. It is configured as follows. On the other hand, the host computer 10 raises the data signal SDA from low to high and then goes low while raising the clock signal SCK and maintaining the high state prior to accessing the memory array 21 of the storage device 20. The storage device 20 is requested to be reset by causing a falling level change, that is, two level changes. When this reset request is detected on the storage device 20 side, the storage device 20 is reset. Therefore, even if the signal line for the reset signal is not connected between the host computer 10 and the storage device 20, the host computer 10 requests the reset to the storage device 20 and resets the data, and then performs data communication with the storage device 20. Starting, access to the memory array 21, that is, information can be read from the memory array 21, and information can be written to the memory array 21. Further, it is possible to eliminate a reset signal line, a terminal for connecting the reset signal line, a wiring, or the like to the storage device 20 or the host computer 10 or a circuit board between the storage device 20 and the host computer 10. For this reason, the circuit configuration of the communication system 1 including the storage device 20 and the host computer 10 can be simplified to reduce the number of design steps and the product cost.

  When the host computer 10 starts data communication with the storage device 20, the host computer 10 sends out ID data 110 through data communication synchronized with the clock signal SCK. The storage device 20 stores the identification data 210 stored in the memory array 21. And the ID data 110 match, access to the memory array 21 by data communication is permitted. Therefore, access from the host computer 10 to the storage device 20, that is, access to the memory array 21 can be appropriately managed.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the first embodiment, the host computer 10 sends a reset request to the storage device 20 and then transmits the ID data 110 to the storage device 20 by data communication synchronized with the clock signal SCK. In the second embodiment, the ID signal 110 is transmitted to the storage device 20 by repeatedly generating a level change that changes the level of the data signal SDA from low to high and from high to low a number of times corresponding to the ID data. To do. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 9 is a timing chart showing an example of a clock signal and a data signal used in the second embodiment. As shown in FIG. 9, while the clock signal SCK rises from low to high and maintains the high signal state (time T10 to T13), the data signal SDA rises from low to high (time T11). When a level change occurs from low to low (time T2), this signal combination is set as a reset request. This is the same as in the first embodiment.

  In the second embodiment, after a reset request is made, the host computer 10 changes the level from low to high and from high to low for the number of times corresponding to the ID data 110 with the clock signal SCK being low. It is generated in the data signal SDA. In the example of FIG. 9, corresponding to the case where the ID data is “2”, a level change that changes from low to high and from high to low is generated twice at times T14 to T15 and times T16 to T17. Yes. Thus, the host computer 10 requests the storage device 20 to reset and sends the ID data 110 to the storage device 20 in the form of the number of level changes.

  Further, as described above, the storage device side of the communication system according to the second embodiment performs processing corresponding to the ID data transmitted as the number of data signal level changes, so that the reset of the first embodiment is performed. Instead of the processing unit 27, a reset processing unit 27 ′ shown in FIG. 10 is provided. The reset processing unit 27 ′ includes a reset request determination unit 270, a reset execution unit 271, a pulse number counter 272, and an ID data transmission unit 273. The reset request determination unit 270 and the reset execution unit 271 are the same as those in the first embodiment.

  The pulse number counter 272 counts the number of times the level of the data signal SDA after the reset request has been changed from low to high and from high to low. The ID data sending unit 273 receives the count value from the pulse number counter 272 and sends this count value to the ID comparator 24 as the ID data 110.

  The ID comparator 24 stores the ID data 110 received from the reset processing unit 27 ′ in the first register 240 and determines whether the ID data 110 and the identification data 210 stored in the second register 241 match. Since the data communication performed between the host computer 10 and the storage device 20 when the ID data 110 and the identification data 210 match in this determination is the same as in the first embodiment, a detailed description will be given. Omitted.

  According to the second embodiment described above, the host computer 10 requests the storage device 20 to reset using the clock signal SCK and the data signal SDA, and then changes the level change corresponding to the ID data 110 to the data. By generating the signal SDA, the memory array 21 of the storage device 20 can be accessed. Therefore, the same effect as the first embodiment can be obtained. Further, since the ID data 110 is sent to the storage device 20 due to the level change of the data signal SDA, the ID data 110 can be reliably sent even when the clock signal SCK is not stable.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the second embodiment, the host computer 10 makes a reset request to the storage device 20, and then causes the data signal SDA to change the level by the number of times corresponding to the ID data 110, whereby the ID data is stored in the storage device 20. In the third embodiment, the ID data 110 is transmitted by causing the level change of the data signal SDA by the number of times corresponding to the ID data 110 together with the reset request.

  FIG. 11 shows an example of a clock signal and a data signal used in the third embodiment. As shown in the drawing, in the period (time T20 to T25) in which the clock signal SCK rises from low to high and maintains the high state, the data signal SDA rises from low to high and then falls to low. When (time T21 to T22) occurs, this signal combination is set as a reset request. This is the same as in the first embodiment and the second embodiment.

  Further, the host computer 10 causes the data signal SDA to change the level from low to high and from high to low for the number of times corresponding to the ID data 110 during the period when the clock signal SCK is high in the reset request. . In the example of FIG. 11, corresponding to the case where the ID data 110 is “2”, the level change from low to high and from high to low is generated twice at times T21 to T22 and times T23 to T24. . In this way, the host computer 10 sends the ID data 110 to the storage device 20 as the number of level changes together with a reset request to the storage device 20. In the present embodiment, the level change (time T21 to T22) of the data signal SDA used in the reset request is counted as one time, but the level change used in the reset request is added to the ID data 110. It may not be included in the number of corresponding level changes.

  Further, on the storage device side of the communication system of the third embodiment, as in the second embodiment, a reset request determination unit 270, a reset execution unit 271, a pulse number counter (count unit) 272, an ID A reset processing unit 27 ′ having a data transmission unit 273 is provided.

  In the third embodiment, the processing performed by the pulse number counter 272 is different from that of the second embodiment. That is, as described above, the pulse number counter 272 counts the number of level changes from low to high and from high to low during the period when the clock signal SCK is high due to a reset request. Other configurations (reset request determination unit 270, reset execution unit 271, ID data transmission unit 273) are the same as those in the second embodiment.

  Next, the operation of the communication system 1 will be described. FIG. 12 is a flowchart showing a procedure of processes executed by the host computer 10 and the storage device 20. Hereinafter, description will be given according to the signal waveform example shown in FIG. 11 and the flowchart of FIG.

  When the processing of FIG. 12 is started, the host computer 10 requests the storage device 20 to be reset by the clock signal SCK and the data signal SDA. For this reason, the host computer 10 first raises the level of the clock signal SCK from low to high (time T20, step S30). After the rise of the clock signal SCK, the host computer 10 performs the data signal SDA for the number of times corresponding to the ID data 110. Is changed from low to high and from high to low (time T21 to 24, step S31). Thereafter, the level of the clock signal SCK falls from high to low (time T25, step S32).

  On the other hand, on the storage device 20 side, the reset request determination unit 270 of the reset processing unit 27 monitors the clock signal SCK and the data signal SDA and detects the rising edge of the clock signal SCK (time T20, step S40). The number counter 272 counts the number of times the level of the data signal SDA has changed (time T21 to 24, step S41). When the reset request determination unit 270 detects the falling edge of the clock signal SCK (time T25, step S42), the reset request determination unit 270 detects that the series of level changes detected in steps S40 to S42 are from the host computer 10. It is determined that the request is a reset request, and the storage device 20 is reset (step S43). Note that the counting in step S41 is performed until the falling of the clock signal SCK is detected in step S42.

  Next, the ID data sending unit 273 uses the count value of the pulse number counter 272, that is, the number of level changes occurring in the data signal SDA during the period in which the clock signal SCK is kept high as the ID data 110, and the ID data 110 is ID The data is sent to the comparator 24 (step S44).

  Subsequent steps S45, S46, and S33 are the same as steps S24, S25, and S14 in the first embodiment. That is, the ID comparator 24 compares the ID data 110 stored in the first register 240 with the identification data 210 stored in the second register 241 and determines whether or not they match (step S45). If the ID data 110 and the identification data 210 match (step S45: Yes), data communication is started between the host computer 10 and the storage device 20, and the host computer 10 executes the read / write command 120, Processing data 130 and ACK data 140 are transmitted (step S33). On the storage device 20 side, the operation code decoder 25 and the I / O controller 26 perform processing according to the received read / write command 120, processing data 130, and ACK data 140, so that the host computer 10 transfers to the memory array 21. Access such as writing and reading of the information is controlled (step S46). When the operation code decoder 25 of the storage device 20 interprets the ACK data 140 included in the transmitted data string 100, or when the ID data 110 and the identification data 210 do not match in the determination in step S45. (Step S25: No), the process of FIG.

  According to the third embodiment described above, the host computer 10 requests the storage device 20 to reset, and changes the level change in which the level of the data signal SDA changes from low to high and from high to low. As many times as the number of times corresponding to the number of times, the memory array 21 can be accessed by performing data communication with the storage device 20. Therefore, the same effect as the first embodiment and the second embodiment can be obtained. Further, unlike the first and second embodiments, the ID data 110 is transmitted to the storage device 20 together with the reset request, so that access to the memory array 21 can be started at an earlier timing. it can.

  The first to third embodiments of the present invention have been described above. However, the present invention is not limited to these embodiments, and can be changed and improved without departing from the spirit and scope of the claims. Of course, the present invention includes equivalents thereof. Various modes can be used without departing from the spirit of the invention. Hereinafter, modified examples will be described.

(Modification 1)
In the first to third embodiments, the level change of the data signal SDA to be low, high, and low while the clock signal SCK is high is used as a reset request from the host computer 10 to the storage device 20. The combination of the clock signal SCK and the data signal SDA corresponding to the reset request is not limited to this. In other words, in the data communication using the data signal SDA synchronized with the clock signal SCK, it is only necessary to decide in advance between the host computer 10 and the storage device 20 that a combination of signals that are not normally used is a reset request. . For example, as shown in FIG. 13A, in the period (time T30 to T33) in which the clock signal SCK falls from the high level and becomes the low level (time T30 to T33), the data signal SDA changes twice from low, high, and low. The level change (time T31, T32) may be a reset request. In addition, as shown in FIG. 13B, in the period (time T40 to T43) in which the clock signal SCK rises from low and is high (time T40 to T43), the data signal SDA changes twice as high, low, and high. The level change (time T41, T42) may be a reset request. However, the number of times that the level of the data signal SDA is changed in the reset request is not limited to two, and a greater number of level changes may be included in the reset request.

  Further, the reset request may be made by changing the level of only the data signal SDA a plurality of times without changing the level of the clock signal SCK. Even in this case, since the combination of the clock signal SCK and the data signal SDA is not used in the data communication synchronized with the clock, it is confused with the data communication signal synchronized with the clock on the storage device 20 side. The reset request can be correctly recognized. However, when the level of the clock signal SCK is maintained after the clock signal SCK is changed to a high or low level as in the first to third embodiments, the level change of the clock signal SCK is also used. Since the reset request is determined, the reset request can be determined more reliably.

(Modification 2)
In the second and third embodiments, the data signal SDA is counted as one time including the level change from low to high and the level change from high to low, and this count value is used as ID data. However, the number of times the level changes from low to high and the number of level changes from high to low may be counted separately, and the sum of both count values may be used as ID data. Alternatively, only one level change may be counted.

(Modification 3)
In the first to third embodiments, the identification data 210 used for permitting access to the memory array 200 is stored in the memory array 200 itself of the storage device 20. The identification data 210 may be stored in a separate storage unit.

(Modification 4)
In the first to third embodiments, the configuration including the storage device 20 for storing the ink cartridge information in the ink cartridge for the ink jet printer has been described. However, the storage device and the communication system according to the present invention are in this mode. It is not limited to. The present invention can be applied to a storage device provided in various replacement parts such as a toner cartridge and a developing unit of a laser printer, and a communication system including the storage device.

  DESCRIPTION OF SYMBOLS 1 ... Communication system, 10 ... Host computer, 20 ... Memory | storage device, 21 ... Memory array as a memory | storage part, 22 ... Address counter, 23 ... Memory controller, 24 ... ID comparator, 25 ... Operation code decoder, 26 ... I / O controller 27 ... reset processing unit 30 ... communication control unit 100 ... data string 110 110 ID data as second identification information 120 ... read / write command 130 ... processing data 210 ... first identification information 270 ... Reset request determination unit, 271 ... Reset execution unit, 272 ... Pulse number counter as count unit, 273 ... ID data transmission unit, CT ... Clock signal terminal as first terminal, DT ... Second terminal Data signal terminal as SCK ... Clock signal , SDA ... data signal.

Claims (8)

A storage device having a first terminal to which a clock signal is input, a second terminal to which a data signal is input, and a storage unit,
A communication control unit for controlling data communication by the clock signal and the data signal, and starting data communication for accessing the storage unit by the data signal synchronized with the clock signal after being initialized by reset;
A reset execution unit that causes the communication control unit to execute the reset when a level change occurs a plurality of times in the data signal during a period in which the clock signal maintains the predetermined level. Storage device. The storage device according to claim 1,
The reset execution unit causes the communication control unit to receive the change in level when the data signal has undergone a plurality of level changes in a period of maintaining the predetermined level after the clock signal has changed to the predetermined level. A storage device characterized by causing a reset to be executed. The storage device according to claim 1 or 2,
The storage unit stores first identification information,
The communication control unit compares the first identification information with the second identification information input by the data signal, and when the first identification information and the second identification information match, the data A storage device that permits access to the storage unit in communication. The storage device according to claim 3.
A count unit that counts the number of times the level of the data signal has changed after starting the data communication;
The communication control unit acquires the second identification information based on a count value of the count unit. The storage device according to claim 3.
A counting unit that counts the number of times the level of the data signal has changed in a period in which the clock signal maintains the predetermined level;
The communication control unit acquires the second identification information based on a count value of the count unit. A cartridge including a storage device having a first terminal to which a clock signal is input, a second terminal to which a data signal is input, and a storage unit,
The storage device
A communication control unit for controlling data communication by the clock signal and the data signal, and starting data communication for accessing the storage unit by the data signal synchronized with the clock signal after being initialized by reset;
A reset execution unit that causes the communication control unit to execute the reset when a level change occurs a plurality of times in the data signal during a period in which the clock signal maintains the predetermined level. cartridge. A communication system in which a storage device having a storage unit and a host device are connected via a clock signal line and a data signal line,
The storage device
Controls data communication by the clock signal of the clock signal line and the data signal of the data signal line, and starts data communication to access the storage unit by the data signal synchronized with the clock signal after being initialized by reset A communication control unit,
A reset execution unit that causes the communication control unit to execute the reset when a level change occurs a plurality of times in the data signal during a period in which the clock signal maintains the predetermined level. Communications system. A control method of a storage device having a first terminal to which a clock signal is input, a second terminal to which a data signal is input, and a storage unit,
Performing a reset when a plurality of level changes occur in the data signal in a period in which the clock signal maintains the predetermined level;
And a step of starting data communication for accessing the storage unit by the data signal synchronized with the clock signal after being initialized by the reset.

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