JP2013010226A - Driving circuit of inkjet head, and inkjet head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving circuit of an inkjet head, which achieves both high voltage output and high speed data transmission, and to provide the inkjet head.SOLUTION: The driving circuit of the inkjet head has a driving section outputting a driving voltage waveform to apply potentials chosen from a common potential and K pieces of potentials to a prescribed number of loads, respectively, and discharges ink by driving the prescribed number of loads. The driving section is structured by stacking a plurality of semiconductor chips, and a minimum wiring width in at least one from among the plurality of semiconductor chips is narrower than a minimum wiring width in the other semiconductor chip. A first semiconductor chip having the narrower minimum wiring width, has a selection signal output section parallely outputting K pieces of driving voltage selection signals per driving voltage waveform on the basis of input data. Other semiconductor chip has a driving voltage waveform generation section generating a driving voltage waveform when the driving voltage selection signal is input.

Description

  The present invention relates to an inkjet head drive circuit and an inkjet head.

  Conventionally, by applying a voltage to a piezoelectric element provided on the wall surface of a pressure chamber that stores ink and changing the pressure in the pressure chamber, ink is ejected from nozzles communicating with the pressure chamber, and an image is printed on the printing surface. There is an ink jet printer provided with an ink jet head to be formed.

  In recent years, with improvement in performance of inkjet printers, improvement in accuracy of inkjet heads has been demanded. Patent Document 1 discloses a technique for improving gradation reproducibility by providing a plurality of voltage application patterns. Patent Document 2 discloses that wiring by a connector stacked in the height direction is performed between a pressure chamber portion of an inkjet head and a drive circuit that drives the pressure chamber, thereby eliminating the need for wire bonding and improving the accuracy. Techniques for integration are disclosed.

JP 2006-240048 A JP 2006-279016 A

  On the other hand, in order to increase the number of display pixels of the ink jet printer, it is necessary to increase the number of nozzles and the number of pressure chambers per unit area. In order to achieve such high integration, it is necessary to downsize individual pressure chambers and miniaturize wiring. However, in order to eject ink from a small pressure chamber, it is necessary to apply a higher voltage than in the past. Then, wiring of a drive circuit having a high voltage resistance performance for supplying a high voltage is required, and there is a problem that the drive circuit becomes large and it becomes difficult to transmit more data at high speed. . Due to these conflicting demands, there is a problem that it is difficult to increase the degree of integration in a drive circuit for driving a conventional ink jet head.

  An object of the present invention is to provide an ink-jet head drive circuit and an ink-jet head that can be highly integrated with both high voltage output and high-speed data transmission.

In order to achieve the above object, the present invention described in claim 1
One or a plurality of driving units for outputting a driving voltage waveform for applying a potential selected from the common potential or K (K ≧ 1) potentials to a predetermined number of loads are provided, and the predetermined number A drive circuit for an inkjet head that ejects ink by driving a load,
The drive unit is configured by laminating a plurality of semiconductor chips,
The minimum wiring width in the wiring formed in at least one of the plurality of semiconductor chips is narrower than the minimum wiring width in the wiring formed in the other semiconductor chips,
The first semiconductor chip having the smallest minimum wiring width includes a selection signal output unit that outputs K driving voltage selection signals in parallel per one driving voltage waveform based on input data,
Of the plurality of semiconductor chips, a second semiconductor chip excluding the first semiconductor chip includes a drive voltage waveform generation unit that generates the drive voltage waveform when the drive voltage selection signal is input. It is a feature.

According to a second aspect of the present invention, in the drive circuit for an ink jet head according to the first aspect,
The selectable number K of potentials applied to each of the predetermined number of loads is 2 or more.

According to a third aspect of the present invention, in the inkjet head drive circuit according to the second aspect,
The drive voltage waveform generation unit is provided in a separate second semiconductor chip for each potential selectable as a potential applied to each of the predetermined number of loads.

According to a fourth aspect of the present invention, in the drive circuit for an ink jet head according to any one of the first to third aspects,
The first semiconductor chip and the second semiconductor chip are wired with a wiring width set based on a supplied voltage range.

According to a fifth aspect of the present invention, in the drive circuit for an inkjet head according to any one of the first to fourth aspects,
The second semiconductor chip is stacked above the first semiconductor chip,
Input / output of signals to and from the second semiconductor chip is performed through the first semiconductor chip.

A sixth aspect of the present invention is the inkjet head drive circuit according to any one of the first to fourth aspects,
The first semiconductor chip is stacked above all the second semiconductor chips,
Input / output of signals to / from the first semiconductor chip is performed through the second semiconductor chip.

According to a seventh aspect of the present invention, in the inkjet head drive circuit according to the sixth aspect,
Only the power supply voltage used in the first semiconductor chip is supplied from the second semiconductor chip to the first semiconductor chip.

The invention according to claim 8 is the drive circuit of the ink jet head according to any one of claims 1 to 7,
The drive voltage selection signal output terminal provided on the first semiconductor chip and the drive voltage selection signal input terminal provided on the second semiconductor chip are respectively arranged in a staggered manner. It is a feature.

The invention according to claim 9 is the drive circuit for an ink jet head according to any one of claims 1 to 8,
The selection signal output unit includes:
A shift register that stores input data in sequence;
A latch circuit that stores the input data stored in the shift register and output in parallel, and outputs the input data at a specified timing;
And a waveform selection unit that generates and outputs the drive voltage selection signal for each of the input data output from the latch circuit.

According to a tenth aspect of the present invention, in the inkjet head drive circuit according to the fifth aspect,
The first semiconductor chip is mounted on a substrate.

The invention according to claim 11
A drive circuit for an inkjet head according to any one of claims 1 to 10,
An ink discharge unit that discharges ink based on a drive voltage waveform output from the drive circuit of the inkjet head; and
An inkjet head comprising:

  According to the present invention, there is an effect that it is possible to achieve both high voltage output and high speed data transmission in the inkjet head drive circuit.

It is sectional drawing which shows the whole structure of the inkjet head of embodiment of this invention. It is a figure explaining the flow of the signal in an inkjet head. It is a figure explaining the flow of the signal in an inkjet head. It is a block diagram explaining the internal structure of a drive circuit. It is a side view which shows the structure of the drive circuit of 1st Embodiment. It is a top view which shows the structure of each IC chip in the drive circuit of 1st Embodiment. It is a figure explaining the drive voltage waveform generation circuit in a drive circuit. It is a figure which shows the drive voltage waveform output from an analog part. It is a side view which shows the structure of the drive circuit of 2nd Embodiment. It is a top view which shows the structure of each IC chip in the drive circuit of 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a cross-sectional view showing the overall structure of the inkjet head according to the first embodiment of the present invention.

  The inkjet head 1 according to the first embodiment includes an ink discharge unit 100 in which a head substrate 10 and a wiring substrate 20 are bonded by an adhesive resin layer 30 and a drive circuit that performs driving for discharging ink droplets from the ink discharge unit 100. 200. In addition, an ink chamber 40 that stores ink therein is provided at an upper portion of the ink discharge unit 100. The wiring board 20 is provided with an FPC (flexible printed circuit board) 50, and the drive circuit 200 is provided on the FPC 50.

The ink ejection unit 100 includes, as an ink flow path, a hole 21 that passes through the wiring substrate 20 and conveys ink in the ink chamber 40 downward, and a pressure chamber 12 that communicates with the hole 21 and stores ink. And a nozzle 11 that communicates with the lower surface of the pressure chamber 12 and discharges ink in the pressure chamber 12 as ink droplets. In addition, the inkjet head 1 is configured to perform an ink ejection operation. The vibration plate 13 covers the upper surface of the pressure chamber 12, the piezoelectric element 16 as a load disposed on the vibration plate 13, and the piezoelectric element 16. The common electrode 14 located on the lower surface, the individual electrode 15 located on the upper surface of the piezoelectric element 16, the bumps 17 and 22 for connecting the individual electrode 15 to the wiring of the wiring board 20, and the FPC 50 and the bump 22 on the wiring board 20 An upper wiring 25, a metal terminal 24, a lower wiring 23, and the like, which are signal paths between them, are provided.
These pressure chamber 12, diaphragm 13, common electrode 14, individual electrode 15, piezoelectric element 16, bumps 17 and 22, lower wiring 23, metal terminal 24, upper wiring 25, and hole 21 are each one nozzle. One nozzle mechanism is provided for each of the nozzles 11 to form a set of nozzle mechanisms.

The pressure chamber 12 has an upper surface covered with the diaphragm 13 and is connected to the nozzle 11 on the lower surface. The pressure chamber 12 applies pressure to the ink stored therein according to the vibration of the diaphragm 13 and pushes the ink to the nozzle 11. The diaphragm 13 is disposed between the piezoelectric element 16 (electrode 14) and the pressure chamber 12. The diaphragm 13 vibrates according to the deformation of the piezoelectric element 16 and changes the pressure in the pressure chamber 12.
For example, PZT (lead zirconate titanate, piezo) is used as the piezoelectric element 16. The piezoelectric element 16 is provided between the common electrode 14 and the individual electrode 15 disposed above and below the piezoelectric element 16, and is deformed according to a potential difference between the common electrode 14 and the individual electrode 15 to vibrate the diaphragm 13. This is an actuator that changes the pressure in the pressure chamber 12.
Each circuit is provided between the individual electrode 15 and the drive circuit 200. The drive voltage waveform output from the drive circuit 200 is supplied to each individual electrode 15. On the other hand, each common electrode 14 is a common electrode connected to a common potential. In the inkjet head 1 of the present embodiment, the ground potential VH0 is applied as a common potential.
The nozzles 11 eject the ink pushed out from the pressure chamber 12 as ink droplets.

Here, as the inkjet head 1 of the present embodiment, a total of 1024 rows of 256 arranged nozzle mechanisms are provided, and arranged as a first nozzle row to a fourth nozzle row 110a to 110d (see FIG. 2). The case where this is done will be described. For example, the nozzle rows 110a to 110d are arranged with a resolution of 300 dpi (dot per inch) in the nozzle row direction. The nozzles in the four nozzle rows 110a to 110d arranged in parallel are arranged so as to complement each other, and the inkjet head 1 can output at a resolution of 1200 dpi as a whole. . In the case of 1200 dpi resolution, the distance between nozzles (nozzle pitch) is about 21.2 μm. In addition, when 1-bit image data for 1024 nozzles is input in series and ink is ejected at an ejection frequency of 50 kHz, data input at about 50 MHz is required.
The number of nozzle mechanisms arranged is not limited to this. Moreover, the same inkjet head 1 can be arranged for each of a plurality of colors.

  2 and 3 are diagrams for explaining the flow of signals in the inkjet head.

As shown in FIG. 2, corresponding to the nozzle rows 110 a to 110 d of the ink discharge unit 100, the drive circuit 200 is provided with four drive units 210 a to 210 d.
Image data, control signals, and drive signals are input to these four drive units 210a to 210d, respectively, and converted into drive voltage waveforms. Then, this drive voltage waveform is supplied to the piezoelectric elements 16 of the nozzle mechanisms of the nozzle arrays 110 a to 110 d, and ink is ejected from the nozzles 11.
These input signals and data will be described in detail later.

As illustrated in FIG. 3, each of the driving units 210 a to 210 d includes a first driving IC (Integrated Circuit) 211 and a second driving IC 212. The first drive IC 211 and the second drive IC 212 are cascade-connected, and half of the image data inputted in series to the first drive IC 211 is further sent to the second drive IC 212 and inputted. Then, a drive voltage waveform for causing each nozzle mechanism to eject ink at a predetermined ejection frequency (for example, 50 kHz) is output.
At this time, the first drive IC 211 generates and outputs drive voltage waveform outputs out1 to out128 to be supplied to each of the piezoelectric elements 16 provided on the wall surface of the pressure chamber 12 in the 128 nozzle mechanisms. Further, from the second drive IC 212, drive voltage waveform outputs out129 to out256 supplied to each of the piezoelectric elements 16 provided on the wall surface of the pressure chamber 12 in the other 128 nozzle mechanisms are generated and output. .

  Note that the data transfer timings by the driving units 210a to 210d and the ink ejection timings of the nozzle arrays 110a to 110d are controlled independently or in conjunction with each other.

Next, the internal configuration of the drive circuit will be described.
FIG. 4 is a diagram illustrating the internal configuration of the drive circuit.
Here, since the configuration of each of the drive units 210a to 210d in the drive circuit 200 is the same, and the configuration of the first drive IC 211 and the second drive IC 212 is also the same, hereinafter, the first drive IC 210a in the drive unit 210a. The drive IC 211 will be described.

  The first drive IC 211 of this embodiment includes a shift register 221, a latch circuit 222, a waveform selection unit (grayscale controller) 223, and a buffer amplifier 231. The first driving IC 211 is formed on different IC chips for a logic unit 220 (selection signal output unit) that performs logical operations using a digital circuit and an analog unit 230 (drive voltage waveform generation unit) that performs analog processing. Thus, signals are exchanged between the IC chips.

The logic unit 220 includes a shift register 221, a latch circuit 222, a waveform selection unit 223, and the like.
The shift register 221 receives 2-bit data Sin0 and Sin1 per pixel per display color as image data from the outside of the inkjet head 1, for example, from a control circuit of the inkjet printer, in synchronization with the transfer clock signal DCLK. The 128 pieces of image data Sin0 and Sin1 are stored in the order of input to the shift register 221 for each bit of data, and are output collectively to the latch circuit 222 as parallel data. The shift register 221 of the first driving IC 211 receives 256 pieces of image data for each bit, and the 128 pieces of image data that have been input first are received from the shift register 221 of the first driving IC 211. After being output as Sout0 and Sout1, they are input as input data Sin0 and Sin1 to the second cascaded drive IC 212. Accordingly, a total of 256 data is output in parallel from the shift register 221 of the first driving IC 211 and the second driving IC 212.

  The latch circuit 222 holds each data output from the shift register 221 until the timing specified by the latch signal LAT, and outputs the data to the waveform selection unit 223.

  Based on the image data signal input from the latch circuit 222, the waveform selection unit 223 synchronizes a selection signal (drive voltage selection signal) for generating a desired drive voltage waveform in the analog unit 230 with the synchronization clock signal GSCLK. To the buffer amplifier 231 of the analog unit 230. The waveform selection unit 223 outputs two selection signals for generating one drive voltage waveform from the two output buses DA1 and DA2 in parallel. That is, the waveform selection unit 223 is provided with 128 sets and 256 output buses.

  On the other hand, the analog unit 230 includes a buffer amplifier 231. Two selection signals output from the output buses DA1 and DA2 of the logic unit 220 are input to the buffer amplifier 231 via the input buses DB1 and DB2 of the analog unit 230. The buffer amplifier 231 generates drive voltage waveforms for 128 channels based on these selection signals and the power supply voltages VH1 and VH2 input to the buffer amplifier 231 and outputs the drive voltage waveforms to each nozzle mechanism of the nozzle array 110a.

  Next, the arrangement of each component in the drive circuit will be described.

  FIG. 5 is a side view showing the structure of the drive circuit provided on the FPC.

  As shown in FIG. 5, in the drive circuit 200 of this embodiment, a logic IC chip 211a (first semiconductor chip) on which a logic unit 220 is mounted and an analog IC chip 211b (second semiconductor) on which an analog unit 230 is mounted. The chip is stacked on the FPC 50. In the driving circuit 200 of the first embodiment, the logic IC chip 211a is disposed on the FPC 50, and the analog IC chip 211b is disposed on the logic IC chip 211a. Bumps are provided between the stacked FPC 50, logic IC chip 211a, and analog IC chip 211b as will be described in detail later, so that the FPC 50, logic IC chip 211a, and analog IC chip 211b Pads (metal electrodes) arranged on opposing surfaces are connected to each other, and signals and power are exchanged with each other. Thus, by dividing the drive circuit into a plurality of chips, it is possible to provide circuits on the upper and lower surfaces of each chip.

FIG. 6 is a plan view of a logic IC chip on which a logic portion is mounted, and a plan view of an analog IC chip on which an analog portion is mounted.
6A shows the lower surface of the logic IC chip (FPC side), FIG. 6B shows the upper surface of the logic IC chip (analog IC chip side), and FIG. 6C shows the lower surface of the analog IC chip (logic The plan view on the IC chip side) is shown.

  On the lower surface of the logic IC chip 211a, as shown in FIGS. 5 and 6A, a power pad 2111 that receives power supplied from the power pad 2101 of the FPC 50 via the bump 2171 and a power pad 2111 are provided. A metal terminal 2112 that is connected and transmits power to the upper surface of the logic IC chip 211a through the logic IC chip 211a, a signal pad 2113 that receives a signal transmitted from the FPC 50, a logic unit 220 that performs logic operation processing, and logic A metal terminal 2115 that sends the selection signal output from the unit 220 to the upper surface of the logic IC chip 211a and a metal that is connected to the drive voltage pad 2117 and sends the drive voltage waveform sent from the upper surface of the logic IC chip 211a to the drive voltage pad 2117 Received from terminal 2118 and metal terminal 2118 A driving voltage pads 2117 to send a dynamic voltage waveform to the FPC50 is provided.

  The signal received by the signal pad 2113 from the signal pad 2103 of the FPC 50 via the bump 2173 includes 2-bit image data Sin0 and Sin1, the transfer clock signal DCLK, the latch signal LAT, the drive signals PLTIM0 to PLTIM2, and the synchronous clock signal GSCLK. . Further, the image data Sout0 and Sout1 output from the shift register 221 of the logic unit 220 are sent to the FPC 50 by the signal pad 2113.

  Various signals received from the FPC 50 by the logic IC chip 211a through the signal pad 2113 are sent to the logic unit 220 for processing, and 256 selection signals are output. The 256 signal lines that output 256 selection signals are respectively connected to the metal terminals 2115 and sent to the upper surface of the logic IC chip 211a. The metal terminal 2115 is, for example, TSV (Through Silicon Via), and is provided through the logic IC chip 211a in the vertical direction.

  As shown in FIG. 6B, the logic IC chip 211a has an upper surface penetrating from the lower surface, metal terminals 2112 provided through the lower surface, power supply pads 2121 connected to the metal terminals 2112 respectively. Are connected to the metal terminal 2118, the selection signal pad (FET drive pad) 2126 connected to the metal terminal 2115, the metal terminal 2118 provided through the lower surface, and the metal terminal 2118, respectively. A driving voltage pad 2127 and the like are arranged.

  As shown in FIG. 6C, a power supply pad 2131, a selection signal pad 2136, a drive voltage pad 2137, and an analog unit 230 are disposed on the lower surface of the analog IC chip 211b.

The power supply pad 2121 disposed on the upper surface of the logic IC chip 211a and the power supply pad 2131 disposed on the lower surface of the analog IC chip 211b are connected by the bump 2181 shown in FIG. 5, and the power supplied from the FPC 50 is The pad 2131 is reached. A plurality (three in this embodiment) of power supply pads 2131 arranged in one row correspond to input / output of different power supply voltages VH1, VH2 and ground voltage VH0, respectively. The same voltage is supplied in parallel using a plurality of power supply pads. The power supply pads are distributed and arranged at places where power is required. For example, as shown in FIG. 6, the power supply pads are arranged so as to be embedded in the logic unit 220 and the analog unit 230 (gap).
Here, the power supply voltage VH2 is not used in the logic IC chip 211a. Therefore, the power supply pad 2111 that has received the power supply voltage VH2 from the power supply pad 2101 on the FPC 50 is sent only from the power supply pad 2121 to the analog IC chip 211b on the upper surface of the logic IC chip 211a. On the other hand, the power supply voltage VH1 and the ground voltage VH0 are used in both the logic IC chip 211a and the analog IC chip 211b. Therefore, the power supply voltage VH1 and the ground voltage VH0 are supplied from the power supply pad 2111 to each part of the logic IC chip 211a. The power supply voltage VH1 and the ground voltage VH0 are supplied from the power supply pad 2121 on the upper surface of the logic IC chip 211a to the analog IC chip. 211b.
In the inkjet head 1 according to the present embodiment, a voltage equal to the voltage VH1 used for driving the analog IC chip 211b is used as a voltage for driving the logic IC chip 211a. However, a dedicated voltage different from the voltage VH1 is used. It is also possible to supply a logic circuit driving voltage (which is lower than the power supply voltage VH2).

As described above, by dividing the IC chip for each necessary voltage, it is possible to individually manufacture the logic IC chip 211a and the analog IC chip 211b having different characteristics. In general, the logic unit 220 requires a large number of logic circuits. Therefore, it is desired to reduce the wiring width to increase the degree of integration and to improve the response performance with respect to high-speed signal level changes. On the other hand, the analog unit 230 needs to have a high voltage resistance against input / output drive voltages, so it is desirable to increase the wiring width and the wiring pitch (interval between wirings).
Specifically, in the logic IC chip 211a on which the logic unit 220 is mounted, for example, the narrowest wiring among the wirings formed in the logic IC chip 211a as a thin wiring that can withstand only the power supply voltage VH1. The circuit is formed with the width (minimum wiring width) set to 300 nm. Note that, in the logic IC chip 211a, wirings connecting the power supply pads 2111, 2121 and the metal terminals 2112 for transmitting a driving voltage to be supplied to the analog unit 230, for example, parts other than the logic unit 220, and the driving voltage pads 2117, 2127 Since a high voltage is applied to the wiring that connects to the metal terminal 2118, it is necessary to form a wiring that is partially thicker than the set wiring width and has a wide wiring pitch.
On the other hand, in the analog IC chip 211b on which the analog unit 230 is mounted, the analog unit 230, the wiring for supplying the power supply voltage VH2 from the power supply pad 2131 to the analog unit 230, and the wiring from the analog unit 230 to the drive voltage pad 2137 are as follows. A power supply voltage VH2 can be applied. Therefore, in the analog IC chip 211b, as a wide wiring to which the power supply voltage VH2 can be applied, for example, a circuit is formed by setting the wiring width (minimum wiring width) and the wiring pitch to 1 μm. ing.
These wiring widths can be appropriately increased or decreased according to the values of the power supply voltages VH1 and VH2.

  The selection signal pad 2126 arranged on the upper surface of the logic IC chip 211a and the selection signal pad 2136 arranged on the lower surface of the analog IC chip 211b are connected by the bump 2186 shown in FIG. The 256 selection signals output from the logic unit 220 arranged on the logic IC chip 211a are arranged on the top surface of the logic IC chip 211a. The selection signal pads 2126 arranged in a staggered manner in two rows from the metal terminals 2115, and the analog IC By being sent to the selection signal pad 2136 having the same arrangement on the chip 211b, the expansion of the width due to the pad having a larger area than the metal terminal 2115 can be suppressed, and the circuit is complicated on the plane. Can be prevented. Then, a selection signal is input from the selection signal pad 2136 to the analog unit 230.

  On the other hand, on the lower surface of the analog IC chip 211b, the drive voltage waveform signal output from the analog unit 230 is sent to the drive voltage pad 2137, and further, the bump 2187, the drive voltage pad 2127, the metal terminal 2118, and the drive voltage pad 2117. The bumps 2177 and the drive voltage pads 2107 on the FPC 50 are sequentially output from the drive circuit and sent to the piezoelectric element 16 of each nozzle mechanism. In this way, a large number of drive voltages can be output to the piezoelectric elements 16 of each nozzle mechanism with an easy and simple laminated structure.

  In the drive circuit of this embodiment, the selection signal pads are arranged in two rows and the drive voltage pads are arranged in one row, but the present invention is not limited to these. The drive voltage pads may be arranged in two rows. In general, since an IC chip can form a circuit more precisely than an FPC, the circuit can be further integrated while suppressing the lateral width due to the arrangement of pads.

  Next, a specific configuration and procedure for generating a drive voltage waveform in the drive circuit will be described.

  FIG. 7 is a diagram illustrating a circuit configuration of a portion that generates and outputs a drive voltage waveform from the selection signal. Specifically, the configuration of a circuit that generates and outputs a drive voltage waveform to one piezoelectric element in the waveform selection unit 223 of the logic unit 220 and the buffer amplifier 231 of the analog unit 230 is shown.

  A selection circuit 2230 that outputs a selection signal for generating a drive voltage waveform for each of the piezoelectric elements 16 provided on the wall surface of the pressure chamber 12 is connected to each of the logic operation units 2231 and the piezoelectric elements 16 of one nozzle mechanism. And a selector 2232. In the waveform selection unit 223 of this embodiment, drive waveform pattern data for converting the value of image data into a waveform pattern is set in the logic operation unit 2231, and one of the image data is selected by the selector 2232 based on the drive waveform pattern data. One drive voltage waveform per bit is generated and output, and a selection signal in which two drive voltage waveforms are combined by the input 2-bit image data is output to the analog unit 230 in synchronization with the synchronous clock signal GSCLK. It is the composition to do.

  In the logical operation unit 2231, drive waveform pattern data for converting the image data signal input to the piezoelectric element 16 of the nth pressure chamber 12 input from the latch circuit 222 into two selection signals is set. In addition, the logical operation unit 2231 receives a set value necessary for setting the synchronous clock signal GSCLK and the drive waveform pattern data. Then, the set drive waveform pattern data is output from the logic operation unit 2231 to the selector 2232.

  Three types of drive signals PLSTIM0 to PLSTIM2 are input to the selector 2232 in synchronization with the synchronous clock signal GSCLK. The selection signal is generated based on these three types of drive signals input to the waveform selection unit 223. The three types of drive signals (Pulse Timing signals) are a non-ejection signal PLSTIM0, a first ejection signal PLSTIM1, and a second ejection signal PLTIM2. These three types of drive signals are digital data indicating temporal changes between the binary values of the high level and the low level. Based on the drive waveform pattern data input from the logic operation unit 2231, one of these three types of drive signals is selected, and the selector 2232 outputs two selection signals D1 and D2.

  Specifically, the selection signal D1 is a signal indicating the first ejection driving period (high level), and either the first ejection signal PLSTIM1 or the non-ejection signal PLTIM0 is selected and output. The selection signal D2 is a signal indicating the second ejection driving period (high level), and either the second ejection signal PLSTIM2 or the non-ejection signal PLSTIM0 is selected and output.

  On the other hand, the drive voltage waveform generation circuit 2310 in the buffer amplifier 231 has a first transistor TR1, a second transistor TR2, a third transistor TR3, respectively, for the piezoelectric element 16 of the nth nozzle mechanism. Inverters I1 and I2, a NOR circuit N1, and three level shifters L1 to L3 are included. The drive voltage waveform generation circuit 2310 receives a voltage VH1 from the first power supply, a voltage VH2 higher than the voltage VH1 from the second power supply, and a predetermined common potential VH0 (this embodiment) from the common power supply. In the embodiment, the ground voltage) is input. The level shifters L1 to L3 receive the voltage VH2 from the second power supply, and can boost the input signal voltage to the level of the power supply voltage VH2. Then, the generation circuit 2310 drives the piezoelectric element 16 of the nozzle mechanism by outputting any one of the voltages VH1, VH2, and the common potential VH0 from the output terminal Outn as the output voltage based on the selection signals D1, D2. The pressure chamber 12 is deformed to eject ink droplets.

The first transistor TR1 is a P-type FET (field effect transistor) having a drain terminal connected to the voltage VH1. The selection signal D1 is input to the gate terminal of the first transistor TR1 through the inverter I1 and the level shifter L1.
When the selection signal D1 is high level, the inverter I1 inverts the signal level and outputs a low level signal to the gate terminal. Then, the first transistor TR1 is turned on and the voltage VH1 is output. When the selection signal D1 is at the low level, the signal inverted to the high level by the inverter I1 is boosted to a voltage higher than the drain voltage by the level shifter L1 and inputted to the gate terminal, and the first transistor TR1 is turned off. Become. Accordingly, the voltage VH1 is not output from the first transistor TR1.

  The second transistor TR2 is a P-type FET having a drain terminal connected to the voltage VH2. The selection signal D2 is input to the gate terminal of the second transistor TR2 through the inverter I2 and the level shifter L2. When the selection signal D2 is at a high level, the inverter I2 inverts the signal level and outputs a low level signal to the gate terminal. Then, the second transistor TR2 is turned on and the voltage VH2 is output. When the selection signal D2 is at the low level, the signal inverted to the high level by the inverter I2 is boosted to the drain voltage level by the level shifter L2 and input to the gate terminal, and the second transistor TR2 is turned off. Therefore, the voltage VH2 is not output from the second transistor TR2.

The third transistor TR3 is an N-type FET whose source terminal is grounded. Further, the output signal of the NOR circuit N1 is input to the gate terminal of the third transistor TR3 via the level shifter L3.
The NOR circuit N1 outputs a NOR value for the two input values of the selection signals D1 and D2. When both the selection signals D1 and D2 are at a low level, a high level signal is output, and the high level signal is input to the gate terminal of the third transistor TR3 via the level shifter L3, and the third transistor TR3. Is turned on, the drain-source is rendered conductive, and the ground voltage level VH0 is output. When at least one of the selection signals D1 and D2 is at a high level, a low level signal is output from the level shifter L3, the third transistor TR3 is turned off and the drain-source is not conducted, and the ground voltage level VH0 Is not output.

The source terminal of the first transistor TR1, the source terminal of the second transistor TR2, and the drain terminal of the third transistor TR3 are connected to the output terminal Outn.
Here, the section of the high level output of the selection signal D1 based on the first ejection signal PLSTIM1 and the section of the high level output of the selection signal D2 based on the second ejection signal PLSIM2 are overlapped as described later (see FIG. 8). Therefore, the selection signal D1 and the selection signal D2 do not become high level at the same time. Accordingly, two or more of the first transistor TR1, the second transistor TR2, and the third transistor TR3 are not turned on at the same time. That is, the connection to the output terminal Outn is a wired OR connection, and the voltage VH1 output from the first transistor TR1, the voltage VH2 output from the second transistor TR2, or the output from the third transistor TR3. Any one of the ground voltage levels VH0 to be output is selectively output from the output terminal Outn.

  FIG. 8 is a diagram showing four types of drive voltage waveforms output from the buffer amplifier 231.

  As shown in FIGS. 8A to 8C, in the inkjet head 1 of the present embodiment, three types of drive voltage waveforms are used as ejection voltage waveforms for ejecting ink droplets. First, when the 2-bit image data is “1, 0”, as shown in FIG. 8A, the power supply voltage VH2 is applied in the first half of the waveform period corresponding to the high level timing of the second ejection signal PLSTIM2. A medium droplet discharge voltage waveform is output. Next, when the 2-bit image data is “0, 1”, as shown in FIG. 8B, the power supply voltage VH1 is applied in the latter half of the waveform period corresponding to the high level period of the first ejection signal PLSTIM1. A small droplet discharge voltage waveform is output. When the 2-bit image data is “1, 1”, as shown in FIG. 8C, the first half of the output voltage waveform includes the second ejection drive voltage VH2 based on the second ejection signal PLSTIM2. In the latter half of the output voltage waveform, a large droplet moving voltage signal from which the first discharge driving voltage VH1 is output based on the first discharge signal PLSTIM1 is output. When the 2-bit image data is “0, 0”, as shown in FIG. 8D, a non-ejection voltage waveform for preventing ink droplets from being ejected is obtained over the waveform period based on the non-ejection signal PLSTIM0. The ground voltage level VH0 is output.

  As described above, the first ejection signal PLSTIM1, the second ejection signal PLSTIM2, and the non-ejection signal in the two selection signals D1 and D2 output from the selection circuit 2230 with respect to the input of one 2-bit image data signal. The amount of ink ejected at a time is determined by the combination of PLSTIM0, that is, the color density of the ink in the pixel portion indicated by the image data is controlled.

  As described above, according to the inkjet head 1 of the first embodiment, the drive circuit is arranged and formed on the different IC chips 211a and 211b in the logic unit 220 and the analog unit 230, and the logic IC chip 211a is formed on the FPC 50. The analog IC chip 211b is further stacked on the logic IC chip 211a. With such a structure, a circuit with a large wiring width corresponding to the voltage required for the analog unit 230 and a circuit with a thin wiring width corresponding only to the voltage required for the logic unit 220 are formed on separate IC chips. Therefore, it is not necessary to form the wiring width of a circuit provided on one chip while controlling it in a complicated process, and the manufacturing process can be facilitated. In addition, by forming a large number of logic circuits, it is possible to form a logic unit that requires a large number of wirings and an analog unit that requires a wiring width due to the need to withstand high voltages, and a circuit that does not waste each of them. . In addition, by stacking two IC chips, wiring connection between the logic portion and the analog portion can be easily performed.

  In addition, since the wiring width of the logic unit 220 can be reduced, the quality and response characteristics of a signal to be transmitted can be improved, and thus the speed of logic operation can be increased.

  In particular, since the shift register 221 is formed on a chip having a narrow wiring width, the response characteristics of the input image data are improved, so that the image data can be transmitted at high speed.

  In addition, since the selection signal is transmitted in the vertical direction by stacking the logic IC chip 211a and the analog IC chip 211b, the analog unit 230 can easily output more selection signal output lines than the output of the drive voltage waveform to the nozzle unit. Can be sent to.

  Further, when transmitting a selection signal from the logic IC chip 211a to the analog IC chip 211b, it becomes possible to arrange the selection signal pads in a staggered manner, and a large number of selection signal lines can be output without increasing the width of the IC chips 211a and 211b. You can enter it.

[Second Embodiment]
The configuration of the ink jet head of the second embodiment is the same as that of the ink jet head of the first embodiment, and the same reference numerals are given and description thereof is omitted.
In the inkjet head of the second embodiment, the order of stacking the logic IC chip 211a and the analog IC chip 211b in the inkjet head of the first embodiment is reversed.

  FIG. 9 is a side view showing the structure of the drive circuit of the inkjet head of the second embodiment.

  As shown in FIG. 9, in the drive circuit 200 of the second embodiment, the analog IC chip 211c is arranged on the upper part of the FPC 50, and the logic IC chip 211d is arranged on the upper part of the analog IC chip 211c. Bumps are provided between the stacked FPC 50, analog IC chip 211c, and logic IC chip 211d, so that pads (metal electrodes) arranged on the FPC 50, analog IC chip 211c, and logic IC chip 211d are provided. ) Are connected, and signals and power are exchanged with each other.

FIG. 10 is a plan view of an analog IC chip on which an analog unit that constitutes a drive unit in the inkjet head according to the second embodiment is mounted, and a logic IC chip on which a logic unit is mounted.
10A shows the bottom surface of the analog IC chip (FPC side), FIG. 10B shows the top surface of the analog IC chip (logic IC chip side), and FIG. 10C shows the bottom surface of the logic IC chip (analog). The plan view on the IC chip side) is shown.

  As shown in FIGS. 9 and 10A, the lower surface of the analog IC chip 211c is connected to the power supply pad 2141 that receives power supplied from the FPC 50 and the power supply pad 2141, and penetrates through the analog IC chip 211c. A metal terminal 2142 that sends power to the upper surface of the analog IC chip 211c, a signal pad 2143 that receives a signal sent from the FPC 50, a metal terminal 2144 that sends a signal received by the signal pad 2143 to the upper surface of the analog IC chip 211c, and an analog A metal terminal 2145 that passes through the IC chip 211c and transmits a selection signal from the upper surface, an analog unit 230, a drive voltage pad 2147 that sends a drive voltage waveform to the FPC 50, and the like are provided.

  On the lower surface of the analog IC chip 211c, a selection signal generated by the logic IC chip 211d and transmitted from the upper surface of the analog IC chip 211c via the metal terminal 2145 is input to the analog unit 230, and a drive voltage waveform is generated. Is done. Then, the generated drive voltage waveform is output from the drive voltage pad 2147 to the drive voltage pad 2107 provided in the FPC 50 via the bump 2177 as shown in FIG. To the piezoelectric element 16.

  On the upper surface of the analog IC chip 211c, as shown in FIG. 10B, a metal terminal 2142 penetrating from the lower surface, a power pad 2151 connected to the metal terminal 2142, and a lower surface are provided. Metal terminals 2145, selection signal pads (FET drive pads) 2156 connected to the metal terminals 2145, metal terminals 2144 provided through the lower surface, and signal pads connected to the metal terminals 2144, respectively. 2153 and the like are arranged.

  As shown in FIG. 10C, a power supply pad 2161, a signal pad 2163, a selection signal pad 2166, and a logic unit 220 are disposed on the lower surface of the logic IC chip 211d.

  On the lower surface of the analog IC chip 211c, the power supplied from the power supply pad 2101 provided on the FPC 50 to the power supply pad 2141 via the bump 2171 is supplied to each part of the analog IC chip 211c, and the analog IC chip 211c is used to supply the analog IC. The power is supplied to the logic IC chip 211d by the power pads 2151 and 2161 which are sent to the upper surface of the chip 211c and connected via the bumps 2191. A plurality (three in this embodiment) of power supply pads 2141 arranged in one row correspond to supply of different power supply voltages VH1, VH2 and ground voltage VH0, respectively. Here, of the voltage levels of the power supply voltage supplied from the FPC 50, the higher voltage VH2 is used only in the analog IC chip 211c. Accordingly, the voltage VH2 may not be supplied to the logic IC chip 211d. In this case, instead, the ground voltage VH0 may be sent in two lines from the lower surface of the analog IC chip 211c, and the metal terminal 2142 and the power supply pad 2151 that transmit the voltage VH2 to the upper surface of the analog IC chip 211c are not provided. It is also good.

  Signals that the signal pad 2143 receives from the signal pad 2103 provided on the FPC 50 via the bumps 2173 on the lower surface of the analog IC chip 211c include image data Sin0 and Sin1, a transfer clock signal DCLK, a latch signal LAT, and drive signals PLSTIM0 to PLSTIM2. , A synchronous clock signal GSCLK is included. Further, the image data Sout0 and Sout1 output from the shift register 221 of the logic unit 220 are sent to the FPC 50 by the signal pad 2143. On the other hand, as described above, these signals used in the logic IC chip 211d are transmitted as they are to the upper surface of the analog IC chip 211c through the metal terminals 2144, and further from the signal pads 2153 through the bumps 2193. It is sent to the signal pad 2163 of 211d.

  On the lower surface of the logic IC chip 211d, a signal transmitted from the FPC 50 and transmitted to the signal pad 2163 of the logic IC chip 211d is input to the logic unit 220. In the logic unit 220, 256 selection signals for 128 nozzle mechanisms are generated and output to the selection signal pads 2166, respectively. The selection signal pads 2166 are staggered in two rows on the lower surface of the logic IC chip 211d. The selection signal is transmitted to the analog IC chip 211c by being connected to the upper surface of the analog IC chip 211c via the selection signal pad 2156 and the bump 2196 that are similarly arranged. In the analog IC chip 211 c, these selection signals are further sent from the upper surface to the lower surface by the metal terminal 2145 and then input to the analog unit 230.

  In the driving circuit of the second embodiment, the arrangement pattern of the selection signal pads and the driving voltage pads is not limited to the above. The lateral width of the IC chip may be further reduced by arranging the drive voltage pads in two rows or arranging the selection signal pads in three rows.

  As described above, according to the structure of the drive circuit of the second embodiment, the drive circuit is arranged and formed on different IC chips in the analog unit and the logic unit, and the analog IC chip 211c is arranged on the FPC 50. A logic IC chip 211d is further stacked on the chip 211c. Even with such a structure, many selection signal lines output from the logic unit 220 can be easily sent to the analog unit 230. In addition, a circuit having a thick wiring width (for example, the narrowest wiring width and wiring pitch is 1 μm) corresponding to the voltage required for the analog unit 230 and only a voltage required for the logic unit 220, and a signal level change. Since a circuit having a narrow wiring width with good response characteristics (for example, the narrowest wiring width and wiring pitch is 300 nm) can be formed independently, a driver circuit of an appropriate size can be easily obtained.

The present invention is not limited to the above-described embodiment, and various modifications can be made.
For example, in the above embodiment, one analog IC chip is provided independently of a logic IC chip for two types of power supply voltages. For example, one logic IC chip is provided for three types of power supply voltages. A chip and two analog IC chips may be provided, and different IC chips may be stacked for each supply voltage to the analog unit. In this case, the number of selection signal lines connecting the logic unit and the analog unit is the number obtained by multiplying the number of nozzles by the number of power supply voltages, and the effect related to the ease of wiring is more remarkable due to the stacked structure. Become.

  Even when three or more types of power supply voltages are used, the logic unit and the analog unit are divided into different IC chips, so that the logic unit that requires a shift register and many logic circuits is thin. The wiring width may be easily formed, and only the analog portion may be formed with a thick wiring width to correspond to the highest voltage level used.

  In the above embodiment, an ink jet head provided with an ink discharge mechanism using a piezoelectric thin film vibration (flexible type) on the upper wall of the ink chamber has been described. However, the form of the ink discharge mechanism is not limited to this. For example, it may be of a shear type (shear mode) that deforms the side wall of the ink chamber, or may be used for a thermal ink jet head.

  In the above embodiment, a plurality of 128-bit driver ICs are cascade-connected. However, other driver ICs may be used, or only one driver IC may be used. In addition, the specific configuration and arrangement shown in the above embodiment such as the number of bits of input image data, the number of latch circuits, the shape of the driving voltage waveform, and the output circuit are appropriately selected within the scope of the present invention. It can be changed.

DESCRIPTION OF SYMBOLS 1 Inkjet head 10 Head substrate 11 Nozzle 12 Pressure chamber 13 Diaphragm 14 Common electrode 15 Individual electrode 16 Piezoelectric element 17 Bump 20 Wiring board 21 Hole 22 Bump 23 Lower wiring 24 Metal terminal 25 Upper wiring 30 Adhesive resin layer 40 Ink chamber 50 FPC
100 Ink Ejecting Units 110a-110d Nozzle Row 200 Driving Circuits 210a-210d Driving Units 211, 212 Driving ICs
211a, 211d Logic IC chips 211b, 211c Analog IC chip 220 Logic unit 221 Shift register 222 Latch circuit 223 Waveform selection unit 2230 Selection circuit 2231 Logic operation unit 2232 Selector 230 Analog unit 231 Buffer amplifier 2310 Generation circuit TR1 to TR3 Transistors I1, I2 Inverter L1 to L3 Level shifter N1 NOR circuit 2101, 2111, 2121, 2131, 2141, 2151, 2161 Power supply pad 2112, 2115, 2118, 2142, 2144, 2145 Metal terminal 2113, 2143, 2153, 2163 Signal pad 2107, 2117, 2127, 2137, 2147 Driving voltage pads 2126, 2136, 2156, 2166 Selection signal pad 2 71,2173,2177,2181,2186,2187,2191,2193,2196 bump DA1, DA2 output bus DB1, DB2 input bus Outn output terminal

Claims (11)

One or a plurality of driving units for outputting a driving voltage waveform for applying a potential selected from the common potential or K (K ≧ 1) potentials to a predetermined number of loads are provided, and the predetermined number A drive circuit for an inkjet head that ejects ink by driving a load,
The drive unit is configured by laminating a plurality of semiconductor chips,
The minimum wiring width in the wiring formed in at least one of the plurality of semiconductor chips is narrower than the minimum wiring width in the wiring formed in the other semiconductor chips,
The first semiconductor chip having the smallest minimum wiring width includes a selection signal output unit that outputs K driving voltage selection signals in parallel per one driving voltage waveform based on input data,
Of the plurality of semiconductor chips, a second semiconductor chip excluding the first semiconductor chip includes a drive voltage waveform generation unit that generates the drive voltage waveform when the drive voltage selection signal is input. A drive circuit for an inkjet head. The inkjet head drive circuit according to claim 1, wherein the selectable number K of potentials applied to each of the predetermined number of loads is 2 or more. The said drive voltage waveform generation part is provided in the said 2nd semiconductor chip separate for every electric potential which can be selected as an electric potential each applied with respect to the said predetermined number of load. The said 2nd semiconductor chip is characterized by the above-mentioned. Ink jet head drive circuit. The said 1st semiconductor chip and the said 2nd semiconductor chip are wired by the wiring width set based on the voltage range supplied, respectively. A drive circuit for an ink jet head according to item. The second semiconductor chip is stacked above the first semiconductor chip,
5. The inkjet head drive circuit according to claim 1, wherein input / output of a signal to the second semiconductor chip is performed via the first semiconductor chip. 6. The first semiconductor chip is stacked above all the second semiconductor chips,
5. The inkjet head drive circuit according to claim 1, wherein input / output of a signal to the first semiconductor chip is performed via the second semiconductor chip. 6. The drive circuit of the ink jet head according to claim 6, wherein only a power supply voltage used in the first semiconductor chip is supplied from the second semiconductor chip to the first semiconductor chip. The drive voltage selection signal output terminal provided on the first semiconductor chip and the drive voltage selection signal input terminal provided on the second semiconductor chip are respectively arranged in a staggered manner. The drive circuit for an ink jet head according to claim 1, wherein the drive circuit is an ink jet head drive circuit. The selection signal output unit includes:
A shift register that stores input data in sequence;
A latch circuit that stores the input data stored in the shift register and output in parallel, and outputs the input data at a specified timing;
The waveform selection part which produces | generates and outputs the said drive voltage selection signal with respect to each of the said input data output from the said latch circuit is provided.The Claims 1-8 characterized by the above-mentioned. Ink jet head drive circuit. The inkjet head drive circuit according to claim 5, wherein the first semiconductor chip is mounted on a substrate. A drive circuit for an inkjet head according to any one of claims 1 to 10,
An ink discharge unit that discharges ink based on a drive voltage waveform output from the drive circuit of the inkjet head; and
An ink jet head comprising:

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