JP2013009051A - Solid state image pickup device and driving method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device which avoids deterioration of resolution in a vertical direction and has a wide dynamic range of detectable light signals and to provide a driving method of the solid state image pickup device.SOLUTION: The solid state image pickup device is provided with: a pixel part 1 in which plural pixels 2 each having a photoelectric converter are arranged two-dimensionally in matrix; a row selection circuit 3 which selects plural pixels 2 from which pixel signals are read, from each row of the pixel part 1; a control part 9 which gives a control signal to the row selection circuit 3 so as to change exposure times of the plural pixels 2 in a row selected by the row selection circuit 3, on a row-by-row basis; and a mixing part 7 which mixes the pixel signals read from the plural pixels 2 in the row selected by the row selection circuit 3, on a column-by-column basis.

Description

  The present invention relates to a solid-state imaging device and a driving method thereof, and more particularly to a technique for expanding a dynamic range.

  The dynamic range of an optical signal (pixel signal) that can be detected by a conventional solid-state imaging device is about 60 dB to 80 dB, about 100 dB to 120 dB that is comparable to the dynamic range of an optical signal that can be detected by the naked eye or a silver salt film, or an in-vehicle camera. In some applications such as surveillance cameras and the like, it is desired to improve to a higher level. Therefore, in Patent Document 1, light that can be detected by independently controlling the exposure time with an electronic shutter for adjacent rows, outputting pixel signals with high sensitivity and low sensitivity, and performing mixing by external signal processing. The dynamic range of the signal is expanded.

JP 2006-253876 A

  However, the technique of Patent Document 1 has a problem that the resolution in the vertical direction deteriorates because the exposure time is changed for each row. In addition, since there is no mixing means in the solid-state imaging device, there is a problem that a line memory or a frame memory is required for external signal processing.

  Accordingly, an object of the present invention is to provide a solid-state imaging device having a wide dynamic range of a detectable optical signal and a driving method thereof without degrading the vertical resolution.

  In order to achieve the above object, in the present invention, a pixel unit in which a plurality of unit pixels having photoelectric conversion elements are two-dimensionally arranged in a matrix and the plurality of unit pixels from which a pixel signal is read out include the pixel unit. A row selection circuit that selects each row, and a control unit that provides a control signal to the row selection circuit so as to change the exposure time in a plurality of unit pixels of the row selected by the row selection circuit for each row; A mixing unit that mixes, for each column, pixel signals read from a plurality of unit pixels in a row selected by the row selection circuit.

  According to this configuration, since the pixel signals detected at two different exposure times are mixed, the dynamic range of the pixel signals that can be detected can be expanded. Further, by switching the combination of rows to be mixed for each frame, it is possible to maintain the vertical resolution of continuous images.

  Further, the control unit may give a control signal to the row selection circuit so as to change the exposure time for each frame.

  According to this configuration, since the exposure time for each row is changed for each frame, the dynamic range of pixel signals that can be detected can be expanded without degrading the vertical resolution of different images.

  The mixing unit may be the row selection circuit, and the control unit may cause the row selection circuit to simultaneously select two or more rows of the pixel unit.

  According to this configuration, the read pixel signal can be mixed with the analog signal.

  The mixing unit may be an ADC counter.

  According to this configuration, the pixel signal can be mixed when the pixel signal of the read analog signal is converted into a digital signal.

  The ADC counter may be an up / down counter.

  According to this configuration, since the up-counting and the down-counting are continuously performed, it is possible to cancel the error signal superimposed on both the reference signal and the pixel signal.

  The mixing unit may be composed of a line memory and a signal processing circuit.

  According to this configuration, since pixel signals having different exposure times are held in the line memory and mixed by the signal processing circuit, it is possible to switch whether or not the pixel signals are mixed depending on the image area.

  Further, in the solid-state imaging device driving method, a control signal in which an exposure time is changed for each row is given to a plurality of unit pixels that have photoelectric conversion elements and are two-dimensionally arranged in a matrix. A reading step of reading out image signals from the plurality of unit pixels for each row, and a mixing step of mixing pixel signals read out from the plurality of unit pixels arranged in the same column with different exposure times by a mixing unit. Including.

  According to this configuration, since the pixel signals detected at two different exposure times are mixed, the dynamic range of the pixel signals that can be detected can be expanded.

  In the reading step, the exposure time may be changed every N (N is a natural number of 2 or more) rows within one frame.

  In the reading step, the exposure time may be changed for each frame.

  According to this configuration, since the exposure time for each row is changed for each frame, the dynamic range of pixel signals that can be detected can be expanded without degrading the vertical resolution of different images.

  In the mixing step, the mixing unit may change a combination of rows in which the plurality of pixels for mixing the pixel signals are arranged for each frame.

  According to this configuration, the vertical resolution of continuous images can be maintained by switching the combination of rows to be mixed for each frame.

  In the mixing step, the mixing unit may simultaneously select two or more rows of the unit pixels.

  In the mixing step, the ADC counter may sequentially add the read pixel signals without resetting the ADC counter for two or more rows.

  According to this configuration, since the read image signals are sequentially AD converted without resetting the ADC counter, the pixel signals read from the unit pixels in two or more rows when the analog signals are converted into digital signals. Can be added.

  A solid-state imaging device having a wide dynamic range of a detectable optical signal and a driving method thereof can be provided without degrading the resolution in the vertical direction.

It is a figure which shows the whole structure of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the structure of the pixel of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the structure of the column circuit part of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the structure of the multiplexer of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the structure of the column selection circuit of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the timing of each control signal regarding operation | movement of the pixel of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the timing of each control signal in the read-out operation | movement of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the combination of the exposure time of each line in the continuous flame | frame in Embodiment 1 of this invention, and the line mixed at the time of an output. It is a figure which shows the relationship between the light quantity in Embodiment 1 of this invention, and an output signal. It is a figure which shows the other example of the combination of the exposure time of each line in the continuous frame in Embodiment 1 of this invention, and the line mixed at the time of an output. It is a figure which shows the whole structure of the solid-state imaging device in Embodiment 2 of this invention. It is a figure which shows the detailed structure of column ADC of the solid-state imaging device in Embodiment 2 of this invention. It is a figure which shows the timing chart of column ADC of the solid-state imaging device in Embodiment 2 of this invention. It is a figure which shows the other timing chart of column ADC of the solid-state imaging device in Embodiment 2 of this invention. It is a figure which shows the timing chart of column ADC of the solid-state imaging device in Embodiment 3 of this invention. It is a figure which shows the whole structure of the solid-state imaging device in Embodiment 4 of this invention. It is a figure which shows the combination of the exposure time of each line in the continuous flame | frame in Embodiment 5 of this invention, and the line mixed at the time of an output.

  Embodiment 1 according to one embodiment of the present invention will be described below. In addition, although this invention is demonstrated using the following embodiment and attached drawing, this is for the purpose of illustration and this invention is not intended to be limited to these.

  The present invention provides a pixel portion in which a plurality of unit pixels having photoelectric conversion elements are two-dimensionally arranged in a matrix, and a row selection that selects the plurality of unit pixels from which pixel signals are read out for each row of the pixel portion. A circuit, a control unit for supplying a control signal to the row selection circuit so as to change an exposure time for each of the plurality of unit pixels in the row selected by the row selection circuit, and the row selection circuit. A mixing unit that mixes pixel signals read from a plurality of unit pixels in a row for each column.

  With this configuration, the dynamic range of an optical signal that can be detected can be expanded without degrading the vertical resolution.

(Embodiment 1)
FIG. 1 is a diagram showing an overall configuration of a solid-state imaging device 100 according to Embodiment 1 of the present invention.

  The solid-state imaging device 100 according to the present embodiment includes an imaging unit 1, a pixel (unit pixel) 2, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, and a sample hold (S / H) circuit. 6, a multiplexer (MUX) 7, a column selection circuit 8, a control unit 9, and an output amplifier 10. The pixel current source circuit 4, the clamp circuit 5, and the sample hold circuit 6 constitute a column circuit unit 20.

  The imaging unit 1 is an imaging region in which pixels 2 that perform photoelectric conversion are two-dimensionally arranged in a matrix. In the present embodiment, an example of 24 pixels arranged two-dimensionally in a 6 × 4 matrix is shown, but the actual total number of pixels is several million or more.

  The row selection circuit 3 includes three control lines of SEL, RST, and TRAN for each horizontal row, and resets (initializes), reads (reads), reads (resets) each pixel 2 of the imaging unit 1 in units of rows. Control line selection (line selection).

  The pixel current source circuit 4 includes a basic unit 4a of the pixel current source circuit in each column, the basic units 4a of the pixel current source circuit are arranged in an array in the column direction, and supplies a signal from the pixel 2 to the vertical signal line. For generating current.

  The clamp circuit 5 includes a clamp circuit basic unit 5a in each column, the basic units 5a of the clamp circuit are arranged in an array in the column direction, and a fixed pattern generated in the pixel 2 from an output in a row unit from the vertical signal line 19 Remove noise components.

  The S / H circuit 6 includes a basic unit 6a of the S / H circuit in each column, the basic units 6a of the S / H circuit are arranged in an array in the column direction, and hold the output of the row unit from the clamp circuit 5. .

  The MUX 7 switches the connection between each basic unit 6 a of the S / H circuit 6 and the output amplifier 10.

  The column selection circuit 8 includes a column selection signal line 30 and sequentially selects columns of the MUX 7.

  The output amplifier 10 receives the output of the S / H circuit 6 via the MUX 7, amplifies it, and outputs it to the outside of the chip.

  The control unit 9 supplies a row selection circuit drive signal to the row selection circuit 3 according to the drive mode.

  FIG. 2 is a circuit diagram showing details of the pixel 2. The circuit of the pixel 2 outputs a reset voltage obtained by amplifying the voltage at the time of initialization and a read voltage obtained by amplifying the voltage at the time of reading to the vertical signal line 19. The pixel 2 includes a photodiode (PD) 11 that photoelectrically converts incident light and outputs charges, a floating diffusion (FD) 13 that accumulates charges generated by the PD 11 and outputs the accumulated charges as a voltage signal, A reset Tr14 that resets the voltage indicated by the FD13 to the initial voltage (here, VDD), a transfer Tr12 that supplies the electric charge output from the PD11 to the FD13, and a voltage that changes following the voltage indicated by the FD13 is output. And the selection Tr 16 that connects the output of the amplification Tr 15 to the vertical signal line 19 when a line select signal is received from the row selection circuit 3. The sources of the reset Tr 14 and the amplifier 15 are connected to the pixel power source 17. The PD 11 is connected to the ground 18.

  FIG. 3 is a diagram showing details of the column circuit unit 20 according to the first embodiment of the present invention, which includes the pixel current source circuit 4, the clamp circuit 5, and the S / H circuit 6. The function of the column circuit unit 20 is to temporarily hold a signal indicating the difference between the reset voltage and the read voltage output from the circuit of the pixel 2 and then output the signal to the MUX 7.

  The pixel current source circuit 4 includes a current source transistor 21 whose gate is supplied with a current source bias potential 21 a and supplies current to the amplifier Tr 15 when a signal is read from the pixel 2.

  The clamp circuit 5 clamps the sampling Tr 22, the pixel output and the difference between the reset signal and the read signal, that is, the clamp capacitor 23 (capacitance value Ccl) for obtaining the pixel signal, and the terminal potential on the opposite side of the clamp capacitor 23. A clamp voltage input terminal 25 for setting the potential (VCL) and a clamp Tr24 are provided.

  The S / H circuit 6 includes an S / H capacitor 27 (capacitance value Csh) that is supplied with an S / H capacitor input signal to a gate and temporarily holds a pixel signal, and an S / H circuit that inputs a signal to the S / H capacitor 27. 6 basic units 6a.

  FIG. 4 is a diagram showing details around the MUX 7. A column selection Tr 28 is disposed between each S / H capacitor 27 and the horizontal common signal line 29. The column selection Tr 28 sequentially outputs a signal held in the S / H capacitor 27 to the horizontal common signal line 29 in accordance with a column selection signal (H [n]) supplied to the gate.

  The signal supplied to the output amplifier 10 via the horizontal common signal line 29 is amplified and then output to the outside of the chip.

  FIG. 5 is a diagram showing details of the row selection circuit 3. The row selection circuit 3 includes an address decoder 31 and a row selection logic circuit 32 arranged for each row. The row selection logic circuit 32 includes a flip-flop 43 and an AND gate 34. In response to the address signal supplied from the control unit 9, the address decoder 31 outputs an H signal to the AND gate 34 of the corresponding row selection logic circuit 32 and simultaneously inputs a write enable signal of the flip-flop 43. H is set in the flip-flop 43 of the selected row, and the row is selected.

  Next, when the pixel control pulses SEL_s, TRAN_s, and RST_s are input after the setting of the selected row is completed, the respective pulses are supplied to the pixels 2 in the selected row. When the driving of the pixel 2 is completed, the value of each flip-flop 43 is reset to L, and the row selection is released.

  Next, the operation of this apparatus will be described. FIG. 6 is a diagram illustrating the timing of the control signal related to the operation of reading out the pixel signal of one frame when focusing on one pixel 2. The period for reading one frame of the pixel signal includes a reset period in which the charge accumulated in the photodiode 11 of each pixel 2 is zero, and an exposure period in which the charge generated by the optical signal (pixel signal) is accumulated in the photodiode 11. And a readout period for reading out a voltage signal corresponding to the accumulated charge amount. The output signal is proportional to the product of the length of the exposure period and the magnitude of the optical signal.

  Next, an operation for reading out an image signal of one frame will be described. FIG. 7 is a diagram illustrating the timing of each control signal supplied to the pixel 2 and the column circuit unit 20.

  As shown in FIG. 7, at timing t1, the row selection signals SEL [1] and SEL [2] are Hi and the first and second rows are simultaneously selected, the transfer Tr12 is off, and the reset Tr14 is on. And the potential of the FD 13 (hereinafter, Vfd) is initialized to the FD reset potential Vfdrst (= VDD). In order to simultaneously input the row selection signal SEL and the reset signal RST to two rows, the address signals of the two rows are sequentially supplied to the address decoder 31 of the row selection circuit 3 and the flip-flop 43 of the row selection logic circuit 32 is supplied. This can be achieved by sequentially setting the selection state to the same (same for TRAN).

  At timing t2, since the transfer Tr12 and the reset Tr14 are off, the reset state of the FD potential is maintained. At this time, since the selection Tr16 is on, Vfdrst−Vth is output as a reset voltage to the vertical signal line 19 (precisely, Vfdrst−Vth−α, but α is omitted here).

  Further, the reset voltage Vfdrst−Vth is output to one terminal of the clamp capacitor 23. On the other hand, the clamp signal (gate signal of the clamp Tr24) and the S / H capacitor input signal (gate signal of the S / H capacitor input Tr26) are Hi, and the other terminal of the clamp capacitor 23 and the potential of the S / H capacitor 27 are Set to VCL.

  At the timing t3, the transfer Tr is turned on, so that the charges accumulated in the PD11 in the first and second rows are transferred to the FD13, and the FD potentials Vfd1 and Vfd2 are voltages Vfdsig1, Decrease by Vfdsig2, and become Vfdrst-Vfdsig1, Vfdrst-Vfdsig2. This step corresponds to the reading step in the present invention.

  At timing t4, when the transfer Tr12 is off and the selection Tr15 is on, and the average of Vfdsig1 and Vfdsig2 is Vfdsig, Vfdrst−Vfdsig−Vth−RI / 2 is output to the vertical signal line 19 as a read voltage. . This read signal (read voltage) corresponds to a signal obtained by mixing (vertical mixing) pixel signals arranged in the same column of the first row and the second row. Due to the potential change of the vertical signal line 19, the input signal of the clamp capacitor 23 also changes by Vfdsig. In the present embodiment, the row selection circuit 3 and the control unit 9 correspond to the mixing unit in the present invention. This step corresponds to the mixing step in the present invention.

  Further, since the clamp Tr24 is off, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig × Ccl / (Ccl + Csh). This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) in the first row and the second row, and at timing t5. The row selection signals SEL [1], SEL [2] and the S / H input signal become Lo and are stored in the S / H capacitor 27.

  Next, at timing t11, H [1] becomes Hi, and the selection Tr in the first column is turned on. As a result, the signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and output to the outside via the output amplifier 10.

  At timing t12, H [2] becomes Hi and the selection Tr16 in the second column is turned on. As a result, the signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside via the output amplifier 10. Similarly, if the column selection signal is sequentially set to Hi, the signal of the S / H capacitor 27 of each column is sequentially output. From the above, pixel signals in which two vertical pixels are mixed are sequentially output.

  Furthermore, if the operation in FIG. 7 is repeated by the number of rows of the pixels 2 arranged in the imaging unit 1/2, the signal of the entire imaging unit 1 is read out. Each pixel signal of the output image at this time is a signal obtained by mixing the pixel signals of 2n-1 rows and 2n rows of pixels 2 in the imaging unit 1. If the combination of readout rows is changed at the same time, it is also possible to obtain an image composed of signals obtained by mixing pixel signals of pixels 2 in 2n rows and 2n + 1 rows.

  On the other hand, the pixel reset operation is executed in units of rows. It is possible to set an appropriate exposure time for each row.

  FIG. 8 shows the combination of the exposure time of each row in consecutive frames and the rows mixed at the time of output. FIG. 8 illustrates an example in which pixel signals of unit pixels are mixed by changing the exposure period every two rows (N = 2) within one frame. Assuming that the exposure periods of the unit pixels arranged in each of the two rows are T1 and T2, and the exposure times T1 and T2 are T1 <T2, in each frame, a short exposure time T1 signal and a long exposure time T2 signal Is obtained as a mixed signal.

  FIG. 9 shows the relationship between the amount of light irradiated on the PD 11 and the output signal. The upper limit of the signal for one exposure time is limited by PD saturation, circuit saturation, and saturation determined by the ADC range (installed after the output amplifier in FIG. 1), and the lower limit is limited by circuit noise and ADC quantization error. Therefore, it is difficult to secure a large dynamic range of the optical signal that can be detected.

  On the other hand, in this embodiment, since the optical signals detected at two different exposure times are mixed, the dynamic range of the optical signals that can be detected can be expanded. In addition, by switching the combination of rows in which pixel signals are mixed for each frame, the vertical resolution can be maintained as two consecutive image sets.

  In the above operation, signals having different exposure times are mixed. However, if the exposure time is fixed for each row and reading is performed without mixing for each row, it is possible to obtain an image similar to that of a general imaging device. is there.

  FIG. 10 shows another example of combinations of the exposure time of each row in consecutive frames and the rows mixed at the time of output. FIG. 10 illustrates an example in which pixel signals of unit pixels are mixed by changing the exposure period every three rows (N = 3) within one frame. If the exposure periods of the unit pixels arranged in each of the three rows are T1, T2, and T3, and the exposure times T1, T2, and T3 are T1 <T2 <T3, a signal with a short exposure time T1 in each frame, A signal obtained by mixing the signal of the intermediate exposure time T2 and the signal of the long exposure time T3 is obtained, and the dynamic range of the detectable optical signal is further expanded.

  Further, by switching the combination of rows to be mixed for each frame, the vertical resolution can be maintained as a set of continuous images. Further, the exposure times of T1, T2, and T3 may be changed for each frame. According to this configuration, the dynamic range can be further expanded as compared with the combination of T1 and T2 shown in FIG.

(Embodiment 2)
Next, a second embodiment will be described. The solid-state imaging device in the present embodiment is different from the solid-state imaging device shown in the first embodiment in that the solid-state imaging device includes a column ADC instead of the MUX and the column selection circuit.

  FIG. 11 is a diagram illustrating an overall configuration of the solid-state imaging device 200 according to the second embodiment. The solid-state imaging device 200 includes an imaging unit 101, a row selection circuit 103, a pixel current source circuit 104, a clamp circuit 105, a sample hold (S / H) circuit 106, a column ADC 144, and a control unit 109. ing. The column current source circuit 104, the clamp circuit 105, and the sample hold circuit 106 constitute a column circuit unit 120.

  The column ADC 144 includes a column ADC basic unit 144a in each column. The column ADC basic units 144a are arranged in an array in the column direction, and the row-unit analog pixel signals held in the S / H circuit 106 are converted into digital signals. Convert.

  The details of the configuration of the pixel 102, the pixel current source circuit 104, the clamp circuit 105, the S / H circuit 106, and the row selection circuit 103 are the same as those described in Embodiment Mode 1.

  FIG. 12 is a diagram showing details of the column ADC 144. The column ADC includes a ramp waveform generation circuit 148, a comparator 147, a counter 149, and a clock generation circuit 150.

  When the signal from the S / H circuit 106 input from the column ADC input terminal 146 is input to the comparator 147, the comparator 147 compares the signal (pixel signal) from the S / H circuit 106 with the ramp waveform. When the ramp waveform is lower than the pixel signal, Hi is output.

  The counter 149 counts up while the clock is supplied and the comparator signal is H.

  The clock generation circuit 150 supplies a clock to the counter 149. The basic unit 144a of the column ADC is composed of a comparator 147 and a counter 149 for one column.

  Next, the AD conversion operation of the column ADC 144 will be described with reference to the timing chart of FIG.

  First, a pixel signal is input at timing t0, the ramp waveform is set to the minimum value of the pixel signal, and the counter 149 is set to zero. Since the ramp waveform is at a level lower than the pixel signal, the latch signal is Hi.

  Next, at the timing t1, the level of the ramp waveform starts to rise. The rising slope is set so as to reach the maximum value of the pixel signal at timing t3. Also, the clock supply to the counter 149 is started, and the counter 149 also counts up in synchronization with the ramp waveform rise.

  At timing t2, since the ramp waveform becomes larger than the pixel signal, the latch signal is switched to the Lo level, and the count-up is stopped at the counter value at that time. As described above, since the ramp waveform rise and count-up are synchronized, the digital value held in the counter 149 is a value corresponding to the pixel signal. The above operation is performed in parallel in each column, and analog pixel signals for one row are AD-converted in parallel and held in latches in each column.

  By the same operation as in the first embodiment, the solid-state imaging device 200 performs analog-digital conversion on the signal read up to the S / H circuit 106 by the column ADC 144. As a result, an image having a wide dynamic range of a detectable optical signal and a high vertical resolution can be obtained as a digital signal.

  According to this configuration, the solid-state imaging device 200 does not require an external ADC as compared with the analog output of the first embodiment, and can avoid disturbance noise mixed in the signal line up to the ADC. There is an advantage that it is suitable for various operations.

  As another configuration of the ADC, an up / down counter having functions of down counting and up counting may be provided as the counter 149 shown in FIG. The AD conversion operation in this case will be described with reference to the timing chart of FIG.

  As shown in FIG. 14, first, the reference signal is input at timing t5, the ramp waveform is set to the minimum value of the reference signal, and the counter 149 is set to zero. Since the ramp waveform is at a level lower than the reference signal, the latch signal is Hi.

  Next, at the timing t6, the level of the ramp waveform starts to rise. Also, the clock supply to the counter 149 is started, and the counter 149 also counts down in synchronization with the ramp waveform rise.

  At timing t7, since the ramp waveform becomes larger than the reference signal, the latch signal is switched to the Lo level, and the countdown stops at the counter value at that time.

  Next, a reference + pixel signal is input at timing t0. The ramp waveform is set to the minimum value of the reference + pixel signal. Since the ramp waveform is at a level lower than the reference + pixel signal, the latch signal is Hi. However, the counter 149 of the column ADC 144 is not reset to zero.

  Next, at the timing t1, the level of the ramp waveform starts to rise. The rising slope is set so as to reach the maximum value of the reference + pixel signal at timing t3. The clock supply to the counter 149 is also started, and the counter 149 also starts counting up in synchronization with the rise of the ramp waveform.

  At timing t2, since the ramp waveform becomes larger than the reference + pixel signal, the latch signal is switched to the Lo level, and the count-up stops at the counter value at that time. Since the up-count is performed without reset after the down-count, the counter value at this time is a difference between the reference signal and the reference + pixel signal, that is, a digital signal corresponding to the pixel signal.

  The above operation is performed in parallel in each column, and analog pixel signals for one row are AD-converted in parallel and held in latches in each column. In this AD conversion operation, since the difference between the reference signal and the reference + pixel signal is digitized, there is an advantage that the offset error of the comparator superimposed on both signals can be canceled.

(Embodiment 3)
Next, Embodiment 3 will be described.

  The overall configuration of the solid-state imaging device in the present embodiment is the same as that of the solid-state imaging device 200 shown in the second embodiment, but the pixel signal readout operation is different. In the second embodiment, pixel signals in a plurality of rows are mixed at the time of reading out the pixel signals. However, in this embodiment, the pixel signals are read out one by one, and the analog-digital conversion circuit (column ADC) 144 reads the pixel signals in the plurality of rows. Are mixed (added). In the present embodiment, the column ADC 144 corresponds to the mixing unit of the present invention.

  FIG. 15 is a diagram illustrating a timing chart of the mixing (adding) operation in the column ADC 144. In FIG. 15, AD conversion of the pixel signal 1 in the row 1 is performed from timing t1 to t3, and the pixel signal 2 in the row 2 is performed from timing t3 to t6. At this time, since the counter is not reset to zero before AD conversion of the pixel signal 2, a digital signal value corresponding to the addition value (mixed value) of the pixel signal 1 and the pixel signal 2 is obtained.

  According to the operation of the solid-state imaging device shown in the present embodiment, there is an advantage that the mixing can be executed with high accuracy as compared with the case where the pixel signal of the second embodiment is read out by analog operation.

(Embodiment 4)
Next, a fourth embodiment will be described.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device according to the third embodiment in that the solid-state imaging device further includes a line memory and a signal processing circuit.

  FIG. 16 is a diagram illustrating an overall configuration of the solid-state imaging apparatus 300 according to the fourth embodiment. The solid-state imaging device 300 includes an imaging unit 201, pixels 202, a row selection circuit 203, a pixel current source circuit 204, a clamp circuit 205, a sample hold (S / H) circuit 206, a column ADC 244, and a control unit. 209, a line memory 251 and a signal processing circuit 252. The pixel current source circuit 204, the clamp circuit 205, and the sample hold circuit 206 constitute a column circuit unit 220.

  In this embodiment, signal reading from the pixels and AD conversion are performed in units of one row, and the pixel signal output from the column ADC 244 after AD conversion is held in the line memory 251. Subsequently, pixel signals in rows with different exposure time settings are read and AD conversion is performed, and the signal processing circuit 252 mixes or adds the pixel signals output from the column ADC 244 after AD conversion and the signals held in the line memory. To do. In the present embodiment, the column ADC 244, the line memory 251 and the signal processing circuit 252 correspond to the mixing unit of the present invention.

  In the present embodiment, since the pixel signal is mixed by the signal processing circuit 252, there is an advantage that flexible mixing can be executed. For example, it is possible to switch on / off whether or not to mix pixels depending on the area of the image. This turns off pixel mixing for areas where a large dynamic range is not required for the detectable optical signal, and turns on pixel mixing for areas where a large dynamic range is required. A signal having the same gradation can be obtained with respect to the signal range.

(Embodiment 5)
Next, a fifth embodiment will be described.

  The entire configuration of the solid-state imaging device according to the present embodiment is one of the configurations of the solid-state imaging device according to the first to fourth embodiments, but the pixel reset operation for determining the exposure period and the pixel signal readout operation are different. .

  FIG. 17 shows the combination of the exposure time of each row in consecutive frames and the rows mixed at the time of output. In FIG. 17, exposure times T1, T2, and T3 are T1 <T2 <T3, and pixel signals of three different exposure times T1, T2, and T3 are vertically mixed, but the combination to be mixed is switched for each frame. On the other hand, the exposure time setting combination is not switched for each frame.

  According to this configuration, since signals having different exposure times are mixed, an image having a wide dynamic range of a detectable optical signal can be obtained with a simple circuit configuration. Further, by changing the mixing combination for each frame, it is possible to suppress a decrease in resolution in the vertical direction due to mixing as a set of continuous images. The image read by the solid-state imaging device according to the present embodiment has a slightly lower resolution than the image read by the solid-state imaging device according to the first to fourth embodiments, but the exposure time can be easily controlled and the scale of the control circuit There is an advantage that can be reduced.

  The present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention.

  For example, the configuration of the solid-state imaging device according to the present invention is not limited to the above-described embodiment, and may be other configurations. For example, the pixel current source circuit, the clamp circuit, the sample hold circuit, the multiplexer, the column selection circuit, the column ADC, the configuration of the digital mixer, or a combination thereof may be used.

  Further, the number of rows in which the read pixel signals are mixed is not limited to the two rows described above, and may be three rows or more. In addition, the plurality of rows in which the pixel signals are mixed is not limited to a continuous row, and may be any combination.

  In addition, the solid-state imaging device according to the present invention includes other embodiments that are realized by combining arbitrary components in the above-described embodiments and a range that does not depart from the gist of the present invention. Modifications obtained by various modifications conceived by a trader and various devices including the solid-state imaging device according to the present invention are also included in the present invention. For example, a movie camera including the solid-state imaging device according to the present invention is also included in the present invention.

  The solid-state imaging device according to the present invention is useful as an image sensor for an imaging device that requires high image quality and high functionality such as a digital single-lens reflex camera and a high-end compact camera.

1, 101, 201 Imaging unit (pixel unit)
2, 102, 202 pixels (unit pixel)
3, 103, 203 Row selection circuit (row selection circuit, mixing unit)
4, 104, 204 Pixel current source circuit 5, 105, 205 Clamp circuit 6, 106, 206 S / H circuit 7 Multiplexer 8 Column selection circuit 9, 109, 209 Control unit 10 Output amplifier 11 Photodiode (PD)
12 Transfer transistor 13 Floating diffusion (FD)
14 reset transistor 15 amplification transistor 16 selection transistor 17 pixel power supply 18 ground 19 vertical signal lines 20, 120, 220 column circuit section 21 current source transistor 22 sampling transistor 23 clamp capacitor 24 clamp transistor 25 clamp voltage input terminal 26 S / H capacitor input Transistor 27 S / H capacitor 28 Column selection transistor 29 Horizontal common signal line 30 Column selection signal line 31 Address decoder 32 Row selection logic circuit 34 AND gate 43 Flip-flops 144, 244 Column ADC (mixing unit)
146 Column ADC input terminal 147 Comparator 148 Ramp waveform generation circuit 149 Counter 150 Clock generation circuit 251 Line memory (mixing unit)
252 Signal processing circuit (mixing unit)

Claims (12)

A pixel unit in which a plurality of unit pixels each having a photoelectric conversion element are two-dimensionally arranged in a matrix;
A row selection circuit that selects the plurality of unit pixels from which pixel signals are read out for each row of the pixel unit;
A control unit that provides a control signal to the row selection circuit so as to change the exposure time in a plurality of unit pixels of the row selected by the row selection circuit for each row;
A solid-state imaging device comprising: a mixing unit that mixes pixel signals read from a plurality of unit pixels in a row selected by the row selection circuit for each column. The solid-state imaging device according to claim 1, wherein the control unit gives a control signal to the row selection circuit so as to change the exposure time for each frame. The mixing unit is the row selection circuit;
The solid-state imaging device according to claim 1, wherein the control unit causes the row selection circuit to simultaneously select two or more rows of the pixel unit. The solid-state imaging device according to claim 1, wherein the mixing unit is an ADC counter. The solid-state imaging device according to claim 4, wherein the ADC counter is configured by an up / down counter. The solid-state imaging device according to claim 1, wherein the mixing unit includes a line memory and a signal processing circuit. A method for driving a solid-state imaging device,
A control signal in which an exposure time is changed for each row is given to a plurality of unit pixels that have a photoelectric conversion element and are two-dimensionally arranged in a matrix, and image signals are output from the plurality of unit pixels for each row. A read step to read;
A solid-state imaging device driving method comprising: a mixing step of mixing pixel signals read out from the plurality of unit pixels arranged in the same row at different exposure times by a mixing unit. The solid-state imaging device driving method according to claim 7, wherein, in the reading step, the exposure time is changed every N (N is a natural number of 2 or more) rows within one frame. The solid-state imaging device driving method according to claim 8, wherein in the reading step, the exposure time is changed for each frame. 8. The method of driving a solid-state imaging device according to claim 7, wherein in the mixing step, the mixing unit changes a combination of rows in which the plurality of pixels that mix the pixel signals are arranged for each frame. The method of driving a solid-state imaging device according to claim 7, wherein in the mixing step, the mixing unit simultaneously selects two or more rows of the unit pixels. The solid-state imaging device driving method according to claim 7, wherein in the mixing step, the ADC counter sequentially adds the read pixel signals without resetting the ADC counter by two or more rows.

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