JP2013004607A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can prevent mask collapse and further prevent side etching of AlCu wiring.SOLUTION: A semiconductor device manufacturing method comprises: forming an AlCu wiring layer 34 by sequentially laminating an under side TiN/Ti film 29, an AlCu film 30 and an upper side TiN/Ti film 31 on a second interlayer film 17 of SiC; subsequently, forming a hard mask 37 of SiOon the AlCu wiring layer 34; forming, by dry etching the AlCu wiring layer 34 by using the hard mask 37, first AlCu wiring 20; forming a sunken part 28 by etching the second interlayer film 17 after forming the first AlCu wiring 20; and concurrently causing C to dissociate from the second interlayer film 17 (SiC) and fixing a reaction product containing the dissociating C onto a side wall protection film 32 to thicken the side wall protection film 32.

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure formed by laminating AlCu wirings and a method for manufacturing the same.

Conventionally, a semiconductor device having a multilayer wiring structure formed by forming wirings in multiple layers is known. The multilayer wiring structure can be formed by repeating a process of forming a metal film on an interlayer insulating film forming each layer and patterning the metal film to form a wiring pattern a plurality of times.
As a method of forming a wiring pattern by patterning a metal film, for example, Patent Document 1 discloses a method of forming a wiring pattern by patterning using a photoresist as a mask.

  In the method of Patent Document 1, first, an insulating film is formed on a Si substrate, and a TiN / Ti film, an Al film, and a TiN film are sequentially stacked on the insulating film. Next, a photoresist having a pattern corresponding to the wiring pattern is formed on the TiN film. Next, using the photoresist as a mask, the TiN film, the Al film, and the TiN / Ti film are sequentially etched to pattern these films to form an Al wiring. At this time, a natural oxide film is formed on the side wall of the Al wiring.

Japanese Patent Laid-Open No. 11-312681

The method for manufacturing a semiconductor device of the present invention includes a lower TiN (titanium nitride) / Ti (titanium) film, an AlCu film, and an upper TiN / film on a lower layer film made of SiC (silicon carbide) or SiOC (carbon-containing silicon oxide). A step of forming an AlCu wiring layer by sequentially stacking a Ti film; a step of forming a hard mask of a predetermined pattern made of an inorganic film on the AlCu wiring layer; and the AlCu wiring layer using the hard mask. By patterning the AlCu wiring layer while forming a side wall protective film containing a reaction product generated by the etching on the side surface of the AlCu film in the middle of etching, a plurality of layers are formed on the lower layer film. Between the step of forming the AlCu wiring and the adjacent AlCu wiring in the lower layer film By dry etching the portion, the reaction product containing C dissociated from the lower layer film by the etching is fixed to the side wall protective film, while the lower layer film is in contact with the surface of the lower layer film in contact with the AlCu wiring Forming a low step portion so as to lower the space between the AlCu wirings, and forming an upper layer film made of SiO ₂ on the lower layer film so as to fill the AlCu wiring after the formation of the low step portion. Including the step of.

According to this method, a hard mask (inorganic film) having a higher etching resistance than an organic photoresist is used as a mask when the AlCu wiring layer is dry-etched. Therefore, unlike the case where a photoresist is used, it is possible to prevent the mask from being lost because it cannot withstand the etching gas during etching.
Further, since the hard mask can exhibit sufficient etching resistance even when it is thin, the aspect ratio of the mask can be kept small even when forming fine wiring. As a result, it is possible to prevent so-called “mask collapse”, in which a mask having a high aspect ratio and extending vertically above the object to be etched falls out of balance during the etching.

  On the other hand, when the AlCu wiring layer is etched without using an organic photoresist as a mask, a product (a product containing C) generated by etching the resist is formed on the side surface of the AlCu film during etching. Not included in the membrane. For this reason, a sidewall protective film having a sufficient thickness is not formed, and such a sidewall protective film has insufficient protection against Cl (chlorine) ions and Cl radicals contained in the etching gas. Therefore, when an organic photoresist is not used, for example, after etching the AlCu wiring layer, when the lower layer film between the AlCu wirings is dug, the side wall protective film is eroded by Cl ions or Cl radicals that have lost their destination. In particular, the AlCu wiring (the AlCu film portion of the wiring) may be side-etched.

  Therefore, in the present invention, the base film (lower layer film) of the AlCu wiring is an SiC film or an SiOC film. As a result, the reaction product containing C (carbon) dissociated from the lower layer film can be increased and the amount of O (oxygen) can be suppressed at the time of dry etching when forming a low step portion in the lower layer film can do. Therefore, the sidewall protective film of the AlCu wiring can be thickened by the reaction product containing C. As a result, when the low step portion is formed in the lower layer film, even if Cl ions or Cl radicals enter between the wirings, the side surface of the AlCu film can be protected by the thick side wall protective film. Therefore, side etching of the AlCu wiring can be prevented.

In the present invention, the AlCu wiring is a wiring made of a metal in which Al as a main component (for example, 99.0 to 99.7% by weight) is alloyed with Cu, and is generally called an Al wiring. is there. This AlCu wiring does not reach the Cu wiring mainly composed of Cu in terms of resistance value, but is very low in cost compared to Cu.
According to the present invention, the step of forming the plurality of AlCu wirings includes the step of forming the AlCu wirings having a width of 85 nm to 180 nm so as to be arranged at intervals of 85 nm to 180 nm, that is, the wiring width and the spacing. Even when (line and space) forms a fine wiring in the above range, the mask aspect ratio can be kept small to prevent “mask collapse”. Therefore, it can be suitably used as a method for manufacturing a semiconductor device having fine wiring.

The step of forming the plurality of AlCu wirings is formed with a dense pattern arranged at a first interval from each other, and a second interval wider than the first interval from the dense pattern. A step of forming an isolated pattern.
For example, when the AlCu wiring layer is formed into a plurality of patterns of dense patterns and isolated patterns, normally, the isolated pattern separated from the dense pattern by a second interval becomes a dense pattern densely spaced at the first interval. In comparison, it is molded relatively quickly. As a result, when the AlCu wiring layer is formed into an isolated pattern, the dense pattern may not be formed yet. In such a case, if the etching is continued with a Cl-based gas suitable for etching the AlCu wiring layer, the AlCu wiring that is the etching target of the Cl-based gas around the isolated pattern (the portion between the dense pattern and the isolated pattern). Since no layer remains, the side surface of the AlCu film having an isolated pattern may be attacked by Cl ions or Cl radicals in the Cl-based gas.

Therefore, according to the present invention, a relatively wide space is formed between adjacent AlCu wirings, such as isolated patterns, and AlCu wirings that are likely to collide with Cl ions or Cl radicals that are horizontal to the lower layer film. In addition, since a thick sidewall protective film is formed, side etching of the AlCu wiring can be effectively prevented.
In the present invention, the step of forming the hard mask preferably includes a step of forming a hard mask having an aspect ratio (hard mask height / hard mask width) of less than 3.

If the aspect ratio of the hard mask is less than 3, “mask collapse” can be reliably prevented.
In the present invention, the step of forming the hard mask may include a step of forming a hard mask made of a SiO ₂ film or a SiON film.
Then, according to the semiconductor device manufacturing method of the present invention, the semiconductor device of the present invention, that is, the lower layer film made of SiC or SiOC, and the lower layer film are formed on the lower TiN / Ti film, the AlCu film, and the upper layer film, respectively. TiN / Ti film is formed by laminating in this order, between a plurality of AlCu wirings having a side wall protective film containing C on the side surface of each AlCu film, and the adjacent AlCu wirings in the lower layer film, A lower step portion formed one step lower than the surface of the lower layer film in contact with the AlCu wiring, and an upper layer film made of SiO ₂ formed on the lower layer film so as to fill the AlCu wiring, The plurality of AlCu wirings each have a width of 85 nm to 180 nm and include a dense pattern arranged at intervals of 85 nm to 180 nm. A body device can be manufactured.

  In the semiconductor device of the present invention, the height of each AlCu wiring may be 140 nm to 205 nm. The height of the AlCu film may be 80 nm to 120 nm. The height of the lower TiN / Ti film may be 20 nm to 30 nm. Furthermore, the upper TiN / Ti film may have a height of 40 nm to 55 nm.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged view of a portion surrounded by a two-dot chain line A in FIG. FIG. 3A is a diagram showing a part of the manufacturing process of the semiconductor device of FIG. FIG. 3B is a diagram showing a step subsequent to FIG. 3A. FIG. 3C is a diagram showing a step subsequent to FIG. 3B. FIG. 3D is a diagram showing a step subsequent to FIG. 3C. FIG. 3E is a diagram showing a step subsequent to that in FIG. 3D. FIG. 3F is a diagram showing a step subsequent to that in FIG. 3E. FIG. 3G is a diagram showing a step subsequent to FIG. 3F. FIG. 4 is a diagram showing a modification of the second interlayer film.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<Overall configuration of semiconductor device>
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
The semiconductor device 1 includes an n ⁺ type silicon substrate 2 and an epitaxial layer 3 made of n ⁻ type silicon stacked on the silicon substrate 2.

A plurality of MOSFETs 4 (Metal Oxide Semiconductor Field Effect Transistors) are formed adjacent to each other in the epitaxial layer 3. Each MOSFET 4 is insulated and isolated from its surroundings by an element isolation portion 5.
The element isolation portion 5 forms a trench (shallow trench 6: about 180 nm deep) dug relatively shallowly from the surface of the epitaxial layer 3, and a thermal oxide film 7 is formed on the inner surface of the shallow trench 6 by a thermal oxidation method. After the formation, it is formed by depositing SiO ₂ (silicon oxide) 8 in the shallow trench 6 by a CVD (Chemical Vapor Deposition) method, and has a so-called STI (Shallow Trench Isolation) structure. ing. The shallow trench 6 is formed, for example, in the shape of an isosceles trapezoid whose width is narrowed toward the bottom thereof, and its minimum width (bottom width) is about 90 nm.

A p-type source region 10 and a p-type drain region 11 are formed in the surface layer portion of the epitaxial layer 3 with the channel region 9 interposed therebetween. The end portions of the source region 10 and the drain region 11 on the channel region 9 side have a small depth and impurity concentration. That is, the MOSFET 4 employs an LDD (Lightly Doped Drain) structure.
A gate insulating film 12 made of, for example, SiO ₂ is formed on the channel region 9, and a gate electrode 13 made of, for example, polycrystalline silicon (polysilicon) is formed on the gate insulating film 12. . The width of the gate electrode 13 is, for example, about 90 nm. A silicide 14 is formed on the surface (upper surface) of the gate electrode 13.

A sidewall 15 made of, for example, SiN (silicon nitride) is formed around the gate insulating film 12 and the gate electrode 13.
On the epitaxial layer 3, the first interlayer film 16, the second interlayer film 17 made of SiC, the third interlayer film 18 and the fourth interlayer film 19 made of SiO ₂ made of SiO ₂ made of SiO _2, layered in this order Has been. The thicknesses of the interlayer films 16 to 19 are, for example, 400 nm to 580 nm for the first interlayer film 16, 350 nm to 450 nm for the second interlayer film 17, 260 nm to 560 nm for the third interlayer film 18, The four interlayer film 19 is 260 nm to 560 nm.

A plurality of first AlCu wirings 20 (first metal) and a plurality of second AlCu wirings 21 (second metal) are formed on the second interlayer film 17 as the lower layer film and the third interlayer film 18 as the upper layer film, respectively. Has been. Thereby, a multilayer wiring structure is formed on the epitaxial layer 3.
The first AlCu wiring 20 is connected to the source region 10 and the drain region 11 by a contact plug 22 made of W (tungsten) that penetrates the first interlayer film 16 and the second interlayer film 17. The contact plug 22 has a two-stage structure of a lower portion 23 penetrating the first interlayer film 16 and an upper portion 24 penetrating the second interlayer film 17, and as shown in FIG. 24 is formed in a reverse trapezoidal (tapered) shape in cross section in which the lower surface diameter D ₁ is smaller than the upper surface diameter D ₂ (D ₁ <D ₂ ). For example, the diameter _{D 1} is 60Nm～110nm, diameter _{D 2} is 110Nm～130nm. For example, the upper portion 24 of the contact plug 22 is formed by performing a process of depositing tungsten in a contact hole of the second interlayer film 17 and a process of polishing the deposited tungsten by CMP (Chemical Mechanical Polishing). In this case, since the film thickness of the second interlayer film 17 is about 2/3 to 4/5 by the CMP process, if the taper of D ₁ <D ₂ , the upper surface of D ₂ ′ when tungsten is deposited is formed. the diameter can be reduced to the diameter D _2. Therefore, the margin for the adjacent contact plug 22 after the CMP process is larger than in the case of D ₁ = D ₂ where the diameter of the upper surface of the upper portion 24 does not change even if the second interlayer film 17 is reduced by the CMP process. Can be wide. As a result, even if the lithography of the first AlCu wiring 20 is slightly shifted in the lateral direction, the first AlCu wiring 20 can be prevented from coming into contact with the adjacent contact plug 22 (upper portion 24).

Further, the second AlCu wiring 21 and the first AlCu wiring 20 are connected by a via 25 made of W (tungsten) that penetrates the third interlayer film 18.
<Structure of main part of first AlCu wiring>
FIG. 2 is an enlarged view of a portion surrounded by a two-dot chain line A in FIG. 1 and represents a main part of a layer in which the first AlCu wiring is formed.

As described above, on the second interlayer film 17 made of SiC, a plurality of first AlCu wirings 20 are formed at intervals. The wiring widths and intervals of the plurality of first AlCu wirings 20 may be uniform or uneven.
In this embodiment, the wiring widths and intervals of the plurality of first AlCu wirings 20 are uneven. For example, the plurality of first AlCu wirings 20 have a first width W ₁ (specifically, 90 nm), and A dense pattern 26 arranged with a _first interval S ₁ (specifically, 90 nm), and a second interval S ₂ (specifically, wider than the first interval S ₁ from the dense pattern 26) And an isolated pattern 27 having a _second width W ₂ (specifically, 5000 nm) wider than the first width W ₁ . That is, in the dense pattern 26, the wiring width _{W 1} and spacing _{S 1} (line and space) is 90 nm / 90 nm.

Between each of the plurality of first AlCu wirings 20 patterned in this manner, a low step portion 28 that is one step lower than the surface of the second interlayer film 17 in contact with each first AlCu wiring 20 is provided in the second interlayer film. 17 is formed. The low step portion 28 is formed by digging the second interlayer film 17 by etching, and the surface distance along the surface of the second interlayer film 17 between the first AlCu wirings 20 adjacent to each other is defined as a linear distance S. _1, longer than _{S 2.} As a result, the surface leakage current in the second interlayer film 17 can be reduced, so that a short circuit between adjacent first AlCu wirings 20 can be prevented even in a fine wiring having a line and space of 90 nm / 90 nm. be able to. Moreover, each low step part 28 is formed in the trapezoid shape, for example, the cross-sectional view which becomes narrow toward the bottom part.

  Each first AlCu wiring 20 has a lower TiN / Ti film 29, an AlCu film 30, and an upper TiN / Ti film 31 stacked in this order, whereby a wiring (AlCu wiring) made of the AlCu film 30 is formed from both the upper and lower sides. / A structure sandwiched between barrier films made of Ti films 29 and 31. The thickness of each film is, for example, 20 nm to 30 nm (specifically, 25 nm) for the lower TiN / Ti film 29, 80 nm to 120 nm (specifically, 100 nm) for the AlCu film 30, and the upper side The TiN / Ti film 31 is 40 nm to 55 nm (specifically, 47 nm).

  In the first AlCu wiring 20, the TiN / Ti film is a film formed by laminating a Ti (titanium) film and a TiN (titanium nitride) film in this order. The AlCu wiring is a wiring made of a metal in which a main component (for example, 99.0 to 99.7% by weight) of Al is alloyed with Cu, and is generally called an Al wiring. Although the AlCu wiring does not reach the Cu wiring containing Cu as a main component in terms of resistance value, the cost is much lower than that of Cu.

A sidewall protective film 32 is formed on the side surface of each first AlCu wiring 20 so as to straddle the sidewalls of the upper TiN / Ti film 31, the AlCu film 30, the lower TiN / Ti film 29, and the low step portion 28. Each side wall protective film 32 is formed with such a thickness as to leave a gap with respect to the side wall protective film 32 of the adjacent first AlCu wiring 20, and the third interlayer film 18 fills the gap.
In this embodiment, each side wall protective film 32 is formed of a reaction product (for example, AlCl ₃ ) generated during etching of an AlCu wiring layer 34 described later (see FIGS. 3D and 3E). A reaction product (for example, CCl _x ) containing C dissociated from the second interlayer film 17 (SiC film) during the etching to form the layer 28 (see FIG. 3F), in the F-based gas supplied during the etching CHF ₃ polymer and the like are included. Of course, the sidewall protective film 32 may contain components other than the components exemplified above.

A SiO ₂ film 33 is formed on the upper surface of each first AlCu wiring 20. This SiO ₂ film 33 remains on the upper surface of the first AlCu wiring 20 without the hard mask 37 described later being removed after the etching is completed.
A third interlayer film 18 made of SiO ₂ is laminated on the second interlayer film 17 so as to fill the entire first AlCu wiring 20. The third interlayer film 18 fills the space between the adjacent first AlCu wires 20. In FIG. 2, a clear boundary appears between the third interlayer film 18 and the SiO ₂ film 33. However, since these films are both made of SiO ₂ , in actuality, in the manufacturing process, these In some cases, the membranes are integrated and there are no boundaries.

The via 25 connected to the first AlCu wiring 20 from above passes through the third interlayer film 18 and the SiO ₂ film 33 and is connected to the upper surface of TiN of the upper TiN / Ti film 31. On the other hand, the contact plug 22 (upper portion 24) connected from the lower side to the first AlCu wiring 20 passes through the second interlayer film 17 and is connected to the lower surface of Ti of the lower TiN / Ti film 29. Yes.
<Method for Manufacturing Semiconductor Device>
3A to 3G are diagrams showing a part of the manufacturing process of the semiconductor device of FIG.

In order to manufacture the semiconductor device 1 described above, for example, the epitaxial layer 3 is grown on the silicon substrate 2 by a known method, and then the element isolation portion 5 having the STI structure is formed. Next, after a plurality of MOSFETs 4 are formed in the epitaxial layer 3, the first interlayer film 16 made of SiO ₂ is laminated on the epitaxial layer 3 by, for example, a plasma CVD method, and the contact plug 22 (the lower portion 23 is formed). ). Next, as shown in FIG. 3A, after the second interlayer film 17 made of SiC is laminated on the first interlayer film 16, for example, by plasma CVD, the contact plug 22 (upper portion 24) is formed. Thus, a contact plug 22 having a two-layer structure is formed.

Next, as shown in FIG. 3A, the lower TiN / Ti film 29, the AlCu film 30, and the upper TiN / Ti film 31 are sequentially laminated on the entire upper surface of the second interlayer film 17, for example, by sputtering. Then, the AlCu wiring layer 34 is formed.
Next, as shown in FIG. 3B, the SiO ₂ film 35 is laminated by, eg, plasma CVD. At this time, the SiO ₂ film 35 is formed with a thickness T _SiO2 of 150 nm to 250 nm, for example.

Next, as shown in FIG. 3C, the hard mask 37 is formed by patterning the SiO ₂ film 35 by a known lithography technique and etching technique. At this time, since in the previous step thickness _{T SiO2} of the SiO ₂ film 35 is a 150 nm to 250 nm, the aspect ratio of the hard mask 37 _(T SiO2 / _{W 1} or _{W 2)} of less than 3 (e.g., 0. 6-2.8). Therefore, the so-called “mask collapse” in which the hard mask 37 collapses out of balance during the etching of the AlCu wiring layer 34 to be described later can be prevented.

Next, as shown in FIG. 3D, the AlCu wiring layer 34 is dry-etched using a hard mask 37. In this dry etching, a Cl-based gas (mixed gas containing Cl as a main component) suitable for etching AlCu, for example, Cl ₂ , CH ₄ , C ₂ H ₄ , BCl _3, and Ar, Cl ₂ : CH _{4 is used. : C 2 H 4: BCl 3} : Ar = 70~100: 4~7: 5~8: 100~180: 450~600 the combined gas mixture at a ratio of supply as the etching gas. Of course, the Cl-based gas is not limited to this mixed gas, and for example, a mixed gas containing CCl ₄ (carbon tetrachloride) or the like can also be used. At this time, the explosion range in the air of CH ₄ (methane) is 5 to 15%, and the explosion range in the air of C ₂ H ₄ (ethylene) is 2.7 to 36%. Dilute with Ar.

Then, the supplied Cl-based gas sequentially etches the AlCu wiring layer 34 from the upper TiN / Ti film 31 toward the AlCu film 30 from the upper layer to the lower layer, and at the same time, the reaction product of the etching (for example, CCl A sidewall protective film 32 including _x ) is formed. That is, in the etching process of the AlCu wiring layer 34, pattern formation of the AlCu wiring layer 34 (formation of the first AlCu wiring 20) and formation of the sidewall protective film 32 are performed simultaneously.

Thereafter, as shown in FIG. 3E, the supply of the Cl-based gas is continued until the etching of the AlCu wiring layer 34 is completed (the etching of the lower TiN / Ti film 29 is completed) and the first AlCu wiring 20 is formed. As the etching of the AlCu wiring layer 34 is completed, the etching gas is changed from a Cl-based gas to an F-based gas suitable for SiO ₂ etching (a mixed gas containing F (fluorine) as a main component), for example, CHF ₃ and the _{Cl 2, CHF 3: Cl 2} = 1~3: 1~1.5 mixed gas at a ratio of _the Cl 2 + BCl ₃ and _{CF 4, Cl 2 + BCl 3} : CF 4 = 6~8: 2~ The mixed gas, C ₂ F ₆ and Cl ₂ mixed at a ratio of 4 are switched to a mixed gas mixed at a ratio of CHF ₃ : Cl ₂ = 1 to 3: 2 to 3 or the like.

The timing of gas switching is performed, for example, when the AlCu wiring layer 34 is formed into at least one first AlCu wiring 20. This is because, for example, Cl-based gas attacks on the first AlCu wiring 20 of the isolated pattern 27 are reduced.
Specifically, when the AlCu wiring layer 34 is formed into a plurality of patterns of the dense pattern 26 and the isolated pattern 27 as in this embodiment, the second pattern S ₂ is usually separated from the dense pattern 26. The isolated patterns 27 that are separated from each other are formed relatively quickly as compared with the dense pattern 26 that is dense at the _first interval S1. As a result, when the AlCu wiring layer 34 is formed into the isolated pattern 27, the dense pattern 26 may not be completely formed. In such a case, if the etching is continued with the Cl-based gas, the AlCu wiring layer 34 to be etched with the Cl-based gas remains around the isolated pattern 27 (the portion between the dense pattern 26 and the isolated pattern 27). Therefore, there is a possibility that the side surface of the AlCu film 30 of the isolated pattern 27 is attacked by Cl ions or Cl radicals in the Cl-based gas that has lost the etching target (has lost its destination). In order to reduce such attacks by Cl-based gas, switching from Cl-based gas to F-based gas is performed at the above timing.

As shown in FIG. 3F, the supplied F-based gas etches the second interlayer film 17 between the wirings 20 adjacent to each other, and at the same time, C (carbon) of the second interlayer film 17 made of SiC. , And a reaction product containing C (for example, CCl _x ) and a polymer of CHF ₃ as a gas component are fixed on the sidewall protective film 32. Thereafter, the low-stage portion 28 is formed in the second interlayer film 17 by continuing the supply of the F-based gas for a predetermined time.

Thereafter, as shown in FIG. 3G, a third interlayer film 18 is formed on the second interlayer film 17 by, eg, CVD. Next, after the via 25 penetrating the third interlayer film 18 and the SiO ₂ film 33 is formed, the second AlCu wiring 21 and the fourth interlayer film 19 are formed.
Through the above steps, the semiconductor device 1 shown in FIGS. 1 and 2 can be obtained.

According to the manufacturing method of the semiconductor device 1 described above, an inorganic film (hard mask 37) made of SiO ₂ having a higher etching resistance than an organic photoresist is used as a mask when the AlCu wiring layer 34 is dry-etched. To do. Therefore, unlike the case where a photoresist is used, it is possible to prevent the mask 37 from withstanding the etching gas and disappearing during the etching (for example, the steps of FIGS. 3D and 3E).

  Further, since the hard mask 37 can exhibit sufficient etching resistance even when it is thin, the aspect ratio of the hard mask 37 can be reduced even when forming fine wiring (line and space 90 nm / 90 nm) such as the dense pattern 26. It can be suppressed to less than 3. As a result, it is possible to prevent so-called “mask collapse”, in which a mask having a high aspect ratio and extending vertically above the object to be etched falls out of balance during the etching.

  On the other hand, when an AlCu wiring layer is etched without using an organic photoresist as a mask, a product (a product containing C) generated by etching the resist is formed on the side surface of the AlCu wiring layer during etching. Not included in the protective film. For this reason, a sidewall protective film having a sufficient thickness is not formed, and such a sidewall protective film has insufficient protection against Cl ions and Cl radicals contained in the Cl-based gas. Therefore, when an organic photoresist is not used, for example, when the low step portion 28 is formed in the second interlayer film 17 (step of FIG. 3H), the sidewall protective film is formed by Cl ions or Cl radicals that have lost their destination. As a result, the AlCu wiring may be side-etched.

  Therefore, in this embodiment, the base film of the first AlCu wiring 20 is the second interlayer film 17 made of SiC. As a result, the reaction product containing C (carbon) dissociated from the second interlayer film 17 (SiC) can be increased during dry etching when the low step portion 28 is formed in the second interlayer film 17. , O (oxygen) amount can be suppressed. Therefore, the sidewall protective film 32 can be thickened by the reaction product containing C. As a result, when the low step portion 28 is formed in the second interlayer film 17, even if Cl ions or Cl radicals enter between the first AlCu wirings 20, the side wall protective film 32 in which the side surfaces of the first AlCu wirings 20 are thickened. You can defend by. Therefore, side etching of the first AlCu wiring 20 can be prevented.

In particular, as in the isolated pattern 27, a relatively wide space is formed between the adjacent first AlCu wirings 20, and the first AlCu wirings 20 are likely to collide with Cl ions or Cl radicals that are horizontal to the silicon substrate 2. In addition, since the thick sidewall protective film 32 is formed, side etching of the first AlCu wiring 20 can be effectively prevented.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.

For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 described above is inverted may be employed. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.
In the above-described embodiment, only the two-layer wiring structure is illustrated as an example of the multilayer wiring structure. However, the present invention can be suitably applied to a three-layer, four-layer or more multilayer wiring structure.

Further, as shown in FIG. 4, the second interlayer film 17 may be formed of a SiOC film instead of the SiC film.
Further, the third interlayer film 18 covering the first AlCu wiring 20 may be formed of a SiC film. In that case, via etching for forming the via 25, first through the SiC of the third interlayer film in a suitable gas for etching 18 (SiC film), after penetration, SiO ₂ with a gas suitable for the etching of SiO ₂ What is necessary is just to penetrate the film | membrane 33. FIG.

Further, as the hard mask 37, a SiON film may be used instead of the SiO ₂ film 35.
The epitaxial layer 3 is not limited to the MOSFET 4 and may be formed with various active elements and passive elements such as a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), and a capacitor.

  In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Silicon substrate 3 Epitaxial layer 4 MOSFET
5 Element isolation part 6 Shallow trench 7 Thermal oxide film 8 SiO ₂
9 Channel region 10 Source region 11 Drain region 12 Gate insulating film 13 Gate electrode 14 Silicide 15 Side wall 16 First interlayer film 17 Second interlayer film 18 Third interlayer film 19 Fourth interlayer film 20 First AlCu wiring 21 Second AlCu wiring 22 Contact plug 23 Lower part of contact plug 24 Upper part of contact plug 25 Via 26 Dense pattern 27 Isolated pattern 28 Low step part 29 Lower TiN / Ti film 30 AlCu film 31 Upper TiN / Ti film 32 Side wall protection Film 33 SiO ₂ film 34 AlCu wiring layer 35 SiO ₂ film 37 Hard mask

Claims (10)

Forming an AlCu wiring layer by sequentially laminating a lower TiN / Ti film, an AlCu film, and an upper TiN / Ti film on a lower layer film made of SiC or SiOC;
Forming a hard mask having a predetermined pattern made of an inorganic film on the AlCu wiring layer;
The AlCu wiring layer is patterned by dry etching the AlCu wiring layer using the hard mask, while forming a side wall protective film containing a reaction product generated by the etching on the side surface of the AlCu film during the etching. A step of forming a plurality of AlCu wirings on the lower layer film,
By dry etching the portion between the adjacent AlCu wirings in the lower layer film, while fixing the reaction product containing C dissociated from the lower layer film by the etching to the sidewall protective film, Forming a low step portion so as to lower the space between the AlCu wires by one step relative to the surface of the lower layer film in contact with the AlCu wires;
And forming an upper layer film made of SiO ₂ on the lower layer film so as to fill the AlCu wiring after the formation of the low step portion.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the plurality of AlCu wirings includes a step of forming AlCu wirings having a width of 85 nm to 180 nm so as to be arranged at intervals of 85 nm to 180 nm.   The step of forming the plurality of AlCu wirings includes a dense pattern arranged at a first interval from each other, and an isolated pattern formed from the dense pattern at a second interval wider than the first interval. The method of manufacturing a semiconductor device according to claim 1, further comprising:   4. The semiconductor according to claim 1, wherein the step of forming a hard mask includes a step of forming a hard mask having an aspect ratio (hard mask height / hard mask width) of less than 3. 5. Device manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the hard mask includes a step of forming a hard mask made of an SiO ₂ film or an SiON film. An underlayer film made of SiC or SiOC;
A sidewall protective film formed on the lower layer film, each formed by laminating a lower TiN / Ti film, an AlCu film, and an upper TiN / Ti film in this order, and including C on the side surface of each AlCu film A plurality of AlCu wires having:
Between the AlCu wirings adjacent to each other in the lower layer film, a low step portion formed one step lower than the surface of the lower layer film in contact with the AlCu wiring;
An upper layer film made of SiO ₂ formed on the lower layer film so as to fill the AlCu wiring,
Each of the plurality of AlCu wirings has a width of 85 nm to 180 nm, and includes a dense pattern arranged at intervals of 85 nm to 180 nm.   The height of each said AlCu wiring is a semiconductor device of Claim 6 which is 140 nm-205 nm.   The semiconductor device according to claim 6, wherein a height of the AlCu film is 80 nm to 120 nm.   The semiconductor device according to claim 6, wherein a height of the lower TiN / Ti film is 20 nm to 30 nm.   The semiconductor device according to claim 6, wherein a height of the upper TiN / Ti film is 40 nm to 55 nm.

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