JP2012256786A - Layout design method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout design method of a semiconductor integrated circuit device in which increase in chip size can be suppressed.SOLUTION: In a semiconductor integrated circuit device including a first power supply line to which an external power supply voltage is supplied, and a second power supply line connected with the first power supply line via a second power supply driver as a switch, and adopting an SCRC system, the overall circuit of the semiconductor integrated circuit device is divided into functional circuits in order to suppress increase in the layout area of the second power supply driver, the size of an MOS transistor used as a second power supply driver is determined, for each functional circuit region, depending on the transistor size of an SCRC use operation circuit, i.e. the circuit to be controlled by the SCRC system.

Description

  The present invention relates to a layout design method for a semiconductor integrated circuit device adopting a SCRC (Subthreshold Current Reduction Circuit) method.

  A semiconductor integrated circuit device such as a DRAM (Dynamic Random Access Memory) is required to further reduce power consumption in order to be applied to a mobile device, and accordingly, a power supply voltage is being lowered. However, when the power supply voltage is lowered, the threshold voltage of the transistor needs to be lowered. When the threshold voltage is lowered, the off-state current of the transistor, that is, the subthreshold leakage current is increased.

  As a method for reducing the subthreshold leakage current, an SCRC method has been conventionally known (see, for example, Patent Document 1). In the SCRC method, a main power supply line (hereinafter referred to as a first power supply line) to which an external power supply voltage is supplied and a sub power connected to the first power supply line via a MOS (Metal-Oxide-Semiconductor) transistor serving as a switch. A power supply line (hereinafter referred to as a second power supply line) is provided, and when the internal circuit connected to the second power supply line is in an idle state (standby state), the first power supply line is turned off. This is a method of reducing the subthreshold leakage current flowing out from each transistor by separating the internal circuit from the transistor.

  In Patent Document 1, the first power supply line and the second power supply line are formed in different wiring layers, so that the circuit that operates with the first power supply line (always energized block) and the second power supply line operate. The document describes that the degree of freedom in layout design is reduced by improving the degree of freedom of circuit (power cutoff block) placement.

JP 2010-021265 A

  In the semiconductor integrated circuit device adopting the above-described SCRC method, required power is supplied to the internal circuit from the external power supply via the first power supply line and the second power supply line, so that the on-resistance of the MOS transistor used as a switch is made as small as possible. It is desirable to do. However, in order to reduce the on-resistance of the MOS transistor, the channel width must be increased, and the layout area of the MOS transistor used as a switch increases. Therefore, there is a problem that the chip size of the semiconductor integrated circuit device increases.

  Furthermore, in the SCRC method, since the first power supply line and the second power supply line are provided on the high potential side and the low potential (ground potential) side, respectively, the number of power supply lines is increased as compared with a semiconductor integrated circuit device that does not employ the SCRC method. The layout area for arranging the power supply lines increases. For example, if the power supply line is thinned in order to suppress the layout area of the power supply line, the wiring resistance increases and the voltage drop due to the power supply line increases. In particular, in the second power supply line, the amount of voltage drop differs according to the distance from the switch, and the amount of voltage drop increases as the distance from the switch increases. Therefore, the second power supply line needs to have a certain width according to its length, and if the layout area of the power supply line increases, the chip size of the semiconductor integrated circuit device further increases.

A layout design method for a semiconductor integrated circuit device according to the present invention includes: a first power supply line to which an external power supply voltage is supplied; and a second power supply line connected to the first power supply line via a second power supply driver serving as a switch. A layout design method for a semiconductor integrated circuit device employing an SCRC method,
Dividing all circuits mounted on the semiconductor integrated circuit device into functional circuits that realize a predetermined function;
Calculate the total value of the transistor size of the SCRC use operation circuit, which is a circuit to be controlled by the SCRC method, for each function-specific circuit,
Based on the total value of the transistor sizes of the SCRC operation circuit for each function-specific circuit, calculate the transistor size of the second power supply driver necessary for the function-specific circuit,
Based on the total value of the transistor size for each circuit by function and the transistor size of the second power supply driver, respectively calculate the layout area required to arrange the circuit by function,
In this method, the function-specific circuits are arranged based on the calculated layout area.

  In the method as described above, the layout of the second power supply driver is determined in order to determine the transistor size of the second power supply driver required for each function-specific circuit in accordance with the transistor size of the SCRC use operation circuit that is the control target of the SCRC method. An increase in area can be minimized.

  According to the present invention, an increase in the chip size of the semiconductor integrated circuit device can be suppressed.

It is a figure which shows the circuit example of the semiconductor integrated circuit device which employ | adopted the SCRC system, The figure (a) is a circuit diagram, The figure (b) is a layout figure. It is a top view which shows the circuit structural example of a semiconductor integrated circuit device. It is a top view which shows the example of circuit arrangement | positioning of the semiconductor integrated circuit device of this invention. It is a top view which shows the other circuit arrangement example of the semiconductor integrated circuit device of this invention. It is a top view which shows the example of arrangement | positioning of the 2nd power supply line of the semiconductor integrated circuit device of this invention. It is a flowchart which shows an example of the process sequence of the layout design method of the semiconductor integrated circuit device of this invention.

  Next, the present invention will be described with reference to the drawings.

  1A and 1B are diagrams showing a circuit example of a semiconductor integrated circuit device adopting the SCRC method. FIG. 1A is a circuit diagram, and FIG. 1B is a layout diagram. FIG. 1 shows an inverter composed of a PMOS transistor P2 and an NMOS transistor N2 and an inverter composed of a PMOS transistor P3 and an NMOS transistor N3 as circuits to be controlled by the SCRC system (hereinafter referred to as SCRC use operation circuit). The SCRC use operation circuit is not limited to an inverter, and may be various logic circuits such as a combinational circuit, a sequential circuit, a counter, and a buffer, or a well-known analog circuit.

  As shown in FIG. 1A, a semiconductor integrated circuit device adopting the SCRC system includes two types of power supply lines for supplying a ground potential VSS and an external power supply voltage VDD as a first power supply line, and a second power supply line. As described above, the power supply line includes two types of power supply lines that supply a virtual ground potential VSS2 and a virtual external power supply voltage VDD2. The first power supply line VDD and the second power supply line VDD2 are connected via a second power supply driver P1 that is a switch, and the first power supply line VSS and the second power supply line VSS2 are connected via a second power supply driver N1 that is a switch. Connected. A PMOS transistor is used for the second power supply driver P1, and an NMOS transistor is used for the second power supply driver N1.

  The second power supply driver P1 is turned on / off according to a control signal CONTROL supplied from a control circuit (not shown), and the second power supply driver N1 is turned on / off according to a control signal CONTROLN supplied from a control circuit (not shown).

  In the inverter, which is an SCRC operation circuit, either the PMOS transistor or the NMOS transistor is connected to the second power supply line, and the second power supply driver P1 or N1 is turned off at the time of idling (standby). Detached from. FIG. 1 shows a configuration example in which either the PMOS transistor or the NMOS transistor included in the SCRC use operation circuit is connected to the second power supply line. It may be connected to a power line.

  Note that a circuit (not shown) in which the PMOS transistor and the NMOS transistor are connected to the first power supply line is a circuit that is not controlled by the SCRC system (hereinafter referred to as an SCRC unused operation circuit).

  As shown in FIG. 1B, the second power supply drivers P1, N1, the PMOS transistors P2, P3 of the SCRC use operation circuit (inverter), and the NMOS transistors N2, N3 of the SCRC use operation circuit (inverter) are respectively It is formed with a transistor size corresponding to the required current supply capability. The transistor size of a PMOS transistor or NMOS transistor is defined by its channel width, and the transistor size increases as the channel width increases.

  FIG. 2 is a plan view showing a circuit configuration example of the semiconductor integrated circuit device.

  2. Description of the Related Art Recent semiconductor integrated circuit devices are provided with a circuit (hereinafter referred to as a function-specific circuit) for realizing a plurality of functions as the number of functions increases and the scale increases.

  FIG. 2 shows a configuration example having the function-specific circuits A to F and the SCRC second power supply circuit including a plurality of second power supply drivers as a semiconductor integrated circuit device.

  FIG. 3 is a plan view showing a circuit arrangement example of the semiconductor integrated circuit device of the present invention, and FIG. 4 is a plan view showing another circuit arrangement example of the semiconductor integrated circuit device of the present invention. FIG. 5 is a plan view showing an arrangement example of the second power supply lines of the semiconductor integrated circuit device of the present invention.

  As shown in FIG. 3, the semiconductor integrated circuit device of this embodiment has a configuration in which a circuit region to be formed on a chip is divided into a plurality of function-specific circuit regions corresponding to the function-specific circuits. The function-specific circuit region has a configuration in which an SCRC use operation circuit and an SCRC non-use operation circuit for realizing a function-specific circuit are arranged in the vicinity of the center, and a second power supply driver is arranged in the vicinity thereof. The second power supply line is arranged at predetermined intervals set in advance as shown in FIG.

  In the semiconductor integrated circuit device of the present embodiment, the transistor size of the second power supply driver for each function-specific circuit region is determined according to the total value of the transistor sizes of all the SCRC operation circuits in the corresponding function-specific circuit. If the transistor size required as the second power supply driver for each function-specific circuit area is realized by using a plurality of MOS transistors so that the current flowing to each SCRC operation circuit of the corresponding function-specific circuit can be supplied. Good.

  FIG. 4 shows an example of circuit arrangement in the case where different second power supply lines are arranged corresponding to the function-specific circuits. FIG. 4 shows an example in which the second power supply line in the circuit area A by function is different from the circuit areas B to F by function. Such a configuration is effective, for example, when the on / off timing of the SCRC operation circuit is different for each function-specific circuit or when the power supply voltage is different for each function-specific circuit.

  Next, a layout design method for a semiconductor integrated circuit device according to the present invention will be described with reference to the drawings.

  FIG. 6 is a flowchart showing an example of the processing procedure of the layout design method of the semiconductor integrated circuit device of the present invention. The layout design (placement / wiring design) of the semiconductor integrated circuit device described below may be performed using an EDA (Electronic Design Automation) tool realized by a known information processing device (computer).

  As described above, in the layout design method of the semiconductor integrated circuit device according to the present embodiment, in order to suppress the increase in the layout area of the second power supply driver, the function depends on the transition size of the SCRC operation circuit for each function-specific circuit region. Thus, the size of the MOS transistor used as the second power supply driver is determined.

  Note that the first power supply line and the second power supply line are arranged at a predetermined interval, and are not included in the following design procedure.

  As shown in FIG. 6, the EDA tool first divides all circuits of the semiconductor integrated circuit device to be designed into functional circuits, and calculates the total transistor size of the SCRC operating circuit for each functional circuit. .

  Next, the EDA tool calculates the transistor size of the second power supply driver necessary for each function-specific circuit based on the total value of the transistor sizes of the SCRC operation circuit for each function-specific circuit.

  Next, the EDA tool calculates a layout area necessary for arranging each function-specific circuit based on the total value of the transistor sizes for each function-specific circuit and the transistor size of the second power supply driver.

  Subsequently, the EDA tool creates circuit arrangement data for arranging the function-specific circuits based on the calculated layout area. At this time, the positions of the SCRC use operation circuit and the second power supply driver are determined so that the wiring resistance value of the second power supply line with respect to each SCRC use operation circuit is as uniform as possible in the function-specific region. As a result, as shown in FIGS. 3 and 4, the SCRC use operation circuit and the SCRC non-use operation circuit for realizing the function-specific circuit are arranged near the center of the function-specific circuit region, and the function-specific circuit region is arranged around the function-specific circuit region. A dual power supply driver is arranged.

  Lastly, all the functional circuits are arranged based on the created circuit arrangement data, and signal lines are arranged.

  According to the semiconductor integrated circuit device of this embodiment, the transistor size of the second power supply driver required for each function-specific circuit is determined in accordance with the transistor size of the SCRC operating circuit that is the SCRC control target. An increase in the layout area of the dual power supply driver can be suppressed to a minimum, and therefore an increase in the chip size of the semiconductor integrated circuit device can be suppressed.

  Further, in the function-specific region, in order to determine the positions of the SCRC use operation circuit and the second power supply driver so that the wiring resistance value of the second power supply line with respect to each SCRC use operation circuit is uniform, Variation in the amount of voltage drop due to the power line is suppressed. In addition, since the second power supply driver is arranged corresponding to the transistor size of each SCRC operation circuit for each function-specific circuit area, the length of the second power supply line can be minimized. For this reason, the second power supply line can be made thin, and the increase in chip size can be further suppressed in addition to the fact that the layout area of the second power supply driver can be suppressed.

N1-N3 NMOS transistor P1-P3 PMOS transistor

Claims (3)

A semiconductor integrated circuit device employing an SCRC system, comprising: a first power supply line to which an external power supply voltage is supplied; and a second power supply line connected to the first power supply line via a second power supply driver serving as a switch. A layout design method,
Dividing all circuits mounted on the semiconductor integrated circuit device into functional circuits that realize a predetermined function;
Calculate the total value of the transistor size of the SCRC use operation circuit, which is a circuit to be controlled by the SCRC method, for each function-specific circuit,
Based on the total value of the transistor sizes of the SCRC operation circuit for each function-specific circuit, calculate the transistor size of the second power supply driver necessary for the function-specific circuit,
Based on the total value of the transistor size for each circuit by function and the transistor size of the second power supply driver, respectively calculate the layout area required to arrange the circuit by function,
A layout design method for a semiconductor integrated circuit device, wherein the circuit according to function is arranged based on the calculated layout area.   Positions of the SCRC use operation circuit and the second power supply driver are determined so that the wiring resistance value of the second power supply line with respect to the SCRC use operation circuit is uniform in the function-specific region where the function-specific circuit is disposed. A layout design method for a semiconductor integrated circuit device.   A semiconductor integrated circuit device designed by the layout design method for a semiconductor integrated circuit device according to claim 1.

Images