JP2012255907A - Pixel circuit, display device, electronic appliance, and driving method for pixel circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique that can surely achieve the luminance that corresponds to an input video signal level.SOLUTION: A pixel circuit, a display device, or an electronic appliance comprises: a display portion; a holding capacitor; a writing transistor writing a driving voltage corresponding to a video signal in the holding capacitor; and a driving transistor driving the display portion based on the driving voltage written in the holding capacitor. The characteristic of the driving transistor is controlled so as to suppress a reverse bias state of the driving transistor at the start of the light quenching. For controlling the characteristic of the driving transistor, the characteristic of the driving transistor is reduced at the time of light quenching, and more specifically, the threshold voltage of the driving transistor is increased and returned to the original state at the time of light emission.

Description

  The technology disclosed in this specification relates to a pixel circuit, a display device, an electronic device, and a driving method of the pixel circuit.

  Today, display devices including pixel circuits (also referred to as pixels) including display elements (also referred to as electro-optical elements) and electronic devices including the display devices are widely used. As a display element of a pixel, there is a display device using an electro-optical element whose luminance changes depending on an applied voltage or a flowing current. For example, a liquid crystal display element is a typical example of an electro-optical element whose luminance changes depending on an applied voltage, and an organic electroluminescence (Organic Electro Luminescence, Organic EL, Organic) (Light Emitting Diode, OLED; hereinafter referred to as “organic EL”) A typical example is an element. The organic EL display device using the latter organic EL element is a so-called self-luminous display device using an electro-optic element which is a self-luminous element as a pixel display element.

  By the way, in a display device using a display element, a simple (passive) matrix method and an active matrix method can be adopted as the driving method. However, although a simple matrix display device has a simple structure, there is a problem that it is difficult to realize a large and high-definition display device.

  For this reason, in recent years, a pixel signal supplied to a display element in a pixel has been changed to an active element similarly provided in the pixel, for example, an insulated gate field effect transistor (generally a transistor such as a thin film transistor (TFT)). Active matrix systems that are used and controlled as switching transistors have been actively developed.

  In a conventional active matrix display device, the threshold voltage and mobility of a transistor that drives a display element vary due to process variations. Further, the characteristics of the display element change with time. Such variations in the characteristics of the driving transistors and fluctuations in the characteristics of the elements constituting the pixel circuit, such as the display elements, affect the light emission luminance. In other words, if video signals of the same level are supplied to each pixel, all pixels should emit light with the same luminance and screen uniformity (uniformity) should be obtained. However, the characteristics of the driving transistors vary. Also, the uniformity of the screen is impaired due to the characteristic variation of the display element. Therefore, in order to uniformly control the light emission luminance over the entire screen of the display device, there is a technique for correcting display unevenness caused by characteristic variations of elements constituting a pixel circuit such as a transistor or a display element in each pixel circuit. For example, it is proposed in Japanese Patent No. 4240059 and Japanese Patent No. 4240068.

Japanese Patent No. 4240059 Japanese Patent No. 4240068

  However, it has been found that when the video signal level is high (that is, when trying to obtain a high luminance), a “luminance deficiency phenomenon” in which the luminance corresponding to the input video signal level cannot be obtained actually occurs.

  Accordingly, an object of the present disclosure is to provide a technique that can more reliably obtain luminance corresponding to an input video signal level.

  A pixel circuit according to a first aspect of the present disclosure includes a display unit, a storage capacitor, a write transistor that writes a drive voltage corresponding to a video signal to the storage capacitor, and a display based on the drive voltage written to the storage capacitor. And a drive transistor for driving the unit, and is configured to be able to suppress a reverse bias state of the drive transistor at the start of extinction. Each pixel circuit described in the dependent claims of the pixel circuit according to the first aspect of the present disclosure defines a further advantageous specific example of the pixel circuit according to the first aspect of the present disclosure.

  The display device according to the second aspect of the present disclosure includes a display unit, a storage capacitor, a write transistor that writes a drive voltage corresponding to a video signal to the storage capacitor, and a display unit based on the drive voltage written to the storage capacitor A display element having a driving transistor for driving the transistor is arranged, and further, a characteristic control unit for controlling the characteristic of the driving transistor is provided so that the reverse bias state of the driving transistor at the start of quenching is suppressed. The display device according to the second aspect can similarly apply each technique and method described in the dependent claims of the pixel circuit according to the first aspect, and the configuration to which the technique and method are applied is similar to the second aspect. A further advantageous embodiment of such a display device is defined.

  An electronic apparatus according to a third aspect of the present disclosure includes a display unit, a storage capacitor, a write transistor that writes a drive voltage corresponding to a video signal to the storage capacitor, and a display unit based on the drive voltage written to the storage capacitor Are arranged so that the reverse bias state of the signal generation unit for generating the video signal supplied to the writing transistor and the driving transistor at the start of extinction is suppressed. And a characteristic control unit for controlling the characteristic of the driving transistor. In the electronic device according to the third aspect, each technique and method described in the dependent claims of the pixel circuit according to the first aspect can be similarly applied, and the configuration to which the technique / method is applied is similar to the third aspect. Further advantageous specific examples of such electronic devices will be defined.

  A driving method of a pixel circuit according to a fourth aspect of the present disclosure is a method of driving a pixel circuit including a driving transistor that drives a display unit, and the reverse bias state of the driving transistor is suppressed at the start of extinction. Thus, the characteristics of the drive transistor are controlled. The technique and method described in the dependent claims of the pixel circuit according to the first aspect can be similarly applied to the driving method of the pixel circuit according to the fourth aspect. Further advantageous specific examples of the driving method of the pixel circuit according to the above aspect will be defined.

  In short, in the technology disclosed in this specification, the reverse bias state of the drive transistor is suppressed by controlling the characteristics of the drive transistor for a certain period before and after the extinction in conjunction with the extinction operation. Since the characteristics of the driving transistor are controlled, the driving capability of the driving transistor can be adjusted. Even if the supplied video signal level is the same, the characteristics of the drive transistor are controlled, and as a result, the luminance corresponding to the actually input video signal level can be obtained.

  For example, when a field effect transistor having a back gate effect is used as a drive transistor, when the video signal level is high (that is, when high brightness is attempted), the luminance corresponding to the input video signal level is actually obtained. It was found that an “insufficient brightness” phenomenon occurs. Using the above technique, even when a field effect transistor having a back gate effect is used as a driving transistor, the luminance corresponding to the input video signal level is reduced while avoiding the reverse bias state of the driving transistor at the start of extinction. It can be obtained more reliably.

  According to the pixel circuit according to the first aspect, the display device according to the second aspect, the electronic device according to the third aspect, and the driving method of the pixel circuit according to the fourth aspect, the reliability of the driving transistor is ensured. However, the luminance corresponding to the input video signal level can be obtained more reliably.

FIG. 1 is a block diagram showing an outline of a configuration example of an active matrix display device. FIG. 2 is a block diagram showing an outline of a configuration example of an active matrix display device compatible with color image display. 3A to 3B are diagrams illustrating a light-emitting element (substantially a pixel circuit). FIG. 4 is a diagram illustrating one form of the pixel circuit of the first comparative example. FIG. 5 is a diagram showing an overall outline of a display device including the pixel circuit of the first comparative example. FIG. 6 is a diagram illustrating one form of the pixel circuit of the second comparative example. FIG. 7 is a diagram illustrating an overall outline of a display device including the pixel circuit of the second comparative example. FIG. 8 is a diagram illustrating one form of the pixel circuit according to the first embodiment. FIG. 9 is a diagram illustrating an overall outline of a display device including the pixel circuit according to the first embodiment. FIG. 10 is a timing chart for explaining a driving method of the pixel circuit of the comparative example. FIG. 11 is a timing chart for explaining problems that occur when the drive timing shown in FIG. 10 is applied to the pixel circuit of the second comparative example. FIG. 12 is a diagram for explaining the substrate potential dependence of transistor characteristics (V _gs -I _ds characteristics). FIG. 13 is a timing chart for explaining a driving method of the pixel circuit according to the first embodiment focusing on the transistor characteristic control signal. FIG. 14 is a timing chart for explaining a driving method of the pixel circuit according to the second embodiment focusing on the transistor characteristic control signal. FIG. 15A to FIG. 15C are diagrams illustrating an example of a circuit configuration that realizes the drive timing of the second embodiment. FIGS. 16A to 16B are diagrams for explaining the third embodiment for controlling the transistor characteristic control signal. FIG. 17A to FIG. 17E are diagrams illustrating Example 4 (electronic device).

  Hereinafter, embodiments of the technology disclosed in this specification will be described in detail with reference to the drawings. When distinguishing each functional element according to its form, an alphabet or “_n” (n is a number) or a combination of these is given as a reference, and this reference is omitted when it is not particularly distinguished. To be described. The same applies to the drawings.

The description will be made in the following order.
1. Overall overview 2. Outline of display device Light emitting element 4. Driving method: Basic 5. Specific application examples:
Control of the back gate of the driving transistor Example 1: Decrease in capacity before quenching, return during light emission, no problem during the process Example 2: Decrease in capacity before quenching and maintain until light emission
Control using power supply drive pulses at the previous stage and the next stage Example 3: Capacity reduction before extinction, return during light emission, return during threshold correction only during the process
Control using power supply drive pulse and self-stage write drive pulse of previous stage and next stage Example 4: Application example to electronic equipment

<Overview>
In the configuration of this embodiment, the pixel circuit, the display device, or the electronic device is written in the display unit, the storage capacitor, the write transistor that writes the driving voltage corresponding to the video signal to the storage capacitor, and the storage capacitor. And a driving transistor for driving the display portion based on the driving voltage. In the driving method of the pixel circuit, the display device, the electronic device, and the pixel circuit (or display device), the characteristics of the driving transistor are set so that the reverse bias state of the driving transistor is suppressed at the start of extinction. Control. In controlling the characteristics of the drive transistor, control is performed so that the characteristics of the drive transistor are lowered during extinction. Here, “degradation of driving transistor characteristics” means “decreasing the amount of current when the potential relationship between the electrode ends is the same”. As an example, the threshold voltage is increased or the mobility is decreased. However, the present invention is not limited to these. For example, the threshold voltage of the driving transistor may be increased and restored to the original value during light emission. By relaxing the threshold voltage in the original state (that is, during light emission), it is possible to prevent a higher signal voltage from being required.

  In the pixel circuit, the display device, the electronic device, and the driving method of the pixel circuit (or display device) according to the present embodiment, the extinction operation is performed in conjunction with the extinction operation for stopping the drive to the display unit by the driving transistor. The reverse bias state of the drive transistor is configured to be able to be suppressed, and the characteristics of the drive transistor are configured to be controllable. By controlling the characteristics of the drive transistor in conjunction with the extinction operation, the drive capability of the drive transistor for the display portion can be adjusted even when the supplied video signal level is the same. As a result, the luminance corresponding to the input video signal level can be more reliably obtained while ensuring the reliability of the drive transistor. Even when a field effect transistor having a back gate effect is used as a drive transistor, the luminance corresponding to the supplied video signal level can be more reliably obtained while ensuring the reliability of the drive transistor.

  In the configuration of the present embodiment, it is preferable that control is performed so that the characteristics of the driving transistor are deteriorated during a certain period before the display part is extinguished until a certain period after the extinction. That is, it is a realistic countermeasure to reduce the characteristics of the drive transistor in a certain period before and after extinction.

  As a configuration of the pixel circuit, there is a case where the power supply side of the main electrode end of the drive transistor is pulse-driven so as to be a high-level power supply voltage and a low-level power supply voltage. The operation is linked. Considering the fact that the reverse bias phenomenon when a field effect transistor having a back gate effect is used as a drive transistor occurs in conjunction with the power supply operation (that is, quenching operation) to the drive transistor, the power supply operation It is preferable to control the characteristics of the drive transistor in conjunction with (that is, the quenching operation). In particular, in terms of preventing the reverse bias phenomenon from occurring more reliably, the characteristics of the driving transistor deteriorate before the power supply to the driving transistor is stopped and the display unit is extinguished rather than at the same time. It is preferable to control so that it does.

  In the configuration of this embodiment, it is preferable that the characteristics of the drive transistor be restored to the original state in conjunction with the start of light emission of the display unit. “In conjunction with the start of light emission on the display unit” is not limited to being simultaneous with the start of light emission. For example, the characteristics may be returned to the original value so that the threshold voltage of the driving transistor becomes small at the same time as the display of the display unit starts. In other words, the threshold value of the driving transistor becomes simultaneous with the writing transistor becoming non-conductive. The voltage may be reduced. Alternatively, the characteristics of the driving transistor may be restored after the display unit starts displaying stably.

  As a device configuration, one pixel circuit (display unit) may be provided, or the display unit may include pixel units arranged in a line shape or a two-dimensional matrix. In the case of a configuration including a pixel portion, the characteristic control unit preferably controls the characteristic of the driving transistor for each display unit. In the case where the display unit includes pixel units arranged in a two-dimensional matrix, the characteristic control unit can be configured to control the characteristics of the drive transistor for each display element by scanning processing. Incidentally, when controlling for each display element, the wells of the drive transistors are preferably separated separately. In the case of performing light emission control in line sequence, the well potential (transistor characteristic control signal) may be separated for each row (or column), and the well of the driving transistor does not exclude the separation for each display element. It is sufficient to separate at least every row (or column).

  In the case where the display unit includes a pixel unit arranged in a two-dimensional matrix, the following configuration can be taken. First, in terms of operation, the pulse signal for controlling the power supply to the drive transistor in the previous stage stops the power supply to the drive transistor in the previous stage and extinguishes the display portion, thereby degrading the characteristics of the drive transistor in the previous stage. be able to. In this case, control is performed so that the characteristics of the drive transistor are deteriorated before the power supply to the drive transistor is stopped and the display portion is extinguished. Further, when the pulse signal for controlling the power supply to the drive transistor at the next stage starts the power supply to the drive transistor at the next stage, the characteristics of the drive transistor at the own stage can be restored. In this case, the characteristics of the drive transistor are restored after the display unit of the own stage starts displaying stably. From the viewpoint of the circuit configuration, it is possible to provide a transistor characteristic control unit that generates a signal for controlling the characteristic of the driving transistor of the own stage based on the pulse signal that controls the power supply to the driving transistor of the previous stage. Preferably, the transistor characteristic control unit controls the characteristics of the driving transistor of the own stage based on a pulse signal for controlling power supply to the driving transistor of the previous stage and a pulse signal for controlling power supply to the driving transistor of the next stage. It is good to generate the signal to do. In addition, since the pulse signal is used for each row such as the preceding stage, the own stage, and the next stage, or the control pulse for the own stage is generated, the drive transistor has a characteristic control terminal that can control the threshold voltage. In the case of a device, the characteristic control end is preferably separated at least for each stage.

  Preferably, a transistor having a characteristic control terminal capable of controlling the threshold voltage is used as the driving transistor. In this case, a control signal for controlling the threshold voltage is supplied to the characteristic control terminal. As a transistor having a characteristic control terminal capable of controlling the threshold voltage, for example, a back gate type thin film transistor or a MOSFET (metal oxide film type field effect transistor) is preferably used. It is good to use.

  In the configuration of the present embodiment, it is preferable that the process for reducing the characteristics of the drive transistor be stopped when the drive transistor is in a state of flowing current. For example, the process for increasing the threshold voltage of the drive transistor is stopped during the threshold voltage correction process of the drive transistor. When the threshold correction is completed, the characteristics of the driving transistor may be reduced again. In this case, for example, in conjunction with the end of the process of supplying a current to the storage capacitor via the drive transistor while writing the drive voltage corresponding to the video signal to the storage capacitor (in other words, the process of correcting the threshold voltage of the drive transistor). The threshold voltage of the driving transistor is preferably increased. For example, the threshold voltage of the drive transistor may be increased simultaneously with the completion of the threshold voltage correction process, in other words, the threshold voltage of the drive transistor may be increased simultaneously with the writing transistor becoming non-conductive. Alternatively, the threshold voltage of the drive transistor may be increased before the end of the threshold voltage correction process. In other words, the threshold voltage of the drive transistor is increased before the write transistor is turned off. Also good. Alternatively, preferably, the threshold voltage of the driving transistor is decreased in conjunction with the writing of the driving voltage to the storage capacitor. For example, the threshold voltage of the driving transistor may be decreased simultaneously with the start of writing of the driving voltage to the storage capacitor. In other words, the threshold voltage of the driving transistor may be decreased simultaneously with the writing transistor becoming conductive.

  In the configuration of the present embodiment, the process for restoring the characteristics of the driving transistor at the time of light emission can take various forms as long as it is “in conjunction with the start of light emission of the display unit”. In addition, the characteristics of the drive transistor may be restored. For example, it is possible to control the characteristics of the drive transistor in conjunction with the process of supplying the current to the storage capacitor via the drive transistor while writing the drive voltage corresponding to the video signal to the storage capacitor with the write transistor turned on. Can take. The process of supplying the current to the storage capacitor through the drive transistor while writing the drive voltage corresponding to the video signal to the storage capacitor with the write transistor turned on can be used for the mobility correction process of the drive transistor. In this case, the threshold voltage of the driving transistor can be reduced in conjunction with the processing. That is, the threshold voltage of the drive transistor can be reduced in conjunction with the start of the mobility correction process of the drive transistor. For example, the threshold voltage of the drive transistor can be reduced simultaneously with the start of the mobility correction process of the drive transistor, in other words, the threshold voltage of the drive transistor can be reduced simultaneously with the writing transistor becoming conductive. .

  Or, conversely, it can be controlled so that the characteristics of the driving transistor deteriorate for a certain period before the display portion emits light. For example, the write transistor is turned on for a certain period corresponding to a process of supplying a current to the storage capacitor via the drive transistor (drive transistor mobility correction process) while writing a drive voltage corresponding to the video signal to the storage capacitor. It can also be controlled so that the characteristics of the driving transistor are degraded. For example, the threshold voltage of the drive transistor may be decreased simultaneously with the start of the mobility correction process of the drive transistor, in other words, the threshold voltage of the drive transistor may be decreased simultaneously with the writing transistor becoming conductive. Alternatively, the threshold voltage of the driving transistor may be decreased in conjunction with the display start of the display unit. For example, the threshold voltage of the driving transistor may be decreased simultaneously with the start of display on the display portion, in other words, the threshold voltage of the driving transistor may be decreased simultaneously with the writing transistor becoming non-conductive.

  Alternatively, the threshold voltage of the driving transistor can be reduced in conjunction with the writing of the driving voltage to the storage capacitor. For example, the threshold voltage of the driving transistor can be reduced simultaneously with the start of writing of the driving voltage to the storage capacitor, in other words, the threshold voltage of the driving transistor can be reduced simultaneously with the writing transistor becoming conductive. .

  A characteristic control unit for controlling the characteristics of the drive transistor so as to suppress the reverse bias state of the drive transistor at the start of extinction can be provided inside or outside the pixel circuit.

  As the display unit, for example, a light emitting element (display element) including a self-luminous light emitting unit such as an organic electroluminescence light emitting unit, an inorganic electroluminescence light emitting unit, an LED light emitting unit, or a semiconductor laser light emitting unit can be used. In particular, it may be an organic electroluminescence light emitting part.

<Outline of display device>
In the following description, in order to facilitate understanding of the correspondence relationship, the resistance value and the capacitance value (capacitance, capacitance), etc., of the circuit constituent member may be indicated by the same reference numerals as those attached to the member. is there.

[Basic]
First, an outline of a display device including a light emitting element will be described. In the following description of the circuit configuration, “electrically connected” is simply referred to as “connected”, and this “electrically connected” is not limited to being directly connected, but other transistors (switching transistors). (This is a typical example.) It is also included to be connected via other electric elements (not limited to active elements but also passive elements).

  The display device includes a plurality of pixel circuits (or simply referred to as pixels). Each pixel circuit includes a display element (electro-optical element) including a light emitting unit and a drive circuit that drives the light emitting unit. As the display unit, for example, a light emitting element including a self-luminous light emitting unit such as an organic electroluminescence light emitting unit, an inorganic electroluminescence light emitting unit, an LED light emitting unit, a semiconductor laser light emitting unit, or the like can be used. Note that a constant current drive type is adopted as a method for driving the light emitting portion of the display element, but in principle, the constant current drive type is not limited to the constant current drive type.

  In the example described below, a case where an organic electroluminescence light emitting unit is provided as a light emitting element will be described. More specifically, the light emitting element is an organic electroluminescent element (organic EL element) having a structure in which a driving circuit and an organic electroluminescent light emitting part (light emitting part ELP) connected to the driving circuit are stacked.

There are various types of driving circuits for driving the light emitting unit ELP, and the pixel circuit includes a driving circuit of 5Tr / 1C type, 4Tr / 1C type, 3Tr / 1C type, or 2Tr / 1C type. Can be configured. In the “αTr / 1C type”, α means the number of transistors, and “1C” means that the capacitor portion has one holding capacitor C _cs (capacitor). The transistors constituting the drive circuit are preferably all n-channel transistors. However, the present invention is not limited to this, and in some cases, some transistors may be p-channel transistors. Good. Note that a transistor may be formed on a semiconductor substrate or the like. The structure of the transistor constituting the drive circuit is not particularly limited, and an insulated gate field effect transistor (typically, a thin film transistor (TFT)) typified by a MOS FET can be used. Further, the transistor constituting the driver circuit may be either an enhancement type or a depletion type, and may be either a single gate type or a dual gate type.

In any configuration, the display device basically has a light emitting unit ELP, a drive transistor TR _D , and a write transistor TR _W (also referred to as a sampling transistor) as in the 2Tr / 1C type as the minimum components. A vertical scanning unit including at least a writing scanning unit, a horizontal driving unit having a function of a signal output unit, and a holding capacitor C _cs . Preferably, in order to form a bootstrap circuit, a storage capacitor C is provided between the control input terminal (gate terminal) of the driving transistor TR _D and one (typically the source terminal) of the main electrode terminal (source / drain region). _cs is connected. Driving transistor TR _D, one main electrode terminal is connected to the light emitting unit ELP, the other main electrode terminal is connected to the power supply line PWL. A power supply voltage (steady voltage or pulsed voltage) is supplied to the power supply line PWL from a power supply circuit or a scanning circuit for power supply voltage.

The horizontal drive unit _displays a video signal V _sig for controlling the luminance in the light emitting unit ELP, a video signal VS in a broad sense representing a reference potential (not limited to one type) used for threshold correction, and the like as a video signal line DTL ( Data line). Write transistor TR _W is one of the main electrode terminal connected to the video signal line DTL, the other main electrode terminal connected to the control input terminal of the drive transistor TR _D. Write scanner supplies a control input terminal of the write transistor TR _W control pulse for turning on / off control of the write transistor TR _W (write drive pulse WS) via a writing scanning line WSL. A connection point between the other end of the main electrode end of the write transistor TR _W , the control input end of the drive transistor TR _D , and one end of the storage capacitor C _cs is referred to as a first node ND ₁ , and is connected to the main electrode end of the drive transistor TR _D. A connection point between one end and the other end of the storage capacitor C _cs is referred to as a second node ND ₂ .

[Configuration example]
1 and 2 are block diagrams illustrating an outline of a configuration example of an active matrix display device that is an embodiment of a display device according to the present disclosure. FIG. 1 is a block diagram showing an outline of the configuration of a general active matrix display device, and FIG. 2 is a block diagram showing an outline in the case of color image display.

  As shown in FIG. 1, the display device 1 has a pixel circuit 10 (also referred to as a pixel) having an organic EL element (not shown) as a plurality of display elements having an aspect ratio X: A display panel unit 100 arranged to form an effective video area of Y (for example, 9:16), and a drive signal generation as an example of a panel control unit that emits various pulse signals for driving and controlling the display panel unit 100 A unit 200 (so-called timing generator) and a video signal processing unit 220 are provided. The drive signal generation unit 200 and the video signal processing unit 220 are built in a one-chip IC (Integrated Circuit), and are arranged outside the display panel unit 100 in this example.

  As shown in the figure, the product form is provided as a display device 1 in the form of a module (composite part) including all of the display panel unit 100, the drive signal generation unit 200, and the video signal processing unit 220. For example, the display device 1 may be provided only by the display panel unit 100. Further, the display device 1 includes a module-shaped one having a sealed configuration. For example, a display module formed by being attached to an opposing portion such as transparent glass on the pixel array portion 102 corresponds. A color filter, a protective film, a light shielding film, and the like may be provided on the transparent facing portion. The display module may be provided with a circuit unit for inputting / outputting a video signal Vsig and various driving pulses to / from the pixel array unit 102 from the outside, an FPC (flexible printed circuit), and the like.

  Such a display device 1 includes various electronic devices such as a portable music player, a digital camera, a notebook personal computer, a mobile phone, and the like using a recording medium such as a semiconductor memory, a mini disk (MD), and a cassette tape. A video signal input to an electronic device such as a portable terminal device or a video camera or a video signal generated in the electronic device can be used for a display unit of an electronic device in any field that displays a still image or a moving image (video).

  The display panel unit 100 includes a pixel array unit 102 in which pixel circuits 10 are arranged in a matrix of M rows × N columns on a substrate 101, a vertical drive unit 103 that scans the pixel circuits 10 in the vertical direction, and pixels A horizontal driving unit 106 (also referred to as a horizontal selector or a data line driving unit) that scans the circuit 10 in the horizontal direction, and an interface that interfaces each driving unit (vertical driving unit 103 and horizontal driving unit 106) with an external circuit. A portion 130 (IF), an external connection terminal portion 108 (pad portion), and the like are integrated. That is, peripheral drive circuits such as the vertical drive unit 103, the horizontal drive unit 106, and the interface unit 130 are formed on the same substrate 101 as the pixel array unit 102. A light emitting element (pixel circuit 10) located in the m-th row (m = 1, 2, 3,..., M) and the n-th column (n = 1, 2, 3,..., N) is represented by 10_n, Indicated by m.

  The interface unit 130 includes a vertical IF unit 133 that interfaces with the vertical drive unit 103 and an external circuit, and a horizontal IF unit 136 that interfaces with the horizontal drive unit 106 and an external circuit.

  The vertical drive unit 103 and the horizontal drive unit 106 constitute a control unit 109 that controls writing of a signal potential to a storage capacitor, threshold correction operation, mobility correction operation, and bootstrap operation. The control unit 109 and the interface unit 130 (vertical IF unit 133 and horizontal IF unit 136) constitute a drive control circuit that drives and controls the pixel circuit 10 of the pixel array unit 102.

  In the case of the 2Tr / 1C type, the vertical drive unit 103 is a drive scanning unit (drive scanner DS; Drive Scan) that functions as a write scanning unit (write scanner WS; Write Scan) or a power supply scanner having power supply capability. ). For example, the pixel array unit 102 is driven by the vertical driving unit 103 from one or both sides in the left-right direction shown in the figure, and is driven by the horizontal driving unit 106 from one side or both sides in the up-down direction shown in the drawing. Yes.

Various pulse signals are supplied to the terminal unit 108 from the drive signal generation unit 200 disposed outside the display device 1. Similarly, the video signal V _sig is supplied from the video signal processing unit 220. In the case of color display support, a video signal V _{sig_R} , a video signal V _{sig_G} , and a video signal V _{sig_B} for each color (in this example, three primary colors R (red), G (green), and B (blue)) are supplied. The

  As an example, as a pulse signal for vertical driving, a shift start pulse SP (two types of SPDS and SPWS in the figure) and a vertical scanning clock CK (two types of CKDS and CKWS in the figure) are examples of a vertical scanning start pulse. ), Necessary pulse signals such as a vertical scanning clock xCK (two types of xCKDS and xCKWS in the figure) whose phases are inverted as necessary, and an enable pulse for instructing a pulse output at a specific timing are supplied. As horizontal drive pulse signals, horizontal start pulse SPH, which is an example of a horizontal scan start pulse, horizontal scan clock CKH, horizontal scan clock xCKH whose phase is reversed as necessary, and enable to instruct pulse output at a specific timing Necessary pulse signals such as pulses are supplied.

  Each terminal of the terminal unit 108 is connected to the vertical driving unit 103 and the horizontal driving unit 106 via the wiring 109. For example, each pulse supplied to the terminal unit 108 is internally adjusted in voltage level by a level shifter unit (not shown) as necessary, and then supplied to each unit of the vertical driving unit 103 and the horizontal driving unit 106 via a buffer. Supplied.

Although the pixel array unit 102 is not shown (details will be described later), the pixel circuit 10 in which pixel transistors are provided for an organic EL element as a display element is two-dimensionally arranged in a matrix, and the pixel array A vertical scanning line SCL is wired for each row, and a video signal line DTL is wired for each column. That is, the pixel circuit 10 is connected to the direct drive unit 103 via the vertical scanning line SCL, and is connected to the horizontal drive unit 106 via the video signal line DTL. Specifically, for each pixel circuit 10 arranged in a matrix, vertical scanning lines SCL_1 to SCL_n for n rows driven by a driving pulse by the vertical driving unit 103 are wired for each pixel row. The vertical drive unit 103 is configured by a combination of logic gates (including latches, shift registers, and the like), and selects each pixel circuit 10 of the pixel array unit 102 in units of rows, that is, supplied from the drive signal generation unit 200. Each pixel circuit 10 is sequentially selected via the vertical scanning line SCL based on the pulse signal of the vertical drive system. The horizontal drive unit 106 is configured by a combination of logic gates (including latches, shift registers, and the like), and selects each pixel circuit 10 of the pixel array unit 102 in units of columns, that is, supplied from the drive signal generation unit 200. Based on the pulse signal of the horizontal drive system, a predetermined potential (for example, video signal V _sig level) in the video signal VS is sampled and written to the holding capacitor C _cs via the video signal line DTL for the selected pixel circuit 10. Make it.

  The display device 1 of the present embodiment is capable of line-sequential driving or dot-sequential driving, and the writing scanning unit 104 and the driving scanning unit 105 of the vertical driving unit 103 are pixels in line sequential (that is, in units of rows). The array unit 102 is scanned, and the horizontal drive unit 106 synchronizes with the scanning by the horizontal drive unit 106. The pixel array unit performs image signals for one horizontal line simultaneously (line sequential) or in units of pixels (dot sequential). Write to 102.

In order to achieve color image display, the pixel array unit 102 includes, for example, as shown in FIG. the pixel circuit 10 _{_R} as pixels, the pixel circuit 10 _{_G,} provided a pixel circuit 10 _{_B} vertically stripes in a predetermined arrangement order. One set of color subpixels constitutes one color pixel. Here, as an example of the subpixel layout, a stripe structure in which subpixels of each color are arranged in a vertical stripe shape is shown, but the subpixel layout is not limited to such an arrangement example. You may employ | adopt the form which shifted the sub pixel to the orthogonal | vertical direction.

  1 and 2 show a configuration in which the vertical drive unit 103 (specifically, its constituent elements) is arranged only on one side of the pixel array unit 102, each element of the vertical drive unit 103 is replaced with the pixel array unit. It is also possible to adopt a configuration in which both are arranged on both the left and right sides of 102. Moreover, it is possible to adopt a configuration in which one and the other of the elements of the vertical drive unit 103 are arranged separately on the left and right. Similarly, FIGS. 1 and 2 show a configuration in which the horizontal driving unit 106 is arranged only on one side of the pixel array unit 102, but the horizontal driving units 106 are arranged on both upper and lower sides with the pixel array unit 102 interposed therebetween. A configuration can also be adopted. In this example, pulse signals such as a vertical shift start pulse, a vertical scan clock, a horizontal start pulse, and a horizontal scan clock are input from the outside of the display panel unit 100. However, drive signals for generating these various timing pulses are used. The generation unit 200 can also be mounted on the display panel unit 100.

  The illustrated configuration only shows one form of the display device, and the product form can take other forms. That is, the display device mainly includes a pixel array unit in which elements constituting the pixel circuit 10 are arranged in a matrix, and a scanning unit that is arranged around the pixel array unit and connected to a scanning line for driving each pixel. The entire apparatus may be configured to include a control unit as a unit, a drive signal generation unit that generates various signals for operating the control unit, and a video signal processing unit. As a product form, a display panel part in which a pixel array part and a control part are mounted on the same base (for example, a glass substrate), a driving signal generation part, and a video signal processing part as shown in the figure (panel) In addition, the display panel unit is equipped with a pixel array unit, and peripheral circuits such as a control unit, a drive signal generation unit, and a video signal processing unit are provided on a separate substrate (for example, a flexible substrate). A mounting form (referred to as a peripheral circuit panel outside arrangement configuration) can be adopted. Further, in the case of a panel arrangement configuration in which the pixel array unit and the control unit are mounted on the same substrate to constitute the display panel unit, the control unit (if necessary) is simultaneously generated in the process of generating the TFT of the pixel array unit. A form for generating each transistor for the drive signal generation unit and the video signal processing unit (referred to as a transistor integrated configuration) and a control unit (on the substrate on which the pixel array unit is mounted by COG (Chip On Glass) mounting technology) It is also possible to adopt a form (referred to as a COG mounting configuration) in which a semiconductor chip for a drive signal generation unit and a video signal processing unit) is directly mounted if necessary. Alternatively, the display device can be provided only by the display panel unit (including at least the pixel array unit).

<Light emitting element>
FIG. 3 is a diagram for explaining the light emitting element 11 (substantially the pixel circuit 10) provided with a drive circuit. Here, FIG. 3A is a schematic partial cross-sectional view of a part of the light emitting element 11 (pixel circuit 10). FIG. 3B is a cross-sectional view illustrating an example of a MOS transistor structure. In FIG. 3A, the insulated gate field effect transistor is assumed to be a thin film transistor (TFT), but in this embodiment, at least the driving transistor TR _D is so-called back as described in the examples below. It is preferable to use a gate type thin film transistor or a MOS type transistor as shown in FIG. 3B, and it is particularly preferable to use a MOS type as shown in FIG. The manufacturing process is complicated (or difficult to manufacture) in order to make the thin film transistor a back gate type structure. On the other hand, in the MOS type as shown in FIG. This is because it functions as (also called bulk).

As shown in FIG. 3A, each transistor and capacitor (retention capacitor C _cs ) constituting the drive circuit of the light-emitting element 11 are formed on the support 20, and the light-emitting portion ELP includes, for example, the interlayer insulating layer 40. _Are formed above the respective transistors and the storage capacitor C _cs constituting the drive circuit. One source / drain region of the driving transistor TR _D is connected to an anode electrode provided in the light emitting unit ELP through a contact hole. In FIG. 3, only the drive transistor TR _D is shown. The writing transistor TR _W and other transistors are hidden and cannot be seen. The light emitting unit ELP has a known configuration and structure such as an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer, and a cathode electrode.

Specifically, the drive transistor TR _D includes a gate electrode 31, a gate insulating layer 32, a semiconductor layer 33, a source / drain region 35 provided in the semiconductor layer 33, and a semiconductor layer 33 between the source / drain regions 35. This portion is constituted by the corresponding channel forming region 34. The storage capacitor C _cs is composed of the other electrode 36, a dielectric layer composed of the extending portion of the gate insulating layer 32, and one electrode 37 (corresponding to the second node ND ₂ ). The gate electrode 31, a part of the gate insulating layer 32, and the other electrode 36 constituting the storage capacitor C _cs are formed on the support 20. One source / drain region 35 of the drive transistor TR _D is connected to a wiring 38, and one source / drain region 35 is connected to one electrode 37. The driving transistor TR _D and the storage capacitor C _cs are covered with an interlayer insulating layer 40, and an anode electrode 51, a hole transport layer, a light emitting layer, an electron transport layer, and a cathode electrode 53 are formed on the interlayer insulating layer 40. A light emitting unit ELP is provided. In FIG. 3, the hole transport layer, the light emitting layer, and the electron transport layer are represented by one layer 52. A second interlayer insulating layer 54 is provided on the portion of the interlayer insulating layer 40 where the light emitting part ELP is not provided, and the transparent substrate 21 is disposed on the second interlayer insulating layer 54 and the cathode electrode 53. The light emitted from the light emitting layer passes through the substrate 21 and is emitted to the outside. One electrode 37 and the anode electrode 51 are connected by a contact hole provided in the interlayer insulating layer 40. The cathode electrode 53 is connected to the wiring 39 provided on the extending portion of the gate insulating layer 32 through the second interlayer insulating layer 54, the contact hole 56 provided in the interlayer insulating layer 40, and the contact hole 55. Yes.

  In the configuration shown in FIG. 3A, when the TFT is a MOS transistor, as shown in FIG. 3B, the semiconductor substrate having the first polarity (P-type or N-type (N-type in the figure)). A gate (narrow region channel) is formed on the surface of the substrate, and a gate terminal is attached via an oxide film (in particular, a gate oxide film) so as to cover the channel. For example, polysilicon can be used as the material of the gate terminal, and it is particularly called a polygate. Further, after forming an oxide film (particularly referred to as a field oxide film) so as to cover the whole including the gate end, a second polarity (here P-type) different from the first polarity is formed at both ends of the gate terminal. Each terminal (source terminal and drain terminal) of the source region and the drain region is attached with a metal material. As a result, a MOS transistor (PMOS) (P-type device) of the second polarity (here P-type) is formed on the surface layer of the semiconductor substrate of the first polarity (N-type). In the P-type device having this structure, the back gate is an N-type substrate and is not individually separated, and control signals cannot be supplied individually or for each row (or column). A control signal common to all P-type devices can be supplied. To form a MOS transistor (NMOS) (N-type device) having a first polarity (N-type here) on the surface layer of a semiconductor substrate having the first polarity (N-type), the first polarity (N-type) is used. A well of the second polarity (P type) is formed on the surface of the semiconductor substrate, and this well (P well) is treated as a semiconductor substrate of the second polarity (P type). A source region, a drain region, and the like may be formed. In the N-type device having this structure, the well of the second polarity (P-type) can be separated individually or by row (or column), so that the well potential (transistor) can be individually or row (or column). The characteristic control signal Vb) can be separated. In forming the MOS transistor (PMOS) (P type device) of the second polarity (here P type) on the surface layer of the semiconductor substrate of the first polarity (N type), the first polarity (N type) The first polarity (N-type) well is formed on the surface of the semiconductor substrate (see the broken line in the figure), and this well (N-well) is treated as the first polarity (N-type) semiconductor substrate. In the same manner, a gate region, a source region, a drain region, and the like may be formed. Thus, in the P-type device having this structure, the first polarity (N-type) well can be separated individually or row by column (or column). In addition, the well potential (transistor characteristic control signal Vb) can be separated. The P-type device (PMOS) and the N-type device (NMOS) are separated by an element isolation region.

[Driving method]
A method for driving the light emitting unit will be described below. In order to facilitate understanding, each transistor constituting the pixel circuit 10 will be described as an n-channel transistor. The light emitting unit ELP has an anode end connected to the second node ND ₂ and a cathode end connected to the cathode wiring cath (its potential is set to the cathode potential V _cath ). Furthermore, the light emission state (luminance) in the light emitting unit ELP is controlled by the magnitude of the value of the drain current I _ds . In the light emitting state of the light emitting element, one of the two main electrode ends (source / drain regions) of the driving transistor TR _D serves as a source end (source region) and the other serves as a drain end (source region). Drain region). The display device is compatible with color display, and is composed of (N / 3) × M pixel circuits 10 arranged in a two-dimensional matrix. One pixel circuit constituting one unit of color display is 3 One of the sub-pixel circuit and is composed of (emitting red red light emitting pixel circuit 10 _{_R,} green light-emitting pixel circuit 10 _{_G} for emitting green light, blue light-emitting pixel circuit 10 _{_B} emitting blue). The light emitting elements constituting each pixel circuit 10 are driven line-sequentially, and the display frame rate is FR (times / second). That is, (N / 3) pixel circuits 10 arranged in the m-th row (where m = 1, 2, 3,..., M), more specifically, each of the N pixel circuits 10. Are simultaneously driven. In other words, in each light-emitting element constituting one row, the timing of light emission / non-light emission is controlled in units of rows to which they belong. Note that the process of writing the video signal for each pixel circuit 10 constituting one row may be the process of simultaneously writing the video signal for all the pixel circuits 10 (also referred to as a simultaneous writing process), or the video signal for each pixel circuit 10 sequentially. A signal writing process (also referred to as a sequential writing process) may be used. Which writing process is used may be appropriately selected according to the configuration of the drive circuit.

  Here, a driving operation related to the light emitting element (pixel circuit 10) located in the m-th row and the n-th column (where n = 1, 2, 3,..., N) will be described. Incidentally, the light emitting element located in the mth row and the nth column is referred to as the (n, m) th light emitting element or the (n, m) th light emitting element pixel circuit. Various processes (threshold correction process, writing process, mobility correction process, etc.) are performed before the horizontal scanning period (m-th horizontal scanning period) of each light emitting element arranged in the m-th row is completed. It is. Note that the writing process and the mobility correction process need to be performed within the m-th horizontal scanning period. On the other hand, depending on the type of the drive circuit, the threshold correction processing and the preprocessing associated therewith can be performed prior to the mth horizontal scanning period.

  After all the above-described various processes are completed, the light emitting units constituting the light emitting elements arranged in the m-th row are caused to emit light. In addition, after all the various processes are completed, the light emitting unit may emit light immediately, or the light emitting unit may emit light after a predetermined period (for example, a horizontal scanning period for a predetermined number of rows) has elapsed. . The “predetermined period” may be appropriately set according to the specifications of the display device, the configuration of the pixel circuit 10 (that is, the drive circuit), and the like. In the following, for convenience of explanation, it is assumed that the light emitting unit emits light immediately after completion of various processes. The light emission of the light emitting units constituting the light emitting elements arranged in the mth row is continued until just before the start of the horizontal scanning period of the light emitting elements arranged in the (m + m ′) th row. “M ′” may be determined according to the design specifications of the display device. That is, the light emission of the light emitting units constituting the light emitting elements arranged in the mth row of a certain display frame is continued until the (m + m′−1) th horizontal scanning period. On the other hand, from the beginning of the (m + m ′) th horizontal scanning period to the mth horizontal scanning period in the next display frame until the writing process and the mobility correction process are completed, they are arranged in the mth row. As a general rule, the light-emitting portion constituting each light-emitting element maintains a non-light-emitting state. By providing a non-light emitting period (also referred to as a non-light emitting period), afterimage blur caused by active matrix driving is reduced, and the quality of moving images can be improved. However, the light emission state / non-light emission state of each pixel circuit 10 (light emitting element) is not limited to the state described above. The time length of the horizontal scanning period is a time length of less than (1 / FR) × (1 / M) seconds. When the value of (m + m ′) exceeds M, the excess horizontal scanning period is processed in the next display frame.

  A transistor in an on state (conducting state) means a state in which a channel is formed between the main electrode ends (between the source / drain regions), and a current flows from one main electrode end to the other main electrode end. It doesn't matter whether it is flowing or not. The transistor being in an off state (non-conducting state) means a state in which no channel is formed between the main electrode ends. The main electrode end of a certain transistor is connected to the main electrode end of another transistor means that the source / drain region of a certain transistor and the source / drain region of another transistor occupy the same region. Includes. Furthermore, the source / drain regions can be composed not only of conductive materials such as polysilicon or amorphous silicon containing impurities, but also metals, alloys, conductive particles, their laminated structures, organic materials (conductive Polymer). In the timing chart used in the following description, the length of the horizontal axis (time length) indicating each period is a schematic one and does not indicate the ratio of the time length of each period.

  The driving method of the pixel circuit 10 includes a preprocessing step, a threshold correction processing step, a video signal writing processing step, a mobility correction step, and a light emission step. The preprocessing step, the threshold correction processing step, the video signal writing processing step, and the mobility correction step are collectively referred to as a non-light emitting step. Depending on the configuration of the pixel circuit 10, the video signal writing process and the mobility correction process may be performed simultaneously. Each process will be outlined.

Incidentally, the drive transistor TR _D is driven so that the drain current I _ds flows according to the following formula (1) in the light emitting state of the light emitting element. When the drain current I _ds flows through the light emitting unit ELP, the light emitting unit ELP emits light. Furthermore, the light emission state (luminance) in the light emitting unit ELP is controlled by the magnitude of the value of the drain current I _ds . In the light emitting state of the light emitting element, one of the two main electrode ends (source / drain regions) of the driving transistor TR _D serves as a source end (source region) while the other serves as a drain end. Work as (drain region). For convenience of description, in the following description, one main electrode end of the drive transistor TR _D may be simply referred to as a source end, and the other main electrode end may be simply referred to as a drain end. Effective mobility μ, channel length L, channel width W, potential difference (gate-source voltage) V between control electrode end potential (gate potential V _g ) and source end potential (source potential V _s ) V _gs , threshold voltage V _th , equivalent capacitance C _ox ((dielectric constant of gate insulating layer) × (dielectric constant of vacuum) / (thickness of gate insulating layer)), coefficient k≡ (1/2) · (W / L) · C _ox .

I _ds = k · μ · (V _gs −V _th ) ² (1)

In the following description, unless otherwise specified, the capacitance C _el of the parasitic capacitance of the light emitting unit ELP is an example of the capacitance C _cs of the holding capacitor C _cs and the parasitic capacitance of the driving transistor TR _D. A source region (second node) of the drive transistor TR _D based on a change in the potential (gate potential V _g ) of the gate end of the drive transistor TR _D is assumed to be a sufficiently large value compared with the capacitance C _gs between the sources. ND ₂ ) potential (source potential V _s ) is not considered.

[Pretreatment process]
The potential difference between the first node ND ₁ and the second node ND ₂ exceeds the threshold voltage V _th of the driving transistor TR _D , and between the second node ND ₂ and the cathode electrode provided in the light emitting unit ELP. The first node initialization voltage (V _ofs ) is applied to the first node ND ₁ and the second node initialization voltage is applied to the second node ND ₂ so that the potential difference between the first node ND ₁ and the threshold voltage V _thEL does not exceed the threshold voltage V _thEL. (V _ini ) is applied. For example, the video signal V _sig for controlling the luminance in the light emitting unit ELP is 0 to 10 volts, the power supply voltage V _cc is 20 volts, the threshold voltage V _th of the driving transistor TR _D is 3 V, the cathode potential V _cath is 0 volts, The threshold voltage V _thEL of the light emitting unit ELP is 3 volts. In this case, the potential V _ofs for initializing the potential of the control input terminal of the drive transistor TR _D (gate potential V _g , that is, the potential of the first node ND ₁ ) is 0 volts, and the potential of the source terminal of the drive transistor TR _D The potential V _ini for initializing (the source potential V _s, that is, the potential of the second node ND ₂ ) is −10 volts.

[Threshold correction processing step]
While maintaining the potential of the first node ND _1, by supplying a drain current I _ds to the drive transistor TR _D, toward an electric potential obtained by subtracting the threshold voltage V _th of the driving transistor TR _D from the first node potential of ND ₁ The potential of the second node ND ₂ is changed. At this time, the pretreatment step after the second node ND ₂ in a voltage exceeding the threshold voltage V _th of the voltage obtained by adding the driving transistor TR _D to the potential (e.g., power supply voltage during light emission), a main driving transistor TR _D It is applied to the other electrode end (the side opposite to the second node ND ₂ ). In the threshold value correction process, (in other words, the driving transistor TR gate-source voltage of the _D V _gs) the potential difference between the first node ND ₁ and the second node ND ₂ is the threshold voltage V of the drive transistor TR _{D The} degree of approaching _th depends on the threshold correction processing time. Thus, for example, if the threshold correction processing time is sufficiently long, the potential of the second node ND ₂ reaches the potential obtained by subtracting the threshold voltage V _th of the drive transistor TR _D from the potential of the first node ND ₁ , and the drive transistor TR _D Is turned off. On the other hand, for example, when the threshold correction processing time must be set short, the potential difference between the first node ND ₁ and the second node ND ₂ is larger than the threshold voltage V _th of the drive transistor TR _D , and the drive transistor TR _D may not be off. As a result of the threshold correction process, the drive transistor TR _D does not necessarily have to be turned off. In the threshold value correction processing step, preferably, the light emitting unit ELP does not emit light by selecting and determining a potential so as to satisfy Expression (2).

_{(V ofs -V th) <(} V thEL + V cath) (2)

[Video signal writing process]
The video signal V _sig is applied from the video signal line DTL to the first node ND ₁ via the write transistor TR _W that is turned on by the write drive pulse WS from the write scanning line WSL, and the first node ND ₁ Increase the potential of ₁ to V _sig . The electric charge based on the potential change (V _in = V _sig −V _ofs ) of the electric first node ND ₁ becomes the holding capacitor C _cs , the parasitic capacitance C _el of the light emitting unit ELP, and the parasitic capacitance (for example, gate) of the driving transistor TR _{D. -The} capacity between sources C _gs etc.). If the capacitance value C _el is sufficiently larger than the capacitance value C _cs and the gate capacitance value C _gs , the change in the potential of the second node ND ₂ based on the potential change (V _sig −V _ofs ) is small. In general, the capacitance value C _el of the parasitic capacitance C _el of the light emitting unit ELP is larger than the capacitance value C _cs and the gate capacitance value C _gs of the storage capacitor C _cs . In consideration of this point, the potential change of the second node ND ₂ caused by the potential change of the first node ND ₁ is not taken into account, unless otherwise required. In this case, the gate-source voltage V _gs can be expressed by Equation (3).

V _g = V _sig
V _s ≒ V _ofs -V _th
V _gs ≈ V _sig − (V _ofs −V _th ) (3)

[Mobility correction process]
While supplying the video signal V _sig to one end of the holding capacitor C _cs via the write transistor TR _W (that is, while writing the drive voltage corresponding to the video signal V _sig to the holding capacitor C _cs ), via the drive transistor TR _D Current is supplied to the holding capacitor C _cs . For example, the drive is performed in a state where the video signal V _sig is supplied from the video signal line DTL to the first node ND ₁ via the write transistor TR _W turned on by the write drive pulse WS from the write scanning line WSL. Power is supplied to the transistor TR _D and the drain current I _ds flows to change the potential of the second node ND ₂ , and after a predetermined period, the write transistor TR _W is turned off. The change in potential of the second node ND ₂ at this time is represented by ΔV (= potential correction value, negative feedback amount). The predetermined period for executing the mobility correction process may be determined in advance as a design value when designing the display device. In this case, the mobility correction period is preferably determined so as to satisfy the formula (2A). By doing so, the light emitting unit ELP does not emit light during the mobility correction period.

(V _ofs −V _th + ΔV) <(V _thEL + V _cath ) (2A)

When the value of mobility μ of the driving transistor TR _D is large, the potential correction value ΔV is large, and when the value of mobility μ is small, the potential correction value ΔV is small. The gate-source voltage V _gs (that is, the potential difference between the first node ND ₁ and the second node ND ₂ ) of the driving transistor TR _D at this time can be expressed by Expression (4). Although the gate-source voltage V _gs defines the luminance at the time of light emission, the potential correction value ΔV is proportional to the drain current I _ds of the driving transistor TR _{D and} the drain current I _ds is proportional to the mobility μ. Since the potential correction value ΔV increases as the mobility μ increases, variations in the mobility μ for each pixel circuit 10 can be removed.

V _gs ≈ V _sig − (V _ofs −V _th ) −ΔV (4)

Incidentally, if the mobility correction process is defined in another expression, the video signal is supplied to the control input terminal of the drive transistor TR _D and one end of the holding capacitor via the write transistor TR _W and held via the drive transistor TR _D. It can also be referred to as a process of supplying current to the capacitor.

[Light emission process]
The first node ND ₁ in a floating state by the OFF state of the writing transistor TR _W by the write drive pulse WS from the write scanning line WSL, a driving transistor TR _D to supply power to the driving transistor TR _D The current I _ds corresponding to the gate-source voltage V _gs (potential difference between the first node ND ₁ and the second node ND ₂ ) of the driving transistor TR _D is caused to flow through the light emitting unit ELP. To emit light.

[Differences due to drive circuit configuration]
Here, the differences between the typical 5Tr / 1C type, 4Tr / 1C type, 3Tr / 1C type, and 2Tr / 1C type are as follows. In the 5Tr / 1C type, a first transistor TR ₁ (light emission control transistor) connected between the main electrode end on the power supply side of the drive transistor TR _{D and} the power supply circuit (power supply unit), and a second node initialization voltage A second transistor TR ₂ to be applied and a third transistor TR ₃ to apply a first node initialization voltage are provided. The first transistor TR ₁ , the second transistor TR ₂ , and the third transistor TR ₃ are all switching transistors. The first transistor TR ₁ is turned on during the light emission period, is turned off, enters the non-light emission period, is turned on once during the subsequent threshold correction period, and is turned on after the mobility correction period (also in the next light emission period). State. The second transistor TR ₂ is turned on only during the initialization period of the second node, and is turned off otherwise. The third transistor TR ₃ is turned on only during the threshold correction period from the initialization period of the first node, and is otherwise turned off. The writing transistor TR _W is turned on from the video signal writing processing period to the mobility correction processing period, and is otherwise turned off.

In the 4Tr / 1C type, the third transistor TR ₃ for applying the first node initialization voltage is omitted from the 5Tr / 1C type, and the first node initialization voltage is time-divisionally divided from the video signal line DTL to the video signal V _sig. Supplied. In order to supply the first node initialization voltage from the video signal line DTL to the first node during the initialization period of the first node, the write transistor TR _W is also turned on during the initialization period of the first node. Typically, the write transistor TR _W is turned on from the initializing period of the first node to the mobility correction processing period, and is otherwise turned off.

In the 3Tr / 1C type, the second transistor TR ₂ and the third transistor TR ₃ are omitted from the 5Tr / 1C type, and the first node initialization voltage and the second node initialization voltage are supplied from the video signal line DTL to the video signal V _sig. And supplied in a time-sharing manner. The potential of the video signal line DTL is set such that the second node is set to the second node initialization voltage during the initialization period of the second node, and the first node is set to the first node initialization voltage during the subsequent initialization period of the first node. in order to set, to the first node initialization voltage V _{Ofs_L} thereafter supplies a voltage V _{Ofs_H} corresponding to the second node initialization voltage (= V _ofs). Correspondingly, the write transistor TR _W is also turned on in the initializing period of the first node and the initializing period of the second node. Typically, the write transistor TR _W is turned on from the initialization period of the second node to the mobility correction processing period, and is otherwise turned off.

Incidentally, in the 3Tr / 1C type, the potential of the second node ND ₂ is changed using the video signal line DTL. Therefore, the capacitance C _cs of the storage capacitor C _cs, design, larger than the other driving circuits (for example, about 1 / 4-1 / 3 of about capacitance C _cs of the electrostatic capacitance C _el ). Therefore, it is considered that the potential change of the second node ND ₂ caused by the potential change of the first node ND ₁ is larger than that of the other driving circuits.

In the 2Tr / 1C type, the first transistor TR ₁ , the second transistor TR _2, and the third transistor TR ₃ are omitted from the 5Tr / 1C type, and the first node initialization voltage is obtained from the video signal line DTL and the video signal V _sig . The second node initialization voltage is supplied in a time-sharing manner, and the second node initialization voltage is applied to the main electrode end on the power source side of the driving transistor TR _D by the first potential V _cc — _H (= 5Tr / 1C type V _cc ) and the second potential V _cc — _L (= 5Tr / 1C type V _ini ). The main electrode end on the power supply side of the driving transistor TR _D is set to the first potential V _{cc_H} during the light emission period and enters the non-light emission period by being _set to the second potential V _{cc_L} , and after the subsequent threshold correction period (next light emission) The first potential V _{cc — H} is also set during the period). In order to supply the first node initialization voltage from the video signal line DTL to the first node during the initialization period of the first node, the write transistor TR _W is also turned on during the initialization period of the first node. Typically, the write transistor TR _W is turned on from the initializing period of the first node to the mobility correction processing period, and is otherwise turned off.

  Here, the case where correction processing is performed for both the threshold voltage and the mobility as the characteristic variation of the drive transistor has been described, but correction processing may be performed for only one of them.

In the 5Tr / 1C type, 4Tr / 1C type, and 3Tr / 1C type operations, the writing process and the mobility correction may be performed separately, and the movement is performed in the writing process as in the case of the 2Tr / 1C type. The degree correction process may be performed together. Specifically, the video signal V _Sig may be applied from the data line DTL to the first node via the write transistor TR _W with the first transistor TR ₁ (light emission control transistor) turned on.

<Specific application examples>
Hereinafter, a specific application example of the technique for controlling the threshold voltage V _th of the driving transistor TR _D will be described. In a display device using an active matrix organic EL panel, for example, various gate signals (control pulses) to be supplied to the control input terminal of the transistor are generated by vertical scanning units arranged on both sides or one side of the panel. Then, the signal is applied to the pixel circuit 10. Furthermore, in a display device using such an organic EL panel, a 2Tr / 1C type pixel circuit 10 may be used in order to reduce the number of elements and increase the definition. In consideration of this point, the following description will be made with a typical example of application to a 2Tr / 1C type configuration.

[Pixel circuit]
4 and FIG. 5 are diagrams showing one mode of a pixel circuit 10X of a first comparative example for each example and a display device including the pixel circuit 10X. A display device including the pixel circuit 10X of the first comparative example in the pixel array unit 102 is referred to as a display device 1X of the first comparative example. FIG. 4 shows a basic configuration (for one pixel), and FIG. 5 shows a specific configuration (the entire display device). 6 and 7 are diagrams showing one mode of a pixel circuit 10Y of a second comparative example for each example and a display device including the pixel circuit 10Y. A display device including the pixel circuit 10Y of the second comparative example in the pixel array unit 102 is referred to as a display device 1Y of the second comparative example. FIG. 6 shows a basic configuration (for one pixel), and FIG. 7 shows a specific configuration (the entire display device). FIG. 8 and FIG. 9 are diagrams illustrating one mode of the pixel circuit 10A of the first embodiment and a display device including the pixel circuit 10A. A display device including the pixel circuit 10A according to the first embodiment in the pixel array unit 102 is referred to as a display device 1A according to the first embodiment. FIG. 8 shows a basic configuration (for one pixel), and FIG. 9 shows a specific configuration (the entire display device). In each of the comparative examples and the first embodiment, the vertical driving unit 103 and the horizontal driving unit 106 provided on the periphery of the pixel circuit 10 on the substrate 101 of the display panel unit 100 are also shown. The same applies to other embodiments described later.

First, the reference A, the reference X, and the reference Y are omitted, and common portions in the comparative example and the first embodiment will be described. The display device 1 causes the electro-optical element in the pixel circuit 10 (in this example, the organic EL element 127 is used as the light emitting unit ELP) to emit light based on the video signal V _sig (specifically, the signal amplitude V _in ). Therefore, the display device 1 includes at least a driving transistor 121 (driving transistor TR _D ) that generates a driving current and a control input terminal (driving transistor TR _D ) that generates a driving current in the pixel circuit 10 arranged in a matrix in the pixel array unit 102. A holding capacitor 120 (holding capacitor C _cs ) connected between the gate end is a typical example) and an output end (the source end is a typical example), and is an example of an electro-optic element connected to the output end of the driving transistor 121 EL element 127 (light emitting unit ELP), and includes a sampling transistor 125 (the write transistor TR _W) for writing the information corresponding to the storage capacitor 120 to the signal amplitude V _in. In the pixel circuit 10, the driving current I _ds based on the information held in the holding capacitor 120 is generated by the driving transistor 121 and is caused to flow through the organic EL element 127 which is an example of an electro-optical element, thereby emitting the organic EL element 127. Let

Since the sampling transistor 125 writes information corresponding to the signal amplitude V _in to the holding capacitor 120, the sampling transistor 125 takes in the signal potential (V _ofs + V _in ) at its input terminal (either the source terminal or the drain terminal) Information corresponding to the signal amplitude Vin is written _{in the} storage capacitor 120 connected to the output terminal (the other of the source terminal and the drain terminal). Of course, the output terminal of the sampling transistor 125 is also connected to the control input terminal of the drive transistor 121.

  Note that the connection configuration of the pixel circuit 10 shown here is the most basic configuration, and the pixel circuit 10 only needs to include at least each of the above-described components. That is, other components) may be included. Further, the “connection” is not limited to the direct connection, but may be a connection through other components. For example, a change such as interposing a switching transistor or a functional unit having a certain function may be added between the connections as necessary. Typically, in order to dynamically control the display period (in other words, the non-light emission time), a switching transistor is provided between the output terminal of the driving transistor 121 and the electro-optical element (organic EL element 127), or The drive transistor 121 may be disposed between a power supply end (a drain end is a typical example) and a power supply line PWL (power supply line 105DSL in this example) which is a power supply wiring. Even in the pixel circuit having such a modified mode, as long as the configuration and operation described in the first embodiment (or other embodiments) can be realized, the modified mode is also applicable to the display device according to the present disclosure. 1 is a pixel circuit 10 that realizes the embodiment of FIG.

Further, in the peripheral portion for driving the pixel circuit 10, for example, the pixel circuit 10 is sequentially scanned by sequentially controlling the sampling transistors 125 in a horizontal cycle, and a video signal is supplied to each holding capacitor 120 for one row. The write scanning unit 104 that writes information according to the signal amplitude V _in of V _sig and the line scanning in the writing scanning unit 104 are applied to the power supply end of each drive transistor 121 for one row. A control unit 109 including a driving scanning unit 105 that outputs a scanning driving pulse (power driving pulse DSL) for controlling power supply is provided. The control unit 109 also receives a video signal V _sig that switches between the reference potential (V _ofs ) and the signal potential (V _ofs + V _in ) within each horizontal period in accordance with the line sequential scanning in the writing scanning unit 104. A horizontal driving unit 106 is provided to control the supply to 125.

The control unit 109 preferably supplies the video signal V _sig to the control input terminal of the drive transistor 121 by turning off the sampling transistor 125 when information corresponding to the signal amplitude V _in is written _{in the} storage capacitor 120. It is preferable to perform control so that the bootstrap operation in which the potential at the control input terminal is interlocked with the potential fluctuation at the output terminal of the drive transistor 121 is stopped. The control unit 109 preferably executes the bootstrap operation even at the beginning of light emission after the end of the sampling operation. That is, the sampling transistor 125 is turned off after the sampling transistor 125 is turned on in a state where the signal potential (V _ofs + V _in ) is supplied to the sampling transistor 125, so that the control input terminal of the driving transistor 121 is turned off. The potential difference at the output end is kept constant.

Further, the control unit 109 preferably controls the bootstrap operation so as to realize the temporal variation correction operation of the electro-optical element (organic EL element 127) in the light emission period. For this reason, the control unit 109 continuously turns off the sampling transistor 125 during the period in which the drive current I _ds based on the information stored in the storage capacitor 120 flows through the electro-optical element (organic EL element 127). In this case, it is preferable that the voltage at the control input terminal and the output terminal can be kept constant and the temporal variation correction operation of the electro-optic element is realized. Even if the current-voltage characteristic of the organic EL element 127 varies with time due to the bootstrap operation of the storage capacitor 120 during light emission, the potential difference between the control input terminal and the output terminal of the drive transistor 121 is kept constant by the bootstrap storage capacitor 120. Therefore, a constant light emission brightness is always maintained. Preferably, the control unit 109 conducts the sampling transistor 125 in a time zone in which the reference potential (= first node initialization voltage V _ofs ) is supplied to the input terminal (source terminal is a typical example) of the sampling transistor 125. As a result, the threshold value correcting operation for holding the voltage corresponding to the threshold voltage V _th of the driving transistor 121 in the holding capacitor 120 is controlled.

The threshold correction operation, if necessary, may repeatedly performed in a plurality of horizontal periods preceding the writing to the storage capacitor 120 of the information corresponding to the signal amplitude V _in. Here, “as necessary” means a case where a voltage corresponding to the threshold voltage of the drive transistor 121 cannot be sufficiently held in the storage capacitor 120 in the threshold correction period within one horizontal cycle. By performing the threshold correction operation a plurality of times, a voltage corresponding to the threshold voltage V _th of the drive transistor 121 is reliably held in the holding capacitor 120.

More preferably, prior to the threshold value correcting operation, the control unit 109 conducts the sampling transistor 125 during a time period in which the reference potential (V _ofs ) is supplied to the input terminal of the sampling transistor 125 to perform threshold value correction. Control is performed to execute a preparatory operation (discharge operation or initialization operation). Prior to the threshold correction operation, the potentials of the control input terminal and the output terminal of the drive transistor 121 are initialized. More specifically, the storage capacitor 120 is connected between the control input terminal and the output terminal, so that the potential difference between both ends of the storage capacitor 120 is set to be equal to or higher than the threshold voltage _Vth .

In the threshold correction in the 2Tr / 1C driving configuration, the control unit 109 _supplies the driving current I _ds to each pixel circuit 10 for one row in accordance with the line sequential scanning in the writing scanning unit 104. the first may be disposed a driving scanning unit 105 to output by switching between different second potential V _{cc - L} is the potential V _{cc - H} and the first potential V _{cc - H} used for flow through the (organic EL element 127). Then, the sampling transistor 125 is turned on in a time zone in which the voltage corresponding to the first potential V _{cc — H} is supplied to the power supply terminal of the driving transistor 121 and the signal potential (V _ofs + V _in ) is supplied to the sampling transistor 121. Thus, it is preferable to perform control so that the threshold value correction operation is performed. In the preparatory operation for threshold correction in the 2TR drive configuration, a voltage corresponding to the second potential V _cc — _L (= second node initialization voltage V _ini ) is supplied to the power supply terminal of the drive transistor 121, and the sampling transistor 125 The sampling transistor 125 is turned on during a time period in which the reference potential (V _ofs ) is supplied to the control input terminal (ie, the first node ND ₁ ) of the drive transistor 121 to the reference potential (V _ofs ). It is _preferable to initialize the potential of the output terminal (that is, the second node ND ₂ ) to the second potential V _{cc_L} .

More preferably, after the threshold correction operation, the control unit 109 is supplied with a voltage corresponding to the first potential V _{cc — H} to the drive transistor 121 and is supplied with the signal potential (V _ofs + V _in ) to the sampling transistor 125. When the information of the signal amplitude Vin is written _in the holding capacitor 120 by making the sampling transistor 125 conductive in the band, the correction for the mobility μ of the driving transistor 121 is controlled to be added to the information written in the holding capacitor 120. At this time, the sampling transistor 125 may be turned on at a predetermined position within a time zone in which the signal potential (V _ofs + V _in ) is supplied to the sampling transistor 125 for a period shorter than the time zone. Hereinafter, an example of the pixel circuit 10 in the 2Tr / 1C driving configuration will be specifically described.

The pixel circuit 10 is basically an n-channel thin film field effect transistor, and a driving transistor is configured. In addition, a circuit for suppressing fluctuations in the drive current I _ds to the organic EL element due to deterioration over time of the organic EL element, that is, a change in the current-voltage characteristic of the organic EL element which is an example of an electro-optical element is corrected. A threshold value correction function and a mobility correction function provided with a drive signal stabilization circuit (part 1) for maintaining the drive current I _ds constant, and preventing fluctuations in the drive current due to characteristic variations (threshold voltage variations and mobility variations) of the drive transistor This is characterized in that a driving method for realizing the above and maintaining the driving current Ids constant is adopted.

As a method of suppressing the influence on the drive current I _ds due to the characteristic variation of the drive transistor 121 (for example, variation or fluctuation in threshold voltage, mobility, etc.), the drive circuit of the 2TR configuration is used as it is as a drive signal stabilization circuit (part 1). This is dealt with by devising the drive timing of each transistor (drive transistor 121 and sampling transistor 125). The pixel circuit 10 has a 2TR drive configuration, and since the number of elements and wirings is small, in addition to being able to achieve high definition, sampling can be performed without deterioration of the video signal V _sig , so that good image quality can be obtained. Can do.

  The pixel circuit 10 has a feature in the connection mode of the storage capacitor 120, and is a bootstrap that is an example of a drive signal stabilization circuit (part 2) as a circuit that prevents fluctuations in the drive current due to deterioration of the organic EL element 127 over time. The circuit is configured. A feature is that it has a drive signal stabilization circuit (part 2) that realizes a bootstrap function that makes the drive current constant even when the current-voltage characteristic of the organic EL element changes with time (to prevent fluctuations in the drive current). Have

  The pixel circuit 10 includes an auxiliary capacitor 310 related to a write gain, a bootstrap gain, and a mobility correction period. However, it is not essential to provide this auxiliary capacity 310. The basic control operation for driving the pixel circuit 10 is the same as that in the pixel circuit 10 that does not include the auxiliary capacitor 310.

  FETs (field effect transistors) are used as the transistors including the driving transistor. In this case, for the drive transistor, the gate end is handled as a control input end, either the source end or the drain end (here, the source end) is handled as the output end, and the other is the power supply end (here the drain end). ).

Specifically, as illustrated in FIGS. 4 and 5, the pixel circuit 10 includes an n-channel driving transistor 121 and a sampling transistor 125, and an organic EL element that is an example of an electro-optical element that emits light when a current flows. 127. In general, since the organic EL element 127 has a rectifying property, it is represented by a diode symbol. The organic EL element 127 has a parasitic capacitance _Cel . In the figure, this parasitic capacitance _Cel is shown in parallel with the organic EL element 127 (diode-like one).

The drive transistor 121 has a drain end D connected to the power supply line 105DSL supplying the first potential _{Vcc_H} or the second potential _{Vcc_L,} and a source end S connected to the anode end A of the organic EL element 127 (connection thereof). The point is a second node ND ₂ and is referred to as a node ND 122), and the cathode terminal K of the organic EL element 127 is connected to the cathode wiring cath (potential is the cathode potential V _cath , for example, GND) common to all the pixel circuits 10. It is connected. The cathode wiring cath may be only a single layer wiring (upper layer wiring) for that purpose. For example, an auxiliary wiring for cathode wiring is provided on the anode layer where the wiring for anode is formed, and the resistance of the cathode wiring is set. The value may be reduced. The auxiliary wiring is wired in a grid, column, or row in the pixel array unit 102 (display area), and is set to a fixed potential at the same potential as the upper layer wiring.

The sampling transistor 125 has a gate terminal G connected to the writing scanning line 104WS from the writing scanning unit 104, a drain terminal D connected to the video signal line 106HS (video signal line DTL), and a source terminal S connected to the driving transistor 121. (The connection point is the first node ND ₁ and the node ND 121). The gate terminal G of the sampling transistor 125 is supplied with an active H write drive pulse WS from the write scanning unit 104. The sampling transistor 125 may have a connection mode in which the source terminal S and the drain terminal D are reversed.

The drain terminal D of the drive transistor 121 is connected to a power supply line 105DSL from the drive scanning unit 105 that functions as a power scanner. The power supply line 105DSL is characterized in that the power supply line 105DSL itself has a power supply capability to the drive transistor 121. The drive scanning unit 105 has a first voltage _{Vcc_H} on the high voltage side corresponding to the power supply voltage and a second voltage on the low voltage side used for the preparatory operation prior to threshold correction with respect to the drain terminal D of the drive transistor 121. _{Vcc_L} (also referred to as initialization voltage or initial voltage) is switched and supplied.

The pixel circuit 10 drives the drain end D side (power supply circuit side) of the drive transistor 121 with the power supply drive pulse DSL that takes two values of the first potential V _{cc_H} and the second potential V _{cc_L} , thereby preparing for threshold correction. The operation can be performed. The second potential V _{cc - L,} and _the reference electric potential (V _ofs) sufficiently lower than the potential of the video signal V _sig of the video signal line 106HS. Specifically, the power supply line 105DSL is low so that the gate-source voltage V _gs (the difference between the gate potential V _g and the source potential V _s ) of the driving transistor 121 is larger than the threshold voltage V _th of the driving transistor 121. A second potential V _{cc_L} on the potential side is set. The reference potential (V _ofs ) is used for an initialization operation prior to the threshold correction operation and also used for precharging the video signal line 106HS in advance.

In such a pixel circuit 10, when driving the organic EL element 127, the first potential V _{cc — H} is supplied to the drain terminal D of the driving transistor 121, and the source terminal S is connected to the anode terminal A side of the organic EL element 127. Thus, a source follower circuit is formed as a whole.

When such a pixel circuit 10 is employed, a 2TR drive configuration using one switching transistor (sampling transistor 125) for scanning in addition to the drive transistor 121 is adopted, and a power supply drive pulse DSL for controlling each switching transistor is used. In addition, by setting the on / off timing of the write drive pulse WS, the influence on the drive current I _ds due to deterioration with time of the organic EL element 127 and characteristic changes of the drive transistor 121 (for example, variations and fluctuations in threshold voltage, mobility, etc.) prevent.

In addition, in the display device 1A according to the first embodiment, for each pixel circuit 10A, a node ND122 (a connection point between the source terminal S of the driving transistor 121 and one terminal of the storage capacitor 120 and the anode terminal A of the organic EL element 127). A supplemental capacitor 310 which is a capacitive element having a capacitance C _sub is added. Regardless of the connection location of the other terminal (referred to as node ND310) of the auxiliary capacitor 310, the auxiliary capacitor 310 is electrically connected in parallel with the organic EL element 127 (its parasitic capacitance C _el ) in terms of circuit configuration. As an example, the connection point of the node ND310 is a cathode wiring cath (may be an upper layer wiring or an auxiliary wiring) common to all the pixel circuits 10 to which the cathode ends K of all the organic EL elements 127 are connected. In addition to this, the connection point of the node ND310 is, for example, a power supply line 105DSL at its own stage (row), a power supply line 105DSL other than its own stage (row), or a fixed potential of any value (including ground potential). It is good also as a point. Depending on the connection point of the node ND310, there are advantages and disadvantages (advantages and disadvantages), but the explanation is omitted here.

The capacitance C _el of the parasitic capacitance C _el of the electrostatic capacitance C _cs and the organic EL element 127 of the storage capacitor 120, with a compromise between write gain G _in a bootstrap gain G _bst, what the gain moderate To be determined. The write gain G _in and the bootstrap gain G _bst can be adjusted by adjusting the capacitance C _sub of the auxiliary capacitor 310. If this is utilized, white balance can be _achieved by relatively adjusting the capacitance C _sub between the RGB three-pixel circuits 10. That is, since the light emission efficiency of the organic EL elements 127 for R, G, and B colors is different, when there is no auxiliary capacitor 310, white balance is obtained when the same drive current I _ds (that is, the same signal amplitude V _in ). because can not be taken, so that the white balance by varying the signal amplitude V _in the color. On the other hand, by adjusting the capacitance C _sub of the auxiliary capacitor 310 relatively between the RGB three pixel circuits 10, white balance can be achieved even at the same drive current I _ds (that is, the same signal amplitude V _in ). I can take it. In addition, by adding the auxiliary capacitor 310, it is possible to adjust the time required for correcting the mobility μ (mobility correction time) without affecting the threshold value correction operation. By making it possible to adjust the mobility correction time using the auxiliary capacitor 310, the mobility can be sufficiently corrected even when the driving of the pixel circuit 10 is accelerated.

[Configuration Specific to Example 1]
Here, in the pixel circuit 10X of the first comparative example and the pixel circuit 10Y of the second comparative example, each transistor is different from a general thin film transistor that does not have a back gate end, and other than a control input end (gate end). In addition, one having a control terminal (hereinafter also referred to as “transistor characteristic control terminal”) capable of controlling transistor characteristics (here, increasing or decreasing the threshold voltage V _th ) is used. Typical examples of the transistor having the “transistor characteristic control terminal” are a back gate type thin film transistor and a MOS type transistor as shown in FIG. Incidentally, in the pixel circuit 10X of the first comparative example, both the sampling transistor 125 and the drive transistor 121 have the transistor characteristic control terminals connected to the ground potential point (the lowest voltage used in the pixel circuit 10 in the light emitting state). In this configuration, the lowest potential used in the pixel is applied to the transistor characteristic control terminal. For this reason, the drain potential cannot be lower than the transistor characteristic control terminal, and the “reverse bias state” described later is not obtained. On the other hand, in the pixel circuit 10Y of the second comparative example, the transistor characteristic control terminal of the sampling transistor 125 is connected to the ground potential point (the lowest voltage used in the pixel circuit 10). The control end is connected to the source end.

  On the other hand, in the first embodiment, the transistor characteristic control unit 620A including the characteristic control scanning unit 621A is provided. The control potential is provided.

Although the “predetermined control potential” will be described in detail later, it is a pulse-like (rectangular wave that gives a binary value) control voltage for suppressing an insufficient luminance phenomenon. As will be described later, since the luminance deficiency phenomenon is related to the back gate effect of the drive transistor 121 during light emission, the configuration of the characteristic control scanning unit 621A of the transistor characteristic control unit 620A is basically related to light emission control. A configuration using signals is adopted. For example, the characteristic control scanning unit 621A generates a scan pulse corresponding to high / low ( _{Vb_H} and _{Vb_L} ) of the transistor characteristic control signal Vb, converts the level of the scan pulse, and _{sets Vb_H} at an appropriate level. It outputs the transistor characteristic control signal Vb Vb _{_L} to the characteristic control scanning lines 621VB. When the characteristic control scanning unit 621A outputs the transistor characteristic control signal Vb of high / low ( _{Vb_H} and _{Vb_L} ), the pulse signal that becomes the source of the power supply driving pulse DSL generated by the logic circuit in the driving scanning unit 105. A configuration using DS may be employed, and the characteristic control scanning unit 621A may be substantially provided in the drive scanning unit 105, but this is not essential.

  Typical “signals related to light emission control” are those shown in other examples described later, but are not limited thereto. In other words, the configuration of the first embodiment is a general-purpose configuration that can be applied to any of the “signals related to the light emission control”, while the other embodiments described later have “related to the light emission control”. It can be said that it is a form in a specific case of “signal”.

[Operation of pixel circuit]
FIG. 10 is a timing chart (ideal state) illustrating an operation when writing information of the signal amplitude V _in to the storage capacitor 120 by a line sequential method as an example of driving timing related to the pixel circuit 10 (each comparative example and Example 1). ). In FIG. 10, the change in the potential of the write scanning line 104WS, the change in the potential of the power supply line 105DSL, and the change in the potential of the video signal line 106HS are shown with a common time axis. In parallel with these potential changes, changes in the gate potential V _g and the source potential V _s of the drive transistor 121 are also shown. Basically, the same driving is performed with a delay of one horizontal scanning period for each row of the write scanning line 104WS and the power supply line 105DSL.

The value of the current flowing through the organic EL element 127 is controlled by the timing of each pulse as in the signal in FIG. In the timing example of Figure 10, the power driving pulse DSL after quenching and node ND122 is initialized by the second electric potential V _{cc - L,} when the application of the first node initialization voltage V _ofs to the video signal line 106HS Then, the sampling transistor 125 is turned on to initialize the node ND121, and in this state, the power source driving pulse DSL is set to the first potential _{Vcc_H} to perform threshold correction. Thereafter, the sampling transistor 125 is turned off, and the video signal V _sig is applied to the video signal line 106HS. In this state, the sampling transistor 125 is turned on to write the signal and simultaneously correct the mobility. After writing the signal, when the sampling transistor 125 is turned off, light emission is started. In this way, the drive is controlled by the phase difference of the pulses such as mobility correction and threshold correction. When the pixel circuit 10A of the display device 1A according to the first embodiment is driven, based on the “signal related to signal writing” (in conjunction with signal writing), the back gate of the sampling transistor 125 is set by the transistor characteristic control signal Vb. Pulse the end.

Hereinafter, the operation will be described in detail focusing on threshold correction and mobility correction. In the pixel circuit 10, as a drive timing, first, the sampling transistor 125 is turned on in accordance with the write drive pulse WS supplied from the write scan line 104WS, and the video signal V _sig supplied from the video signal line 106HS is used. Sampling and holding in the holding capacitor 120. In the following, for ease of explanation and understanding, unless otherwise specified, it is assumed that the write gain is 1 (ideal value), and information on the signal amplitude Vin is written and held _in the holding capacitor 120. Or, simply describe it as sampling. If write gain is less than 1, not the magnitude itself of the signal amplitude V _in, gain-multiplied information corresponding to the magnitude of the signal amplitude V _in is to be held in the storage capacitor 120.

The drive timing for the pixel circuit 10 is that when writing the information of the signal amplitude V _in of the video signal V _sig to the holding capacitor 120, from the viewpoint of sequential scanning, the video signals for one row are simultaneously applied to the video signal lines 106HS in each column. Line-sequential driving is performed. In particular, in the basic concept when performing threshold correction and mobility correction at the drive timing in the pixel circuit 10 having the 2TR configuration, first, the video signal V _sig is converted into the reference potential (V _ofs ) and the signal potential (V _ofs + V). _in ) in a time division within a 1H period. Specifically, the period in which the video signal V _sig is at the reference potential (V _ofs ) that is the ineffective period is the first half of one horizontal period, and the signal potential (V _sig = V _ofs + V _in ) is _in the effective period. The period is the second half of one horizontal period. When dividing one horizontal period into the first half part and the second half part, it is typically divided into almost one half period, but this is not essential, and the second half part may be longer than the first half part, Conversely, the second half may be shorter than the first half.

The writing drive pulse WS used for signal writing is also used for threshold correction and mobility correction, and the sampling transistor 125 is turned on by activating the write driving pulse WS twice within 1H period. Then, threshold correction is performed at the first on-timing, and signal writing and mobility correction are simultaneously performed at the second on-timing. After that, the driving transistor 121 receives a current from the power supply line 105DSL at the first potential (high potential side) and receives the signal potential held in the holding capacitor 120 (the potential corresponding to the potential of the video signal V _sig during the effective period). ), A drive current I _{ds is} passed through the organic EL element 127. Note that the luminance of the organic EL element 127 is controlled by adjusting the potential of the video signal line 106HS while maintaining the ON state of the sampling transistor 125, instead of activating the write drive pulse WS twice in the 1H period. Signal potential (= V _ofs + V _in ).

For example, the vertical drive unit 103 conducts the sampling transistor 125 in a time zone in which the power supply line 105DSL is at the first potential and the video signal line 106HS is at the reference potential (V _ofs ) that is the ineffective period of the video signal V _sig. A write drive pulse WS is output as a control signal to be held, and a voltage corresponding to the threshold voltage V _th of the drive transistor 121 is held in the holding capacitor 120. This operation realizes a threshold correction function. This threshold value correction function can cancel the influence of the threshold voltage V _th of the drive transistor 121 that varies for each pixel circuit 10.

The vertical drive unit 103 repeatedly executes the threshold correction operation in a plurality of horizontal periods preceding the sampling of the signal amplitude V _in to reliably hold the voltage corresponding to the threshold voltage V _th of the drive transistor 121 in the storage capacitor 120. It is good to make it. A sufficiently long writing time is secured by executing the threshold correction operation a plurality of times. In this way, a voltage corresponding to the threshold voltage V _th of the drive transistor 121 can be reliably held in advance in the storage capacitor 120.

Voltage corresponding to the held threshold voltage V _th is used to cancel the threshold voltage V _th of the drive transistor 121. Therefore, even if the threshold voltage V _th of the drive transistor 121 varies for each pixel circuit 10, it is completely canceled for each pixel circuit 10. Therefore, the uniformity of the image, that is, the uniformity of the light emission luminance over the entire screen of the display device. Will increase. In particular, luminance unevenness that tends to appear when the signal potential is low gradation can be prevented.

Preferably, prior to the threshold correction operation, the vertical drive unit 103 has the power supply line 105DSL at the second potential and the video signal line 106HS at the reference potential (V _ofs ), which is the ineffective period of the video signal V _sig. In the time zone, the write drive pulse WS is activated (H level in this example) to turn on the sampling transistor 125, and then the power supply line 105DSL is set to the first potential while the write drive pulse WS remains active H. Set.

By doing so, the source terminal S is reset to the second potential V _{cc_L} sufficiently lower than the reference potential (V _ofs ) (discharge period C = second node initialization period), and the gate terminal G of the drive transistor 121 is used as the reference After resetting to the potential (V _ofs ) (initialization period D = first node initialization period), the threshold correction operation is started (threshold correction period E). Subsequent threshold correction operation can be reliably executed by such reset operation (initialization operation) of the gate potential and the source potential. The discharge period C and the initialization period D are also collectively referred to as a threshold correction preparation period (= preprocessing period) in which the gate potential V _g and the source potential V _s of the drive transistor 121 are initialized.

In the threshold value correction period E, that the potential of the power supply line 105DSL transits from the second potential V _{cc - L} on the low potential side to the first potential V _{cc - H} on the high potential side, the source potential V _s of the driving transistor 121 starts to rise To do. That is, the gate terminal G of the drive transistor 121 is held at the reference potential (V _ofs ) of the video signal V _sig until the potential V _s of the source terminal S of the drive transistor 121 rises and the drive transistor 121 is cut off. A drain current tends to flow. When cut off, the source potential V _s of the drive transistor 121 becomes “V _ofs −V _th ”. In the threshold correction period E, the drain current flows exclusively to the storage capacitor 120 side (when C _cs << _Cel ) and does not flow to the organic EL element 127 side, so that the organic EL element 127 is cut off. _Is set to the potential V _cath of the ground wiring cath common to all pixels.

Since the equivalent circuit of the organic EL element 127 is represented by a parallel circuit of a diode and the parasitic capacitance C _el, as long as _{"V el ≦ V cath + V} thEL", that is, the leakage current of the organic EL element 127 to the driving transistor 121 As long as it is much smaller than the flowing current, the drain current I _ds of the driving transistor 121 is used to charge the storage capacitor 120 and the parasitic capacitance _Cel . As a result, the voltage V _el at the anode end A of the organic EL element 127, that is, the potential of the node ND122 increases with time. Then, when the potential difference between the potential of the node ND122 (source potential V _s ) and the voltage of the node ND121 (gate potential V _g ) is just the threshold voltage V _th , the driving transistor 121 changes from the on state to the off state, and the drain current I _ds stops flowing, and the threshold correction period ends. That is, after a predetermined time has elapsed, the gate-source voltage V _gs of the drive transistor 121 takes a value of the threshold voltage V _th .

Here, the threshold correction operation may be executed only once, but this is not essential. The threshold correction operation may be repeated a plurality of times with one horizontal period as a processing cycle. For example, ideally, a voltage corresponding to the threshold voltage V _th is written in the storage capacitor 120 connected between the gate terminal G and the source terminal S of the driving transistor 121 by one threshold correction. However, the threshold correction period E is from the timing when the write drive pulse WS is set to active H to the timing when it returns to inactive L. When this period is not sufficiently secured, the threshold correction period E is set to a voltage corresponding to the threshold voltage _Vth. It ends before reaching. In order to solve this problem, it is preferable to repeat the threshold correction operation a plurality of times. The timing is omitted from the illustration.

When the threshold correction operation is executed a plurality of times, the processing cycle of the threshold correction operation in one horizontal period is the reference potential (via the video signal line 106HS in the first half of the one horizontal period prior to the threshold correction operation. supply V _ofs) because undergo an initialization operation for setting the source potential to the second potential V _{cc - L.} Inevitably, the threshold correction period is shorter than one horizontal period. Accordingly, an accurate voltage corresponding to the threshold voltage _Vth is held in this short one-time threshold correction operation period due to the magnitude relationship between the capacitance C _cs of the holding capacitor 120 and the second potential V _{cc_L} and other factors. There may be cases where the capacitor 120 cannot be held and partitioned. It is preferable to execute the threshold correction operation a plurality of times for this purpose. That is, a plurality of horizontal periods preceding the sampling (signal writing) to the storage capacitor 120 of the signal amplitude V _in, a voltage corresponding to the threshold voltage V _th of that in reliably drive transistor 121 to repeatedly execute the threshold value correction operation It is preferable to hold in the holding capacitor 120.

The pixel circuit 10 has a mobility correction function in addition to the threshold value correction function. That is, the vertical drive unit 103 makes the sampling transistor 125 conductive in the time zone in which the video signal line 106HS is in the signal potential (V _ofs + V _in ) during which the video signal V _sig is valid. The write drive pulse WS supplied to is activated (H level in this example) only for a period shorter than the above-described time zone. In this period, the parasitic capacitance _Cel and the storage capacitor 120 of the organic EL element 127 are charged through the drive transistor 121 in a state where the signal potential (V _ofs + V _in ) is supplied to the control input terminal of the drive transistor 121. The write drive pulse (sometimes in the sampling period is also the mobility correction period) the active period of the WS to by appropriately setting, when holding the information corresponding to the signal amplitude V _in the storage capacitor 120, at the same time the driving transistor 121 Can be added to the mobility μ. Actually signal electric potential (V _ofs + V _in) to the video signal line 106HS by the horizontal driving unit 106, the period to activate H writing driving pulse WS, the write period of the signal amplitude V _in to the hold capacitor 120 (Also referred to as a sampling period).

In particular, in the driving timing in the pixel circuit 10 is in the first potential V _{cc - H} power supply line 105DSL is high potential side, and the time zone in which the video signal V _sig is in the valid period (the period of the signal amplitude V _in) The write drive pulse WS is activated at. That is, as a result, the mobility correction time (including the sampling period) is equal to the time width in which the potential of the video signal line 106HS is at the signal potential (V _ofs + V _in ) during the effective period of the video signal V _sig and the write drive pulse WS The active period is determined by the overlapping range. In particular, since the active period width of the write drive pulse WS is determined to be narrow so that the video signal line 106HS falls within the time width at the signal potential, as a result, the mobility correction time is the write drive pulse WS. Determined. To be precise, the mobility correction time (also the sampling period) is the time from when the write drive pulse WS rises and the sampling transistor 125 is turned on until the write drive pulse WS falls and the sampling transistor 125 is turned off. It becomes.

Specifically, in the sampling period, the sampling transistor 125 is turned on (on) _while the gate potential V _g of the driving transistor 121 is at the signal potential (V _ofs + V _in ). Therefore, in the writing & mobility correction period H, the drive current I _ds flows through the drive transistor 121 while the gate terminal G of the drive transistor 121 is fixed to the signal potential (V _ofs + V _in ). Information of the signal amplitude V _in is held in the form Komu added to the threshold voltage V _th of the drive transistor 121. As a result, fluctuations in the threshold voltage V _th of the drive transistor 121 are always canceled, and threshold correction is performed. By this threshold correction, the gate-source voltage V _gs held in the holding capacitor 120 becomes “V _sig + V _th ” = “V _in + V _th ”. At the same time, since the mobility correction is executed during this sampling period, the sampling period also serves as the mobility correction period (writing & mobility correction period H).

Here, when the threshold voltage of the organic EL device 127 was set to _{V thEL, "V ofs -V th} <V thEL" By setting a, the organic EL element 127 is placed in a reverse bias state, the cut-off Since it is in a state (high impedance state), it does not emit light, and exhibits simple capacitance characteristics rather than diode characteristics. Thus the drain current (driving current I _ds) flowing through the drive transistor 121 is capacitive coupled to both the electrostatic capacitance C _el of the parasitic capacitance (equivalent capacitance) C _el of the electrostatic capacitance C _cs and the organic EL element 127 of the storage capacitor 120 It is written in “C = C _cs + C _el ”. Accordingly, the drain current of the drive transistor 121 begins to charge flows into the parasitic capacitance C _el of the organic EL element 127. As a result, the source potential V _s of the driving transistor 121 increases.

In the timing chart of FIG. 10, this increase is represented by ΔV. This increase, that is, the potential correction value ΔV, which is a mobility correction parameter, is subtracted from the gate-source voltage “V _gs = V _in + V _th ” held in the holding capacitor 120 by threshold correction, and “V _{Since gs} = V _in + V _th −ΔV ”, negative feedback is applied. At this time, the source potential V _s of the drive transistor 121 is “−V _th + ΔV” obtained by subtracting the voltage “V _gs = V _in + V _th −ΔV” held in the storage capacitor from the gate potential V _g (= V _in ). "

In this manner, in the driving timing in the pixel circuit 10, the writing and mobility correction period H, [Delta] V (negative feedback amount, the mobility correction parameter) for correcting the sampling and the mobility μ of the signal amplitude V _in the adjustment of the performed It is. The write scanning unit 104 can adjust the time width of the write & mobility correction period H, thereby optimizing the negative feedback amount of the drive current I _ds for the storage capacitor 120.

The potential correction value ΔV is I _ds · t / C _el , and even if the drive current I _ds varies due to variations in the mobility μ for each pixel circuit 10, the potential correction value ΔV is corresponding to each. The variation in mobility μ for each pixel circuit 10 can be corrected. That is, when a constant signal amplitude V _in, the absolute value of the mobility μ greater the potential correction value ΔV of the drive transistor 121 is increased. In other words, since the potential correction value ΔV increases as the mobility μ increases, variations in the mobility μ for each pixel circuit 10 can be removed.

The pixel circuit 10 also has a bootstrap function. That is, the writing scanning unit 104 cancels the application of the writing driving pulse WS to the writing scanning line 104WS at the stage when the information of the signal amplitude Vin is held _in the holding capacitor 120 (ie, inactive L (low)). The sampling transistor 125 is turned off, and the gate terminal G of the drive transistor 121 is electrically disconnected from the video signal line 106HS (light emission period I). Proceeding to the light emission period I, the horizontal driving unit 106 returns the potential of the video signal line 106HS to _the reference electric potential (V _ofs) at a later appropriate time.

  The light emitting state of the organic EL element 127 is continued until the (m + m′−1) th horizontal scanning period. Thus, the light emission operation of the organic EL element 127 constituting the (n, m) th subpixel is completed. Thereafter, the process proceeds to the next frame (or field), and the threshold correction preparation operation, the threshold correction operation, the mobility correction operation, and the light emission operation are repeated again.

In the light emission period I, the gate terminal G of the drive transistor 121 is disconnected from the video signal line 106HS. Since the application of the signal potential (V _ofs + V _in ) to the gate terminal G of the drive transistor 121 is released, the gate potential V _g of the drive transistor 121 can be increased. A storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121, and a bootstrap operation is performed by the effect of the storage capacitor 120. Assuming that the bootstrap gain is 1 (ideal value), the gate potential V _g is interlocked with the fluctuation of the source potential V _s of the driving transistor 121, and the gate-source voltage V _gs is kept constant. be able to. At this time, the drive current I _ds flowing through the drive transistor 121 flows through the organic EL element 127, and the anode potential of the organic EL element 127 rises according to the drive current I _ds . Let this rise be V _el . Eventually, as the source potential V _s rises, the reverse bias state of the organic EL element 127 is canceled, so that the organic EL element 127 actually starts to emit light by the inflow of the drive current I _ds .

Here, the relationship between the drive current I _{ds and the} gate voltage V _gs is obtained by substituting “V _sig + V _th −ΔV” or “V _in + V _th −ΔV” into the equation (1) representing the transistor characteristics. , Expression (5A) or Expression (5B) (both expressions are collectively expressed as Expression (5)).

I _ds = k · μ · (V _sig −V _ofs −ΔV) ² (5A)
I _ds = k · μ · (V _in −V _ofs −ΔV) ² (5B)

From this equation (5), it can be seen that the term of the threshold voltage Vth is canceled and the drive current I _ds supplied to the organic EL element 127 does not depend on the threshold voltage V _th of the drive transistor 121. In other words, the current I _ds flowing through the organic EL element 127 is determined based on the value of the video signal V _sig for controlling the luminance in the organic EL element 127 when V _ofs is set to 0 volt. This is proportional to the square of the value obtained by subtracting the value of the potential correction value ΔV at the second node ND ₂ (source end of the driving transistor 121) due to the mobility μ. In other words, the current I _ds flowing through the organic EL element 127 does not depend on the threshold voltage V _thEL of the organic EL element 127 and the threshold voltage V _th of the drive transistor 121. That is, the light emission amount (luminance) of the organic EL element 127 is not affected by the threshold voltage V _thEL of the organic EL element 127 and the threshold voltage V _th of the drive transistor 121. The luminance of the (n, m) th organic EL element 127 is a value corresponding to the current I _ds .

Moreover, since the potential correction value ΔV increases as the driving transistor 121 has a higher mobility μ, the value of the gate-source voltage V _gs decreases. Therefore, in the equation (5), even if the value of the mobility μ is large, the value of (V _sig −V _ofs −ΔV) ² becomes small. As a result, the drain current I _ds can be corrected. That is, even in the drive transistors 121 having different mobility μ, if the value of the video signal V _sig is the same, the drain current I _ds becomes substantially the same. The current I _{ds to} be controlled is made uniform. That is, it is possible to correct the luminance variation of the organic EL element 127 caused by the variation in mobility μ (further, the variation in k).

In addition, a storage capacitor 120 is connected between the gate terminal G and the source terminal S of the drive transistor 121, and a bootstrap operation is performed at the beginning of the light emission period due to the effect of the storage capacitor 120. Therefore, the gate potential V _g and the source potential V _{s of} the drive transistor 121 rise while the gate-source voltage “V _gs = V _in + V _th −ΔV” of the drive transistor 121 is maintained constant. When the source potential V _s of the driving transistor 121 becomes “−V _th + ΔV + V _el ”, the gate potential V _g becomes “V _in + V _e l”. At this time, since the gate-source voltage V _gs of the drive transistor 121 is constant, the drive transistor 121 allows a constant current (drive current I _ds ) to flow through the organic EL element 127. As a result, the potential at the anode end A of the organic EL element 127 (= potential at the node ND122) rises to a voltage at which a current called a drive current I _{ds in} a saturated state can flow through the organic EL element 127.

Here, the organic EL element 127 has its IV characteristic changed as the light emission time becomes longer. Therefore, the potential of the node ND122 also changes with time. However, even if the anode potential fluctuates due to such deterioration of the organic EL element 127 with time, the gate-source voltage V _gs held in the holding capacitor 120 is always kept constant at “V _in + V _th −ΔV”. Is done. Since the drive transistor 121 operates as a constant current source, even if the IV characteristic of the organic EL element 127 changes with time, and the source potential V _s of the drive transistor 121 changes accordingly, the drive transistor 121 is driven by the storage capacitor 120. Since the gate-source potential V _{gs of the} transistor 121 is kept constant (≈V _in + V _th −ΔV), the current flowing through the organic EL element 127 does not change, and thus the emission luminance of the organic EL element 127 is also constant. Kept. Actually, since the bootstrap gain is smaller than “1”, the gate-source potential V _gs is smaller than “V _in + V _th −ΔV”, but the gate-source potential V according to the bootstrap gain. There is no change in being kept in _gs .

As described above, the pixel circuit 10 automatically configures a threshold correction circuit and a mobility correction circuit by devising drive timing. That is, the pixel circuit 10, in order to prevent the influence on the drive current I _ds according to characteristic variations of the driving transistor 121 (variations in the threshold voltage V _t h and a carrier mobility μ in the present example), the threshold voltage V _th and the carrier mobility It functions as a drive signal stabilization circuit that corrects the influence of μ and maintains a constant drive current. Since not only the bootstrap operation but also the threshold correction operation and the mobility correction operation are executed, the gate-source voltage V _gs maintained in the bootstrap operation is a voltage and mobility corresponding to the threshold voltage V _th. Since it is adjusted by the correction potential correction value ΔV for correction, the light emission luminance of the organic EL element 127 is not affected by variations in the threshold voltage V _th and the mobility μ of the driving transistor 121, and the organic EL element 127 Not affected by deterioration over time. As a result, the display device 1 can display with a stable gradation corresponding to the input video signal V _sig (signal amplitude V _in ), and can obtain a high-quality image.

  Further, since the pixel circuit 10 can be configured by a source follower circuit using an n-channel type drive transistor 121, even if the current organic EL element of the anode / cathode electrode is used as it is, Drive becomes possible. In addition, the pixel circuit 10 can be configured using only n-channel transistors including the driving transistor 121 and the peripheral sampling transistor 125 and the like, so that the cost can be reduced in transistor fabrication.

[Causes of the phenomenon of insufficient brightness]
FIG. 11 is a timing chart for explaining problems that occur when the drive timing shown in FIG. 10 is applied to the pixel circuit 10Y of the second comparative example, and shows enlarged views before and after extinction. .

At the time of signal writing operation in the sampling period & mobility correction period, it is important to write the information corresponding to the signal potential Vin _{in the} storage capacitor 120 more greatly and more faithfully (with linearity). “Large” is defined by a so-called write gain G _in . In order to obtain luminance efficiently with respect to the signal potential V _in of the video signal V _sig, a condition in which the source potential V _s does not increase due to the drive current I _ds flowing with the increase of the gate potential V _g of the drive transistor 121 at the time of writing. That is, the ratio of the voltage held in the holding capacitor 120 of the capacitance C _{cs to} the video signal V _sig (signal potential V _in ) when the source potential V _s of the driving transistor 121 is low at the time of writing (writing gain G _in ). Should be as high as possible. Under such conditions, the write gain G _in includes the capacitance C _{cs of} the storage capacitor 120, the capacitance C _gs of the parasitic capacitance C 121 _gs formed at the gate terminal G of the drive transistor 121, and the parasitic of the organic EL element 127. Using the capacitance C _el
G _in = C2 / (C1 + C2) = (C _cs + C _gs ) / {(C _cs + C _gs ) + C _el }
It can be expressed as. In consideration of the auxiliary capacitor 310, C _el may be set to “C _el + C _sub ”.

The capacitance C _gs of the parasitic capacitance C 121 _gs may be considered small compared to the parasitic capacitance C _el of the electrostatic capacitance C _cs and the organic EL element 127 of the storage capacitor 120, therefore, writing gain G _in the storage capacitor If the parasitic capacitance C _el of the organic EL element 127 is sufficiently larger than the electrostatic capacitance C _{cs of} 120, in other words, the capacitance value added between the gate end G and the source end S of the drive transistor 121 (here Then, the capacitance C _cs of the holding capacitor 120 is reduced, or the source terminal S of the drive transistor 121 (that is, the anode terminal A of the organic EL element 127) and the cathode wiring cath (that is, the cathode terminal K of the organic EL element 127). the added capacitance value between) (When here to increase the parasitic capacitance C _el) of the organic EL element 127, becomes closer to "1" as possible, the size of more signal potential V _in You can write voltage information close to the storage capacitor 120.

On the other hand, with regard to “more faithfully (with linearity)”, it has been found that it is necessary to consider the back gate effect (also referred to as the substrate bias effect). That is, when a field effect transistor having a back gate effect is used for the driving transistor TR _D , a luminance corresponding to the inputted video signal level cannot be obtained even when a large video signal level is inputted to obtain high luminance. Occurs. For example, a MOS transistor is used. For example, normally, since the base potential (back gate potential) of the drive transistor 121 (MOS transistor) needs to be the lowest voltage used in the pixel in the light emitting state, as in the first comparative example of FIGS. A minimum voltage (ground potential) is applied as a fixed potential to the base potential. In this case, the gate potential and the source potential have to be increased so as to require higher emission luminance, and the base-source voltage V _bs (potential difference between the source end and the base end (back gate end)) increases. It becomes. However, in this case, the threshold voltage V _th of the drive transistor 121 increases as the base-source voltage V _bs increases due to the substrate bias effect, so that the luminance moves in a suppressed direction. V _gs must open (increase the signal amplitude V _in) voltage high of the video signal V _sig from the resulting must be set.

In order to solve the problem of the first comparative example, as in the pixel circuit 10Y of the second comparative example, the transistor characteristic control terminal of the driving transistor 121 is connected to the source terminal, that is, the base potential (back gate potential) of the driving transistor 121. , it is conceivable to match the well potential) and the source potential V _s. However, in the case of the second comparative example, when the driving transistor 121 is turned off (when the second potential V _{cc_L} is supplied to the drain end), the drain end of the driving transistor 121 becomes lower than the base potential (back gate voltage). Since it is in a reverse bias state, there are concerns about adverse effects on reliability. This point will be described with reference to enlarged views before and after extinction in FIG.

As shown in the enlarged views before and after extinction, the power supply driving pulse DSL is set to the second potential Vcc_L to enter the extinction period, and the driving transistor 121 is turned off. At this time, the drain potential V _d of the driving transistor 121 drops rapidly, but the source potential V _s (= base potential V _b ) does not drop instantaneously, so that the drain potential V _d becomes lower than the base potential V _b. Since it becomes a bias state, reliability is impaired. That is, the power driving pulse DSL Immediately after quenching and to the second potential Vcc_L, while the drain voltage V _d of the drive transistor 121 is descending to the short time the second potential V _{cc - L,} the source potential V _s, and the base potential V _b Since the voltage drops while discharging the parasitic capacitance C _cs and the auxiliary capacitance 310 (C _sub ) of the organic EL element 127, a certain amount of time is required. Therefore, a “reverse bias” state occurs in which the drain voltage V _d of the drive transistor 121 is lower than the base potential V _b , and there is a concern about adverse effects on reliability.

  As described above, both the pixel circuit 10X of the first comparative example and the pixel circuit 10Y of the second comparative example are difficult to produce high luminance due to the substrate bias effect at the driving timing shown in FIG. 10, or due to the reverse bias phenomenon. There are problems such as loss of reliability.

[Measures against brightness deficiency phenomenon]
When a transistor having a back gate effect is used as a driving transistor, high luminance is hardly generated, and there is a concern that display linearity may be lost. For this reason, there is a need to develop a system that solves the problem that high luminance due to the substrate bias effect is difficult to occur without sacrificing reliability.

In terms of not impairing the reliability, the transistor characteristics control of the drive transistor 121 is performed by using the minimum voltage used in the pixel circuit 10 as a whole operation instead of the minimum voltage (for example, ground potential) in the light emission state as the transistor characteristic control signal Vb. What is necessary is just to supply to an edge. However, if this state continues even during light emission, the base-source voltage V _bs in the light emission state is much higher than when the lowest voltage in the light emission state is supplied to the transistor characteristic control terminal due to the back gate effect (substrate bias effect). Since it increases, it becomes more difficult to produce high brightness, and the linearity of the display is increasingly lost.

Therefore, in the present embodiment, first, the minimum voltage used in the pixel circuit 10 as a whole operation is set to the low level of the transistor characteristic control signal Vb so that the reliability is not deteriorated for a certain period of time when extinction is performed. This is supplied to the transistor characteristic control terminal. The “certain period during extinction” may be a period until the first node ND ₁ and (node ND121) and the second node ND ₂ (node ND122) reach their initialization voltages after the extinction operation. That is, it is preferable to keep the transistor characteristic control signal Vb to the transistor characteristic control terminal of the drive transistor 121 at a low level until the initialization of the first node ND ₁ and the second node ND ₂ is completed. Further, the timing for supplying the lowest voltage used in the pixel circuit 10 as a whole of the operation may be substantially the same as or before (a little before) the start of the extinction period. If it is “before that”, the reverse bias state at the time of extinction can be prevented more reliably.

Furthermore, in this embodiment, the luminance deficiency phenomenon caused by the back gate effect is eliminated by improving the transistor characteristics during light emission. “Improving transistor characteristics” means mitigating the increase in the base-source voltage V _bs due to the back gate effect, and as an example, the threshold voltage V _th is decreased. “During light emission” does not mean that the signal writing or mobility correction is completed and immediately after entering the light emission period, but it may be immediately before the light emission period starts, or signal writing or mobility correction is completed. The drive current Ids from the drive transistor 121 flows to the organic EL element 127 and charges the parasitic capacitance _Cel while the bootstrap operation increases the source potential V _s and the gate voltage V _g of the drive transistor 121 and actually the organic EL element 127. Or may be at an appropriate time thereafter until the light is emitted. That is, the organic EL element 127 may actually be in a substantial light emission state in which light emission is almost stable. In other words, the transistor characteristic control signal Vb that can decrease the threshold voltage _Vth of the driving transistor 121 is preferably supplied to the transistor characteristic control terminal when the state becomes at least a “substantial light emission state”.

〔principle〕
FIG. 12 to FIG. 13 are diagrams for explaining the principle of countermeasures against the luminance deficiency phenomenon caused by the back gate effect. Here, FIG. 12 is a diagram for explaining the substrate potential dependence of transistor characteristics (V _gs -I _ds characteristics). FIG. 13 is a timing chart for explaining a driving method of the pixel circuit according to the first embodiment, focusing on the transistor characteristic control signal Vb. In the drawing, enlarged views before and after extinction are shown.

As is well known, in a back gate type thin film transistor and a MOS type transistor, transistor characteristics vary due to the back gate effect. For example, a MOS transistor is usually handled as a three-terminal device in the same way as a bipolar transistor, but the substrate and well in which the source region and drain region are formed should be considered as a control terminal (transistor characteristic control end). Because there is, it should be handled as 4 terminals accurately. When a transistor characteristic control signal Vb (also referred to as a back gate voltage, a substrate potential, or a base potential) is applied between a source and a transistor characteristic control terminal (for example, a substrate (also referred to as a body)), the transistor characteristics are controlled. Can do. Normally, the back gate voltage is applied as a negative voltage so that the diode is cut off. For example, when a back gate voltage is applied, the depletion layer immediately below the source and drain channels changes like the diode, and the potential of the semiconductor surface changes. Therefore, the charge in the depletion layer differs between when no back gate voltage is applied and when the transistor characteristic (V _gs -I _ds characteristic) changes as shown in FIG. 12, and therefore the threshold voltage V _th changes. . When the back gate effect is taken into account, it is known that the threshold voltage V _th has a characteristic that increases by about ½ power with respect to the back gate voltage. Incidentally, in the simple theory, the threshold voltage V _th increases by a power of 1/2 with respect to the back gate voltage.

As shown in FIG. 12, the higher the substrate potential (that is, the transistor characteristic control signal Vb), the lower the threshold value and the more the drain current I _ds flows. Conversely, the threshold value increases as the substrate potential (that is, the transistor characteristic control signal Vb) decreases. Therefore, at the time of light emission, the transistor characteristic control signal Vb is increased from that at the time of non-light emission (during extinction) to reduce the threshold value, thereby alleviating the problem that high luminance is difficult to be achieved due to the substrate bias effect during light emission. In order to prevent the driving transistor 121 from being in a reverse bias state during extinction, the transistor characteristic control signal Vb is lowered as compared with that during light emission. Thereby, an effective method of applying the transistor characteristic control signal Vb is realized in which the reverse bias phenomenon at the time of extinction is relaxed and the reliability is ensured.

Incidentally, the value of the transistor characteristic control signal Vb at the time of extinction is _{Vb_L,} and the value of the transistor characteristic control signal Vb at the time of light emission is _{Vb_H} . The value _{Vb_L} of the transistor characteristic control signal Vb is the overall operation of the pixel circuit 10 (here, in particular, the lowest voltage used in the pixel circuit 10 during the threshold correction preparation period, for example, the second node initialization voltage (V _ini )) It is preferable to set it to less than that, etc. When the value _{Vb_L} of the transistor characteristic control signal Vb is higher than the second node initialization voltage (V _ini ) (but less than _{Vb_HL} ), a slightly reverse bias state occurs. On the other hand, the value _{Vb_H} of the transistor characteristic control signal Vb is a minimum voltage applied to the driving transistor 121 during light emission, for example, a first node initialization voltage (V _ofs ) or it may be set to more like. When the value Vb _{_H} transistor characteristic control signal Vb is higher than the first node initialization voltage (V _ofs), emission Since a reverse bias state, better to suitable values so as not to excessively reverse biased.

By doing so, as shown in the enlarged views before and after extinction in FIG. 13, the drain potential V _d of the drive transistor 121 drops to the second node initialization voltage (V _ini ) when the power supply drive pulse DSL _rises. However, since the base potential V _b = V _ini is almost simultaneously with or before that, the drive transistor 121 is not in the reverse bias state. In addition, since the base potential V _b is raised during light emission, the increase in the base-source voltage V _bs during light emission is mitigated, that is, the threshold voltage V _th is reduced to prevent the need for a higher signal voltage. be able to. Even when a transistor having a back gate effect is used for the driving transistor 121, the problem that high luminance due to the substrate bias effect is difficult to occur can be solved without sacrificing reliability. When MOS process is used, it is possible to solve the problem that high luminance due to the substrate bias effect is difficult to occur, and to realize an effective back gate voltage application method that ensures the reliability by relaxing the reverse bias phenomenon during extinction. . When the MOS process is used, V _bs at the time of light emission can be suppressed to be small, and high luminance can be _achieved .

[From a certain period of time after extinction until the light emission state]
In principle, there is no question as to how to set the value of the transistor characteristic control signal Vb between the elapse of a certain period of time during extinction and the light emission state. Good. Hereinafter, the period from the elapse of a certain period during extinction to the light emitting state is simply referred to as “non-light emitting period”.

First, it is preferable to increase (increase) the threshold voltage _Vth by reducing the characteristics of the driving transistor 121 as compared with that during light emission at least during a period in which no current flows through the driving transistor 121 in an ideal state. By supplying the transistor characteristic control signal Vb to the transistor characteristic control terminal of the driving transistor 121 and reducing the transistor characteristic in a certain period before light emission after the transistor characteristic correction processing (here, threshold correction), the driving transistor 121 is decreased. The display unevenness phenomenon caused by the leak of the image is eliminated. From this point of view, it does not matter whether or not the characteristics of the driving transistor 121 are reduced during another period of non-light emission after the elapse of a certain period during extinction until the light emission state. In the example shown in FIG. 13, the “period in which no current flows through the drive transistor 121 in the ideal state” is the period from the threshold correction period E to the start of the signal writing & mobility correction period (specifically, the preparation period G). This is a period during which the write pulse WS is low (period F in the figure). Therefore, in Example 1, at least during the period when the write pulse WS is low (period F in the figure), the transistor characteristic control signal Vb of the drive transistor 121 is decreased to the value _{Vb_L} to further increase the threshold voltage _Vth . Good.

Leakage can be prevented by lowering the transistor characteristic control signal Vb for a certain period before light emission from the normal time to increase the threshold, and as a result, display unevenness can be suppressed / eliminated. The transistor characteristic control unit 640 is configured to set the transistor characteristic control signal Vb of the driving transistor 121 for each pixel circuit 10, and as shown in FIG. 13, the transistor characteristic control signal Vb of the driving transistor 121 is lowered for a certain period before light emission. By doing so, the threshold voltage _Vth can be further increased, and the drive transistor 121 can be reliably maintained in the OFF state. If the driving transistor 121 can be maintained in the off state, the display unevenness phenomenon due to leakage can be suppressed / eliminated. Leakage occurs during the period from threshold correction to video signal writing, and display unevenness caused by this leak can be improved.

In principle, for other non-light emission periods, the transistor characteristic control signal Vb is set to the same value _{Vb_H} as the light emission state, or the level when the write pulse WS is low (low level: _{Vb_L} ) It is free to do. That is, the characteristics of the drive transistor 121 may be reduced (in this case, the threshold voltage is increased) at least in a “period in which no current flows in the drive transistor 121 in an ideal state” than during normal time (when light is emitted). Whether or not the characteristics of the driving transistor 121 are deteriorated in other periods is basically free.

However, in the point that the display unevenness due to the leakage current of the drive transistor 121 during the write & mobility correction preparation period after the threshold value correction operation until the start of signal writing and mobility correction is more reliably suppressed. It is preferable to lower the characteristics of the drive transistor 121 in the mobility correction preparation period H as compared with other periods. Specifically, the transistor characteristics of the drive transistor 121 are deteriorated during the period after the threshold correction period E until the writing & mobility correction period H (specifically, the preparation period G) starts (as an example). (Threshold voltage _Vth is increased).

For example, whether or not the characteristics of the driving transistor 121 are deteriorated during the other period of non-light emission, while the characteristics of the driving transistor 121 are deteriorated during the “period in which no current flows through the driving transistor 121 in the ideal state”. If the unquestioned, and more to expand the threshold voltage V _th lowering the transistor characteristics control signal Vb of the drive transistor 121 to the threshold correction period E, the threshold voltage V _th when the transistor characteristics were lowered in the storage capacitor 120 There is a concern that the threshold value correction is insufficient due to a difference between the threshold voltage V _th at the time of light emission and the threshold voltage V _th at the time of light emission. Further, the period from the elapse of the threshold correction period E to the start of the writing & mobility correction period H is also the same as the threshold voltage V _th in the threshold correction period E, and the countermeasure against the leak may be insufficient.

Considering this point, it is preferable to stop the process of reducing the characteristics of the drive transistor 121 when the drive transistor 121 is in a state of flowing current. That is, during the period of the correction process of the threshold voltage V _th of the drive transistor 121, the process of increasing the threshold voltage _th of the drive transistor 121 is stopped (this form is referred to as a first drive example). At least “when the current does not flow through the driving transistor 121 in the ideal state, the transistor characteristic control signal Vb is set to _{Vb_L} to lower the characteristics of the driving transistor 121 as compared with the time of light emission, and during the threshold correction period E, the transistor characteristic control signal Vb is Although _{Vb_H} is the same as that at the time of light emission, it does not matter whether or not the characteristics of the driving transistor 121 are deteriorated during another period of non-light emission.

For example, the characteristics of the drive transistor 121 can be lowered before the end of the threshold correction period E, and can be stopped simultaneously with the start of signal writing (this form is described as a second drive example). Specifically, based on the driving timing of the first driving example, the deterioration of the transistor characteristics of the driving transistor 121 is stopped almost simultaneously with the start of the write & mobility correction period H (that is, the transistor characteristic control signal Vb is ( _Return from _{Vb_L} to _{Vb_H} ). In addition, the transistor characteristics of the drive transistor 121 start to deteriorate slightly before the end of the threshold correction period E (that is, the transistor characteristics control signal Vb is changed from _{Vb_H} to _{Vb_L} ). That is, the substrate potential of the drive transistor 121 is lowered slightly before the end of the threshold correction, that is, slightly before (immediately before) the fall of the write pulse WS, and is increased almost simultaneously with the rise of the write pulse WS at the start of signal writing. What is necessary is just to comprise. Leakage within the floating period of the drive transistor 121 after threshold correction can be suppressed by lowering the substrate potential of the drive transistor 121 and raising the threshold voltage _Vth slightly before the end of threshold correction. That is, with respect to the drive transistor 121, the substrate-source voltage V _bs is expanded by reducing the transistor characteristic control signal Vb (that is, the substrate potential) from the state where V _gs ≈V _th immediately before the threshold correction is completed. Therefore, the threshold voltage V _th spreads to V _th-exp due to the substrate bias effect, and thus V _gs <V _th-exp , and leakage in the subsequent write & mobility correction preparation period can be reliably suppressed.

Alternatively, the transistor characteristic control signal Vb may be kept at a low level during signal writing or mobility correction (this form is referred to as a third driving example). For example, the characteristics of the driving transistor 121 may be reduced before the threshold correction is completed, and the characteristics may be stopped almost simultaneously with the start of light emission. Specifically, based on the driving timing of the first driving example, the deterioration of the transistor characteristics of the driving transistor 121 is stopped almost simultaneously with the start of light emission (that is, the transistor characteristic control signal Vb is changed from _{Vb_L} to _{Vb_H} Back to). In addition, the transistor characteristics of the drive transistor 121 start to deteriorate slightly before the end of the threshold correction period E (that is, the transistor characteristics control signal Vb is changed from _{Vb_H} to _{Vb_L} ). In short, the substrate potential of the drive transistor 121 is lowered slightly before the end of threshold correction, that is, slightly before (just before) the fall of the write pulse WS, and the write pulse WS at the start of light emission (at the start of the bootstrap operation). It may be configured to be raised almost simultaneously with the falling edge of. Even in the case of the third driving example, similarly to the second driving example, it is possible to reliably suppress leakage in the floating period of the driving transistor 121 after the threshold correction.

The merit of the third driving example will be described below. When the driving transistor 121 having an excessively high (high) mobility μ is used, the mobility correction is excessively applied, the gate-source voltage V _gs immediately before light emission is crushed, and the brightness and uniformity are significantly decreased. Is concerned. In order to suppress this problem, it is necessary to narrow the mobility correction pulse. However, in practice, it is difficult to set and manage the pulse width from the viewpoint of the circuit configuration, delay, and other aspects of operation with a narrow mobility correction pulse. For example, since the mobility μ is high in the MOSFET, there is a concern that mobility correction is applied too much and it is necessary to set the mobility correction pulse to about several nanoseconds so that the luminance does not decrease. Control of such a narrow pulse is difficult. In view of this point, it is desirable to reduce the value of the current flowing during the mobility correction period without narrowing the mobility correction pulse (mainly maintaining the current state). At the drive timing of the third drive example, the threshold voltage V _th during the mobility correction period increases, and this effect can be obtained.

Alternatively, it is possible to reduce the characteristics of the drive transistor 121 almost simultaneously with the end of the threshold correction, that is, almost simultaneously with the fall of the write pulse WS, and to stop the write at the start of signal writing (this form is the fourth drive). (Example) Furthermore, it is possible to reduce the characteristics of the drive transistor 121 almost simultaneously with the end of threshold correction, that is, almost simultaneously with the fall of the write pulse WS, and to stop almost simultaneously with the start of light emission (referred to as a fifth drive example). ). In the fourth driving example and the fifth driving example, the gate-source voltage V _gs held at both ends of the holding capacitor 120 after the threshold correction is higher than the threshold voltage V at the time of light emission than in the second driving example or the third driving example. _A value closer to _th .

  14 to 15 are diagrams for explaining the second embodiment for controlling the transistor characteristic control signal Vb. Here, FIG. 14 is a timing chart for explaining a driving method of the pixel circuit according to the second embodiment focusing on the transistor characteristic control signal Vb. FIG. 15 is a diagram illustrating a circuit configuration example that realizes the drive timing of the second embodiment illustrated in FIG. 14.

In the first embodiment, there is no question as to how to set the value of the transistor characteristic control signal Vb between the elapse of a certain period of time during extinction and the light emission state. And the various variation which can be taken in this non-light-emission period was demonstrated. On the other hand, in the second embodiment, the value of the transistor characteristic control signal Vb between the elapse of a certain period of time after extinction and the light emission state is set to a low level (that is, _{Vb_L} ) (reducing the characteristics of the driving transistor). Example). Since the light emission state is at a high level (that is, _{Vb_H} ), a rectangular wave that gives a binary value is applied to the transistor characteristic control terminal (base potential Vb) of the drive transistor 121 as a whole.

For example, the value of the first node initialization voltage (V _ofs ) is set to V _ofs −V _th > 0 in order to apply threshold correction due to the configuration of this circuit. Furthermore, this circuit is based on the assumption that a MOS transistor is used, and the lowest potential in the pixel is 0 V, and it is not common to make it negative. Therefore, in this configuration, the well potential (transistor characteristic control signal Vb) is set to low level = 0 V (= V _ini ) and high level = V _ofs . On the contrary, in the case where V _ofs = 0V, it is necessary to set V _ini and the lowest voltage in the pixel to, for example, −3 V which is less than V _ofs −V _th. The control signal Vb) needs to be low level = -3V and high level = 0V = V _ofs . In view of actual use, it can be said that the possibility of V _ofs = 0 V or less is low.

As an example, in order to set the transistor characteristic control terminal to the low level during extinction, as shown in FIG. _{_L} ). As a timing that defines the time before the fall of the n-th power supply pulse DSL_n, here, the fall of the power supply pulse DSL_n-1 at the previous stage (n-1 stage) is used.

Further, it is raised again to a high voltage (second voltage: _{Vb_H} ) during light emission (medium). Here, the rise of the power supply pulse DSL_n + 1 at the next stage (n + 1 stage) is used as the timing for defining the rise of the power supply pulse DSL_n at the time of light emission (middle) at the nth stage. Thereby, a low voltage (first voltage: Vb _{_L)} the falling time of the power driving pulse DSL_n-1 of the preceding stage is falling earlier power driving pulse DSL_n of its own stage (n-1 stage) is lowered to the When the next stage (n + 1 stage) power source driving pulse DSL_n + 1 rises during light emission, it is raised again. In order to realize such timing, the pixel circuit 10 separates the transistor characteristic control terminal (base potential Vb), that is, the well of the driving transistor 121 for each V line.

  FIG. 15 shows a circuit configuration example that realizes the drive timing shown in FIG. FIG. 15A shows a configuration example of the drive scanning unit 105. FIG. 15B is a configuration example of the drive scanning unit 105 and the characteristic control scanning unit 621B when the second embodiment is applied.

  As illustrated in FIG. 15A, the drive scanning unit 105 includes a shift register unit 410, a logic circuit unit 420, and an output buffer unit 440. Although not shown, an interface unit is provided in the preceding stage of the shift register unit 410.

  The shift register unit 410 includes registers 412 (S / R) cascaded in a plurality of stages (at least for the number of rows), and sequentially selects the pixel circuits 10 of the pixel array unit 102 in units of rows. For example, as shown in FIG. 15B, when a start pulse SPDS is applied to the first stage register 412 from an interface unit (not shown), the start pulse SPDS is converted to a shift lock CKDS (vertical scanning clock) from the interface unit (not shown). The data is sequentially shifted by the register 412 and output from each stage as an active H shift pulse SFTP having one unit period width (here, 1 horizontal period: 1H) (reference element “_n” in the figure indicates the number of stages). . One cycle of the shift lock CKDS input to the register 412 is the same as one cycle of the drive pulse, and the power supply drive pulse DSL is the same as one horizontal cycle.

  The logic circuit unit 420 has a logic circuit 422 (Logic) for each stage, and the shift pulse SFTP from the register 412 at each stage is supplied to the logic circuit 422 at the corresponding stage, and from an interface unit (not shown). An enable pulse ENDS is given. Based on the shift pulse SFTP and the enable pulse ENDS, the logic circuit 422 generates a pulse signal that is a source of the power drive pulse DSL supplied to the power supply line 105DSL of the pixel array unit 102 in accordance with the prescribed logic. In some cases, a window pulse extending over a plurality of shift locks CKDS is generated based on the shift pulse SFTP, and applied to the power supply line 105DSL of the pixel array unit 102 according to a prescribed logic based on the window pulse and the enable pulse ENDS. In some cases, a pulse signal that is a source of the power supply driving pulse DSL is generated (the example of FIG. 14 corresponds). For example, as shown in FIG. 15B, by taking the logical product of the shift pulse SFTP and the enable pulse ENDS, the pulse signal DS that is substantially the source of the power supply drive pulse DSL is sequentially shifted and output. .

The output buffer unit 440 has a buffer 442 (Buffer) for each stage, and receives a pulse signal DS having a relatively narrow amplitude (a so-called logic level with a low overall voltage level) from the logic circuit 422 of the corresponding stage. The level is converted and output as a power drive pulse DSL to the power supply line 105DSL of the corresponding row. The buffer 442 switches between two types of power supply voltages (first potential _{Vcc_H} and second potential _{Vcc_L} ) via the power supply line 105DSL of each row and supplies the power supply drive pulse DSL to the drain terminal of the drive transistor 121. The level of the pulse signal DS generated by the corresponding logic circuit 422 is converted into the first potential V _{cc_H} and the second potential V _{cc_L} . For this reason, the buffer 442 includes an output circuit having sufficient driving capability in a portion connected to the power supply line 105DSL. Although not shown, the output circuit includes, as an example, a first inverter that operates at a low voltage (logic circuit level), and a second inverter that operates at a high voltage (first potential V _{cc_H} and second potential V _{cc_L} ). Have The second inverter includes a p-channel transistor (p-type transistor) and an n-channel transistor (n-type transistor) between a supply terminal for the first potential Vcc_H and a supply terminal for the second potential Vcc_L. Are arranged in series. The source terminal of the p-type transistor is connected to the supply terminal for the first potential Vcc_H, and the source terminal of the n-type transistor is connected to the supply terminal for the second potential Vcc_L. The drain ends of the p-type transistor and the n-type transistor are connected in common, and the connection point is connected to the power supply line 105DSL. As a whole, the output circuit constitutes a CMOS buffer. The first inverter is supplied with a pulse signal DS in phase with the power supply drive pulse DSL from the logic circuit 422 by the second inverter. In the second inverter, the gate terminals of the p-type transistor and the n-type transistor are connected in common, and the pulse signal NDS obtained by logically inverting the pulse signal DS in phase with the power supply driving pulse DSL at the connection point is obtained by the second inverter. Supplied. Since the n-type transistor is turned off and the p-type transistor is turned on when the pulse signal NDS is at L level, the first potential Vcc_H is supplied to the power supply line 105DSL, while the p-type transistor is turned off when the pulse signal NDS is at H level. In addition, since the n-type transistor is turned on, the second potential Vcc_L is supplied to the power supply line 105DSL. As can be seen from this operation, the output circuit functions as a power supply voltage switching circuit.

The characteristic control scanning unit 621B of the second embodiment uses a pulse signal DS (having the same phase relationship as the power supply driving pulse DSL) output from the logic circuit unit 420 (specifically, the logic circuit 422) of the driving scanning unit 105 as a transistor. A pulse signal VB that is a source of the characteristic control signal Vb is generated, and the pulse signal VB is level-converted to a low level such as V _ini and a high level is converted to V _ofs , respectively. For this reason, as shown in FIG. 15C, the characteristic control scanning unit 621B has a logic circuit unit 630 having a logic circuit 632 for each stage and an output buffer unit (not shown) having a buffer for each stage. ing. As can be seen, the characteristic control scanning unit 621B has substantially the same configuration as the driving scanning unit 105 except that the shift register unit 410 is not provided. In the figure, the characteristic control scanning unit 621B is provided separately from the drive scanning unit 105, but the characteristic control scanning unit 621B may be provided in the drive scanning unit 105. Incidentally, since the transistor characteristic control signal Vb is supplied for each row, the well potential (transistor characteristic control signal) of the drive transistor 121 may be separated for each row, and the well of the drive transistor 121 eliminates separation for each element. No, but at least line by line.

  The logic circuit unit 630 uses an AND gate as the logic circuit 632. The logic circuit 632_2 (AND gate) at its own stage (n-th stage) includes the pulse signal DS_n-1 output from the preceding logic circuit 422_n-1 and the pulse signal DS_n + output from the next logic circuit 422_n + 1. A pulse signal VB_n is generated by performing a logical product with 1. By performing the same operation in the logic circuit 632 of each stage, the pulse signal VB that is substantially the source of the transistor characteristic control signal Vb is sequentially shifted and output.

The output buffer unit (not shown) has a buffer for each stage, and converts the level of the pulse signal VB having a relatively narrow amplitude (so-called logic level having a low overall voltage level) from the logic circuit 632 of the corresponding stage. Thus, the transistor characteristic control signal Vb is output to the characteristic control scanning line 621VB of the corresponding row. Buffer, for example, the same configuration as the buffer 442, through each row of the characteristic control scanning lines 621VB 2 kinds of voltage (low level V _ini here, a high level is set to V _ofs) by switching the drive The pulse signal VB generated by the logic circuit 632 corresponding to the transistor characteristic control signal Vb is level-converted to V _ini and V _ofs so as to be supplied to the transistor characteristic control terminal of the transistor 121. Hereinafter be omitted detailed description, buffer, the buffer 442, the first potential V _{cc - H} changed to V _ofs, it may be considered to change the second potential V _{cc - L} to V _ini. Incidentally, the second potential V _{cc_L} originally corresponds to V _ini .

In such a configuration of the characteristic control scanning unit 621B, in order to obtain the waveform of the transistor characteristic control signal Vb, logical processing (specifically logical product) is performed using the pulse signal DS that is the source of the power supply driving pulse DSL. transistor characteristic control signal may be generated a pulse signal VB to be original Vb, V to be used for V _ini (i.e. second potential V _{cc - L)} to a low level set in the setting of high level _ofs (horizontal drive unit 106 Therefore, it is not necessary to add a new power supply or pulse from the outside. Incidentally, the first node initialization voltage (V _ofs ) is not used as the high level, or the second node initialization voltage (V _ini ) is not used as the low level. Needless to say, when a voltage different from the voltage used is used at a high level or a low level, a power supply for the voltage is required.

[Modification]
The characteristic control scanning unit 621B performs the timing for raising the transistor characteristic control signal Vb to the high level (V _ofs ) in the light emitting period in the second embodiment. You may not go to the timing. However, in this case, it is necessary to set the high level to V _ofs −V _th so that the base potential Vb does not exceed the source potential Vs of the drive transistor 121 (the reverse bias state does not occur).

  FIG. 16 is a diagram for explaining a third embodiment for controlling the transistor characteristic control signal Vb. Here, FIG. 16A is a timing chart for explaining a driving method of the pixel circuit according to the third embodiment focusing on the transistor characteristic control signal Vb. FIG. 16B is a diagram illustrating a circuit configuration example that realizes the drive timing illustrated in FIG.

In the third embodiment, as shown in FIG. 16A, the first driving example and the third driving example described in the first embodiment are performed. That is, based on the first embodiment, the first driving example in which the transistor characteristic control signal Vb is set to the high level is applied during the correction processing of the threshold voltage V _th of the driving transistor 121, and signal writing is performed after the threshold correction operation. Until the mobility correction is completed, the third driving example in which the transistor characteristic control signal Vb is set to the low level is applied.

For example, its own stage (n-th stage to) falling previously low voltage power driving pulse DSL_n (first voltage: Vb _{_L)} is lowered to the. As the timing for defining the time before the falling edge of the n-th power supply driving pulse DSL_n, the falling edge of the power driving pulse DSL_n-1 at the previous stage (n−1 stage) is used as in the second embodiment. In order to apply the first driving example, as the timing for setting the transistor characteristic control signal Vb to the high level, for example, the n-th power supply driving pulse DSL (the source pulse signal DS_n) is written in the n-th stage at the low level. The rising edge of the embedded drive pulse WS_n is used. In order to apply the third driving example, as the timing when the transistor characteristic control signal Vb is set to the low level, for example, the n-th power supply driving pulse DSL (the pulse signal DS_n based on it) is written at the n-th level. The first falling edge of the embedded drive pulse WS_n is used. Further, it is raised again to a high voltage (second voltage: _{Vb_H} ) during light emission (medium). As the timing for defining the rising edge of the power supply driving pulse DSL_n at the time of light emission at the nth stage (middle), the rising edge of the power supply driving pulse DSL_n + 1 at the next stage (n + 1 stage) is used as in the second embodiment.

Thereby, a low voltage (first voltage: Vb _{_L)} the falling time of the power driving pulse DSL_n-1 of the preceding stage is falling earlier power driving pulse DSL_n of its own stage (n-1 stage) is lowered to the The threshold voltage is increased to a high voltage (second voltage: _{Vb_H} ), the threshold voltage is decreased to a low voltage (first voltage: _{Vb_L} ) from the completion of threshold correction to the completion of writing & mobility correction, and further, at the time of light emission Is raised again at the rising edge of the power supply drive pulse DSL_n + 1 of the next stage (n + 1 stage). In order to realize such timing, the pixel circuit 10 separates the transistor characteristic control terminal (base potential Vb), that is, the well of the driving transistor 121 for each V line.

  FIG. 16B shows a circuit configuration example that realizes the drive timing shown in FIG. The characteristic control scanning unit 621C according to the third embodiment includes a logic circuit unit 640 having a logic circuit 641 for each stage, an output buffer unit (not shown) having a buffer for each stage, and the logic circuit 632 described in the second embodiment. Have. The output buffer unit is the same as that described in the second embodiment.

  As shown in detail for the n-th stage, the logic circuit 641 includes an inverter 642 and an inverter 643, an AND gate 644 and an AND gate 646, an edge trigger type RSFF 648 (RS flip-flop), and an OR gate 649. Have.

  A pulse signal DS_n that is a source of the n-th power supply driving pulse DSL_n is supplied from an unillustrated logic circuit 422_2 to the inverter 642_n and one input terminal of the AND gate 646_n. A pulse signal that is a source of the n-th write drive pulse WS_n is supplied from a logic circuit (not shown) to the inverter 643_n and one input terminal of the AND gate 644_n. The output pulse of the inverter 642_n is supplied to the other input terminal of the AND gate 644_n, and the output pulse of the inverter 643_n is supplied to the other input terminal of the AND gate 646_n. The output pulse of the AND gate 644 — n is supplied to the set end of the RSFF 648 — n, and the output pulse of the AND gate 646 — n is supplied to the reset end of the RSFF 648 — n. As a result, an output pulse (648Q_n) that becomes high level at the rising edge of the write drive pulse WS_n and becomes low level at the falling edge of the write drive pulse WS_n is output to the non-inverting output terminal Q of RSFF648_n.

In the OR gate 649, an output pulse (648Q_n) is supplied to one input terminal, and an output pulse of the logic circuit 632_n is supplied to the other input terminal. As a result, during the period from the fall of the (n−1) th power drive pulse DSL_n−1 to the rise of the (n + 1) th power drive pulse DSL_n + 1, the nth write drive pulse WS_n rises and falls. The OR gate 649 outputs a pulse signal that is the source of the transistor characteristic control signal Vb_n that is at a high level and the others are at a low level. By supplying this pulse signal to a buffer of an output buffer unit (not shown), a transistor characteristic control signal Vb having a high level of V _ofs and a low level of V _ini is generated as in the second embodiment.

[Modification]
The characteristic control scanning unit 621C uses the rising edge of the write drive pulse WS_n-1 and the power supply drive pulse DSL_n-1 (the pulse signal DS_n-1 as the source) instead of the rising edge of the write drive pulse WS_n. You can also As a circuit configuration, if the write drive pulse WS_n to one input terminal of the AND gate 644_n is changed to a pulse signal that is the source of the write drive pulse WS_n-1, or a pulse signal DS_n-1 from the logic circuit 422. Good.

  FIG. 17 is a diagram for explaining the fourth embodiment. Embodiment 4 is an electronic apparatus equipped with a display device to which the above-described technology is applied to suppress and eliminate the luminance deficiency phenomenon caused by the back gate effect while relaxing the reverse bias phenomenon at the time of extinction and ensuring reliability. It is an example about. The display unevenness suppression process of this embodiment can be applied to a display device including a current-driven display element used in various electronic devices such as a game machine, an electronic book, an electronic dictionary, and a mobile phone.

  For example, FIG. 17A is a perspective view illustrating an external appearance example when the electronic apparatus 700 is a television receiver 702 using a display module 704 which is an example of an image display device. The television receiver 702 has a structure in which a display module 704 is disposed in front of a front panel 703 supported by a base 706, and a filter glass 705 is provided on the display surface. FIG. 17B is a diagram illustrating an appearance example when the electronic apparatus 700 is a digital camera 712. The digital camera 712 includes a display module 714, a control switch 716, a shutter button 717, and others. FIG. 17C is a diagram illustrating an appearance example when the electronic apparatus 700 is a video camera 722. The video camera 722 is provided with an imaging lens 725 for imaging a subject in front of the main body 723, and further, a display module 724, a shooting start / stop switch 726, and the like are arranged. FIG. 17D illustrates an example of an external appearance when the electronic apparatus 700 is a computer 732. The computer 732 includes a lower casing 733a, an upper casing 733b, a display module 734, a Web camera 735, a keyboard 736, and the like. FIG. 17E illustrates an example of an external appearance when the electronic device 700 is a mobile phone 742. The cellular phone 742 is a foldable type, and includes an upper housing 743a, a lower housing 743b, a display module 744a, a sub display 744b, a camera 745, a connecting portion 746 (in this example, a hinge portion), a picture light 747, and the like. Yes.

  Here, the display module 704, the display module 714, the display module 724, the display module 734, the display module 744a, and the sub-display 744b are manufactured by using the display device according to the present embodiment. As a result, each electronic device 700 can not only correct the luminance variation caused by the variation in threshold voltage and mobility of the driving transistor (and also variation in k), but also alleviates the reverse bias phenomenon during extinction. On the other hand, the luminance deficiency phenomenon caused by the back gate effect can be suppressed and eliminated, and high-quality display can be performed while ensuring reliability.

  As mentioned above, although the technique disclosed by this specification was demonstrated using embodiment, the technical scope of the content of a statement of a claim is not limited to the range as described in the said embodiment. Various modifications or improvements can be added to the above-described embodiment without departing from the gist of the technique disclosed in the present specification, and the form added with such a modification or improvement is also technical of the technology disclosed in the present specification. Included in the range. The embodiments described above do not limit the technology according to the claims, and all combinations of features described in the embodiments are the means for solving the problems to which the technology disclosed in the present specification is directed. It is not always essential. The above-described embodiments include technologies at various stages, and various technologies can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some configuration requirements are deleted from all the configuration requirements shown in the embodiment, these configuration requirements are deleted as long as the effect corresponding to the problem targeted by the technology disclosed in this specification can be obtained. The configured configuration can also be extracted as a technique disclosed in this specification.

  For example, it is needless to say that a complementary configuration in which, for example, the transistors are switched between the n-channel and the p-channel and the polarity of the power source or the signal is reversed in accordance with the replacement.

Considering the description of the embodiment, the technology according to the claims described in the claims is an example, and for example, the following technologies are extracted. The following is listed.
[Appendix 1]
A display unit;
Holding capacity,
A write transistor that writes a driving voltage corresponding to the video signal to the storage capacitor;
A driving transistor for driving the display unit based on the driving voltage written in the storage capacitor;
And
A pixel circuit configured to be able to suppress a reverse bias state of a driving transistor at the start of extinction.
[Appendix 2]
The pixel circuit according to appendix 1, wherein the pixel circuit is configured to be controllable so that characteristics of the driving transistor are deteriorated from a certain period before extinction of the display portion to a certain period after extinction.
[Appendix 3]
The pixel circuit according to appendix 1 or appendix 2, wherein the pixel circuit is configured to be controllable so that characteristics of the drive transistor are deteriorated before the power supply to the drive transistor is stopped and the display unit is extinguished.
[Appendix 4]
4. The pixel circuit according to appendix 2 or appendix 3, wherein the characteristics of the drive transistor are restored in conjunction with the start of light emission of the display unit.
[Appendix 5]
Item 5. The pixel circuit according to appendix 4, wherein the characteristics of the drive transistor are restored after the display unit starts displaying stably.
[Appendix 6]
A pixel portion in which a display portion is arranged;
6. The pixel circuit according to any one of appendix 1 to appendix 5, which controls the characteristics of the drive transistor for each display unit.
[Appendix 7]
The pixel circuit according to appendix 6, wherein the pixel unit is a display unit arranged in a two-dimensional matrix.
[Appendix 8]
Item 8. The pixel circuit according to appendix 7, wherein a pulse signal for controlling power supply to the drive transistor in the previous stage stops the power supply to the drive transistor in the previous stage and extinguishes the display unit, thereby degrading the characteristics of the drive transistor in the previous stage. .
[Appendix 9]
Item 9. The pixel circuit according to appendix 8, wherein the pulse signal for controlling power supply to the next-stage drive transistor returns the characteristics of the drive transistor of the first stage to the original state when the power supply to the next-stage drive transistor is started.
[Appendix 10]
9. The pixel circuit according to appendix 7 or appendix 8, wherein the pixel circuit includes a transistor characteristic control unit that generates a signal for controlling the characteristic of the drive transistor of the own stage based on a pulse signal that controls power supply to the drive transistor of the previous stage.
[Appendix 11]
The transistor characteristic control unit outputs a signal for controlling the characteristics of the driving transistor of the own stage based on the pulse signal for controlling the power supply to the driving transistor of the previous stage and the pulse signal for controlling the power supply to the driving transistor of the next stage. The pixel circuit according to appendix 10, which is generated.
[Appendix 12]
The driving transistor has a characteristic control terminal capable of controlling the threshold voltage,
The pixel circuit according to any one of appendix 7 to appendix 11, wherein the characteristic control terminal is separated at least for each stage.
[Appendix 13]
The driving transistor has a characteristic control terminal capable of controlling the threshold voltage,
12. The pixel circuit according to any one of supplementary notes 1 to 11, wherein a control signal for controlling a threshold voltage is supplied to a characteristic control terminal.
[Appendix 14]
14. The pixel circuit according to appendix 12 or appendix 13, wherein the drive transistor is a metal oxide film type field effect transistor.
[Appendix 15]
14. The pixel circuit according to appendix 12 or appendix 13, wherein the drive transistor is a back gate type thin film transistor.
[Appendix 16]
16. The pixel circuit according to any one of appendix 1 to appendix 15, wherein when the drive transistor is in a state of passing a current, the process of reducing the characteristics of the drive transistor is stopped.
[Appendix 17]
The characteristics of the driving transistor can be controlled in conjunction with the process of supplying the current to the holding capacitor through the driving transistor while writing the driving voltage corresponding to the video signal to the holding capacitor while the writing transistor is turned on. The pixel circuit according to any one of appendices 1 to 16.
[Appendix 18]
Display,
Holding capacity,
A writing transistor for writing a driving voltage corresponding to a video signal into a storage capacitor; and
A driving transistor for driving the display unit based on the driving voltage written in the storage capacitor;
Display elements comprising:
Furthermore, a display device including a characteristic control unit that controls the characteristics of the drive transistor so that the reverse bias state of the drive transistor at the start of extinction is suppressed.
[Appendix 19]
Display,
Holding capacity,
A writing transistor for writing a driving voltage corresponding to a video signal into a storage capacitor; and
A driving transistor for driving the display unit based on the driving voltage written in the storage capacitor;
Display elements comprising:
Furthermore,
A signal generator for generating a video signal supplied to the write transistor;
A characteristic control unit for controlling the characteristics of the drive transistor so that the reverse bias state of the drive transistor at the start of extinction is suppressed;
And electronic equipment.
[Appendix 20]
A method of driving a pixel circuit including a driving transistor for driving a display unit,
A pixel circuit driving method for controlling characteristics of a driving transistor so that a reverse bias state of the driving transistor is suppressed at the start of extinction.

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10 ... Pixel circuit, 11 ... Light emitting element, 100 ... Display panel part, 101 ... Substrate, 102 ... Pixel array part, 103 ... Vertical drive part, 104 ... Write scanning part, 105 ... Drive scanning part, DESCRIPTION OF SYMBOLS 106 ... Horizontal drive part, 120 ... Holding capacity, 121 ... Drive transistor, 125 ... Sampling transistor (write transistor), 127 ... Organic EL element, 130 ... Interface part, 200 ... Drive signal generation part, 220 ... Video signal processing part 310 ... Auxiliary capacitor 620 ... Transistor characteristic control unit 621 ... Characteristic control scanning unit

Claims (20)

A display unit;
Holding capacity,
A write transistor that writes a driving voltage corresponding to the video signal to the storage capacitor;
A driving transistor for driving the display unit based on the driving voltage written in the storage capacitor;
And
A pixel circuit configured to suppress a reverse bias state of a driving transistor at the start of extinction.   2. The pixel circuit according to claim 1, wherein the pixel circuit is configured to be controllable so that characteristics of the driving transistor are deteriorated from a certain period before extinction of the display portion to a certain period after extinction.   2. The pixel circuit according to claim 1, wherein the pixel circuit is configured to be controlled so that characteristics of the drive transistor are deteriorated before the power supply to the drive transistor is stopped and the display portion is extinguished. 3.   The pixel circuit according to claim 2, wherein the characteristics of the drive transistor are restored in conjunction with the start of light emission of the display unit.   The pixel circuit according to claim 4, wherein the characteristics of the drive transistor are restored after the display unit starts displaying stably. A pixel portion in which a display portion is arranged;
The pixel circuit according to claim 1, wherein the characteristics of the driving transistor are controlled for each display unit.   The pixel circuit according to claim 6, wherein the pixel unit has a display unit arranged in a two-dimensional matrix.   The pixel according to claim 7, wherein a pulse signal for controlling power supply to the previous drive transistor stops the power supply to the previous drive transistor and reduces the characteristics of the drive transistor when the display unit is extinguished. circuit.   9. The pixel circuit according to claim 8, wherein a pulse signal for controlling power supply to the next stage driving transistor restores the characteristics of the driving transistor at the first stage when power supply to the next stage driving transistor is started.   8. The pixel circuit according to claim 7, further comprising: a transistor characteristic control unit that generates a signal for controlling the characteristic of the driving transistor of the own stage based on a pulse signal that controls power supply to the driving transistor of the previous stage.   The transistor characteristic control unit outputs a signal for controlling the characteristics of the driving transistor of the own stage based on the pulse signal for controlling the power supply to the driving transistor of the previous stage and the pulse signal for controlling the power supply to the driving transistor of the next stage. The pixel circuit according to claim 10 to be generated. The driving transistor has a characteristic control terminal capable of controlling the threshold voltage,
The pixel circuit according to claim 7, wherein the characteristic control terminals are separated at least for each stage. The driving transistor has a characteristic control terminal capable of controlling the threshold voltage,
The pixel circuit according to claim 1, wherein a control signal for controlling the threshold voltage is supplied to the characteristic control terminal.   The pixel circuit according to claim 12, wherein the driving transistor is a metal oxide film type field effect transistor.   The pixel circuit according to claim 12, wherein the driving transistor is a back-gate thin film transistor.   The pixel circuit according to claim 1, wherein when the driving transistor is in a state of passing a current, the process of reducing the characteristics of the driving transistor is stopped.   The characteristics of the driving transistor can be controlled in conjunction with the process of supplying the current to the holding capacitor through the driving transistor while writing the driving voltage corresponding to the video signal to the holding capacitor while the writing transistor is turned on. The pixel circuit according to claim 1. Display,
Holding capacity,
A writing transistor for writing a driving voltage corresponding to a video signal into a storage capacitor; and
A driving transistor for driving the display unit based on the driving voltage written in the storage capacitor;
Display elements comprising:
Furthermore, a display device including a characteristic control unit that controls the characteristics of the drive transistor so that the reverse bias state of the drive transistor at the start of extinction is suppressed. Display,
Holding capacity,
A writing transistor for writing a driving voltage corresponding to a video signal into a storage capacitor; and
A driving transistor for driving the display unit based on the driving voltage written in the storage capacitor;
Display elements comprising:
Furthermore,
A signal generator for generating a video signal supplied to the write transistor;
A characteristic control unit for controlling the characteristics of the drive transistor so that the reverse bias state of the drive transistor at the start of extinction is suppressed;
And electronic equipment. A method of driving a pixel circuit including a driving transistor for driving a display unit,
A pixel circuit driving method for controlling characteristics of a driving transistor so that a reverse bias state of the driving transistor is suppressed at the start of extinction.

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