JP2012253280A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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JP2012253280A
JP2012253280A JP2011126592A JP2011126592A JP2012253280A JP 2012253280 A JP2012253280 A JP 2012253280A JP 2011126592 A JP2011126592 A JP 2011126592A JP 2011126592 A JP2011126592 A JP 2011126592A JP 2012253280 A JP2012253280 A JP 2012253280A
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wiring
semiconductor device
plating layer
substrate
connection pad
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Akihiko Hatazawa
秋彦 畑澤
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a compact semiconductor device having a connection pad near an outer peripheral end of a wiring board, which can inhibit occurrence of short circuit between adjacent connection parts.SOLUTION: A semiconductor device manufacturing method comprises: forming a plating prevention layer having an insulation quality so as to cover a portion corresponding to a dicing region among electric power supply wiring exposed on a first opening formed in a first solder resist; subsequently forming a plating layer on a surface of a connection pad; subsequently, after mounting a semiconductor chip on each of a plurality of wiring boards, cutting a wiring mother substrate along the dicing region via the plating prevention layer.

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

近年、携帯機器等の小型・薄型化により、配線基板、及び該配線基板上に実装された半導体チップよりなる半導体装置の小型化の要求が望まれている。
これに伴い、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の半導体装置では、配線基板端部と、配線基板に実装される半導体チップの端部との距離を短くすることで、半導体装置の小型化を図ることが検討されている。 In recent years, there has been a demand for downsizing of a semiconductor device including a wiring board and a semiconductor chip mounted on the wiring board due to downsizing and thinning of portable devices and the like.
Accordingly, in a BGA (Ball Grid Array) type semiconductor device, the distance between the end portion of the wiring substrate and the end portion of the semiconductor chip mounted on the wiring substrate is shortened, thereby reducing the size of the semiconductor device. Is being considered.

特許文献１には、ＢＧＡ型の半導体装置を製造する際、配線基板のダイシング領域に跨って給電用配線を配置し、給電用配線をメッキ後に、ダイシングにより給電用配線を切断することが開示されている。   Patent Document 1 discloses that when a BGA type semiconductor device is manufactured, a power supply wiring is arranged across a dicing region of a wiring board, and after the power supply wiring is plated, the power supply wiring is cut by dicing. ing.

特開２００６−１００６５１号公報JP 2006-1000065 A1

しかしながら、配線基板の外周端と半導体チップの外周端との距離を短くしてＢＧＡ型の半導体装置を製造する場合において、半導体チップの電極パッドと配線基板の接続パッドとを電気的に接続する金属ワイヤを所定のループで張設するためには、半導体チップの外周端から接続パッドまでの距離をできるだけ多くとる必要がある。このため、接続パッドは、配線基板の外周端の近傍に配置される。   However, when a BGA type semiconductor device is manufactured by shortening the distance between the outer peripheral edge of the wiring board and the outer peripheral edge of the semiconductor chip, the metal that electrically connects the electrode pads of the semiconductor chip and the connection pads of the wiring board. In order to stretch the wire in a predetermined loop, it is necessary to take as much distance as possible from the outer peripheral end of the semiconductor chip to the connection pad. For this reason, the connection pad is disposed in the vicinity of the outer peripheral edge of the wiring board.

また、配線基板は、複数の配線基板形成領域、及び該配線基板形成領域を区画するダイシング領域を有した基板本体の各配線基板形成領域に形成され、その後、各配線基板形成領域に半導体チップを実装した後、ダイサーによりダイシング領域を切断することで製造される。   The wiring board is formed in each wiring board forming area of the substrate body having a plurality of wiring board forming areas and a dicing area that partitions the wiring board forming areas, and then a semiconductor chip is placed in each wiring board forming area. After mounting, it is manufactured by cutting the dicing area with a dicer.

したがって、ある配線基板形成領域に形成された接続パッドと、該配線基板形成領域と隣り合う位置に配置された配線基板形成領域に形成された接続パッドと、の距離が狭くなる（具体的には、例えば、２００μｍ以下になると）と、隣り合う２つの配線基板形成領域に形成された接続パッド間にソルダーレジストを形成することが困難となる。   Therefore, the distance between the connection pad formed in a certain wiring board formation region and the connection pad formed in the wiring board formation region disposed adjacent to the wiring board formation region is narrow (specifically, For example, when the thickness is 200 μm or less, it becomes difficult to form a solder resist between connection pads formed in two adjacent wiring board formation regions.

この場合、隣り合う２つの配線基板形成領域に形成された接続パッドを露出する開口部をソルダーレジストに形成する。言い換えれば、隣り合う２つの配線基板形成領域に共通の開口部が、ソルダーレジストに形成される。該開口部は、ダイシング領域上の給電用配線も露出する。
このため、ソルダーレジストに開口部を形成後、接続パッド上にメッキ層を形成すると、
該開口部に露出されたダイシング領域上の給電用配線にもメッキ層が形成されてしまう。 In this case, an opening for exposing a connection pad formed in two adjacent wiring board formation regions is formed in the solder resist. In other words, an opening common to two adjacent wiring board formation regions is formed in the solder resist. The opening also exposes the power supply wiring on the dicing area.
For this reason, after forming the opening in the solder resist and forming a plating layer on the connection pad,
A plating layer is also formed on the power supply wiring on the dicing region exposed in the opening.

また、配線基板に実装される半導体チップの電極パッドの数が多く、接続パッドの配置が狭ピッチ化された配線基板においては、ダイシング領域上の給電用配線にメッキ層が形成されると、ダイシング時にメッキ層を切断する際、給電用配線上のメッキ層にダレが生じてしまい、隣接する接続パッド間でショートする虞があった。   In addition, in a wiring board in which the number of electrode pads of a semiconductor chip mounted on the wiring board is large and the arrangement of connection pads is narrowed, if a plating layer is formed on the power supply wiring on the dicing area, dicing is performed. Sometimes, when the plating layer is cut, the plating layer on the power supply wiring is sagged, and there is a possibility of short-circuiting between adjacent connection pads.

具体的には、例えば、Ｃｕ配線よりなる給電用配線上に、Ｎｉメッキ層と、Ａｕメッキ層と、を順次積層して、Ｎｉ／Ａｕメッキ層を形成した場合、Ｎｉメッキ層が柔らかいため、Ｎｉメッキ層のダレが生じ易い。   Specifically, for example, when a Ni / Au plating layer is formed by sequentially laminating a Ni plating layer and an Au plating layer on a power supply wiring made of a Cu wiring, the Ni plating layer is soft, Ni plating layer sag easily occurs.

本発明の一観点によれば、配線基板が形成される複数の配線基板形成領域、及び前記配線基板形成領域を区画するダイシング領域を有する基板本体と、前記基板本体の表面のうち、前記ダイシング領域の近傍に位置する複数の前記配線基板形成領域のそれぞれに、列状に配置された複数の接続パッドと、前記基板本体の表面のうち、前記ダイシング領域、及び該ダイシング領域と前記接続パッドとの間に位置する前記配線基板形成領域に配置され、かつ前記接続パッドのそれぞれと接続される複数の接続部を備えた給電用配線と、前記基板本体の表面に設けられ、前記ダイシング領域の両側に位置する前記複数の接続パッド、及び該複数の接続パッド間に位置する前記給電用配線を露出する第１の開口部を有する第１のソルダーレジストと、前記基板本体の裏面のうち、複数の前記配線基板形成領域に配置され、前記接続パッドと電気的に接続された外部接続用パッドと、前記基板本体の裏面に設けられ、前記外部接続用パッドを露出する第２の開口部を有する第２のソルダーレジストと、を備え、複数の前記配線基板が連結された配線母基板を準備する工程と、前記給電用配線のうち、前記第１の開口部に露出され、かつ前記ダイシング領域に対応する部分を覆うように、絶縁性を有したメッキ防止層を形成する工程と、前記メッキ防止層を形成後、前記接続パッドの表面にメッキ層を形成する工程と、前記メッキ層を介して、半導体チップに設けられた電極パッドと前記接続パッドとを電気的に接続することで、複数の前記配線基板のそれぞれに前記半導体チップを実装する工程と、前記半導体チップを実装後、前記メッキ防止層を介して、前記ダイシング領域に沿って前記配線母基板を切断する工程と、を含むことを特徴とする半導体装置の製造方法が提供される。   According to an aspect of the present invention, a substrate body having a plurality of wiring board forming regions in which a wiring substrate is formed, a dicing region that partitions the wiring substrate forming region, and the dicing region among the surfaces of the substrate body. A plurality of connection pads arranged in a row in each of the plurality of wiring board forming regions located in the vicinity of the dicing region, and the dicing region of the surface of the substrate body, and the dicing region and the connection pad Provided on the surface of the substrate main body and a power supply wiring provided with a plurality of connection portions arranged in the wiring board formation region located between and connected to each of the connection pads, on both sides of the dicing region A first solder resist having a first opening that exposes the plurality of connection pads positioned and the power supply wiring positioned between the plurality of connection pads; Out of the back surface of the substrate body, external connection pads that are disposed in a plurality of the wiring board formation regions and are electrically connected to the connection pads, and provided on the back surface of the substrate body, the external connection pads are A second solder resist having a second opening that is exposed, and a step of preparing a wiring mother board to which a plurality of the wiring boards are connected; and the first opening of the power supply wiring Forming a plating prevention layer having an insulating property so as to cover a portion corresponding to the dicing region, and after forming the plating prevention layer, forming a plating layer on the surface of the connection pad A step of mounting the semiconductor chip on each of the plurality of wiring boards by electrically connecting the electrode pads provided on the semiconductor chip and the connection pads through the plating layer and the process. When the rear mounting of the semiconductor chip, through the plating prevention layer, a method of manufacturing a semiconductor device characterized by comprising the a step of cutting the wiring mother substrate along the dicing region is provided.

本発明の半導体装置の製造方法によれば、第１のソルダーレジストに形成された第１の開口部に露出された給電用配線のうち、ダイシング領域に対応する部分を覆うように、絶縁性を有したメッキ防止層を形成し、その後、接続パッドの表面にメッキ層を形成することで、ダイシング領域に対応する給電用配線にメッキ層が形成されることがなくなる。   According to the method for manufacturing a semiconductor device of the present invention, insulation is provided so as to cover a portion corresponding to the dicing region in the power supply wiring exposed in the first opening formed in the first solder resist. By forming the plating prevention layer that is provided and then forming the plating layer on the surface of the connection pad, the plating layer is not formed on the power supply wiring corresponding to the dicing region.

その後、メッキ層を介して、複数の配線基板のそれぞれに対して半導体チップを実装した後、メッキ防止層を介して、ダイシング領域に沿って配線母基板を切断することにより、メッキ層を切断する際に発生するメッキ層のダレにより、ダイシング領域の近傍に位置する配線基板形成領域に形成され、隣接する接続部間が電気的に接続されることがなくなる。   Then, after mounting a semiconductor chip on each of the plurality of wiring boards via the plating layer, the plating layer is cut by cutting the wiring mother board along the dicing region via the plating prevention layer. Due to the sagging of the plating layer that occurs at this time, it is formed in the wiring board forming region located in the vicinity of the dicing region, and the adjacent connection portions are not electrically connected.

これにより、配線基板の外周端近傍に接続パッドを有し、かつ小型化された半導体装置において、隣接する接続部間におけるショートの発生を抑制できる（言い換えれば、隣接する接続パッド間のショートの発生を抑制できる。）。   As a result, in a semiconductor device having a connection pad near the outer peripheral edge of the wiring board and reduced in size, occurrence of a short circuit between adjacent connection parts can be suppressed (in other words, occurrence of a short circuit between adjacent connection pads). Can be suppressed.)

本発明の実施の形態に係る半導体装置の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the semiconductor device which concerns on embodiment of this invention. 図１に示す本実施の形態の半導体装置のＡ−Ａ線方向の断面図である。FIG. 2 is a cross-sectional view of the semiconductor device of the present embodiment shown in FIG. 1 in the AA line direction. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その１）であり、製造途中の半導体装置の断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure (the 1) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention, and is sectional drawing of the semiconductor device in the middle of manufacture. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その１）であり、図３Ａに示す構造体の領域Ｄの平面図である。FIG. 3B is a diagram (part 1) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention, and is a plan view of a region D of the structure illustrated in FIG. 3A; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その２）であり、製造途中の半導体装置の断面図である。FIG. 7 is a second diagram illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view of the semiconductor device that is being manufactured; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その２）であり、図４Ａに示す構造体の領域Ｄの平面図である。FIG. 4B is a diagram (part 2) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention, and is a plan view of the region D of the structure illustrated in FIG. 4A; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その３）であり、製造途中の半導体装置の断面図である。FIG. 9 is a diagram (part 3) illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view of the semiconductor device in the middle of manufacturing; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その３）であり、図５Ａに示す構造体の領域Ｄの平面図である。FIG. 6B is a diagram (part 3) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention, and is a plan view of a region D of the structure illustrated in FIG. 5A; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その４）であり、製造途中の半導体装置の断面図である。FIG. 8 is a view (No. 4) showing a manufacturing step of the semiconductor device according to the embodiment of the invention, and is a cross-sectional view of the semiconductor device during manufacturing; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その４）であり、図６Ａに示す構造体の領域Ｄの平面図である。FIG. 6D is a view (No. 4) illustrating the manufacturing process of the semiconductor device according to the embodiment of the invention, and is a plan view of the region D of the structure shown in FIG. 6A; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その５）である。It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その６）である。It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を示す図（その７）であり、製造途中の半導体装置の断面図である。FIG. 7 is a view (No. 7) showing a manufacturing step of the semiconductor device according to the embodiment of the invention, and a sectional view of the semiconductor device in the middle of manufacturing; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その７）であり、図９Ａに示す構造体の領域Ｇの平面図である。FIG. 9B is a view (No. 7) showing a manufacturing step of the semiconductor device according to the embodiment of the invention, and is a plan view of the region G of the structure shown in FIG. 9A; 本発明の実施の形態に係る半導体装置の製造工程を示す図（その８）である。It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明を適用可能な他の半導体装置の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the other semiconductor device which can apply this invention.

以下、図面を参照して本発明を適用した実施の形態について詳細に説明する。なお、以下の説明で用いる図面は、本発明の実施の形態の構成を説明するためのものであり、図示される各部の大きさや厚さや寸法等は、実際の半導体チップ、半導体装置、及び配線母基板の寸法関係とは異なる場合がある。   Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. The drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, etc. of each part shown in the drawings are actual semiconductor chips, semiconductor devices, and wirings. The dimensional relationship of the mother board may be different.

（実施の形態）
図１は、本発明の実施の形態に係る半導体装置の概略構成を示す断面図であり、図２は、図１に示す本実施の形態の半導体装置のＡ−Ａ線方向の断面図である。
図１では、説明の便宜上、本実施の形態の半導体装置１０の構成要素である図２に示すメッキ層１４及び封止樹脂２１の図示を省略する。また、図１では、本実施の形態の半導体装置１０の一例として、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の半導体装置を図示する。また、図２において、図１と同一構成部分には、同一符号を付す。 (Embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the semiconductor device according to the present embodiment shown in FIG. .
In FIG. 1, for convenience of explanation, illustration of the plating layer 14 and the sealing resin 21 shown in FIG. 2 which are components of the semiconductor device 10 of the present embodiment is omitted. FIG. 1 illustrates a BGA (Ball Grid Array) type semiconductor device as an example of the semiconductor device 10 of the present embodiment. In FIG. 2, the same components as those in FIG.

図２を参照するに、本実施の形態の半導体装置１０は、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の半導体装置であり、配線基板１１と、メッキ防止層１３と、メッキ層１４と、接着部材１６と、半導体チップ１７と、金属ワイヤ１９と、封止樹脂２１と、外部接続端子２２と、を有する。
半導体装置１０は、配線基板１１の外周端近傍に接続パッド３１を有し、かつ小型化された半導体装置である。配線基板１１の外周端と半導体チップ１７の外周端との距離Ｓは、０．４ｍｍ以下とされている。 Referring to FIG. 2, the semiconductor device 10 according to the present embodiment is a BGA (Ball Grid Array) type semiconductor device, and includes a wiring board 11, a plating prevention layer 13, a plating layer 14, an adhesive member 16, and the like. The semiconductor chip 17, the metal wire 19, the sealing resin 21, and the external connection terminal 22 are included.
The semiconductor device 10 has a connection pad 31 in the vicinity of the outer peripheral end of the wiring board 11 and is a miniaturized semiconductor device. A distance S between the outer peripheral end of the wiring substrate 11 and the outer peripheral end of the semiconductor chip 17 is set to 0.4 mm or less.

図２を参照するに、配線基板１１は、基板本体２５と、給電用配線２７を構成する接続部２８と、接続パッド３１と、第１の配線３２と、外部接続用パッド３４と、第２の配線３５と、貫通電極３７と、第１のソルダーレジスト３８と、第２のソルダーレジスト３９と、を有する。   Referring to FIG. 2, the wiring board 11 includes a board body 25, a connection portion 28 constituting a power supply wiring 27, a connection pad 31, a first wiring 32, an external connection pad 34, Wiring 35, through electrode 37, first solder resist 38, and second solder resist 39.

図２を参照するに、基板本体２５は、板状とされた矩形の絶縁基板であり、平坦な表面２５ａ及び裏面２５ｂを有する。基板本体２５としては、例えば、ガラスエポキシ樹脂基板を用いることができる。   Referring to FIG. 2, the substrate body 25 is a rectangular insulating substrate having a plate shape, and has a flat front surface 25a and a back surface 25b. As the substrate body 25, for example, a glass epoxy resin substrate can be used.

図１及び図２を参照するに、接続部２８は、基板本体２５の表面２５ａの対向する２辺にそれぞれ複数設けられている。接続部２８は、基板本体２５の最外周に列状に配置されている。接続部２８は、各接続パッド３１に対して１つずつ接続されている。接続パッド３１の幅が狭くなると、隣接する接続部２８の間隔は狭くなる。   Referring to FIGS. 1 and 2, a plurality of connection portions 28 are provided on two opposing sides of the surface 25 a of the substrate body 25. The connection portions 28 are arranged in a row on the outermost periphery of the substrate body 25. One connection portion 28 is connected to each connection pad 31. When the width of the connection pad 31 is reduced, the interval between the adjacent connection portions 28 is reduced.

接続部２８は、後述する図３Ａに示す給電用配線２７の構成要素の１つである。給電用配線２７は、電解めっき法により、接続パッド３１の表面３１ａ及び外部接続用パッド３４の表面３４ａにメッキ層１４を形成する際の給電用の配線である。上記給電用配線２７の材料としては、例えば、Ｃｕを用いることができる。   The connection portion 28 is one of the components of the power supply wiring 27 shown in FIG. 3A described later. The power supply wiring 27 is a power supply wiring for forming the plating layer 14 on the surface 31a of the connection pad 31 and the surface 34a of the external connection pad 34 by electrolytic plating. For example, Cu can be used as the material of the power supply wiring 27.

図１及び図２を参照するに、接続パッド３１は、接続部２８の形成領域よりも内側に位置する基板本体２５の表面２５ａに複数設けられており、各々１つの接続部２８と接続されている。接続パッド３１は、基板本体２５の対向する２辺の近傍に、それぞれ列状に配置されている。つまり、配線基板１１は、対向配置され、複数の接続パッド３１よりなる２つの接続パッド群を有する。   Referring to FIG. 1 and FIG. 2, a plurality of connection pads 31 are provided on the surface 25 a of the substrate body 25 located inside the region where the connection portion 28 is formed, and each connection pad 31 is connected to one connection portion 28. Yes. The connection pads 31 are arranged in a row in the vicinity of two opposing sides of the substrate body 25. In other words, the wiring substrate 11 has two connection pad groups that are arranged to face each other and include a plurality of connection pads 31.

本実施の形態の半導体装置１０を構成する配線基板１１では、図１に示すように、図１の左側に配列された接続パッド３１よりも図１の右側に配列された接続パッド３１のサイズを小さくすることで、図１の左側に配列された接続パッド３１の数よりも、図１の右側に配列された接続パッド３１の数が多くなるように構成されている。これにより、図１の右側に示す接続パッド３１は、図１の左側に示す接続パッド３１と比較して狭ピッチで配置されている。   In the wiring substrate 11 constituting the semiconductor device 10 of the present embodiment, as shown in FIG. 1, the size of the connection pads 31 arranged on the right side in FIG. 1 is made larger than the connection pads 31 arranged on the left side in FIG. By making it smaller, the number of connection pads 31 arranged on the right side in FIG. 1 is larger than the number of connection pads 31 arranged on the left side in FIG. Accordingly, the connection pads 31 shown on the right side of FIG. 1 are arranged at a narrower pitch than the connection pads 31 shown on the left side of FIG.

また、接続パッド３１は、ワイヤボンディング接続の信頼性を向上させるために、金属ワイヤ１９の張設する向きに合わせて傾けて配置されている。上記構成とされた接続パッド３１の材料としては、例えば、Ｃｕを用いることができる。   In addition, the connection pad 31 is arranged to be inclined in accordance with the direction in which the metal wire 19 is stretched in order to improve the reliability of the wire bonding connection. As a material of the connection pad 31 having the above-described configuration, for example, Cu can be used.

図１及び図２を参照するに、第１の配線３２は、接続パッド３１の形成領域よりも内側に位置する基板本体２５の表面２５ａに複数設けられている。第１の配線３２は、接続パッド３１と接続されている。これにより、第１の配線３２は、接続パッド３１を介して、接続部２８と電気的に接続されている。上記構成とされた第１の配線３２の材料としては、例えば、Ｃｕを用いることができる。   Referring to FIG. 1 and FIG. 2, a plurality of first wirings 32 are provided on the surface 25 a of the substrate body 25 located inside the region where the connection pads 31 are formed. The first wiring 32 is connected to the connection pad 31. Accordingly, the first wiring 32 is electrically connected to the connection portion 28 via the connection pad 31. As a material of the first wiring 32 configured as described above, for example, Cu can be used.

図２を参照するに、外部接続用パッド３４は、基板本体２５の裏面２５ｂに複数設けられている。外部接続用パッド３４の材料としては、例えば、Ｃｕを用いることができる。
第２の配線３５は、基板本体２５の裏面２５ｂに設けられており、外部接続用パッド３４と接続されている。第２の配線３５の材料としては、例えば、Ｃｕを用いることができる。 Referring to FIG. 2, a plurality of external connection pads 34 are provided on the back surface 25 b of the substrate body 25. As a material of the external connection pad 34, for example, Cu can be used.
The second wiring 35 is provided on the back surface 25 b of the substrate body 25 and is connected to the external connection pad 34. For example, Cu can be used as the material of the second wiring 35.

貫通電極３７は、第１の配線３２と第２の配線３５との間に位置する基板本体２５を貫通するように設けられている。貫通電極３７の上端は、第１の配線３２と接続されており、貫通電極３７の下端は、第２の配線３５と接続されている。これにより、貫通電極３７は、第１及び第２の配線３２，３５を介して、接続パッド３１と外部接続用パッド３４とを電気的に接続している。   The through electrode 37 is provided so as to penetrate the substrate body 25 located between the first wiring 32 and the second wiring 35. The upper end of the through electrode 37 is connected to the first wiring 32, and the lower end of the through electrode 37 is connected to the second wiring 35. Thereby, the through electrode 37 electrically connects the connection pad 31 and the external connection pad 34 via the first and second wirings 32 and 35.

図１及び図２を参照するに、第１のソルダーレジスト３８は、基板本体２５の表面２５ａに設けられている。第１のソルダーレジスト３８は、２つの開口部４１を有する。一方の開口部４１は、基板本体２５の対向する２辺のうち、一方の辺に形成された複数の接続部２８及び複数の接続パッド３１を露出するように形成されている。   With reference to FIGS. 1 and 2, the first solder resist 38 is provided on the surface 25 a of the substrate body 25. The first solder resist 38 has two openings 41. One opening 41 is formed so as to expose the plurality of connection portions 28 and the plurality of connection pads 31 formed on one side of the two opposite sides of the substrate body 25.

また、他方の開口部４１は、基板本体２５の対向する２辺のうち、他方の辺に形成された複数の接続部２８及び複数の接続パッド３１を露出するように形成されている。上記２つの開口部４１は、第１の配線３２のうち、接続パッド３１の近傍に位置する部分を露出している。
また、第１のソルダーレジスト３８の表面３８ａは、半導体チップ１７が接着されるチップ接着領域Ｅを有する。 The other opening 41 is formed so as to expose the plurality of connection portions 28 and the plurality of connection pads 31 formed on the other side of the two opposing sides of the substrate body 25. The two openings 41 expose portions of the first wiring 32 located in the vicinity of the connection pads 31.
Further, the surface 38a of the first solder resist 38 has a chip bonding region E to which the semiconductor chip 17 is bonded.

図２を参照するに、第２のソルダーレジスト３９は、第２の配線３５を覆うように、基板本体２５の裏面２５ｂに設けられている。第２のソルダーレジスト３９は、外部接続用パッド３４の表面３４ａを露出する第２の開口部４２を有する。
上記第１及び第２のソルダーレジスト３８，３９の材料としては、例えば、熱硬化性のエポキシ樹脂を用いることができる。 Referring to FIG. 2, the second solder resist 39 is provided on the back surface 25 b of the substrate body 25 so as to cover the second wiring 35. The second solder resist 39 has a second opening 42 that exposes the surface 34 a of the external connection pad 34.
As a material of the first and second solder resists 38 and 39, for example, a thermosetting epoxy resin can be used.

図１及び図２を参照するに、メッキ防止層１３は、接続部２８が形成された基板本体２５の対向する２辺の最外周に位置する基板本体２５の表面２５ａに、複数の接続部２８の一部（基板本体２５の対向する２辺の最外周側に位置する部分）を覆うように設けられている。   Referring to FIGS. 1 and 2, the plating prevention layer 13 has a plurality of connection portions 28 on the surface 25 a of the substrate body 25 located on the outermost periphery of two opposing sides of the substrate body 25 on which the connection portions 28 are formed. Is provided so as to cover a part (a part located on the outermost peripheral side of two opposing sides of the substrate body 25).

メッキ防止層１３は、後述する図３Ａに示すダイシング領域Ｃに形成された給電用配線本体６２（給電用配線２７の構成要素の一部）にメッキ層１４が形成されることを防止する絶縁樹脂層である。
メッキ防止層１３の材料としては、給電用配線２７を構成するＣｕ、及び封止樹脂２１との密着性のよいものを用いる。具体的には、メッキ防止層１３の材料としては、例えば、エポキシ系樹脂を用いることができる。 The plating prevention layer 13 is an insulating resin that prevents the plating layer 14 from being formed on the power supply wiring body 62 (part of the components of the power supply wiring 27) formed in the dicing area C shown in FIG. Is a layer.
As the material for the plating prevention layer 13, a material having good adhesion to Cu and the sealing resin 21 constituting the power supply wiring 27 is used. Specifically, as the material of the plating prevention layer 13, for example, an epoxy resin can be used.

図２を参照するに、メッキ層１４は、複数の接続パッド３１の表面３１ａ及び側面、開口部４１に露出された接続部２８、開口部４１に露出された第１の配線３２、外部接続用パッド３４の表面３４ａを覆うように設けられている。   Referring to FIG. 2, the plating layer 14 includes a surface 31 a and side surfaces of a plurality of connection pads 31, a connection portion 28 exposed at the opening 41, a first wiring 32 exposed at the opening 41, and an external connection It is provided so as to cover the surface 34 a of the pad 34.

メッキ層１４は、複数の接続パッド３１、開口部４１に露出された接続部２８、開口部４１に露出された第１の配線３２、及び外部接続用パッド３４がＣｕよりなる場合、複数の接続パッド３１、開口部４１に露出された接続部２８及び第１の配線３２、及び外部接続用パッド３４に含まれるＣｕの酸化や該Ｃｕの拡散を防止する機能を有する。
この場合、メッキ層１４としては、Ｎｉメッキ層５１と、金属ワイヤ１９と接続されるＡｕメッキ層５２と、を順次積層したＮｉ／Ａｕメッキ層を用いることができる。Ｎｉメッキ層５１は、ダイシングブレードで切断した際、ダレが発生しやすいメッキ層である。 The plated layer 14 includes a plurality of connection pads 31, a connection portion 28 exposed at the opening 41, a first wiring 32 exposed at the opening 41, and an external connection pad 34 made of Cu. The pad 31, the connecting portion 28 exposed to the opening 41, the first wiring 32, and the external connection pad 34 have a function of preventing oxidation of Cu and diffusion of the Cu.
In this case, as the plating layer 14, a Ni / Au plating layer in which a Ni plating layer 51 and an Au plating layer 52 connected to the metal wire 19 are sequentially laminated can be used. The Ni plating layer 51 is a plating layer that is prone to sagging when cut with a dicing blade.

図２を参照するに、半導体チップ１７は、半導体基板４５と、回路素子層４６と、電極パッド４７と、を有しており、半導体基板４５の裏面４５ｂに配置された接着部材１６により、第１のソルダーレジスト３８のチップ接着領域Ｅに接着されている。接着部材１６としては、例えば、接着剤や接着フィルム（具体的には、例えば、ＤＡＦ（Ｄｉｅ Ａｔｔａｃｈｅｄ Ｆｉｌｍ））等を用いることができる。   Referring to FIG. 2, the semiconductor chip 17 includes a semiconductor substrate 45, a circuit element layer 46, and an electrode pad 47, and the first adhesive member 16 disposed on the back surface 45 b of the semiconductor substrate 45 causes the first It is bonded to the chip bonding region E of one solder resist 38. For example, an adhesive or an adhesive film (specifically, for example, DAF (Die Attached Film)) can be used as the adhesive member 16.

半導体基板４５は、矩形とされている。半導体基板４５としては、例えば、単結晶シリコン基板を用いることができる。
回路素子層４６は、半導体基板４５の表面４５ａに設けられている。回路素子層４６は、図示していないトランジスタ、及び複数の層間絶縁層及び配線パターンを有した多層配線構造とされている。 The semiconductor substrate 45 is rectangular. As the semiconductor substrate 45, for example, a single crystal silicon substrate can be used.
The circuit element layer 46 is provided on the surface 45 a of the semiconductor substrate 45. The circuit element layer 46 has a multilayer wiring structure including a transistor (not shown), a plurality of interlayer insulating layers, and a wiring pattern.

図１を参照するに、電極パッド４７は、配線基板１１に設けられた複数の接続パッド３１と対向するように、回路素子層４６の表面に設けられている。電極パッド４７は、回路素子層４６の対向する２辺の近傍に、列状に配置されている。つまり、半導体チップ１７は、列状に配置された２つの電極パッド群を有する。
電極パッド４７は、回路素子層４６に設けられた配線パターン（図示せず）を介して、トランジスタ（図示せず）と電気的に接続されている。 Referring to FIG. 1, the electrode pad 47 is provided on the surface of the circuit element layer 46 so as to face the plurality of connection pads 31 provided on the wiring substrate 11. The electrode pads 47 are arranged in a row in the vicinity of two opposing sides of the circuit element layer 46. That is, the semiconductor chip 17 has two electrode pad groups arranged in a row.
The electrode pad 47 is electrically connected to a transistor (not shown) through a wiring pattern (not shown) provided in the circuit element layer 46.

図１及び図２を参照するに、金属ワイヤ１９は、一方の端がメッキ層１４を介して、接続パッド３１と接続されており、他方の端が半導体チップ１７の電極パッド４７と接続されている。つまり、半導体チップ１７は、配線基板１１に対してワイヤボンディング接続されている。これにより、半導体チップ１７は、配線基板１１と電気的に接続されている。金属ワイヤ１９としては、例えば、Ａｕワイヤを用いることができる。   1 and 2, one end of the metal wire 19 is connected to the connection pad 31 through the plating layer 14, and the other end is connected to the electrode pad 47 of the semiconductor chip 17. Yes. That is, the semiconductor chip 17 is connected to the wiring substrate 11 by wire bonding. Thereby, the semiconductor chip 17 is electrically connected to the wiring substrate 11. As the metal wire 19, for example, an Au wire can be used.

図２を参照するに、封止樹脂２１は、半導体チップ１７及び金属ワイヤ１９を覆うように、配線基板１１の表面側に設けられている。これにより、封止樹脂２１は、半導体チップ１７及び金属ワイヤ１９を封止すると共に、メッキ防止層１３と接触している。
封止樹脂２１の上面２１ａは、平坦な面とされている。封止樹脂２１は、例えば、トランスファーモールド法により形成することができる。封止樹脂２１の材料としては、例えば、フィラー（例えば、ガラス繊維等）含有した熱硬化性樹脂（例えば、エポキシ系樹脂）を用いることができる。 Referring to FIG. 2, the sealing resin 21 is provided on the surface side of the wiring substrate 11 so as to cover the semiconductor chip 17 and the metal wire 19. Thereby, the sealing resin 21 seals the semiconductor chip 17 and the metal wire 19 and is in contact with the plating prevention layer 13.
The upper surface 21a of the sealing resin 21 is a flat surface. The sealing resin 21 can be formed by, for example, a transfer mold method. As a material of the sealing resin 21, for example, a thermosetting resin (for example, epoxy resin) containing a filler (for example, glass fiber or the like) can be used.

外部接続端子２２は、メッキ層１４を介して、外部接続用パッド３４に設けられている。これにより、外部接続端子２２は、外部接続用パッド３４を介して、半導体チップ１７と電気的に接続されている。外部接続端子２２は、半導体チップ１７をマザーボード等の実装基板（図示せず）に実装する際、該実装基板に設けられたパッド（図示せず）と接続される端子である。   The external connection terminal 22 is provided on the external connection pad 34 via the plating layer 14. Thus, the external connection terminal 22 is electrically connected to the semiconductor chip 17 via the external connection pad 34. The external connection terminal 22 is a terminal connected to a pad (not shown) provided on the mounting board when the semiconductor chip 17 is mounted on a mounting board (not shown) such as a mother board.

図３Ａ、図３Ｂ、図４Ａ、図４Ｂ、図５Ａ、図５Ｂ、図６Ａ、図６Ｂ、図７、図８、図９Ａ、図９Ｂ、及び図１０は、本発明の実施の形態に係る半導体装置の製造工程を示す図である。
図３Ａは、断面図であり、図３Ｂは、図３Ａに示す構造体の領域Ｄの平面図である。図４Ａは、断面図であり、図４Ｂは、図４Ａに示す構造体の領域Ｄの平面図である。図５Ａは、断面図であり、図５Ｂは、図５Ａに示す構造体の領域Ｄの平面図である。図６Ａは、断面図であり、図６Ｂは、図６Ａに示す構造体の領域Ｄの平面図である。図７及び図８は、断面図である。図９Ａは、断面図であり、図９Ｂは、図９Ａに示す構造体の領域Ｇの平面図である。図１０は、断面図である。
図３Ａ、図３Ｂ、図４Ａ、図４Ｂ、図５Ａ、図５Ｂ、図６Ａ、図６Ｂ、図７、図８、図９Ａ、図９Ｂ、及び図１０において、図１及び図２に示す本実施の形態の半導体装置１０と同一構成部分には、同一符号を付す。 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7, 8, 9A, 9B, and 10 are semiconductors according to embodiments of the present invention. It is a figure which shows the manufacturing process of an apparatus.
3A is a sectional view, and FIG. 3B is a plan view of a region D of the structure shown in FIG. 3A. 4A is a cross-sectional view, and FIG. 4B is a plan view of a region D of the structure shown in FIG. 4A. 5A is a cross-sectional view, and FIG. 5B is a plan view of a region D of the structure shown in FIG. 5A. 6A is a sectional view, and FIG. 6B is a plan view of a region D of the structure shown in FIG. 6A. 7 and 8 are cross-sectional views. 9A is a cross-sectional view, and FIG. 9B is a plan view of a region G of the structure shown in FIG. 9A. FIG. 10 is a cross-sectional view.
3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7, 8, 9A, 9B, and 10 in FIG. 1 and FIG. The same reference numerals are given to the same components as those of the semiconductor device 10 of the form.

図３Ａ、図３Ｂ、図４Ａ、図４Ｂ、図５Ａ、図５Ｂ、図６Ａ、図６Ｂ、図７、図８、図９Ａ、図９Ｂ、及び図１０を参照して、本実施の形態の半導体装置１０の製造方法について説明する。   3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7, 8, 9A, 9B, and 10, the semiconductor of this embodiment A method for manufacturing the device 10 will be described.

始めに、図３Ａ及び図３Ｂに示す工程では、配線基板１１が形成される複数の配線基板形成領域Ｂ、及び配線基板形成領域Ｂを区画するダイシング領域Ｃを有する基板本体２５と、基板本体２５の表面２５ａのうち、ダイシング領域Ｃの近傍に位置する複数の配線基板形成領域Ｃのそれぞれに、列状に配置された複数の接続パッド３１と、基板本体２５の表面２５ａのうち、ダイシング領域Ｃに配置された給電用配線本体６２、及びダイシング領域Ｃと接続パッド３１との間に位置する配線基板形成領域Ｂに配置され、かつ給電用配線本体６２、及び接続パッド３１のそれぞれと接続される複数の接続部２８を備えた給電用配線２７と、基板本体２５の表面２５ａに設けられ、ダイシング領域Ｃの両側に位置する複数の接続パッド３１、及び複数の接続パッド３１間に位置する給電用配線２７を露出する第１の開口部６４を有する第１のソルダーレジスト３８と、基板本体２５の裏面２５ｂのうち、複数の配線基板形成領域Ｂに配置され、接続パッド３１と電気的に接続された外部接続用パッド３４と、基板本体２５の裏面２５ｂに設けられ、外部接続用パッド３４を露出する第２の開口部４２を有した第２のソルダーレジスト３９と、を有し、複数の配線基板１１が連結された配線母基板６０を準備する。   First, in the process shown in FIGS. 3A and 3B, a substrate body 25 having a plurality of wiring substrate formation regions B on which the wiring substrate 11 is formed, and a dicing region C partitioning the wiring substrate formation region B, and the substrate body 25 The plurality of connection pads 31 arranged in a row in each of the plurality of wiring board formation regions C located in the vicinity of the dicing region C of the surface 25a of the substrate and the dicing region C of the surface 25a of the substrate body 25 The power supply wiring main body 62 and the wiring board forming region B located between the dicing region C and the connection pad 31 are connected to the power supply wiring main body 62 and the connection pad 31, respectively. A power supply wiring 27 having a plurality of connection portions 28, a plurality of connection pads 31 provided on both sides of the dicing region C, provided on the surface 25a of the substrate body 25; The first solder resist 38 having the first opening 64 that exposes the power supply wiring 27 positioned between the plurality of connection pads 31 and the back surface 25b of the substrate body 25 are arranged in a plurality of wiring board formation regions B. The second solder having the external connection pad 34 electrically connected to the connection pad 31 and the second opening 42 provided on the back surface 25b of the substrate body 25 and exposing the external connection pad 34. And a wiring mother board 60 having a plurality of wiring boards 11 connected thereto.

第１のソルダーレジスト３８の表面３８ａは、後述する図６Ａに示す半導体チップ１７が接着されるチップ接着領域Ｅを有する。
ダイシング領域Ｃの幅は、例えば、２００μｍとすることができる。図３Ａ及び図３Ｂに示す基板本体２５は、個片化される前の基板本体であり、個片することで、図２に示す基板本体２５となる。つまり、図３Ａ及び図３Ｂに示す基板本体２５は、図２に示す基板本体２５が複数連結されたものである。 The surface 38a of the first solder resist 38 has a chip bonding region E to which a semiconductor chip 17 shown in FIG.
The width of the dicing area C can be set to 200 μm, for example. The substrate main body 25 shown in FIGS. 3A and 3B is a substrate main body before being singulated, and the substrate main body 25 shown in FIG. That is, the substrate main body 25 shown in FIGS. 3A and 3B is obtained by connecting a plurality of substrate main bodies 25 shown in FIG.

第１の開口部６４は、ダイシング領域Ｃにおいて配線母基板６０を切断することで、２つの開口部４１（図１及び図２参照）となる。つまり、第１の開口部６４は、一体とされた２つの開口部４１により構成されている。   The first opening 64 becomes two openings 41 (see FIGS. 1 and 2) by cutting the wiring mother board 60 in the dicing region C. That is, the first opening 64 is constituted by two openings 41 that are integrated.

次いで、図４Ａ及び図４Ｂに示す工程では、給電用配線２７のうち、第１の開口部６４に露出され、かつダイシング領域Ｃに対応する部分（具体的には、給電用配線本体６２、及び給電用配線本体６２の近傍に位置する複数の接続部２８の一部）を覆うように、絶縁性を有したメッキ防止層１３を形成する。   4A and 4B, a portion of the power supply wiring 27 that is exposed to the first opening 64 and corresponds to the dicing region C (specifically, the power supply wiring main body 62, and An insulating plating prevention layer 13 is formed so as to cover a part of the plurality of connection portions 28 located in the vicinity of the power supply wiring main body 62.

具体的には、メッキ防止層１３は、ディスペンサーやジェット塗布により形成する。また、メッキ防止層１３としては、給電用配線２７の材料であるＣｕ、及び後述する図７に示す封止樹脂２１との密着性のよいものを用いるとよい。具体的には、メッキ防止層１３として、エポキシ系樹脂等の絶縁樹脂層を形成する。   Specifically, the plating prevention layer 13 is formed by a dispenser or jet coating. Further, as the plating preventing layer 13, it is preferable to use a material having good adhesion with Cu as a material of the power supply wiring 27 and a sealing resin 21 shown in FIG. Specifically, an insulating resin layer such as an epoxy resin is formed as the plating prevention layer 13.

メッキ防止層１３は、その幅Ｆがダイシング領域Ｃの幅よりも広くなるように形成するとよい。具体的には、ダイシング領域Ｃの幅が２００μｍの場合、例えば、メッキ防止層１３の幅Ｆは、２５０μｍとすることができる。   The anti-plating layer 13 is preferably formed such that its width F is wider than the width of the dicing area C. Specifically, when the width of the dicing region C is 200 μm, for example, the width F of the plating prevention layer 13 can be set to 250 μm.

次いで、図５Ａ及び図５Ｂに示す工程では、給電用配線２７を給電層とする電解メッキ法により、接続パッド３１の表面３１ａ、及び外部接続用パッド３４の表面３４ａを覆うメッキ層１４を形成する。
具体的には、接続パッド３１の表面３１ａ、及び外部接続用パッド３４の表面３４ａに、Ｎｉメッキ層５１と、Ａｕメッキ層５２と、を順次積層させることで、メッキ層１４としてＮｉ／Ａｕメッキ層を形成する。 5A and 5B, the plating layer 14 that covers the surface 31a of the connection pad 31 and the surface 34a of the external connection pad 34 is formed by electrolytic plating using the power supply wiring 27 as a power supply layer. .
Specifically, a Ni plating layer 51 and an Au plating layer 52 are sequentially laminated on the surface 31a of the connection pad 31 and the surface 34a of the external connection pad 34, thereby forming the Ni / Au plating as the plating layer 14. Form a layer.

このとき、メッキ層１４は、接続パッド３１の側面、外部接続用パッド３４の側面、第１の開口部６４により露出された第１の配線３２、及び第１の開口部６４により露出された接続部２８にも形成されるが、給電用配線２７のうち、ダイシング領域Ｃに対応する部分（具体的には、給電用配線本体６２、及び給電用配線本体６２の近傍に位置する複数の接続部２８の一部）は、絶縁性を有したメッキ防止層１３で覆われているため、メッキ層１４が形成されることはない。   At this time, the plating layer 14 is connected to the side surface of the connection pad 31, the side surface of the external connection pad 34, the first wiring 32 exposed by the first opening 64, and the connection exposed by the first opening 64. Although formed in the portion 28, a portion corresponding to the dicing region C in the power supply wiring 27 (specifically, the power supply wiring main body 62 and a plurality of connection portions located in the vicinity of the power supply wiring main body 62. 28) is covered with an insulating plating prevention layer 13, so that the plating layer 14 is not formed.

次いで、図６Ａ及び図６Ｂに示す工程では、接着部材１６により、半導体チップ１７をフェイスアップした状態で第１のソルダーレジスト３８のチップ接着領域Ｅに接着する。
次いで、メッキ層１４を介して、半導体チップ１７に設けられた電極パッド４７と配線基板１１に設けられた接続パッド３１とを電気的に接続することで、複数の配線基板１１のそれぞれに半導体チップ１７を実装する。 6A and 6B, the bonding member 16 bonds the semiconductor chip 17 to the chip bonding region E of the first solder resist 38 with the face up.
Next, the electrode pads 47 provided on the semiconductor chip 17 and the connection pads 31 provided on the wiring substrate 11 are electrically connected via the plating layer 14 to each of the plurality of wiring substrates 11. 17 is implemented.

具体的には、金属ワイヤ１９（例えば、Ａｕワイヤ）により、電極パッド３１とメッキ層１４が形成された接続パッドとをワイヤボンディング接続することで、配線基板１１に半導体チップ１７を実装する。   Specifically, the semiconductor chip 17 is mounted on the wiring substrate 11 by wire bonding connection between the electrode pad 31 and the connection pad on which the plating layer 14 is formed by using a metal wire 19 (for example, Au wire).

次いで、図７に示す工程では、配線母基板６０の表面側に、複数の配線基板１１に実装された半導体チップ１７を覆う封止樹脂２１を形成する。
具体的には、例えば、トランスファーモールド法により、封止樹脂２１を形成する。これにより、上面２１ａが平坦な面とされた封止樹脂２１を形成することができる。また、封止樹脂２１の母材としては、ガラス繊維等よりなるフィラーを含有した熱硬化性樹脂（例えば、エポキシ系樹脂）を用いることができる。 Next, in the step shown in FIG. 7, the sealing resin 21 that covers the semiconductor chips 17 mounted on the plurality of wiring boards 11 is formed on the surface side of the wiring mother board 60.
Specifically, for example, the sealing resin 21 is formed by a transfer molding method. Thereby, it is possible to form the sealing resin 21 whose upper surface 21a is a flat surface. Moreover, as a base material of the sealing resin 21, a thermosetting resin (for example, epoxy resin) containing a filler made of glass fiber or the like can be used.

次いで、図８に示す工程では、図７に示す構造体を上下反転させ、その後、メッキ層１４を介して、外部接続用パッド３４に外部接続端子２２を配置する。
具体的には、図示していない吸着機構により、外部接続端子２２であるはんだボールを吸着し、配線基板１１毎に、メッキ層１４を介して、外部接続用パッド３４にはんだボールを配置する。 Next, in the process shown in FIG. 8, the structure shown in FIG. 7 is turned upside down, and then the external connection terminals 22 are arranged on the external connection pads 34 via the plating layer 14.
Specifically, a solder ball as the external connection terminal 22 is sucked by a suction mechanism (not shown), and the solder ball is arranged on the external connection pad 34 via the plating layer 14 for each wiring board 11.

これにより、外部接続端子２２は、メッキ層１４及び外部接続用パッド３４を介して、半導体チップ１７と電気的に接続されると共に、各配線基板形成領域Ｂに半導体装置１０が形成される。この段階では、複数の半導体装置１０は、連結されており、個片化されていない。   As a result, the external connection terminals 22 are electrically connected to the semiconductor chip 17 via the plating layer 14 and the external connection pads 34, and the semiconductor device 10 is formed in each wiring board formation region B. At this stage, the plurality of semiconductor devices 10 are connected and are not separated.

次いで、図９Ａ及び図９Ｂに示す工程では、図８に示す構造体に設けられた封止樹脂２１の上面２１ａに、ダイシングテープ６６を貼り付ける。
次いで、図８に示すメッキ防止層１３を介して、ダイシング領域Ｃに沿って、図８に示す封止樹脂２１、及び図８に示す配線母基板６０（具体的には、メッキ防止層１３に覆われた給電用配線２７、基板本体２５、及び第２のソルダーレジスト３９）を切断することで、複数の半導体装置１０を個片化する。 9A and 9B, a dicing tape 66 is pasted on the upper surface 21a of the sealing resin 21 provided in the structure shown in FIG.
Next, the sealing resin 21 shown in FIG. 8 and the wiring mother board 60 shown in FIG. 8 (specifically, on the plating prevention layer 13) along the dicing region C through the plating prevention layer 13 shown in FIG. By cutting the covered power supply wiring 27, the substrate body 25, and the second solder resist 39), the plurality of semiconductor devices 10 are separated into individual pieces.

このとき、ダイシング領域Ｃには、Ｎｉメッキ層５１を含んだメッキ層１４が形成されていないため、ダイシング領域ＣにおいてＮｉメッキ層５１のダレが発生することがない。これにより、ダイシング領域Ｃの近傍に位置する配線基板形成領域Ｂに配置され、かつ隣接する接続部２８間が、上記Ｎｉメッキ層５１のダレにより電気的に接続されることがなくなる。   At this time, since the plating layer 14 including the Ni plating layer 51 is not formed in the dicing area C, the sagging of the Ni plating layer 51 does not occur in the dicing area C. As a result, the connection portions 28 arranged in the wiring board forming region B located in the vicinity of the dicing region C and being adjacent to each other are not electrically connected by the sagging of the Ni plating layer 51.

したがって、配線基板１１の外周端付近に接続パッド３１を有し、かつ小型化された半導体装置１０においても、隣接する接続部２８間におけるショートの発生を抑制できる（言い換えれば、隣接する接続パッド３１間のショートの発生を抑制できる。）。
また、隣接する接続部２８間におけるショートの発生を抑制できることにより、接続部２８と接続される接続パッド３１の狭ピッチ化が可能となるので、半導体装置１０のさらなる小型化を図ることができる。 Therefore, even in the semiconductor device 10 having the connection pad 31 near the outer peripheral end of the wiring substrate 11 and having a reduced size, occurrence of a short circuit between the adjacent connection portions 28 can be suppressed (in other words, the adjacent connection pad 31 The occurrence of a short circuit can be suppressed.)
In addition, since the occurrence of a short circuit between adjacent connection portions 28 can be suppressed, the connection pads 31 connected to the connection portions 28 can be narrowed in pitch, and the semiconductor device 10 can be further downsized.

また、図８に示す配線母基板６０を切断することで、第１の開口部６４（図８参照）が２つに分割され、２つの開口部４１となる。   Further, by cutting the wiring mother board 60 shown in FIG. 8, the first opening 64 (see FIG. 8) is divided into two and becomes two openings 41.

次いで、図１０に示す工程では、図９Ａに示す個片化された複数の半導体装置１０をダイシングテープ６６からピックアップして、図９Ａに示す状態から複数の半導体装置１０の上下を反転させる。これにより、図１０に示すように、複数の半導体装置１０が製造される。   Next, in the process shown in FIG. 10, the plurality of separated semiconductor devices 10 shown in FIG. 9A are picked up from the dicing tape 66, and the plurality of semiconductor devices 10 are turned upside down from the state shown in FIG. 9A. Thereby, as shown in FIG. 10, a plurality of semiconductor devices 10 are manufactured.

本実施の形態の半導体装置の製造方法によれば、第１のソルダーレジスト３８に形成された第１の開口部６４に露出された給電用配線２７のうち、ダイシング領域Ｃに対応する部分を覆うように、絶縁性を有したメッキ防止層１３を形成し、その後、接続パッド３１の表面３１ａに、Ｎｉメッキ層５１及びＡｕメッキ層５２よりなるメッキ層１４を形成することで、ダイシング領域Ｃに対応する給電用配線２７にメッキ層１４が形成されることがなくなる。   According to the manufacturing method of the semiconductor device of the present embodiment, the portion corresponding to the dicing region C is covered in the power supply wiring 27 exposed in the first opening 64 formed in the first solder resist 38. In this way, the plating prevention layer 13 having insulating properties is formed, and then the plating layer 14 composed of the Ni plating layer 51 and the Au plating layer 52 is formed on the surface 31 a of the connection pad 31, so that the dicing region C is formed. The plating layer 14 is not formed on the corresponding power supply wiring 27.

その後、メッキ層１４を介して、複数の配線基板１１のそれぞれに対して半導体チップ１７を実装した後、メッキ防止層１３を介して、ダイシング領域Ｃに沿って配線母基板６０を切断することにより、ダイシング領域Ｃにはダレが発生しやすいＮｉメッキ層５１を含むメッキ層１４が形成されていないため、Ｎｉメッキ層５１を切断する際に発生するＮｉメッキ層５１のダレにより、ダイシング領域Ｃの近傍に位置する配線基板形成領域Ｂに形成された接続部２８（給電用配線２７の構成要素の１つ）間が電気的に接続されることがなくなる。   Thereafter, the semiconductor chip 17 is mounted on each of the plurality of wiring boards 11 via the plating layer 14, and then the wiring mother board 60 is cut along the dicing region C via the plating prevention layer 13. In the dicing area C, the plating layer 14 including the Ni plating layer 51 that is prone to sagging is not formed. Therefore, the sagging of the Ni plating layer 51 that occurs when cutting the Ni plating layer 51 causes The connection portion 28 (one of the components of the power supply wiring 27) formed in the wiring board forming region B located in the vicinity is not electrically connected.

これにより、配線基板１１の外周端近傍に接続パッド３１を有し、かつ小型化された半導体装置１０においても、隣接する接続部２８間におけるショートの発生を抑制できる（言い換えれば、隣接する接続パッド３１間のショートの発生を抑制できる。）。   Thereby, even in the semiconductor device 10 having the connection pad 31 near the outer peripheral end of the wiring board 11 and having a reduced size, occurrence of a short circuit between the adjacent connection portions 28 can be suppressed (in other words, adjacent connection pads). The occurrence of a short circuit between 31 can be suppressed.)

また、図１０に示すように、配線基板１１の外周端と半導体チップ１７の外周端との距離Ｓが０．４ｍｍ以下となるように、半導体装置１０を製造することで、複数の配線基板形成領域Ｂ及びダイシング領域Ｃを有した図３に示す基板本体２５から、より多くの数の半導体装置１０を取得することが可能となる。   Also, as shown in FIG. 10, a plurality of wiring boards are formed by manufacturing the semiconductor device 10 so that the distance S between the outer circumference edge of the wiring board 11 and the outer circumference edge of the semiconductor chip 17 is 0.4 mm or less. A larger number of semiconductor devices 10 can be obtained from the substrate body 25 shown in FIG. 3 having the region B and the dicing region C.

以上、本発明の好ましい実施の形態について詳述したが、本発明はかかる特定の実施の形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

図１１は、本発明を適用可能な他の半導体装置の概略構成を示す断面図である。図１１において、図１に示す本実施の形態の半導体装置１０と同一構成部分には、同一符号を付す。   FIG. 11 is a cross-sectional view showing a schematic configuration of another semiconductor device to which the present invention is applicable. 11, the same components as those of the semiconductor device 10 of the present embodiment shown in FIG.

なお、本実施の形態の半導体装置１０の製造方法では、一例として、メッキ層１４を介して、配線基板１１の接続パッド３１と、半導体チップ１７の電極パッド４７とをワイヤボンディング接続する場合を例に挙げて説明したが、本実施の半導体装置の製造方法は、図１１に示すように、メッキ層１４を介して、配線基板１１の接続パッド３１と、半導体チップ１７の電極パッド４７とをフリップチップ接続した半導体装置７０（配線基板１１との外周端と半導体チップ１７の外周端との距離Ｓが０．４ｍｍ以下の半導体装置）にも適用可能である。   In the method of manufacturing the semiconductor device 10 according to the present embodiment, as an example, the connection pad 31 of the wiring substrate 11 and the electrode pad 47 of the semiconductor chip 17 are connected by wire bonding via the plating layer 14 as an example. As described above, the method of manufacturing a semiconductor device of this embodiment flips the connection pads 31 of the wiring board 11 and the electrode pads 47 of the semiconductor chip 17 through the plating layer 14 as shown in FIG. The present invention is also applicable to a chip-connected semiconductor device 70 (a semiconductor device in which the distance S between the outer peripheral end of the wiring substrate 11 and the outer peripheral end of the semiconductor chip 17 is 0.4 mm or less).

また、本実施の形態の半導体装置１０の製造方法では、配線基板１１上に１つの半導体チップ１７を実装する場合を例に挙げて説明したが、本発明は、半導体チップ１７の外周端と配線基板１１の外周端との距離Ｓが短い半導体装置であれば、配線基板１１上に２つ以上の半導体チップ１７を積み重ねた構成とされた半導体装置の製造方法に適用してもよい。   Further, in the method for manufacturing the semiconductor device 10 of the present embodiment, the case where one semiconductor chip 17 is mounted on the wiring substrate 11 has been described as an example. Any semiconductor device having a short distance S from the outer peripheral edge of the substrate 11 may be applied to a method of manufacturing a semiconductor device in which two or more semiconductor chips 17 are stacked on the wiring substrate 11.

また、本実施の形態では、矩形とされた基板本体２５の対向する２辺に列状の接続パッド３１が配置された配線基板１１を用いた場合を例に挙げて説明したが、基板本体の４辺に、列状の接続パッド３１が配置された配線基板を用いて、半導体装置を製造してもよい。   In the present embodiment, the case where the wiring substrate 11 in which the row-shaped connection pads 31 are arranged on the two opposite sides of the rectangular substrate body 25 is described as an example. You may manufacture a semiconductor device using the wiring board by which the line-shaped connection pad 31 is arrange | positioned on four sides.

本発明は、半導体装置の製造方法に適用可能である。   The present invention is applicable to a method for manufacturing a semiconductor device.

１０，７０…半導体装置、１１…配線基板、１３…メッキ防止層、１４…メッキ層、１６…接着部材、１７…半導体チップ、１９…金属ワイヤ、２１…封止樹脂、２１ａ…上面、２２…外部接続端子、２５…基板本体、２７…給電用配線、２８…接続部、３１…接続パッド、２５ａ，３１ａ,３４ａ，３８ａ，４５ａ…表面、２５ｂ，４５ｂ…裏面、３２…第１の配線、３４…外部接続用パッド、３５…第２の配線、３７…貫通電極、３８…第１のソルダーレジスト、３９…第２のソルダーレジスト、４１…開口部、４２…第２の開口部、４５…半導体基板、４６…回路素子層、４７…電極パッド、５１…Ｎｉメッキ層、５２…Ａｕメッキ層、６０…配線母基板、６２…給電用配線本体、６４…第１の開口部、６６…ダイシングテープ、Ｂ…配線基板形成領域、Ｃ…ダイシング領域、Ｄ，Ｇ…領域、Ｆ…幅、Ｓ…距離   DESCRIPTION OF SYMBOLS 10,70 ... Semiconductor device, 11 ... Wiring board, 13 ... Plating prevention layer, 14 ... Plating layer, 16 ... Adhesive member, 17 ... Semiconductor chip, 19 ... Metal wire, 21 ... Sealing resin, 21a ... Upper surface, 22 ... External connection terminals, 25 ... board body, 27 ... power supply wiring, 28 ... connection portion, 31 ... connection pad, 25a, 31a, 34a, 38a, 45a ... front surface, 25b, 45b ... back surface, 32 ... first wiring, 34 ... External connection pad, 35 ... Second wiring, 37 ... Through electrode, 38 ... First solder resist, 39 ... Second solder resist, 41 ... Opening, 42 ... Second opening, 45 ... Semiconductor substrate 46... Circuit element layer 47. Electrode pad 51. Ni plated layer 52. Au plated layer 60. Wiring mother board 62 62 Power supply wiring body 64 64 First opening 66 Dicing Tape, B ... Line substrate forming region, C ... Dicing region, D, G ... region, F ... Width, S ... Distance

Claims (7)

配線基板が形成される複数の配線基板形成領域、及び前記配線基板形成領域を区画するダイシング領域を有する基板本体と、前記基板本体の表面のうち、前記ダイシング領域の近傍に位置する複数の前記配線基板形成領域のそれぞれに、列状に配置された複数の接続パッドと、前記基板本体の表面のうち、前記ダイシング領域、及び該ダイシング領域と前記接続パッドとの間に位置する前記配線基板形成領域に配置され、かつ前記接続パッドのそれぞれと接続される複数の接続部を備えた給電用配線と、前記基板本体の表面に設けられ、前記ダイシング領域の両側に位置する前記複数の接続パッド、及び該複数の接続パッド間に位置する前記給電用配線を露出する第１の開口部を有する第１のソルダーレジストと、前記基板本体の裏面のうち、複数の前記配線基板形成領域に配置され、前記接続パッドと電気的に接続された外部接続用パッドと、前記基板本体の裏面に設けられ、前記外部接続用パッドを露出する第２の開口部を有する第２のソルダーレジストと、を備え、複数の前記配線基板が連結された配線母基板を準備する工程と、
前記給電用配線のうち、前記第１の開口部に露出され、かつ前記ダイシング領域に対応する部分を覆うように、絶縁性を有したメッキ防止層を形成する工程と、
前記メッキ防止層を形成後、前記接続パッドの表面にメッキ層を形成する工程と、
前記メッキ層を介して、半導体チップに設けられた電極パッドと前記接続パッドとを電気的に接続することで、複数の前記配線基板のそれぞれに前記半導体チップを実装する工程と、
前記半導体チップを実装後、前記メッキ防止層を介して、前記ダイシング領域に沿って前記配線母基板を切断する工程と、
を含むことを特徴とする半導体装置の製造方法。 A plurality of wiring substrate forming regions on which a wiring substrate is formed; a substrate body having a dicing region that partitions the wiring substrate forming region; and a plurality of the wirings positioned in the vicinity of the dicing region on the surface of the substrate body A plurality of connection pads arranged in a row in each of the substrate formation regions, and the dicing region of the surface of the substrate body, and the wiring substrate formation region positioned between the dicing region and the connection pads And a plurality of connection pads provided on the surface of the substrate body and located on both sides of the dicing region, and a plurality of connection wirings provided with a plurality of connection portions connected to each of the connection pads, and A first solder resist having a first opening exposing the power supply wiring located between the plurality of connection pads, and a back surface of the substrate body An external connection pad disposed in a plurality of wiring board formation regions and electrically connected to the connection pad; and a second opening provided on the back surface of the substrate body and exposing the external connection pad. A second solder resist, and a step of preparing a wiring mother board in which a plurality of the wiring boards are connected;
Forming an insulating plating prevention layer so as to cover a portion of the power supply wiring that is exposed to the first opening and corresponds to the dicing region;
After forming the plating prevention layer, forming a plating layer on the surface of the connection pad;
Mounting the semiconductor chip on each of the plurality of wiring boards by electrically connecting the electrode pads provided on the semiconductor chip and the connection pads via the plating layer;
After mounting the semiconductor chip, cutting the wiring mother board along the dicing region via the plating prevention layer;
A method for manufacturing a semiconductor device, comprising: 前記メッキ防止層として、絶縁樹脂層を形成することを特徴とする請求項１記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein an insulating resin layer is formed as the plating prevention layer. 前記メッキ防止層は、該メッキ防止層の幅が、前記ダイシング領域の幅よりも広くなるように形成することを特徴とする請求項１または２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the anti-plating layer is formed so that the width of the anti-plating layer is wider than the width of the dicing region. 前記接続パッド及び前記外部接続用パッドの材料として、Ｃｕを用いることを特徴とする請求項１ないし３のうち、いずれか１項記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein Cu is used as a material for the connection pad and the external connection pad. 前記メッキ層は、Ｎｉメッキ層と、Ａｕメッキ層と、を順次積層させることで形成することを特徴とする請求項１ないし４のうち、いずれか１項記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein the plating layer is formed by sequentially laminating a Ni plating layer and an Au plating layer. 6. 前記半導体チップを実装する工程では、前記電極パッドと前記接続パッドとをワイヤボンディング接続することを特徴とする請求項１ないし５のうち、いずれか１項記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of mounting the semiconductor chip, the electrode pad and the connection pad are connected by wire bonding. 前記半導体チップを実装する工程では、前記配線基板と前記半導体チップとをフリップチップ接続することを特徴とする請求項１ないし５のうち、いずれか１項記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of mounting the semiconductor chip, the wiring board and the semiconductor chip are flip-chip connected.
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