JP2012248557A - Thin multilayer wire bonding capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin multilayer wire bonding capacitor having a high capacity.SOLUTION: Capacitor electrode layers 2 are printed on the front face and the rear face of a dielectric ceramic layer 1 to thereby prepare a layer which functions as a capacitor. Conduction layers 3 are laminated over and under this layer to obtain an element thickness, thereby achieving mechanical strength. The conduction layers 3 are provided with via-holes which are filled with an interlayer conduction material 5 by hole-filling printing. A surface electrode layer 6 is arranged on each of the conduction layers 3 which is electrically connected to each of the capacitor electrode layers 2 via the interlayer conduction material 5. As described above, the dielectric ceramic layer 1 for obtaining capacitance and the conduction layers 3 for ensuring the mechanical strength are formed separately from each other.

Description

The present invention relates to increasing the capacity of a wire bonding capacitor.

Conventional wire bonding capacitors include a single plate type and a multilayer type. As shown in FIG. 1, the single plate type is a capacitor that enables wire bond connection by installing surface electrode layers on the front and back surfaces of a dielectric layer, and is reported in, for example, Japanese Patent Application Laid-Open No. 2001-332441. ing.

On the other hand, as shown in FIG. 2, the multilayer type is a capacitor designed to obtain a high capacity by laminating a dielectric layer and an internal electrode layer in a direction perpendicular to the mounting surface. The surface electrode is installed in parallel to the mounting surface so that connection is possible. Such a multilayer wire bonding capacitor has been reported in Japanese Patent Laid-Open No. 7-16948 and is well known.

JP 2001-332441 A Japanese Patent Laid-Open No. 7-16948

However, since a single-plate wire bonding capacitor requires an element thickness of about 150 μm in order to maintain the mechanical strength of the element itself, it is difficult to make the element thickness thinner than 150 μm in order to obtain a high capacity. There is a problem that.

In addition, although the multilayer wire bonding capacitor can increase the number of layers without increasing the thickness of the element and obtain a high capacity, in order to ensure the overlapping area of the internal electrodes that contribute to the capacitance Since a certain thickness of the element is required, there is a problem that the element thickness cannot be further reduced.

Accordingly, in order to solve the above-described problems, the present invention provides a thin multilayer wire bonding capacitor in which the thickness of the element can be made thinner than that of the multilayer type and in addition, a higher capacity than that of the single plate type can be obtained. With the goal.

A dielectric ceramic layer, a capacitor electrode layer printed on the front and back surfaces of the dielectric ceramic layer, a conductive layer having a via hole, an interlayer conductive material filled in the via hole, and a conductive layer disposed on the conductive layer A multilayer wire bonding capacitor comprising a surface electrode layer, wherein the capacitor electrode layer and the surface electrode layer are electrically connected via the interlayer conductive material.

The conductive layer is a multilayer wire bonding capacitor having two or more via holes.

The conductive layer is a multilayer wire bonding capacitor installed on a front surface side and a back surface side of the dielectric ceramic layer.

A multilayer wire bonding capacitor in which at least one dummy internal electrode layer is disposed between the capacitor electrode layer and the surface electrode layer.

The multilayer wire bonding capacitor has a thickness in the range of 100 μm to 300 μm.

According to the present invention, it is possible to obtain a large capacitance with a product thickness equivalent to that of a single-plate wire bonding capacitor.

Sectional drawing of the conventional single plate type wire bonding capacitor. Sectional drawing of the conventional multilayer wire bonding capacitor. 1 is a perspective view of a multilayer wire bonding capacitor according to the present invention. FIG. AA sectional drawing of FIG. 1 is an exploded perspective view of a multilayer wire bonding capacitor according to the present invention. Sectional drawing in the 1st process which showed the manufacturing process of this invention. Sectional drawing in the 2nd process which showed the manufacturing process of this invention. Sectional drawing in the 3rd process which showed the manufacturing process of this invention. Sectional drawing in the 4th process which showed the manufacturing process of this invention. Sectional drawing of other embodiment of this invention. Sectional drawing of other embodiment of this invention. Sectional drawing of other embodiment of this invention. The equivalent circuit of embodiment of FIG.

Embodiments of the present invention will be described in detail with reference to the drawings. 3 is an embodiment of the multilayer wire bonding capacitor according to the present invention, FIG. 4 is a sectional view thereof, and FIG. 5 is an exploded perspective view thereof. First, a dielectric ceramic layer 1 that is a layer for obtaining the capacitance of a product is prepared by a conventionally known method such as a doctor blade method, and a capacitor electrode layer 2 is formed on the surface of the dielectric ceramic layer 1. Screen printing is performed to obtain an electrode-printed green sheet as shown in FIG.

Next, the conductive layer 3 is prepared by a method similar to that for the dielectric ceramic layer 1, and the via hole 4 is formed in the conductive layer 3 by a method such as die punching or laser. Then, the conductive layer having the via hole 4 is laminated and pressure-bonded on the capacitor electrode layer 2 to obtain a laminated body as shown in FIG. Then, as shown in FIG. 8, the via hole 4 is filled with an interlayer conductive material 5 by screen filling by screen printing. Thereafter, the surface electrode layer 6 is screen-printed to obtain an intermediate laminate 7 shown in FIG. The via hole 4 needs to be disposed at a site where the capacitor electrode layer 2 and the surface electrode layer 6 can be electrically connected.

Then, the intermediate laminate 7 is turned upside down, and a capacitor electrode layer, a conductive layer having a via hole, an interlayer conductive material, and a surface electrode layer are installed on the opposite side of the dielectric ceramic layer 1 in the same manner. Then, a green body of the multilayer wire bonding capacitor is obtained.

Thereafter, firing, plating and the like are performed in the same manner as conventionally known multilayer capacitors to obtain the multilayer wire bonding capacitor 8.

Since the capacitance of the capacitor is inversely proportional to the distance between the electrodes, the capacitance of the thin multilayer wire bonding capacitor according to the present invention varies depending on the thickness of the dielectric ceramic layer 1. That is, the thinner the dielectric ceramic layer 1 and the smaller the distance between the capacitor electrodes, the higher the capacity of the laminated wire bonding capacitor. Therefore, the thinner the dielectric ceramic layer 1 is, the higher the capacity.

Further, since the capacitance of the capacitor is proportional to the electrode effective area, the larger the area of the capacitor electrode layer 2, the higher the capacity of the laminated wire bonding capacitor. However, increasing the area of the capacitor electrode layer means increasing the product size, so it is not desirable to increase the area of the capacitor electrode layer for the purpose of increasing the capacitance.

In the present invention, the conductive layer 3 is provided for the purpose of maintaining the mechanical strength in order to prevent the mechanical strength of the multilayer wire bonding capacitor 8 from being reduced when the dielectric ceramic layer 1 is thinned. . Accordingly, when the thickness of the dielectric ceramic layer 1 is set to, for example, 150 μm or more, a certain degree of mechanical strength can be obtained only by the dielectric ceramic layer 1, and thus the effect of employing the present invention is reduced.

A conventionally known single-plate wire bonding capacitor as shown in FIG. 1 maintains the mechanical strength of the product only by the thickness of the dielectric ceramic layer 1, whereas the product of the present invention is static. By separating the dielectric ceramic layer 1 for acquiring electric capacity and the conductive layer 3 for maintaining mechanical strength, the mechanical strength can be maintained while securing a high capacity. Therefore, by adjusting the thickness of the conductive layer 3, it is possible to adjust the thickness of the product to have a desired product strength while ensuring a high capacity. That is, even if the dielectric ceramic layer 1 is thinned to about 1 μm in order to obtain a high capacity, the strength of the product can be maintained by installing the conductive layer 3 about 150 μm.

In addition, the multilayer wire bonding capacitor according to the present invention preferably has a thickness of 100 μm to 300 μm. If the thickness is 100 μm or less, the product strength is reduced, which may cause damage in the manufacturing process and the mounting process. On the other hand, when the thickness is 300 μm or more, the multilayer wire bonding capacitor can obtain a higher capacity, and the effect of the present invention cannot be obtained.

The conductive layer 3 may be made of an insulating ceramic, but is fired at the same time as the dielectric ceramic layer 1. Therefore, a material having a shrinkage rate close to that of the dielectric ceramic layer 1 is used to avoid occurrence of defects such as cracks after firing. Although it is desirable to use it, it is most desirable to use the same material as the dielectric ceramic layer 1.

In addition, the capacitor electrode layer, surface electrode layer, interlayer conductive material layer, and dummy internal electrode layer used in the present invention are made of Ni, Cu, Ag, Pd, Pt, or an alloy thereof.

Next, another embodiment of the present invention will be described. If the dielectric ceramic layer 1 is thinned to, for example, 10 μm or less in order to obtain a high capacity, the thickness of the conductive layer 3 needs to be 100 μm or more in order to ensure the mechanical strength of the product. Since the conductive layer 3 must be provided with the via hole 4 and filled with the interlayer conductive material 5, it becomes difficult to reliably fill the via hole with no interlayer conductive material as the thickness of the conductive layer 3 increases.

FIG. 10 shows an embodiment in which the dielectric ceramic layer 1 is thinned. Two conductive layers 3 are provided above and below the dielectric ceramic layer 1, respectively, and a dummy internal layer is provided between the conductive layer and the conductive layer. The electrode layer 9 is formed by printing. In this way, it is possible to reduce the thickness of the conductive layer 3 per layer, and therefore it is possible to reliably fill the via hole with the interlayer conductive material without a gap. In addition, the provision of the dummy internal electrode layer 9 can suppress the occurrence of defects due to thermal stress during simultaneous firing. That is, there is a difference in shrinkage between electrode layers such as capacitor electrode layers, surface electrode layers, dummy internal electrode layers, and conductive layers and dielectric ceramic layers, and the difference in shrinkage rate increases as the thickness of the conductive layer increases. Since it appears more prominently and causes defects such as cracks, the occurrence of defects can be suppressed by reducing the thickness of the conductive layer 3 per layer. Two or more dummy internal electrode layers may be installed.

Next, another embodiment of the present invention will be described. As shown in FIG. 11, the conductive layer 3 and the surface electrode layer 6 can be provided only on one surface of the dielectric ceramic layer 1. This embodiment is an embodiment in which the number of manufacturing steps can be minimized, and it is desirable to implement when the thickness of the dielectric ceramic layer 1 can be taken to some extent. When the dielectric ceramic layer 1 is thinned, there is a high possibility that defects such as warpage and distortion occur due to thermal stress during simultaneous firing. In addition, cracks may occur due to thermal stress during soldering when mounting on a substrate. Therefore, the embodiment as shown in FIG. 11 is not suitable when the dielectric ceramic layer 1 is thin.

FIG. 12 shows still another embodiment. When two via holes are provided per conductive layer, the equivalent circuit is as shown in FIG. 13, and the series equivalent resistance 11 (ESR) and the series equivalent inductance 10 (ESL) are arranged in parallel. And ESL can be reduced to ½, respectively, and thus high frequency characteristics can be improved. Further, when the number of via holes installed is increased to 2 or more per conductive layer, ESR and ESL can be reduced in inverse proportion to the number of via holes installed. This embodiment is effective when the chip size is large because it is necessary to install two or more via holes.

As described above, the details of the present invention have been described with reference to examples. However, the present invention is shown only as specific embodiments of the present invention, and the effects of the invention are remarkably impaired based on the technical idea. It should be understood that a part of the embodiment can be modified and implemented without limit.

The present invention can be widely used in fields such as optical transceivers.

1; Dielectric ceramic layer 2; Capacitor electrode layer 3; Conductive layer 4; Via hole 5; Interlayer conductive material 6; Surface electrode layer 7; Intermediate laminate 8; Multilayer wire bonding capacitor 9; Dummy internal electrode layer 10 ;, series equivalent inductance (ESL)
11 ;, Series equivalent resistance (ESR)

Claims (5)

A dielectric ceramic layer, a capacitor electrode layer printed on the front and back surfaces of the dielectric ceramic layer, a conductive layer having a via hole, an interlayer conductive material filled in the via hole, and a conductive layer disposed on the conductive layer A multilayer wire bonding capacitor comprising a surface electrode layer, wherein the capacitor electrode layer and the surface electrode layer are electrically connected via the interlayer conductive material. The multilayer wire bonding capacitor according to claim 1, wherein the conductive layer has two or more via holes. The multilayer wire bonding capacitor according to claim 1, wherein the conductive layer is disposed on a front surface side and a back surface side of the dielectric ceramic layer. 4. The multilayer wire bonding capacitor according to claim 1, wherein at least one dummy internal electrode layer is disposed between the capacitor electrode layer and the surface electrode layer. The multilayer wire bonding capacitor according to claim 1, wherein the multilayer wire bonding capacitor has a thickness in a range of 100 μm to 300 μm.

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