JP2012248240A - Magnetic memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the lifetime of a magnetic resistance element.SOLUTION: The magnetic memory includes: a magnetic resistance element that has a recording layer the magnetization direction of which is variable, a reference layer the magnetization direction of which is invariable and a tunnel barrier layer sandwiched by the recording layer and the reference layer; and a writing circuit that writes a piece of data on the magnetic resistance element using a first and a second writing voltage for writing a first piece of data and a second piece of data on the magnetic resistance element. Before applying a first writing voltage V0, V1 to the magnetic resistance element, the writing circuit applies a dummy voltage DV1, DV0 which has a polarity opposite to the first writing voltage.

Description

  Embodiments described herein relate generally to a magnetic memory.

  A magnetic random access memory (MRAM) uses an MTJ (Magnetic Tunnel Junction) element using a magnetoresistive effect in which a resistance value changes depending on the direction of magnetization as a memory element. The MTJ element has a three-layer structure of a reference layer, a recording layer, and an insulating layer that is sandwiched between the reference layer and the recording layer and forms a tunnel barrier. The magnetization of the reference layer is fixed in one direction and does not reverse even when a write operation is performed. On the other hand, the magnetization of the recording layer is reversed by a torque externally applied by the writing operation.

  There is known an MRAM using a spin injection writing method in which writing is performed by directly passing a current through an MTJ element. When a write current is passed through the MTJ element, the resistance value of the MTJ element changes depending on the relative directions of the two magnetic layers. That is, the resistance value of the MTJ element is low when the magnetization directions of the recording layer and the reference layer are parallel, and high when it is antiparallel. By associating the low resistance state and high resistance state of the MTJ element with binary data, the MTJ element can be used as a memory element.

In the spin injection MRAM, a write current having a high current density of, for example, MA / cm ² order is applied to an insulating layer that forms a tunnel barrier at the time of writing. For this reason, if spin injection writing is repeated many times for one MTJ element, the tunnel barrier deteriorates, tunnel resistance may change, and eventually dielectric breakdown may occur. The reliability is not obtained.

JP 2007-310949 A

  Embodiments provide a magnetic memory capable of improving the lifetime of a magnetoresistive element.

  The magnetic memory according to the embodiment includes a magnetoresistive element having a recording layer in which the magnetization direction is variable, a reference layer in which the magnetization direction is unchanged, and a tunnel barrier layer sandwiched between the recording layer and the reference layer, And a write circuit for writing data to the magnetoresistive element using first and second write voltages for writing first and second data to the magnetoresistive element, respectively. The write circuit applies a dummy voltage having a polarity opposite to that of the first write voltage before applying the first write voltage to the magnetoresistive element.

1 is a block diagram showing a configuration of an MRAM according to a first embodiment. The circuit diagram of a memory cell array. Sectional drawing of an MTJ element. The schematic diagram explaining the magnetization state of an MTJ element. A Weibull distribution showing the dielectric breakdown lifetime of the MTJ element. The figure explaining the normal write-in voltage applied to an MTJ element. FIG. 6 is a diagram for explaining a write voltage applied to the MTJ element according to the first embodiment. The figure explaining the write voltage in the case of writing data "000" to an MTJ element. The figure explaining the write voltage in the case of writing data "111" to an MTJ element. The figure explaining the write voltage in the case of writing data "010" to an MTJ element. The figure explaining the write-in voltage applied to the MTJ element which concerns on 2nd Embodiment. The schematic diagram explaining the state of the tunnel barrier layer 21B when a write voltage is applied to the MTJ element.

  Hereinafter, embodiments will be described with reference to the drawings. However, it should be noted that the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as the actual ones. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
[1. Configuration of magnetic memory]
FIG. 1 is a block diagram showing a configuration of an MRAM (magnetic memory) 10 according to the first embodiment. The memory cell array 11 is configured by arranging memory cells including MTJ elements (magnetoresistance elements) in a matrix. The memory cell array 11 includes m word lines WL1 to WLm each extending in a first direction, and n bit line pairs BL1 each extending in a second direction intersecting the first direction. , / BL1 to BLn, / BLn. m and n are each an integer of 1 or more.

  A row decoder 12 is connected to the word lines WL1 to WLm. The row decoder 12 selects one of the m word lines WL based on the row address.

  A read circuit (sense amplifier) 15 and a write circuit (write driver) 16 are connected to the bit line pairs BL1, / BL1 to BLn, / BLn via a column selection circuit 13. The column selection circuit 13 includes, for example, a number of N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) corresponding to all the bit lines, and in accordance with instructions from the column decoder 14, bit line pairs BL, Select / BL. The column decoder 14 decodes the column address and sends this decode signal to the column selection circuit 13.

  The read circuit 15 applies a read voltage to the selected memory cell to be read. Then, the data stored in the selected memory cell is detected based on the read current flowing through the selected memory cell. Data read by the read circuit 15 is output to the outside via an input / output buffer (I / O buffer) 19.

  The write circuit 16 receives write data from the outside via the I / O buffer 19. The write circuit 16 applies a write voltage to the bit line pair BL, / BL connected to the selected memory cell to be written. Then, data is written to the selected memory cell by supplying a write current to the selected memory cell.

  The address buffer 17 receives an address from the outside. Then, the address buffer 17 sends the row address to the row decoder 12 and sends the column address to the column decoder 14. The control signal buffer 18 receives a control signal from the outside and sends this control signal to the read circuit 15 and the write circuit 16.

  FIG. 2 is a circuit diagram of the memory cell array 11. In FIG. 2, (2 × 2) memory cells MC are shown as an example. The memory cell MC includes one MTJ element 21 and one selection transistor 22. As the selection transistor 22, for example, an N-channel MOSFET is used. One end of the MTJ element 21 is connected to the bit line BL, and the other end of the MTJ element 21 is connected to one end of the current path of the selection transistor 22. The other end of the current path of the selection transistor 22 is connected to the bit line / BL. The gate of the selection transistor 22 is connected to the word line WL.

  FIG. 3 is a cross-sectional view of the MTJ element 21. The MTJ element 21 is configured by sequentially stacking a recording layer (also referred to as a storage layer or a free layer) 21A, a nonmagnetic layer (tunnel barrier layer) 21B, and a reference layer (also referred to as a fixed layer) 21C. Note that the stacking order may be reversed. Each of the recording layer 21A and the reference layer 21C is made of a ferromagnetic material. An insulating layer such as MgO is used as the tunnel barrier layer 21B.

  Each of the recording layer 21A and the reference layer 21C has magnetic anisotropy in a direction perpendicular to the film surface, and their easy magnetization direction is perpendicular to the film surface. Note that the magnetization directions of the recording layer 21A and the reference layer 21C may be parallel to the film surface.

  The recording layer 21A has a variable magnetization (or spin) direction (inverted). The reference layer 21C has an invariable magnetization direction (fixed). The reference layer 21C is set so as to have a sufficiently higher perpendicular magnetic anisotropy energy than the recording layer 21A. The magnetic anisotropy can be set by adjusting the material configuration and the film thickness. In this way, the magnetization reversal current of the recording layer 21A is reduced, and the magnetization reversal current of the reference layer 21C is made larger than that of the recording layer 21A. Thereby, it is possible to realize the MTJ element 21 including the recording layer 21A having a variable magnetization direction and the reference layer 21C having a constant magnetization direction with respect to a predetermined write current.

  FIG. 4 is a schematic diagram for explaining the magnetization state of the MTJ element 21. In the present embodiment, a spin injection writing method is adopted in which a write current is directly supplied to the MTJ element 21 and the magnetization state of the MTJ element 21 is controlled by this write current. The MTJ element 21 can take either a low resistance state or a high resistance state depending on whether the relative relationship of magnetization between the recording layer 21A and the reference layer 21C is parallel or antiparallel.

  As shown in FIG. 4A, when a write current from the recording layer 21A to the reference layer 21C is passed through the MTJ element 21, the relative relationship of magnetization between the recording layer 21A and the reference layer 21C becomes parallel. In the parallel state, the MTJ element 21 has the lowest resistance value, and the MTJ element 21 is set in the low resistance state. The low resistance state of the MTJ element 21 is defined as data “0”, for example. Such an operation is called 0 writing.

  On the other hand, as shown in FIG. 4B, when a write current from the reference layer 21C to the recording layer 21A is passed through the MTJ element 21, the relative relationship of magnetization between the recording layer 21A and the reference layer 21C is antiparallel. become. In the anti-parallel state, the MTJ element 21 has the highest resistance value, and the MTJ element 21 is set to the high resistance state. The high resistance state of the MTJ element 21 is defined as, for example, data “1”. Such an operation is called one writing.

  Thus, the MTJ element 21 can be used as a storage element capable of storing 1-bit data (binary data). The assignment of the resistance state and data of the MTJ element 21 can be arbitrarily set.

  When reading data from the MTJ element 21, the read circuit 15 applies a read voltage to the MTJ element 21 and detects the resistance value of the MTJ element 21 based on the read current flowing through the MTJ element 21 at this time. This read voltage is set to a value sufficiently smaller than the threshold value at which magnetization is reversed by spin injection.

[2. Writing method]
FIG. 5 is a Weibull distribution showing the dielectric breakdown lifetime of the MTJ element (specifically, the tunnel barrier layer) when a voltage pulse is applied to the MTJ element. The horizontal axis in FIG. 5 represents the dielectric breakdown lifetime (s), and the vertical axis in FIG. 5 represents ln (−ln (1-F (t))). “F (t)” represents the cumulative failure probability, and “ln” represents the natural logarithm. FIG. 5 shows (1) a dielectric breakdown life when a voltage pulse on one side, for example, a voltage pulse for 1 writing is applied, and (2) a voltage pulse on both sides, ie, a voltage pulse for 1 writing and a voltage pulse for 0 writing. The comparison shows the dielectric breakdown lifetime when voltage pulses are applied alternately. MTJ element used in the experiment of FIG. 5 is a vertical magnetization film having an L1 ₀ structure of Fe-based in the recording layer, a perpendicular magnetization film in the reference layer comprises a ferrimagnetic material, is used MgO tunnel barrier layer. The experiment was performed with the pulse width of the voltage pulse being about 30 ns and the pulse period being about 100 ns. The applied voltage was set to about 0.92V. The voltage pulse used in this experiment is for an acceleration test, and the conditions are made stricter than the voltage pulse used in the actual write operation.

  In FIG. 5, the time (T63) corresponding to the cumulative failure probability F (t) = 63% when the voltage pulse for one write is continuously applied is about 10 s, and the voltage pulse for one write and the zero write are written. When the voltage pulse for application is applied alternately, it is about 1000 s. From this numerical value, when voltage pulses having different polarities are alternately applied to the MTJ element, it is expected that the lifetime will be improved by about 100 times compared to the case where voltage pulses having the same polarity are continuously applied. From this result, the dielectric breakdown lifetime of the MTJ element can be improved by constructing a writing algorithm that does not continuously apply voltage pulses of the same polarity.

  FIG. 6 is a diagram for explaining a normal write voltage applied to the MTJ element. FIG. 6A is a diagram for explaining a voltage pulse for 0 writing, and FIG. 6B is a diagram for explaining a voltage pulse for 1 writing. In FIG. 6, the voltage pulse V0 for 0 writing is represented by a negative polarity, and the voltage pulse V1 for 1 writing is represented by a positive polarity. As shown in FIG. 6, in a normal write operation, a voltage pulse of a predetermined magnitude is applied to the MTJ element by one pulse. Note that the absolute value and pulse width of the voltage pulse V0 for 0 writing and the voltage pulse V1 for 1 writing need not be the same, and the 0 writing operation and the 1 writing operation can be optimally performed according to the characteristics of the MTJ element. Is set as appropriate.

  FIG. 7 is a diagram for explaining the write voltage of this embodiment applied to the MTJ element. FIG. 7A is a diagram for explaining the write voltage during the zero write operation, and FIG. 7B is a diagram for explaining the write voltage during the one write operation.

  As shown in FIG. 7A, in the zero write operation, the write circuit 16 applies a dummy voltage having a polarity opposite to that of the zero write voltage pulse V0 before applying the zero write voltage pulse V0 to the MTJ element. A pulse DV1 is applied to the MTJ element. The dummy voltage pulse DV1 is for preventing the voltage pulse having the same polarity from being continuously applied to the MTJ element, and the magnitude thereof is equal to or larger than the magnitude of the voltage pulse V1 for one writing. Set to a small voltage. Specifically, the magnitude of the dummy voltage pulse DV1 can be set in the range from about the same as the voltage pulse V1 for one writing to about half. Although there is a possibility that the magnetization state of the MTJ element is changed by the dummy voltage pulse DV1, there is no problem because the MTJ element is finally set to a low resistance state by the voltage pulse V0 for 0 writing.

  As shown in FIG. 7B, in one write operation, the write circuit 16 applies a dummy voltage having a polarity opposite to that of the one write voltage pulse V1 before applying the one write voltage pulse V1 to the MTJ element. A pulse DV0 is applied to the MTJ element. The dummy voltage pulse DV0 is for preventing the voltage pulse having the same polarity from being continuously applied to the MTJ element, and the magnitude thereof is equal to or larger than the magnitude of the voltage pulse V0 for 0 writing. Set to a small voltage. Specifically, the magnitude of the dummy voltage pulse DV0 can be set in a range from about the same as the voltage pulse V0 for 0 writing to about half. Although there is a possibility that the magnetization state of the MTJ element is changed by the dummy voltage pulse DV0, there is no problem because the MTJ element is finally set to the high resistance state by the voltage pulse V1 for one writing.

The following three write sequences A to C are conceivable as the write sequence according to the present embodiment.
(A) The 0 write operation is performed in FIG. 7A and the 1 write operation is performed in FIG. 7B. (B) The 0 write operation is performed in FIG. 7A and the 1 write operation is performed in FIG. (C) The 0 write operation is performed in FIG. 6A, and the 1 write operation is performed in FIG. 7B. For the MTJ element, whether the upper side is the reference layer or the recording layer, the material and the film formation process conditions Depending on the difference, there are a case where the dielectric breakdown lifetime of the tunnel barrier layer by one write is short and a case where the dielectric breakdown lifetime of the tunnel barrier layer by zero write is short. When the dielectric breakdown lifetime of the tunnel barrier layer by one writing is shorter than that by zero writing, the writing sequence avoids the continuous application of voltage pulses having the same polarity as the voltage pulse V1 for at least one writing. Therefore, it is preferable to adopt the writing condition (A) or (C). On the other hand, when the dielectric breakdown lifetime of the tunnel barrier layer by 0 writing is shorter than that by 1 writing, the write sequence avoids the continuous application of voltage pulses having at least the same polarity as the voltage pulse V0 for 0 writing. Since it is preferable, it is preferable to adopt the write condition (A) or (B).

  Spin injection writing generally requires a larger current for one writing than for zero writing, so that a larger current value is set for one writing than for zero writing. Therefore, if the dielectric breakdown lifetime of the tunnel barrier layer is the same for both 1 writing and 0 writing for the same current value, the dielectric breakdown lifetime of the tunnel barrier layer is 0 writing for 1 writing in actual use. It is considered to be shorter. In this case, by adopting the write condition (C), the dielectric breakdown life of one write on the weak side can be improved.

  Next, an operation for continuously writing data to the MTJ element will be described. FIG. 8 is a diagram for explaining the write voltage in the operation of writing data “000” to the MTJ element. When data “000”, that is, data “0” is written in the MTJ element three times in succession, normally, as shown in FIG. 8A, a voltage pulse V0 for 0 writing is continuously applied. On the other hand, when the zero write operation of the present embodiment is adopted, as shown in FIG. 8B, voltage pulses having different polarities of the dummy voltage pulse DV1 and the zero write voltage pulse V0 are alternately applied to the MTJ element. Therefore, it is possible to prevent the voltage pulse V0 for 0 writing from being continuously applied to the MTJ element.

  FIG. 9 is a diagram for explaining the write voltage in the operation of writing data “111” to the MTJ element. When data “111”, that is, data “1” is written in the MTJ element three times in succession, normally, one write voltage pulse V1 is continuously applied as shown in FIG. On the other hand, when the one write operation of the present embodiment is adopted, as shown in FIG. 9B, voltage pulses having different polarities such as a dummy voltage pulse DV0 and a voltage pulse V1 for one write are alternately applied to the MTJ element. Thus, it is possible to prevent the voltage pulse V1 for one writing from being continuously applied to the MTJ element.

  FIG. 10 is a diagram illustrating a write voltage in an operation of writing data “010” to the MTJ element. When data “010”, that is, data “0” and data “1” are alternately written to the MTJ element, normally, as shown in FIG. 10A, a voltage pulse V0 for writing 0 and a voltage for writing 1 Pulses V1 are alternately applied to the MTJ element. On the other hand, when the 0 write operation and the 1 write operation of this embodiment are adopted, as shown in FIG. 10B, voltage pulses having the same polarity are applied to the MTJ element twice.

  As can be understood from FIGS. 8 to 10, when the write operation of the present embodiment shown in FIG. 7 is adopted, the number of times that the voltage pulse of the same polarity is continuously applied to the MTJ element is two times, It is possible to prevent voltage pulses having the same polarity from being applied to the MTJ element continuously.

  Note that the write operation of this embodiment is controlled by the write circuit 16 shown in FIG. When the voltage pulse V0 for writing 0 is applied to the MTJ element, the voltage pulse V0 is applied to the bit line / BL while the ground voltage VSS is applied to the bit line BL. In addition, when the voltage pulse V1 for one writing is applied to the MTJ element, the voltage pulse V1 is applied to the bit line BL while the ground voltage VSS is applied to the bit line / BL. The same applies to the dummy voltage pulses DV0 and DV1.

[3. effect]
As described above in detail, in the first embodiment, the MRAM 10 includes the write circuit 16 that executes the 0 write operation for writing data “0” to the MTJ element and the 1 write operation for writing data “1” to the MTJ element. I have. In the zero write operation, the write circuit 16 applies a dummy voltage pulse DV1 having a polarity opposite to that of the zero write voltage pulse V0 to the MTJ element before applying the zero write voltage pulse V0 to the MTJ element. . In one write operation, the write circuit 16 applies a dummy voltage pulse DV0 having a polarity opposite to that of the one write voltage pulse V1 to the MTJ element before applying the one write voltage pulse V1 to the MTJ element. .

  Therefore, according to the first embodiment, it is possible to prevent the write voltage having the same polarity from being applied to the MTJ element continuously several times. As a result, deterioration of the tunnel barrier layer can be suppressed, so that the dielectric breakdown lifetime of the MTJ element can be improved. As a result, the MRAM 10 having high reliability as a memory can be realized.

  Note that the resistance value (for example, the resistance value when data “0” is stored) of the MTJ element may fluctuate as the number of times of writing increases. Specifically, the resistance value of the MTJ element decreases as the number of times of writing increases. The data stored in the MTJ element is read by causing the read circuit 15 to pass a read current sufficiently smaller than the write current to the MTJ element and detecting the resistance value of the MTJ element at this time. Therefore, if the resistance value of the MTJ element falls below a specified value, the data stored in the MTJ element cannot be read accurately in terms of circuit design. In order to avoid such a malfunction of the read operation, a lower limit value when the resistance value of the MTJ element fluctuates is defined, and the time when the resistance value of the MTJ element falls below the lower limit value is defined as the resistance fluctuation life of the MTJ element. The dielectric breakdown life of the MTJ element may be replaced with the resistance fluctuation life of the MTJ element. That is, even if the dielectric breakdown lifetime is replaced with the resistance variation lifetime, the present embodiment is similarly established.

[Second Embodiment]
In the second embodiment, in the zero write operation, after the zero write voltage pulse V0 is applied to the MTJ element, the dummy voltage pulse DV1 having the opposite polarity to the zero write voltage pulse V0 is applied to the MTJ element. In one write operation, after a voltage pulse V1 for one write is applied to the MTJ element, a dummy voltage pulse DV0 having a polarity opposite to that of the voltage pulse V1 for one write is applied to the MTJ element. This prevents the write voltage having the same polarity from being continuously applied to the MTJ element many times.

  FIG. 11 is a diagram for explaining the write voltage applied to the MTJ element according to the second embodiment. FIG. 11A is a diagram for explaining a write voltage for 0 write, and FIG. 11B is a diagram for explaining a write voltage for 1 write.

  As shown in FIG. 11A, in the zero write operation, the write circuit 16 applies a zero write voltage pulse V0 to the MTJ element and then has a dummy voltage pulse having a polarity opposite to that of the zero write voltage pulse V0. DV1 is applied to the MTJ element. The magnitude of the dummy voltage pulse DV1 is set smaller than the magnitude of the voltage pulse V1 for 1 writing. Specifically, the magnitude of the dummy voltage pulse DV1 is the probability that the magnetization arrangement of the MTJ element is reversed from the parallel state to the antiparallel state so that the magnetization of the recording layer is not reversed by the dummy voltage pulse DV1. Is set to be sufficiently small. For example, when reading is performed by applying a read voltage in one write direction to the MTJ element, the dummy voltage pulse is set to about the read voltage.

  As shown in FIG. 11B, in one write operation, the write circuit 16 applies a voltage pulse V1 for one write to the MTJ element and then a dummy voltage pulse having a polarity opposite to that of the voltage pulse V1 for one write. DV0 is applied to the MTJ element. The magnitude of the dummy voltage pulse DV0 is set smaller than the magnitude of the voltage pulse V0 for 0 writing. Specifically, the magnitude of the dummy voltage pulse DV0 is the probability that the magnetization arrangement of the MTJ element is reversed from the antiparallel state to the parallel state so that the magnetization of the recording layer is not reversed by the dummy voltage pulse DV0. Is set to be sufficiently small. For example, when reading is performed by applying a read voltage in the zero write direction to the MTJ element, the dummy voltage pulse is set to about the read voltage.

  In the present embodiment, since the magnitude of the dummy voltage pulse DV1 is set smaller than the magnitude of the voltage pulse V1 for one write, the current flowing through the MTJ element by the dummy voltage pulse DV1 is the voltage pulse for one write. It becomes smaller than the electric current which flows into an MTJ element by V1. Therefore, the pulse width of the dummy voltage pulse DV1 is preferably larger than the pulse width of the voltage pulse V1 for one writing. As a result, the integrated current flowing through the MTJ element by the dummy voltage pulse DV1 can be set to the same level as the integrated current flowing through the MTJ element by the voltage pulse V1 for 1 writing. As a result, when the dummy voltage pulse DV1 is applied to the MTJ element, the load applied to the MTJ element is almost the same when the one-write voltage pulse V1 is applied to the MTJ element. It is expected that the lifetime or resistance variation lifetime will be further improved. Similarly, the pulse width of the dummy voltage pulse DV0 is preferably larger than the pulse width of the voltage pulse V0 for 0 writing. Such a method for setting the pulse width of the dummy voltage pulse can also be applied to the first embodiment.

  As described above in detail, according to the second embodiment, it is possible to prevent a write voltage having the same polarity from being continuously applied to the MTJ element many times. As a result, deterioration of the tunnel barrier layer can be suppressed, so that the dielectric breakdown lifetime of the MTJ element can be improved. As a result, the MRAM 10 having high reliability as a memory can be realized.

  As in the first embodiment, the dummy voltage pulse may be applied only to the write operation in which the dielectric breakdown life or resistance variation life of the MTJ element is short among the 0 write operation and the 1 write operation.

  The reason why the dielectric breakdown life or resistance variation life of the MTJ element is improved by alternate writing will be considered below. FIG. 12 is a schematic diagram for explaining the state of the tunnel barrier layer 21 </ b> B when a write voltage is applied to the MTJ element 21.

  FIG. 12A shows an initial state of the MTJ element 21, that is, a state where no write operation is performed. A plurality of lattice defects (including oxygen vacancies) are formed on the side of the tunnel barrier layer 21B close to the reference layer 21C.

  FIG. 12B shows a state of lattice defects when, for example, a write operation in which the reference layer 21C is grounded and a positive write voltage is applied to the recording layer 21A, that is, a one-side write operation is continuously performed on the MTJ element 21. ing. The lattice defects in the tunnel barrier layer 21B are moved by the electric field applied thereto. For this reason, in one-side writing, an electric field in one direction is continuously applied to the tunnel barrier layer 21B, so that the lattice defect moves to the recording layer 21A side. At this time, the probability that a leak path passing through the lattice defect occurs in the tunnel barrier layer 21B increases. It is considered that due to this leak path, the dielectric breakdown of the MTJ element 21 proceeds or the resistance fluctuation of the MTJ element increases.

  FIG. 12C shows a state of lattice defects when a write operation in which voltage pulses having different polarities are alternately applied to the MTJ element 21, that is, an alternate write operation is continuously performed on the MTJ element 21. In alternate writing, the moving direction of the lattice defect changes for each pulse, so the state of the lattice defect does not change much from the initial state of FIG. 12A, and the probability of occurrence of a leak path decreases. For this reason, it is considered that the dielectric breakdown life or resistance variation life of the MTJ element 21 is improved.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... MRAM, 11 ... Memory cell array, 12 ... Row decoder, 13 ... Column selection circuit, 14 ... Column decoder, 15 ... Read circuit, 16 ... Write circuit, 17 ... Address buffer, 18 ... Control signal buffer, 19 ... Input / output Buffer, 21 ... MTJ element, 21A ... recording layer, 21B ... tunnel barrier layer, 21C ... reference layer, 22 ... select transistor.

Claims (5)

A magnetoresistive element having a recording layer in which the magnetization direction is variable, a reference layer in which the magnetization direction is unchanged, and a tunnel barrier layer sandwiched between the recording layer and the reference layer;
A write circuit for writing data to the magnetoresistive element using first and second write voltages for writing first and second data to the magnetoresistive element, respectively;
Comprising
2. The magnetic memory according to claim 1, wherein the write circuit applies a dummy voltage having a polarity opposite to that of the first write voltage before applying the first write voltage to the magnetoresistive element.   The magnetic memory according to claim 1, wherein the dummy voltage is equal to or lower than the second write voltage. A magnetoresistive element having a recording layer in which the magnetization direction is variable, a reference layer in which the magnetization direction is unchanged, and a tunnel barrier layer sandwiched between the recording layer and the reference layer;
A write circuit for writing data to the magnetoresistive element using first and second write voltages for writing first and second data to the magnetoresistive element, respectively;
Comprising
The magnetic memory according to claim 1, wherein the write circuit applies a dummy voltage having a polarity opposite to the first write voltage after applying the first write voltage to the magnetoresistive element.   4. The magnetic memory according to claim 3, wherein the dummy voltage is smaller than the second write voltage.   The first write operation using the first write voltage has a shorter dielectric breakdown lifetime or resistance variation life of the magnetoresistive element than the second write operation using the second write voltage. The magnetic memory according to claim 1, wherein the magnetic memory is a magnetic memory.

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