JP2012244593A - A/d conversion device, a/d conversion method and solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D conversion device which helps to reduce power consumption without sacrificing output resolution, as well as an A/D conversion method and a solid state image pickup device.SOLUTION: The A/D conversion device comprises: a pulse delay circuit having n pieces of delay elements (n=positive integer equal to or greater than 2) connected in circular ring form for delaying a pulse signal according to an analog input signal, which propagates the pulse signal from first time of day to a second time of day; a counter circuit which counts the number of turns from the first time of day to a third time of day which is shorter than the second time of day; a high-order bit latch circuit which outputs the number of turns till the third time of day as a high-order bit latched value; a low-order bit latch circuit which outputs the position of the third time of day as a first low-order bit latched value and the position of the second time of day as a second low-order bit latched value; and a digital arithmetic circuit which generates a digital output value corresponding to the magnitude of the analog input signal on the basis of a high-order bit estimated value of the number of turns from the first time of day to the second time of day and the second low-order bit latched value.

Description

  The present invention relates to an A / D conversion device, an A / D conversion method, and a solid-state imaging device.

  In recent years, CMOS (Complementary Metal Oxide Semiconductor) image sensors have attracted attention and have been put to practical use as solid-state imaging devices. This CMOS image sensor can be manufactured using a general semiconductor manufacturing process, whereas a CCD (Charge Coupled Device) image sensor is manufactured by a dedicated manufacturing process. For this reason, for example, a multifunctional CMOS image sensor can be realized by incorporating various functional circuits in the sensor, such as SOC (System On Chip).

  In recent years, a solid-state imaging device incorporating an analog / digital converter (hereinafter referred to as “A / D conversion circuit”) is used as a solid-state imaging device mounted on a digital camera, a digital video camera, an endoscope, or the like. Examples are increasing. In an A / D conversion circuit built in such a solid-state imaging device, a pulse delay type A / D conversion circuit (see Patent Document 1) in which all of the circuit is realized by a digital circuit may be used. In the following description, an A / D conversion circuit indicates a pulse delay type A / D conversion circuit.

  FIG. 7 is a block diagram showing a schematic configuration of a conventional A / D conversion circuit. The conventional A / D conversion circuit 400 shown in FIG. 7 includes a pulse delay circuit 401, a buffer 2, a clock generation circuit 402, and a pulse position digitizing circuit 403.

  In the pulse delay circuit 401, a plurality of delay elements are connected in an annular shape. In FIG. 7, the delay element 1a at the first stage is a logic gate having two input terminals such as a NAND gate (NAND circuit), and the delay element 1b at the other stage is a logic NOT gate (NOT circuit). The case where it is comprised by the logic gate which has one input terminal like this is shown. In the following description, when the delay element 1a and the delay element 1b are not distinguished, they are simply referred to as “delay element 1”.

  The pulse signal Pin and the output signal of the last-stage delay element 1b are input to the first-stage delay element 1a. Further, the output signal of the preceding delay element 1 is input to each delay element 1b after the next stage. When the pulse signal Pin is input to the delay element 1a at the first stage, traveling in the pulse delay circuit 401 is started. At this time, each delay element 1 propagates (runs) the input pulse signal Pin with a propagation delay time corresponding to the magnitude of the drive voltage applied via the buffer 2. Each delay element 1 has a voltage characteristic that delays the input signal (pulse signal Pin) longer as the drive voltage (analog input signal Vin) applied through the buffer 2 is lower. The output signal output from each delay element 1 is output to the pulse position digitizing circuit 403 as the traveling position of the pulse signal Pin traveling within the pulse delay circuit 401.

  The clock generation circuit 402 generates a pulse signal Pin and a sampling clock CK whose sampling period is Ts, and outputs the pulse signal Pin to the pulse delay circuit 401 and the sampling clock CK to the pulse position digitization circuit 403, respectively.

The pulse position digitizing circuit 403 includes a latch & encoder circuit 4031, a counter 4032, a latch circuit 4033, and a subtraction circuit 4034.
The latch & encoder circuit 4031 detects the traveling position of the pulse signal Pin traveling in the pulse delay circuit 401 in synchronization with the edge of the sampling clock CK input from the clock generation circuit 402. The latch & encoder circuit 4031 converts (encodes) the detected traveling position of the pulse signal Pin into a numerical value of b bits (b is a positive integer) and outputs the converted value to the subtracting circuit 4034.

The counter 4032 acquires the number of times that the pulse signal Pin has circulated in the annular pulse delay circuit 401 within the sampling period Ts. Further, the counter 4032 outputs the acquired number of turns to the latch circuit 4033 as a count value of a bits (a is a positive integer).
The latch circuit 4033 latches the count value output from the counter 4032 in synchronization with the edge of the sampling clock CK input from the clock generation circuit 402 and outputs it to the subtraction circuit 4034.

  The subtraction circuit 4034 takes in a combined digital output value ab in which the output signal from the latch circuit 4033 is the upper bit output value a and the output signal from the latch & encoder circuit 4031 is the lower bit output value b. Then, a subtraction process is performed to subtract the synthesized digital output value ab obtained by the previous sampling from the synthesized digital output value ab obtained by the latest (current) sampling, and represents the number of delay elements 1 to which the pulse signal Pin has propagated within the sampling period Ts. A digital output value DT is calculated. In this way, the conventional A / D conversion circuit 400 shown in FIG. 7 can convert the analog input signal Vin into the digital output value DT, that is, A / D conversion.

Japanese Patent No. 3064644

  Whenever the pulse signal Pin circulates in the pulse delay circuit 401, the counter 4032 provided in the pulse position digitizing circuit 403 counts the number of laps and consumes power. For this reason, the counter 4032 continuously consumes power during the sampling period Ts, and the power consumption of the counter 4032 greatly affects the power consumption of the entire A / D conversion circuit 400.

  Therefore, a method for reducing the power consumption of the A / D conversion circuit 400 by reducing the power consumption of the counter 4032 by shortening the sampling period Ts by utilizing the relationship that the power consumption of the counter 4032 is proportional to the sampling period Ts. Can be considered. However, the A / D conversion circuit 400 has a property that the resolution of the digital output value DT to be output increases as the sampling period Ts increases. Therefore, if the sampling period Ts is shortened, the power consumption of the counter 4032 can be reduced, but the resolution of the digital output value DT output from the A / D conversion circuit 400 is lowered.

  The present invention has been made based on the above problem recognition, and provides an A / D conversion device, an A / D conversion method, and a solid-state imaging device capable of reducing power consumption without sacrificing output resolution. It is intended to provide.

  In order to solve the above problem, the A / D converter according to the present invention delays a pulse signal in accordance with the magnitude of an analog input signal and propagates n (n: positive integer, n ≧ 2) delays And the n delay elements are connected in a ring shape, and the pulse signal input to any one of the n delay elements at a first time is at least a second time. From the first time to a third time shorter than the second time, based on the pulse delay circuit that sequentially propagates to and the output signal of any one delay element in the pulse delay circuit, A counter circuit that counts the number of times that the pulse signal has circulated in the pulse delay circuit, and the counter circuit acquires the number of times counted until the third time, and the acquired number of times is an upper bit latch value. Output as A position bit latch circuit and a position of the pulse signal propagating in the pulse delay circuit at the third time based on an output signal of each delay element in the pulse delay circuit, The acquired position is output as a first lower bit latch value, the position of the pulse signal propagating through the pulse delay circuit at the second time is acquired, and the acquired position is set as a second lower bit. A lower bit latch circuit that outputs as a latch value, the number of the delay elements in the pulse delay circuit, the upper bit latch value, the first lower bit latch value, and the second lower bit latch value, Based on the first time to the second time, an upper bit estimated value that estimates the number of times the pulse signal circulated in the pulse delay circuit is calculated, A bit estimate value, based on said second lower bit latch value, characterized in that it comprises a digital arithmetic circuit which generates a digital output value corresponding to the magnitude of the analog input signal.

  In the digital arithmetic circuit of the present invention, the pulse signal propagates in the pulse delay circuit by the third time based on the upper bit latch value and the first lower bit latch value. A first count value that is the number of delay elements is calculated, and the pulse signal passes through the pulse delay circuit by integration of the calculated first count value and a predetermined coefficient that is greater than 1 and less than n. A second count value that is an estimate of the number of delay elements propagated up to a second time is calculated, the calculated second count value, the number of delay elements in the pulse delay circuit, The upper bit estimated value is calculated based on the second lower bit latch value, and the digital output value is generated based on the calculated upper bit estimated value and the second lower bit latch value Special To.

  The digital arithmetic circuit of the present invention calculates a maximum value and a minimum value of the first count value, and calculates the calculated maximum value and minimum value of the first count value and the predetermined coefficient, respectively. The maximum value and the minimum value of the second count value are calculated by integration, the maximum value and the minimum value of the calculated second count value, the number of the delay elements in the pulse delay circuit, The upper bit estimated value is determined based on a second lower bit latch value, and the digital output value is generated based on the determined upper bit estimated value and the second lower bit latch value. It is characterized by that.

  In the digital arithmetic circuit of the present invention, the quotient obtained by dividing the maximum value and the minimum value of the calculated second count value by the number of the delay elements in the pulse delay circuit, respectively, And the remainder when the maximum value and the minimum value of the calculated second count value are divided by the number of the delay elements in the pulse delay circuit, respectively. Based on the second lower bit latch value and the minimum value of the position or the maximum value of the position, the upper bit estimated value is set to the maximum value of the number of laps or the minimum value of the number of laps. It is determined that either one of them is determined.

  In the digital arithmetic circuit of the present invention, when the second lower bit latch value is not less than the minimum value of the position or not less than the maximum value of the position, the minimum value of the number of laps is set to the upper bit. When the second lower bit latch value is smaller than the minimum value of the position or smaller than the maximum value of the position, the maximum value of the number of laps is set as the upper bit estimated value. It is characterized by determining.

  Further, the maximum value of the error when the low-order bit latch circuit of the present invention acquires the position of the pulse signal propagating in the pulse delay circuit is represented by the number of the delay elements in the pulse delay circuit. The error Δm is larger than 0 and smaller than (n−1) / 2, and the predetermined coefficient is smaller than n / (2 · Δm + 1).

  The A / D conversion method of the present invention includes n (n: positive integer, n ≧ 2) delay elements that propagate the pulse signal by delaying according to the magnitude of the analog input signal, n delay elements are connected in an annular shape, and the pulse signal input to any one of the n delay elements is sequentially transmitted to a pulse delay circuit that sequentially propagates the pulse signal at a first time. And a pulse propagation step for sequentially propagating the pulse signal until at least a second time, and an output signal of any one delay element in the pulse delay circuit, the pulse signal in the pulse delay circuit A counting circuit that counts the number of laps of the pulse signal from the first time to a third time shorter than the second time; The upper bit latch circuit that obtains the number of laps counted by the counter circuit and outputs the obtained number of laps as an upper bit latch value causes the counter circuit to obtain the number of laps counted until the third time. Based on an upper bit latch step to be output as an upper bit latch value and an output signal of each delay element in the pulse delay circuit, the position of the pulse signal propagating in the pulse delay circuit is acquired, A lower bit latch circuit that outputs the obtained position as a lower bit latch value causes the position of the pulse signal propagating in the pulse delay circuit to be obtained at the third time, thereby obtaining a first lower bit latch value. And the position of the pulse signal propagating through the pulse delay circuit at the second time is acquired to obtain the second lower order video. A lower bit latch step to be output as a latch value, the number of the delay elements in the pulse delay circuit, the upper bit latch value, the first lower bit latch value, and the second lower bit latch value, From the first time to the second time, an upper bit estimated value obtained by estimating the number of times that the pulse signal circulated in the pulse delay circuit is calculated, and the calculated upper bit estimated value And a digital operation step of generating a digital output value corresponding to the magnitude of the analog input signal based on the second lower bit latch value.

  In addition, the solid-state imaging device of the present invention has a pixel portion in which a plurality of pixels that output photoelectric conversion signals corresponding to the amount of incident light are arranged in a two-dimensional matrix, and a pulse signal according to the magnitude of the analog input signal. There are n (n: positive integer, n ≧ 2) delay elements that propagate with delay, the n delay elements are connected in a ring shape, and the n delay elements are connected at a first time. Based on a pulse delay circuit that sequentially propagates the pulse signal input to any one delay element until at least a second time, and an output signal of any one delay element in the pulse delay circuit, the first A counter circuit that counts the number of times the pulse signal has circulated in the pulse delay circuit from a time 1 to a third time shorter than the second time, and the counter circuit includes the third time The lap counted up to A high-order bit latch circuit that obtains a number and outputs the obtained number of laps as a high-order bit latch value, and the pulse at the third time based on an output signal of each delay element in the pulse delay circuit The position of the pulse signal propagating in the delay circuit is acquired, the acquired position is output as a first lower bit latch value, and the pulse delay circuit is propagating in the second time A lower bit latch circuit that obtains a position of a pulse signal and outputs the obtained position as a second lower bit latch value; the number of the delay elements in the pulse delay circuit; the upper bit latch value; Based on the first lower bit latch value and the second lower bit latch value, the pulse signal is generated in the pulse delay circuit from the first time to the second time. An upper bit estimated value obtained by estimating the number of laps is calculated, and a digital output value corresponding to the magnitude of the analog input signal is calculated based on the calculated upper bit estimated value and the second lower bit latch value. A column A / D conversion circuit in which a plurality of A / D conversion devices each including an A / D conversion circuit corresponding to each column of the pixel portion are arranged, and the column A / D conversion A clock generation circuit that outputs a clock signal representing the first time, the second time, and the third time to each of the A / D conversion circuits included in the circuit, and the column A The / D conversion circuit uses each of the photoelectric conversion signals output from the pixels in each column of the pixel unit as an analog input signal of the corresponding A / D conversion circuit, and the clock generation circuit The digital signal generated by each of the A / D conversion circuits is output as an output signal from the column A / D conversion circuit according to the input clock signal.

  According to the present invention, it is possible to reduce the power consumption without sacrificing the output resolution of the digital output value output from the A / D converter.

1 is a block diagram showing a schematic configuration of an A / D conversion circuit according to a first embodiment of the present invention. The relationship between the sampling time and the digital output value in the A / D conversion circuit of the first embodiment, and the timing of each clock signal in the analog / digital conversion operation by the A / D conversion circuit of the first embodiment are shown. It is a timing chart. It is the figure which showed the relationship between the analog input signal and digital output value in the A / D conversion circuit of the 1st embodiment. It is the flowchart which showed the process sequence of the digital arithmetic circuit in the A / D conversion circuit of the 1st embodiment. It is the figure which showed typically the structure of the delay element in the pulse delay circuit of an A / D conversion circuit, and the relationship of the travel position of a pulse signal. 1 is a block diagram showing a schematic configuration of a solid-state imaging device of a column A / D conversion circuit system in which a plurality of A / D conversion circuits of the present invention are mounted for each column. It is the block diagram which showed schematic structure of the conventional A / D conversion circuit.

<First Embodiment>
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an A / D conversion circuit according to the first embodiment. The A / D conversion circuit 100 illustrated in FIG. 1 includes a pulse delay circuit 101, a buffer 2, a clock generation circuit 102, and a pulse position digitizing circuit 103. In the following description, a sampling period for converting the analog input signal Vin input to the A / D conversion circuit 100 into the digital output value Dout is “Ts”.

  The pulse delay circuit 101 is an annular delay circuit in which n (n: positive integer, n ≧ 2) delay elements are connected in an annular shape. In FIG. 1, a delay element 1a at the first stage is a logic gate having two input terminals such as a NAND gate (NAND circuit), and a delay element 1b at the other stage is a logic NOT gate (NOT circuit). The case where it is comprised by the logic gate which has one input terminal like this is shown. In the following description, when the delay element 1a and the delay element 1b are not distinguished, they are simply referred to as “delay elements 1”, the number of delay elements 1 in the pulse delay circuit 101 is “n”, and “ The number of delay elements is n ”.

  The pulse signal Pin and the output signal of the last-stage delay element 1b are input to the first-stage delay element 1a. Further, the output signal of the preceding delay element 1 is input to each delay element 1b after the next stage. When the pulse signal Pin is input to the delay element 1a at the first stage, traveling in the pulse delay circuit 101 is started. At this time, each delay element 1 propagates (runs) the input pulse signal Pin with a propagation delay time corresponding to the magnitude of the drive voltage applied via the buffer 2. Each delay element 1 has a voltage characteristic that delays the input signal (pulse signal Pin) longer as the drive voltage (analog input signal Vin) applied through the buffer 2 is lower. The output signal output from each delay element 1 is output to the pulse position digitizing circuit 103 as the traveling position of the pulse signal Pin traveling within the pulse delay circuit 101.

  The clock generation circuit 102 generates a pulse signal Pin and outputs it to the pulse delay circuit 101. Further, the clock generation circuit 102 sets an arbitrary coefficient k that satisfies 1 <k <n (k is a rational number), and based on the set coefficient k, the lower bit latch clock CKL, the upper bit latch clock CKM, and A counter clock CKC is generated. The clock generation circuit 102 outputs the generated lower bit latch clock CKL, upper bit latch clock CKM, counter clock CKC, and the set coefficient k to the pulse position digitizing circuit 103. A detailed description of the coefficient k set by the clock generation circuit 102 and the lower bit latch clock CKL, the upper bit latch clock CKM, and the counter clock CKC generated based on the coefficient k will be described later.

  In the pulse position digitizing circuit 103, the pulse signal Pin passes within the sampling period Ts in synchronization with the edges of the lower bit latch clock CKL, the upper bit latch clock CKM, and the counter clock CKC input from the clock generation circuit 102. The number of delay elements 1 in the pulse delay circuit 101 is detected. Further, the pulse position digitizing circuit 103 calculates and outputs a digital output value Dout that is a result of A / D conversion based on the detected number of delay elements 1 and the coefficient k input from the clock generation circuit 102. To do. The pulse position digitizing circuit 103 includes a lower bit latch & encoder circuit 1031, a counter 1032, an upper bit latch circuit 1033, and a digital arithmetic circuit 1034.

  The lower bit latch & encoder circuit 1031 detects the traveling position of the pulse signal Pin traveling in the pulse delay circuit 101 in synchronization with the rising edge of the lower bit latch clock CKL input from the clock generation circuit 102. More specifically, the lower bit latch & encoder circuit 1031 detects the travel position of the pulse signal Pin at the timing of sampling time Ts / k and sampling time Ts, which will be described later. Then, the lower bit latch & encoder circuit 1031 converts (encodes) the detected traveling position of the pulse signal Pin into a numerical value of b bits (b is a positive integer) and outputs it to the digital arithmetic circuit 1034.

  In the following description, the output signal from the lower bit latch & encoder circuit 1031 is simply referred to as “travel position” or “lower bit output value”. In the following description, the traveling position of the pulse signal Pin detected at the sampling time Ts / k is “m1” (m1 is an integer satisfying 0 ≦ m1 ≦ n−1), and the sampling time Ts. The travel position of the detected pulse signal Pin is “m2” (m2 is an integer satisfying 0 ≦ m2 ≦ n−1).

  The counter 1032 starts driving in synchronization with the rising edge of the counter clock CKC input from the clock generation circuit 102, and stops driving in synchronization with the falling edge of the counter clock CKC. That is, the driving of the counter 1032 is controlled by the counter clock CKC input from the clock generation circuit 102. For example, when the counter clock CKC rises at the sampling time 0 and the counter clock CKC falls at the sampling time Ts / k, the driving period of the counter 1032 is a period from the sampling time 0 to the sampling time Ts / k, that is, The period becomes 1 / k of the sampling period Ts.

  Further, the counter 1032 acquires the number of times that the pulse signal Pin has circulated in the annular pulse delay circuit 101 within the drive period, in the above-described case, the sampling period Ts / k. The counter 1032 outputs the acquired number of turns to the upper bit latch circuit 1033 as a count value of a bits (a is a positive integer).

  The upper bit latch circuit 1033 synchronizes with the rising edge of the upper bit latch clock CKM input from the clock generation circuit 102, that is, the count value output from the counter 1032, that is, the sampling period Ts / The number of turns of the pulse signal Pin that circulates the pulse delay circuit 101 within the period k is latched and output to the digital arithmetic circuit 1034.

  In the following description, the output value from the upper bit latch circuit 1033 is simply referred to as “number of rounds” or “upper bit output value”. In the following description, the number of turns in the sampling period Ts / k is “r1” (r1 is an integer of 0 or more).

  The digital arithmetic circuit 1034 includes a traveling position m1 and a traveling position m2 of the pulse signal Pin output from the lower bit latch & encoder circuit 1031; a number of turns r1 of the pulse signal Pin output from the upper bit latch circuit 1033; and a pulse delay. Five values of the number n of delay elements in the circuit 101 and the coefficient k input from the clock generation circuit 102 are fetched. Then, based on the five values taken in, the number of delay elements 1 to which the pulse signal Pin has propagated within the sampling period Ts is calculated, and a digital output value Dout obtained by quantifying the calculated number of delay elements 1 is output. In this way, in the A / D conversion circuit 100 of the first embodiment, the analog input signal Vin is A / D converted into the digital output value Dout. Note that a detailed description of a calculation method (arithmetic processing method) of the digital output value Dout in the digital arithmetic circuit 1034 will be described later.

  Next, an operation procedure of A / D conversion in the A / D conversion circuit 100 of the first embodiment will be described. In the following description, the operation of the components in the A / D conversion circuit 100 will be described along with the elapse of the sampling time within the sampling period Ts. FIG. 2 shows the relationship between the sampling time and the digital output value Dout in the A / D conversion circuit 100 of the first embodiment, and the analog-digital conversion operation by the A / D conversion circuit 100 of the first embodiment. It is a timing chart which showed the timing of each clock signal.

  At the sampling time 0, the counter 1032 starts driving in synchronization with the rising edge of the counter clock CKC input from the clock generation circuit 102. At this time, the clock generation circuit 102 inputs the pulse signal Pin to the first-stage delay element 1 a in the pulse delay circuit 101. As a result, the pulse signal Pin starts traveling in the pulse delay circuit 101. In this way, A / D conversion sampling by the A / D conversion circuit 100 is started.

  At the sampling time Ts / k, the counter 1032 stops driving in synchronization with the falling edge of the counter clock CKC input from the clock generation circuit 102. Thus, the driving period of the counter 1032 is 1 / k of the sampling period Ts. At this time, the lower bit latch & encoder circuit 1031 detects the traveling position of the pulse signal Pin in the pulse delay circuit 101 in synchronization with the rising edge of the lower bit latch clock CKL input from the clock generation circuit 102. The detected traveling position m1 is output to the digital arithmetic circuit 1034. The upper bit latch circuit 1033 is a pulse that circulates the pulse delay circuit 101 during the drive period Ts / k output from the counter 1032 in synchronization with the rising edge of the upper bit latch clock CKM input from the clock generation circuit 102. The number of turns of the signal Pin is detected, and the detected number of turns r1 is output to the digital arithmetic circuit 1034.

  When the running position m1 input from the lower bit latch & encoder circuit 1031 and the lap number r1 input from the upper bit latch circuit 1033 are input, the digital arithmetic circuit 1034 receives the input running position m1 and lap number r1. Based on the number n of delay elements in the pulse delay circuit 101 and the coefficient k set by the clock generation circuit 102, calculation processing of the digital output value Dout is started.

  In the period from the sampling time Ts / k to the sampling time Ts, the counter 1032 stops driving. Note that the pulse signal Pin continues running in the pulse delay circuit 101 even during a period in which the counter 1032 is stopped.

  At the sampling time Ts, the lower bit latch & encoder circuit 1031 detects the traveling position of the pulse signal Pin in the pulse delay circuit 101 in synchronization with the rising edge of the lower bit latch clock CKL input from the clock generation circuit 102. The detected traveling position m2 is output to the digital arithmetic circuit 1034. Thereby, the A / D conversion sampling in the A / D conversion circuit 100 is completed.

  When the traveling position m2 input from the lower bit latch & encoder circuit 1031 is input, the digital arithmetic circuit 1034 performs sampling based on the input traveling position m2 and the result calculated at the sampling time Ts / k. Prediction (arithmetic processing) of the frequency r2 of the pulse signal Pin that has circulated the pulse delay circuit 101 within the period Ts is performed. Then, based on the predicted number of revolutions r2 and the traveling position m2, a digital output value Dout in which the number of delay elements 1 to which the pulse signal Pin has propagated within the sampling period Ts is digitized is output.

  Here, the digital output value Dout calculated by the digital arithmetic circuit 1034 will be described. As shown in FIG. 2, the digital output value Dout output from the A / D conversion circuit increases in proportion to the sampling period. Therefore, if the digital output value DK at the sampling time Ts / k is known, the digital output value DT at the sampling period Ts can be predicted from the ratio of the sampling periods. That is, the A / D conversion circuit 100 predicts the digital output value DT by calculating the digital output value DK based on the traveling position m1 detected at the sampling time Ts / k and the number of laps r1. You can also.

  However, as shown in FIG. 3, the digital output value k · DK obtained by simply multiplying the digital output value DK during the sampling period Ts / k by k is exactly the same as the digital output value DT during the sampling period Ts. It does not match. This is because the output resolution of the A / D conversion circuit varies depending on the sampling period. More specifically, the actual digital output value DT varies finely according to the analog input signal Vin as shown by the line A in FIG. 3, but the digital output value k · DK is shown in FIG. As shown by the line B, it changes with a multiple of the coefficient k. That is, the digital output value DT at the sampling period Ts has higher output resolution than the digital output value DK at the sampling period Ts / k where the sampling period is short. For this reason, the digital output value k · DK does not exactly match the digital output value DT.

  Therefore, the A / D conversion circuit 100 includes the lower bit output value m2 detected at the sampling time Ts in addition to the upper bit output value r1 and lower bit output value m1 detected at the sampling time Ts / k. Based on a total of five values including a total of three measurement results and two numerical values of delay element number n and coefficient k, the upper bit output value r2 at the sampling time Ts (r2 is 0 or more) Accurately). Then, based on the upper bit output value r2 and the lower bit output value m2, a digital output value Dout having an output resolution equivalent to the digital output value DT is calculated.

  Thus, if the upper bit output value r2 at the sampling time Ts can be predicted without actually being measured (detected) by the counter 1032, as shown in FIG. Can be driven only during the period from Ts / k to Ts / k, and can be stopped during the period from sampling time Ts / k to Ts. In other words, the A / D conversion circuit 100 reduces the driving period of the counter 1032 to a sampling period Ts / k that is 1 / k times the conventional sampling period Ts, while providing an output resolution equivalent to that of the conventional digital output value DT. The digital output value Dout can be calculated.

  Then, the power consumed by the counter 1032 can be reduced while the counter 1032 is stopped. Therefore, in the A / D conversion circuit 100, the power consumption of the counter 1032 is reduced to 1 / k compared with the conventional A / D conversion circuit without sacrificing the output resolution when the sampling period is the sampling period Ts. can do.

  Note that the counter 1032 does not have to be stopped during the entire period from the sampling time Ts / k to the sampling time Ts. For example, in a period from the sampling time Ts / k to the sampling time Ts, a configuration in which the driving is temporarily performed in a predetermined period or a predetermined timing may be employed. That is, in the period from the sampling time Ts / k to the sampling time Ts, if there is at least a period during which the counter 1032 is stopped, the power consumption of the counter 1032 is reduced according to the period during which the counter 1032 is stopped. This can be reduced as compared with the / D conversion circuit.

<First calculation method>
Next, a first calculation method (arithmetic processing method) of the digital output value Dout in the A / D conversion circuit 100 according to the first embodiment of the present invention will be described. In the A / D conversion circuit 100, the digital arithmetic circuit 1034 calculates the digital output value Dout by the first calculation method. In the following description, a digital output value Dout having an output resolution equivalent to that of the digital output value DT during the sampling period Ts is simply referred to as “digital output value Dout”.

  When the traveling position of the pulse signal Pin traveling within the pulse delay circuit 101 is measured, it can be considered that two errors are mainly added to the measurement result. One is a quantization error. This quantization error is an error corresponding to a delay time of one delay element 1, that is, a time of 1 / n round (n is the number of delay elements) of the pulse delay circuit 101 in which the pulse signal Pin travels. The other is a measurement error. This measurement error is a variation in measurement values due to fluctuations in the power supply of the A / D conversion circuit. In the first calculation method described below, the digital output in the case where only the quantization error is considered without considering the measurement error small enough to be ignored with respect to the measurement result in the A / D conversion circuit 100. A method for calculating the value Dout will be described.

  In the first calculation method in the A / D conversion circuit 100, at the sampling time Ts / k, the upper bit latch circuit 1033 receives the upper bit output value r1, and the lower bit latch & encoder circuit 1031 receives the lower bit output value m1. In the case where each can be measured accurately, there is a condition such as the following equation (1) for the coefficient k.

  In the above equation (1), k represents a coefficient set by the clock generation circuit 102, and n represents the number of delay elements 1 (the number of delay elements) provided in the pulse delay circuit 101. If the coefficient k satisfies the condition of the above equation (1), the digital output value Dout can be uniquely calculated by the first calculation method.

  Here, proof about the above formula (1) is performed. When the sampling time Ts / k is compared with the sampling time Ts, Ts / k <Ts. Therefore, the coefficient k is k> 1. Here, the error included in the lower bit output value m1 at the sampling time Ts / k is only the quantization error. This quantization error is a delay time of one delay element 1 in the pulse delay circuit 101 in which the pulse signal Pin travels. When this delay time is converted into the number of laps of the pulse signal Pin that circulates in the pulse delay circuit 101, 1 / n round. Here, when the sampling period is multiplied by k to change from the sampling period Ts / k to the sampling period Ts, the error range (= 1 / n round) of the lower bit output value m1 is also multiplied by k.

  Therefore, when the error range (= k / n rounds) of the lower bit output value m1 multiplied by k is the number of rounds of one or more rounds of the pulse delay circuit 101 on which the pulse signal Pin travels, the sampling time Ts There are a plurality of higher-order bit output values r2 (r2 is an integer of 0 or more), and the digital calculated value Dout cannot be calculated uniquely. Therefore, in order to uniquely calculate the digital calculated value Dout, the following equation (2) must be established.

  If the coefficient k is an arbitrary value satisfying the condition of the above equation (1), there is only one higher-order bit output value r2 at the sampling time Ts, so that the digital output value Dout can be uniquely calculated. . Therefore, when only the quantization error is considered in the measurement result, the digital output value Dout can be uniquely calculated as long as the coefficient k satisfies the condition of the expression (1).

  Next, a processing procedure for calculating the digital output value Dout in the digital arithmetic circuit 1034 in the A / D conversion circuit 100 according to the first embodiment of the present invention will be described. FIG. 4 is a flowchart showing a processing procedure of the digital arithmetic circuit 1034 in the A / D conversion circuit 100 of the first embodiment. In the following description, the value obtained by converting the number of delay elements 1 in the pulse delay circuit 101 through which the pulse signal Pin has propagated into the number of rounds of the pulse signal Pin that has circulated through the pulse delay circuit 101 is referred to as “the number of propagation cycles”. That's it. However, the resolution of the number of propagated delay elements 1 is set to one or less of the delay elements 1.

  Before the operation of the A / D conversion circuit 100 is started, the clock generation circuit 102 sets in advance a value of an arbitrary coefficient k that satisfies the condition “1 <k <n” of the above equation (1). Then, the clock generation circuit 102 outputs the lower bit latch clock CKL, the upper bit latch clock CKM, the counter clock CKC, and the pulse signal Pin based on the set coefficient k, and starts the operation of the A / D conversion circuit 100. . Then, the digital arithmetic circuit 1034 of the A / D conversion circuit 100 performs each process of the flowchart shown in FIG. 4 based on each value obtained during the operation of the A / D conversion circuit 100.

  The process A shown in FIG. 4 is a process for obtaining the error range of the propagation lap number x1 at the sampling time Ts / k. In process A, the digital arithmetic circuit 1034 obtains the upper bit output value r1 (r1 is an integer equal to or larger than 0) obtained by the upper bit latch circuit 1033 and the lower bit latch & encoder circuit 1031 at the sampling time Ts / k. Based on the lower bit output value m1 (m1 is an integer satisfying 0 ≦ m1 ≦ n−1), the minimum value Min1 and the maximum value Max1 of the propagation frequency during the sampling period Ts / k are expressed by the following equations (3 ).

  Thus, the following expression (4) is established for the propagation frequency x1 (x1 is an arbitrary number equal to or greater than 0) at the sampling time Ts / k.

  In the process B shown in FIG. 4, the propagation frequency x2 at the sampling time Ts (x2 is an arbitrary number greater than or equal to 0) that is k times the error range of the propagation frequency x1 at the sampling time Ts / k. This is a process for obtaining the error range. In the process B, the digital arithmetic circuit 1034 uses the minimum value Min1 and the maximum value Max1 calculated in the process A to obtain the minimum value Min2 and the maximum value Max2 of the propagation frequency during the sampling period Ts, using the following formula (5 ).

  The upper bit output value r3, lower bit output value m3, upper bit output value r4, and lower bit output value m4 assumed in the above equation (5) are values calculated by the following equation (6).

  In the above equation (6), QUIOTENT [p, q] and MOD [p, q] are expressed as functions for calculating the quotient and remainder of p / q, respectively. The upper bit output value r3 and the upper bit output value r4 are integers of 0 or more, and the lower bit output value m3 and the lower bit output value m4 are 0 ≦ m3 ≦ n−1 and 0 ≦ m4 ≦ n−1, respectively. It is an integer that satisfies Thereby, the following expression (7) is established for the propagation frequency x2 (x1 is an arbitrary number equal to or greater than 0) at the sampling time Ts.

  Further, the propagation frequency x2 at the sampling time Ts is detected by the lower bit latch & encoder circuit 1031 at the upper bit output value r2 (r2 is an integer of 0 or more) at the sampling time Ts and at the sampling time Ts. The lower bit output value m2 (m2 is an integer satisfying 0 ≦ m2 ≦ n−1) can be expressed by the following equation (8).

  In the A / D conversion circuit 100, since the counter 1032 is stopped at the sampling time Ts, the upper bit latch circuit 1033 does not acquire the upper bit output value r2 at the sampling time Ts. Accordingly, the upper bit output value r2 is an unknown number. Therefore, the digital arithmetic circuit 1034 calculates the upper bit output value r2 at the sampling time Ts by the following processing C, processing D, and processing E, and at the sampling time Ts shown in the above equation (8). The propagation frequency x2 is determined.

  The process C shown in FIG. 4 compares the magnitude relationship between the low-order bit output value m2 at the sampling time Ts and the low-order bit output value m3 expressed by the above equations (5) and (6), and the unknown number This is a process of selecting the higher-order bit output value r2. Therefore, the digital arithmetic circuit 1034 executes the process C after the lower bit latch & encoder circuit 1031 acquires the lower bit output value m2 at the sampling time Ts. If the lower bit output value m2 is greater than or equal to the lower bit output value m3 as a result of executing the process C, the digital arithmetic circuit 1034 next executes the process D, and the lower bit output value m2 becomes the lower bit output value m3. If it is smaller than this, the process E is executed next.

  Process D and process E shown in FIG. 4 are processes for determining the upper bit output value r2 according to the result of process C. The digital arithmetic circuit 1034 converts the upper bit output value r2 at the sampling time Ts to the upper bit output value r3 or the upper bit output value represented by the equations (5) and (6) by the process D or the process E. Set to any value of r4. When the result of the process C is TRUE, that is, m2 ≧ m3, the digital arithmetic circuit 1034 sets the upper bit output value r3 as the upper bit output value r2 in the process D (r2 = r3). Further, when the result of the process C is FALSE, that is, m2 <m3, the digital arithmetic circuit 1034 sets the upper bit output value r4 as the upper bit output value r2 in the process E (r2 = r4). Thus, the propagation frequency x2 at the sampling time Ts shown in the above equation (8) is determined.

  In the process C shown in FIG. 4, the magnitude relationship between the lower-order bit output value m2 at the sampling time Ts and the lower-order bit output value m4 expressed by the above formulas (5) and (6) is compared. By doing so, it is also possible to select the upper bit output value r2 which is an unknown number. That is, m2 ≧ m4 obtained by changing the lower bit output value m3 of the expression for determining the process C to the lower bit output value m4 may be an expression for determining the process C. At this time, if the lower bit output value m2 is equal to or higher than the lower bit output value m4 (m2 ≧ m4), the digital arithmetic circuit 1034 sets the upper bit output value r3 as the upper bit output value r2 in process D ( r2 = r3). If the lower bit output value m2 is smaller than the lower bit output value m4 (m2 <m4), the digital arithmetic circuit 1034 sets the upper bit output value r4 as the upper bit output value r2 in process E (r2 = R4). Even with such processing, it is possible to determine the propagation frequency x2 of the sampling time Ts shown in the above equation (8).

  The process F shown in FIG. 4 is a process for calculating the digital output value Dout based on the propagation frequency x2 at the sampling time Ts shown in the above equation (8). In process F, the digital arithmetic circuit 1034 binarizes the propagation frequency x2, and outputs the binarized value as the digital output value Dout A / D converted by the A / D conversion circuit 100.

  In this manner, in the first calculation method in the A / D conversion circuit 100, the digital arithmetic circuit 1034 calculates the digital output value Dout at the sampling time Ts by the processing procedure shown in FIG. The digital output value Dout corresponding to the analog input signal Vin input to the / D conversion circuit 100 can be uniquely calculated.

  Here, a specific example in the case where the digital arithmetic circuit 1034 in the A / D conversion circuit 100 calculates the digital output value Dout by the first calculation method will be described. In the following description, reference is made to a diagram schematically showing the relationship between the configuration of the delay elements in the pulse delay circuit of the A / D conversion circuit shown in FIG. 5 and the travel position of the pulse signal. In FIG. 5, the error range of the propagation lap number x2 at the sampling time Ts calculated by the digital arithmetic circuit 1034 and the travel position in the pulse delay circuit 101 of the pulse signal Pin indicating the propagation lap number x2 are schematically shown. Yes.

<First specific example>
First, in the first specific example, a case where the coefficient k set by the clock generation circuit 102 satisfies the condition “1 <k <n” of the coefficient k shown in the above equation (1) will be described. In the first specific example, the number of delay elements n = 8, coefficient k = 7, upper bit output value r1 = 3, lower bit output value m1 = 5, and lower bit output value m2 = 6.

  In the process A, the following equation (9) holds for the minimum value Min1 and the maximum value Max1 from the above equation (3).

  Then, according to the above equation (4), the following equation (10) is established for the propagation frequency x1 at the sampling time Ts / k.

  In the process B, the upper bit output value r3, the lower bit output value m3, the upper bit output value r4, the lower bit output value m4, the minimum value Min2, and the maximum value Max2 from the above equations (5) and (6). The following equation (11) is established.

  Then, according to the above equation (7), the following equation (12) is established for the propagation frequency x2 at the sampling time Ts.

  From the above equation (12), the traveling position of the pulse signal Pin in the pulse delay circuit 101 at the sampling time Ts is determined from the third-stage delay element 1 in the 25th cycle as shown in FIG. It is predicted that it is within the range of the second delay element 1 in the 26th cycle.

  In the first specific example, since the lower bit output value m2 = 6 and the lower bit output value m3 = 3 from the above equation (11), “m2 ≧ m3” is satisfied in the process C. That is, the result of process C is TRUE. Thereby, the processing shifts to the processing D.

  In process D, the upper bit output value r3 is set to the upper bit output value r2, so that the upper bit output value r2 = 25. Accordingly, the propagation frequency x2 at the sampling time Ts is expressed by the following equation (13) from the above equation (8).

  From the above equation (12) and the above equation (13), the propagation frequency x2 is uniquely determined to be the position of the sixth-stage delay element 1 in the 25th cycle shown in FIG. In process F, the digital output value Dout is calculated by binarizing the propagation frequency x2 at the sampling time Ts shown in the above equation (13).

  Thus, when the coefficient k set by the clock generation circuit 102 satisfies the condition “1 <k <n” of the coefficient k shown in the above equation (1), the propagation frequency x2 is Since there is only one type shown in equation (13), the propagation frequency x2 can be uniquely calculated, and the digital output value Dout A / D converted by the A / D conversion circuit 100 is uniquely calculated. be able to.

<Second specific example>
Next, in the second specific example, a case where the coefficient k set by the clock generation circuit 102 does not satisfy the condition “1 <k <n” of the coefficient k shown in the above equation (1) will be described. . In the second specific example, the number of delay elements n = 8, coefficient k = 9, upper bit output value r1 = 2, lower bit output value m1 = 3, and lower bit output value m2 = 3.

  In the process A, the following expression (14) holds for the minimum value Min1 and the maximum value Max1 from the above expression (3).

  Then, from the above equation (4), the following equation (15) is established for the propagation frequency x1 at the sampling time Ts / k.

  In the process B, the upper bit output value r3, the lower bit output value m3, the upper bit output value r4, the lower bit output value m4, the minimum value Min2, and the maximum value Max2 from the above equations (5) and (6). The following formula (16) is established.

  Then, from the above equation (7), the following equation (17) is established for the propagation frequency x2 at the sampling time Ts.

  From the above equation (17), the traveling position of the pulse signal Pin in the pulse delay circuit 101 at the sampling time Ts is determined from the third-stage delay element 1 in the 21st turn as shown in FIG. The range of the delay element 1 in the fourth stage on the 22nd round is predicted.

  In the second specific example, since the lower bit output value m2 = 3 and the lower bit output value m3 = 3 from the above equation (17), “m2 ≧ m3” is satisfied in the process C. That is, the result of process C is TRUE. Thereby, the processing shifts to the processing D.

  In process D, the upper bit output value r3 is set to the upper bit output value r2, so that the upper bit output value r2 = 21. Accordingly, the propagation frequency x2 at the sampling time Ts is expressed by the following equation (18) from the above equation (8).

  From the above equation (18), the propagation frequency x2 is determined to be the position of the third-stage delay element 1 in the 21st cycle shown in FIG. 5B. However, as can be seen from the above equation (17) and FIG. 5B, the lower bit output value m3 = 3, that is, the traveling position of the pulse signal Pin in the pulse delay circuit 101 at the sampling time Ts is the third stage. In the case of the position of the delay element 1, it is also present on the 22nd round. For this reason, there are two propagation rounds x2 as shown in the following equation (19), and the propagation rounds x2 cannot be uniquely determined.

  The reason why there are two propagation rounds x2 in this way is due to the coefficient k set in advance by the clock generation circuit 102. In the second specific example, the number of delay elements n = 8, whereas the coefficient k = 9, and the coefficient k is the condition “1 <k <n” of the coefficient k shown in the above equation (1). Is not satisfied.

  That is, when the coefficient k set by the clock generation circuit 102 does not satisfy the condition “1 <k <n” of the coefficient k shown in the above expression (1), the propagation frequency x2 is expressed by the above expression ( As shown in 19), there are two types, and the propagation frequency x2 cannot be calculated uniquely. Therefore, in order to uniquely calculate the A / D converted digital output value Dout by the A / D conversion circuit 100, the condition “1 <k <n” of the coefficient k shown in the above equation (1) is satisfied. Need to be.

  As described above, in the A / D conversion circuit 100 of the first embodiment, the output resolution during the sampling period Ts in the conventional A / D conversion circuit 400 shown in FIG. It is possible to calculate a digital output value Dout having an output resolution of.

  In the description of the first calculation method in the A / D conversion circuit 100 of the first embodiment, it is added to the measurement result when the traveling position of the pulse signal Pin traveling within the pulse delay circuit 101 is measured. The case where only the quantization error is considered among the two errors (quantization error and measurement error) considered to have been described. In the case where a measurement error is added in addition to the quantization error as an error in the measurement result when the traveling position of the pulse signal Pin traveling in the pulse delay circuit 101 is measured, the above equation (1) shows By making the condition “1 <k <n” of the coefficient k corresponding to the measurement error, the digital output value Dout in consideration of the quantization error and the measurement error can be calculated.

<Second calculation method>
Next, a second calculation method (arithmetic processing method) of the digital output value Dout in the A / D conversion circuit 100 according to the first embodiment of the present invention will be described. In the second calculation method, the measurement result when the traveling position of the pulse signal Pin traveling in the pulse delay circuit 101 is measured is considered when two errors, a quantization error and a measurement error, are considered. A method for calculating the digital output value Dout will be described.

  In the A / D conversion circuit 100, as in the first calculation method described above, the digital arithmetic circuit 1034 calculates the digital output value Dout by the second calculation method. That is, the calculation of the digital output value Dout by the second calculation method is different only in the calculation method (arithmetic processing method) by the digital arithmetic circuit 1034, and the operation of each component in the A / D conversion circuit 100 is the same. is there. The processing procedure when the digital output value Dout is calculated by the second calculation method is the same as the processing procedure shown in FIG. Therefore, in the following description, only operations and processing procedures that are different from the operations and processing procedures of the respective constituent elements similar to those of the first calculation method will be described, and detailed description thereof will be omitted.

  In the second calculation method in the A / D conversion circuit 100, the condition for the coefficient k is as shown in the following equation (20). That is, the condition of the coefficient k (k is a rational number) in the first calculation method is changed to the following expression (20).

  In the above equation (20), Δm is the maximum value of the measurement error in the lower bit output value m1 and the lower bit output value m2 acquired by the lower bit latch & encoder circuit 1031 and the number of delay elements 1 in the pulse delay circuit 101. It is a measurement error expressed by In addition, the measurement error Δm satisfies the condition (21) from the range of the coefficient k in the expression (20).

  The clock generation circuit 102 sets an arbitrary coefficient k that satisfies the condition “1 <k <n / (2 · Δm + 1)” of the above equation (20) before the operation of the A / D conversion circuit 100 is started. The lower bit latch clock CKL, the upper bit latch clock CKM, and the counter clock CKC are generated based on the set coefficient k. Then, the clock generation circuit 102 outputs the set coefficient k, the lower bit latch clock CKL, the upper bit latch clock CKM, the counter clock CKC, and the pulse signal Pin based on the set coefficient k to the pulse position digitizing circuit 103. To do.

  Next, a digital output value Dout calculation method by the second calculation method in the digital arithmetic circuit 1034 in the A / D conversion circuit 100 according to the first embodiment of the present invention will be described.

  In the second calculation method in the A / D conversion circuit 100, the measurement error of the lower bit output value m1 and the lower bit output value m2 detected by the lower bit latch & encoder circuit 1031 at the sampling time Ts / k and the sampling time Ts. However, when there are ± Δm at the maximum, conditions such as the above expression (20) and the above expression (21) exist as conditions in the second calculation method. That is, if the coefficient k is an arbitrary value that satisfies the condition of the above expression (20) and the measurement error Δm is a measurement error that satisfies the condition of the above expression (21), the digital output value Dout is calculated by the second calculation method. Can be calculated uniquely.

  Here, proof about the above formula (20) and the above formula (21) is performed. When the sampling time Ts / k is compared with the sampling time Ts, Ts / k <Ts, and therefore the coefficient k is k> 1. Then, similarly to the condition “1 <k <n” in the above equation (1) in the first calculation method, the error range of the propagation frequency x1 at the sampling time Ts / k and the propagation at the sampling time Ts. Consider the error range from the number of turns x2. As for the error range of the propagation frequency x1 at the sampling time Ts / k, the following equation (22) is established as in the above equations (3) and (4).

  Further, the error range of the propagation frequency x2 at the sampling time Ts is obtained by multiplying the error range of the propagation frequency x1 of the above equation (22) by k as in the above equation (5). (23) holds.

  As shown in the above equation (22) and the above equation (23), the error range of the propagation frequency x1 at the sampling time Ts / k and the error range of the propagation frequency x2 at the sampling time Ts are: A measurement error Δm is added to the quantization error. If the error range of the propagation frequency x2 at the sampling time Ts is less than one frequency of the pulse delay circuit 101 on which the pulse signal Pin travels, the digital calculation value Dout can be uniquely calculated. Therefore, the following equation (24) is established for the coefficient k.

  As described above, when two errors of the quantization error and the measurement error are considered with respect to the measurement result when the traveling position of the pulse signal Pin traveling within the pulse delay circuit 101 is measured, the above equation (20 ) And the measurement error Δm satisfying the condition of the above equation (21), the digital output value Dout can be uniquely calculated by the second calculation method.

  The processing of the digital arithmetic circuit 1034 only changes the condition of the coefficient k, and other processing and processing procedures can be executed in the same manner as the timing shown in FIG. 2 and the processing procedure shown in FIG. . That is, in the second calculation method, the condition “1 <k <n” of the above equation (1) in the first calculation method is changed to the condition “1 <k” of the above equation (20) in the second calculation method. <N / (2 · Δm + 1) ”and the condition“ 0 <Δm <(n−1) / 2 ”in the above equation (21) is changed to the digital output value Dout as in the first calculation method. Can be calculated uniquely.

  As described above, the A / D conversion circuit 100 according to the first embodiment can calculate the digital output value Dout in consideration of the quantization error and the measurement error by the second calculation method.

  As described above, in the A / D conversion circuit 100 of the first embodiment, the sampling in the conventional A / D conversion circuit 400 shown in FIG. 7 is performed by the first calculation method or the second calculation method. The digital output value Dout having an output resolution equivalent to the output resolution during the period Ts can be calculated.

  Furthermore, in the A / D conversion circuit 100 of the first embodiment, the counter 1032 can be stopped during the period from the sampling time Ts / k to Ts. That is, in the A / D conversion circuit 100 of the first embodiment, the driving period of the counter 1032 is 1 / k times that of the sampling period Ts that is the driving period of the counter in the conventional A / D conversion circuit. The sampling period can be shortened to Ts / k. Thus, in the A / D conversion circuit 100 of the first embodiment, the counter 1032 does not sacrifice the output resolution for the digital output value DT in the conventional A / D conversion circuit 400 shown in FIG. Power consumption can be reduced to 1 / k.

  In the A / D conversion circuit 100 according to the first embodiment, there is a period in which the counter 1032 is stopped in the period from the sampling time Ts / k to the sampling time Ts. For this reason, the number of rounds in the pulse delay circuit 101 of the pulse signal Pin acquired by the counter 1032 is a small number. That is, in the A / D conversion circuit 100 of the first embodiment, the number of bits of the counter 1032 can be reduced as compared with the counter 4032 in the conventional A / D conversion circuit 400 shown in FIG. As a result, the A / D conversion circuit 100 of the first embodiment can reduce the circuit scale as compared with the conventional A / D conversion circuit 400 shown in FIG.

<Second Embodiment>
Hereinafter, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing a schematic configuration of a column A / D conversion circuit type solid-state imaging device in which a plurality of A / D conversion circuits of the present invention are mounted for each column. The solid-state imaging device 300 illustrated in FIG. 6 includes a pixel unit 301, a vertical scanning circuit 302, a horizontal scanning circuit 303, a signal processing circuit 304, a column A / D conversion circuit 305, and a control circuit 306. ing. 6 illustrates an example in which the solid-state imaging device 300 includes the A / D conversion circuit 100 according to the first embodiment illustrated in FIG.

  The solid-state imaging device 300 performs various signal processing by the signal processing circuit 304 on the photoelectric conversion signal generated by each pixel 3 of the pixel unit 301, and then performs A / D conversion by the column A / D conversion circuit 305. Output as a digital output value Dout.

  The control circuit 306 outputs a control signal for driving the vertical scanning circuit 302, the horizontal scanning circuit 303, the signal processing circuit 304, and the column A / D conversion circuit 305.

  The vertical scanning circuit 302 selects the pixels 3 in the pixel unit 301 in units of rows of the pixel unit 301 in accordance with the control signal output from the control circuit 306, and the photoelectric conversion generated from each pixel 3 in the selected row. The signal is output to the signal processing circuit 304.

  The pixel unit 301 is a pixel array in which a plurality of pixels 3 are two-dimensionally arranged in the row direction and the column direction. Each pixel 3 includes a photodiode, generates a photoelectric conversion signal corresponding to the amount of light incident within a certain accumulation time, and outputs the generated photoelectric conversion signal to the signal processing circuit 304 according to the selection from the vertical scanning circuit 302. Output to.

  The signal processing circuit 304 removes reset noise and 1 / f noise from the photoelectric conversion signal input from the pixel unit 301 in accordance with the control signal input from the control circuit 306, and then amplifies the signal. The signal processing circuit 304 outputs the amplified signal to the column A / D conversion circuit 305 as an analog input signal Vin.

  The column A / D conversion circuit 305 includes a plurality of A / D conversion circuits 100 having the same configuration as the number of columns of the pixel portion 301. However, the A / D conversion circuit 100 provided in the column A / D conversion circuit 305 does not have a configuration including the clock generation circuit 102, but one clock generation circuit 102 common to all the A / D conversion circuits 100. Only have. Each of the A / D conversion circuits 100 provided in each column outputs a digital signal obtained by A / D converting the analog input signal Vin input from the signal processing circuit 304 in accordance with the control signal input from the control circuit 306. Output.

  The horizontal scanning circuit 303 converts the digital signal A / D converted by each A / D conversion circuit 100 of the column A / D conversion circuit 305 in accordance with the control signal input from the control circuit 306 into the column of the pixel unit 301. The digital signal of the selected column is sequentially output as a digital output value Dout output from the solid-state imaging device 300.

  As described above, in the solid-state imaging device 300 according to the second embodiment, the signal processing circuit 304 performs various types of signal processing on the photoelectric conversion signal generated by each pixel 3 of the pixel unit 301, and analog An input signal Vin is acquired. Thereafter, a digital signal obtained by A / D converting the analog input signal Vin by the column A / D conversion circuit 305 is output as a digital output value Dout. At this time, each A / D conversion circuit 100 in the column A / D conversion circuit 305 sets the driving period of the counter 1032 in each pulse position digitizing circuit 103 to the driving period of the counter in the conventional A / D conversion circuit. A digital output value having an output resolution equivalent to the digital output value during the sampling period Ts in the conventional A / D converter circuit while being shortened to the sampling period Ts / k which is 1 / k times the certain sampling period Ts. Dout can be calculated. As a result, each A / D conversion circuit 100 in the column A / D conversion circuit 305 does not sacrifice the output resolution for the digital output value in the conventional A / D conversion circuit, and does not sacrifice the output position in each pulse position digitization circuit 103. The power consumption of the counter 1032 can be reduced to 1 / k.

  Thus, the column A / D conversion circuit 305 in the solid-state imaging device 300 of the second embodiment includes the conventional A / D conversion circuit 400 shown in FIG. 7 in each column of the pixel unit. Compared to the conventional column A / D conversion circuit that does not, the power consumption of all the counters 1032 can be reduced to 1 / k without sacrificing the output resolution during the sampling period Ts. The effect of reducing the power consumption can be obtained by increasing the number of A / D conversion circuits provided in the column A / D conversion circuit type solid-state imaging device, that is, the number of counters. it can.

  In the solid-state imaging device 300 according to the second embodiment, the A / D conversion circuit 100 according to the first embodiment shown in FIG. 1 is used as each A / D conversion circuit in the column A / D conversion circuit 305. I have. As described above, the A / D conversion circuit 100 outputs the digital output value Dout having the same resolution as the conventional A / D conversion circuit 400 shown in FIG. 7 even when the circuit scale of the counter 1032 is reduced. can do. From this, in the solid-state imaging device 300 of the second embodiment, the circuit scale of the column A / D conversion circuit 305 can be reduced. This reduction in circuit scale is effective when an A / D conversion circuit is mounted in a narrow area like the solid-state imaging device 300, and the solid-state imaging device 300 is in a state where the circuit scale is reduced. The digital output value Dout having the same resolution as that of the conventional solid-state imaging device can be output.

  In the solid-state imaging device 300 of the second embodiment, a case where a plurality of A / D conversion circuits 100 having the same configuration are provided in the column A / D conversion circuit 305 as many as the number of columns of the pixel unit 301 will be described. However, a configuration in which a plurality of one A / D conversion circuit 100 is provided for each of a plurality of columns of the pixel portion 301 may be employed. In other words, the A / D conversion circuit 100 can be shared by a plurality of columns of the pixel portion 301. Even with such a configuration, similarly, the effect of reducing the power consumption of the counter 1032 can be obtained.

  In the solid-state imaging device 300 according to the second embodiment, the case where only one clock generation circuit 102 common to all the A / D conversion circuits 100 is provided in the column A / D conversion circuit 305 has been described. However, the common clock generation circuit 102 may be provided in the control circuit 306 or the horizontal scanning circuit 303, for example. In addition, the common clock generation circuit 102 may be provided in a control device outside the solid-state imaging device 300. Thereby, the circuit scale of the solid-state imaging device 300 can be reduced without sacrificing the output resolution with respect to the conventional column A / D conversion circuit type solid-state imaging device.

  As described above, according to the embodiment for carrying out the present invention, the configuration of the delay element in the pulse delay circuit in the A / D conversion circuit, and the value acquired in the sampling period Ts / k shorter than the sampling period Ts. Based on the above, a value to be acquired in the sampling period Ts is predicted. Then, a digital output value Dout is calculated based on the predicted value. As a result, it is possible to output a digital output value Dout having an output resolution equivalent to the output resolution during the sampling period Ts in the conventional A / D conversion circuit without lowering the accuracy of A / D conversion.

  Further, according to the embodiment for carrying out the present invention, at least A / D in the period from the sampling time Ts / k to the sampling time Ts in the sampling period Ts for the A / D conversion circuit to perform A / D conversion. A period in which the driving of the counter in the D conversion circuit can be stopped can be provided. Thereby, the power consumption of the counter can be reduced as compared with the conventional A / D conversion circuit.

  Moreover, according to the form for implementing this invention, the number of bits of a counter can be decreased by stopping the drive of a counter. As a result, the circuit scale of the counter can be reduced, that is, the circuit scale of the A / D conversion circuit can be reduced.

  Further, according to the embodiment for carrying out the present invention, when the A / D conversion circuit is mounted in the solid-state imaging device, a larger number of counters are provided according to the number of each mounted A / D conversion circuit. The effect of reducing power consumption and the effect of reducing the circuit scale can be obtained. Thereby, it is possible to provide a solid-state imaging device that realizes a reduction in circuit scale and low power consumption without sacrificing the output resolution of the digital output value with respect to the conventional solid-state imaging device.

  In this embodiment, an example in which a NAND circuit and a NOT circuit are used as the delay element 1 has been described. However, the circuit used as the delay element 1 is limited to a mode for carrying out the present invention. is not. For example, the delay element 1 may be a delay element having various configurations such as a NOR circuit (negative OR gate) and a differential circuit.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

100 ... A / D conversion circuit (A / D conversion device)
101: Pulse delay circuit 1, 1a, 1b ... Delay element 2 ... Buffer 102 ... Clock generation circuit (clock generation circuit)
103 ... Pulse position digitizing circuit 1031 ... Lower bit latch & encoder circuit (lower bit latch circuit)
1032 ... Counter (counter circuit)
1033: Upper bit latch circuit 1034 ... Digital arithmetic circuit 300 ... Solid-state imaging device 301 ... Pixel unit 3 ... Pixel 302 ... Vertical scanning circuit 303 ... Horizontal scanning circuit 304 ... .Signal processing circuit 305: Column A / D conversion circuit (A / D conversion device)
306... Control circuit ((clock generation circuit))
400 ... A / D conversion circuit 401 ... pulse delay circuit 402 ... clock generation circuit 403 ... pulse position digitizing circuit 4031 ... latch & encoder circuit 4032 ... counter 4033 ... latch Circuit 4034... Subtraction circuit

Claims (8)

It has n (n: positive integer, n ≧ 2) delay elements that delay and propagate a pulse signal according to the magnitude of the analog input signal, and the n delay elements are connected in an annular shape, A pulse delay circuit for sequentially propagating the pulse signal input to any one of the n delay elements at a first time until at least a second time;
Based on the output signal of any one delay element in the pulse delay circuit, the pulse signal passes through the pulse delay circuit from the first time to a third time shorter than the second time. A counter circuit for counting the number of laps,
The counter circuit acquires the number of turns counted until the third time, and outputs the acquired number of turns as an upper bit latch value;
Based on the output signal of each of the delay elements in the pulse delay circuit, the position of the pulse signal propagating through the pulse delay circuit at the third time is acquired, and the acquired position is determined as the first position. Output as the lower bit latch value, acquire the position of the pulse signal propagating through the pulse delay circuit at the second time, and output the acquired position as the second lower bit latch value. A bit latch circuit;
Based on the number of delay elements in the pulse delay circuit, the upper bit latch value, the first lower bit latch value, and the second lower bit latch value, the first time from the first time By the second time, an upper bit estimated value that estimates the number of times that the pulse signal has circulated in the pulse delay circuit is calculated, the calculated upper bit estimated value, the second lower bit latch value, And a digital arithmetic circuit for generating a digital output value corresponding to the magnitude of the analog input signal,
An A / D conversion device comprising: The digital arithmetic circuit is:
Based on the upper bit latch value and the first lower bit latch value, a first count value that is the number of the delay elements that the pulse signal has propagated through the pulse delay circuit up to the third time To calculate
Estimating the number of the delay elements that the pulse signal has propagated through the pulse delay circuit by the second time by integrating the calculated first count value and a predetermined coefficient greater than 1 and less than n. Calculate the second count value,
Based on the calculated second count value, the number of the delay elements in the pulse delay circuit, and the second lower bit latch value, the upper bit estimated value is calculated,
Generating the digital output value based on the calculated upper bit estimated value and the second lower bit latch value;
The A / D converter according to claim 1. The digital arithmetic circuit is:
Calculating a maximum value and a minimum value of the first count value;
Calculating the maximum value and the minimum value of the second count value by integrating the calculated maximum value and minimum value of the first count value and the predetermined coefficient, respectively;
Based on the calculated maximum value and minimum value of the second count value, the number of the delay elements in the pulse delay circuit, and the second lower bit latch value, the upper bit estimated value is determined. ,
Based on the determined upper bit estimated value and the second lower bit latch value, the digital output value is generated.
The A / D conversion device according to claim 2. The digital arithmetic circuit is:
A quotient obtained by dividing the calculated maximum value and minimum value of the second count value by the number of delay elements in the pulse delay circuit, respectively, is set as the maximum value and minimum value of the number of laps, respectively.
The remainder when the calculated maximum value and minimum value of the second count value are respectively divided by the number of the delay elements in the pulse delay circuit is set as the maximum value and the minimum value of the position, respectively.
Based on the second lower bit latch value and the minimum value of the position or the maximum value of the position, the upper bit estimated value is set to either the maximum value of the number of turns or the minimum value of the number of turns. To decide,
The A / D converter according to claim 3. The digital arithmetic circuit is:
When the second lower bit latch value is not less than the minimum value of the position or not less than the maximum value of the position, the minimum value of the number of laps is determined as the upper bit estimated value;
When the second lower bit latch value is smaller than the minimum value of the position or smaller than the maximum value of the position, the maximum value of the number of rounds is determined as the upper bit estimated value;
The A / D conversion device according to claim 4. An error Δm representing the maximum value of the error when the lower bit latch circuit acquires the position of the pulse signal propagating in the pulse delay circuit by the number of the delay elements in the pulse delay circuit,
Greater than 0 and less than (n-1) / 2,
The predetermined coefficient is
smaller than n / (2 · Δm + 1),
The A / D conversion device according to claim 5. It has n (n: positive integer, n ≧ 2) delay elements that delay and propagate a pulse signal according to the magnitude of the analog input signal, and the n delay elements are connected in an annular shape, The pulse signal input to one of the n delay elements is sequentially input to the pulse delay circuit that propagates the pulse signal at a first time, and the pulse is output at least until the second time. A pulse propagation step for sequentially propagating signals;
Based on the output signal of any one of the delay elements in the pulse delay circuit, the counter circuit that counts the number of times that the pulse signal has circulated in the pulse delay circuit is supplied to the counter circuit from the first time. A counting step for counting the number of laps of the pulse signal until a third time shorter than the time;
The upper bit latch circuit that obtains the number of turns counted by the counter circuit and outputs the obtained number of turns as an upper bit latch value causes the counter circuit to obtain the number of turns counted until the third time. An upper bit latch step for outputting as an upper bit latch value,
Based on the output signal of each delay element in the pulse delay circuit, the position of the pulse signal propagating in the pulse delay circuit is acquired, and the acquired position is output as a lower bit latch value. The bit latch circuit is caused to acquire the position of the pulse signal propagating in the pulse delay circuit at the third time and output as a first lower bit latch value, and the pulse delay at the second time. A lower bit latch step for obtaining a position of the pulse signal propagating in the circuit and outputting the position as a second lower bit latch value;
Based on the number of delay elements in the pulse delay circuit, the upper bit latch value, the first lower bit latch value, and the second lower bit latch value, the first time from the first time By the second time, an upper bit estimated value that estimates the number of times that the pulse signal has circulated in the pulse delay circuit is calculated, the calculated upper bit estimated value, the second lower bit latch value, A digital operation step of generating a digital output value according to the magnitude of the analog input signal,
A / D conversion method characterized by including. A pixel unit in which a plurality of pixels that output photoelectric conversion signals according to the amount of incident light are arranged in a two-dimensional matrix;
It has n (n: positive integer, n ≧ 2) delay elements that delay and propagate a pulse signal according to the magnitude of the analog input signal, and the n delay elements are connected in an annular shape, A pulse delay circuit for sequentially propagating the pulse signal input to any one of the n delay elements at a first time until at least a second time; and any one of the pulse delay circuits A counter circuit that counts the number of times that the pulse signal has circulated in the pulse delay circuit from the first time to a third time shorter than the second time, based on the output signals of two delay elements. The counter circuit acquires the number of laps counted until the third time, and outputs the acquired number of laps as an upper bit latch value, and each of the pulse delay circuits. The position of the pulse signal propagating in the pulse delay circuit at the third time is acquired based on the output signal of the delay element, and the acquired position is output as the first lower bit latch value A lower bit latch circuit that acquires a position of the pulse signal propagating in the pulse delay circuit at the second time, and outputs the acquired position as a second lower bit latch value; and Based on the number of the delay elements in the delay circuit, the upper bit latch value, the first lower bit latch value, and the second lower bit latch value, the second time from the first time. An upper bit estimated value obtained by estimating the number of times that the pulse signal has circulated in the pulse delay circuit by the time is calculated based on the calculated upper bit estimated value and the second lower bit latch value. A plurality of A / D conversion devices each including a digital arithmetic circuit that generates a digital output value corresponding to the magnitude of the analog input signal as an A / D conversion circuit corresponding to each column of the pixel portion. Column A / D conversion circuit,
A clock generation circuit that outputs a clock signal representing the first time, the second time, and the third time to each of the A / D conversion circuits included in the column A / D conversion circuit;
With
The column A / D conversion circuit includes:
Each of the photoelectric conversion signals output from the pixels in each column of the pixel unit is used as an analog input signal of the corresponding A / D conversion circuit,
In response to the clock signal input from the clock generation circuit, the digital signal generated by each A / D conversion circuit is output as an output signal from the column A / D conversion circuit, respectively.
A solid-state imaging device.

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