JP2012244557A - Flip-flop circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the life of clock wiring supplied to a flip-flop circuit.SOLUTION: A flip-flop circuit comprising a master latch unit and a slave latch unit operates synchronously with first and second clock signals separated into two channels. There is a period in which both of the first and the second clock signals are inactive and a period in which either of them is active. When both of the first and the second clock signals are inactive, the master latch unit takes in data from a data input, while the slave latch unit retains data from the master latch unit. On the other hand, when either of the first and the second clock signals is active, the master latch unit retains data from the data input, while the slave latch unit takes in data from the master latch unit. The first and the second clock signals separated into two channels are reduced in frequency to a half that of the clock signals supplied to a conventional flip-flop circuit, so that the activation rate of clock wiring is halved, resulting in an extended life of the wiring.

Description

  The present invention relates to a flip-flop circuit and a semiconductor integrated circuit including the flip-flop circuit. In particular, the present invention relates to a technique for extending the life of a clock signal supplied to a flip-flop circuit.

  In recent years, as the operating speed of semiconductor devices has been increased, the number of switching times of internal circuits has increased. An increase in the number of times of switching leads to an increase in the number of times of charging / discharging of the internal metal wiring, causing electromigration (EM) due to an increase in the activation rate, resulting in a problem of reducing the wiring life. In the internal wiring, when the wiring on the clock path is compared with the wiring on the other data path, the operation rate is twice or more, which is a factor for determining the wiring life of the entire product. For this reason, in particular, there is an increasing need for extending the wiring life for the wiring on the clock path.

  In Patent Document 1, the time until the signal processing circuit reaches its lifetime is grasped in advance, a certain condition is determined based on the time, and the switching is performed before the signal processing circuit reaches the lifetime. A semiconductor device capable of extending the lifetime has been disclosed.

  FIG. 8 is a block diagram showing a configuration of a conventional semiconductor device disclosed in Patent Document 1. In FIG. In FIG. 8, clock trees 201a and 201b as signal processing circuits are connected in parallel between a block 202 and a clock driver 203 that supplies a clock signal to the block 202. The clock trees 201a and 201b have the same structure, and are configured to perform the same processing on the clock signal output from the clock driver 203 and output it to the block 202. In FIG. 8, a switch 200 for selecting a supply destination of the power supply voltage is connected between the clock trees 201a and 201b. Further, a nonvolatile built-in timer 204 that measures the supply time of the power supply voltage is provided.

  In the semiconductor device configured as described above, the switch 200 is set so that the power supply voltage is supplied to the clock tree 201a at the start of operation. The built-in timer 204 starts measuring the supply time of the power supply voltage. When the supply time reaches a predetermined value, the built-in timer 204 outputs a signal to that effect to the switch 200. When the switch 200 receives a signal indicating that the power supply time has reached a predetermined value from the built-in timer 204, the switch 200 is switched so that the power supply voltage is supplied to the clock tree 201b. Accordingly, the lifetimes of the clock trees 201a and 201b with respect to the frequency of the clock signal output from the clock driver 203 are estimated in advance, and the time until the built-in timer 204 switches the switch 200 is calculated by subtracting some margin from the lifetime. If the predetermined value is set, the clock signal can be transmitted stably between the clock driver 203 and the block 202 over a long period of time by switching to the clock tree 201b before the clock tree 201a breaks down. For example, even if the lifetime of each of the clock trees 201a and 201b is reduced by half as the frequency of the clock signal output from the clock driver 203 increases, the entire semiconductor device maintains the same lifetime as before the increase in frequency. It is possible.

JP 2002-305435 A

  The following analysis is given by the present invention.

  However, the prior art shown in FIG. 8 is configured to supply the same clock by dividing the clock tree into two. Therefore, a clock is input from one clock driver 203 via the wiring 206 to each clock tree. In addition, any clock supplied to the block 202 via each clock tree is input via the wiring 205. Therefore, the wiring 205 and the wiring 206 become a clock signal propagation path that cannot be switched. Therefore, the activation rate of the wiring 205 and the wiring 206 cannot be lowered, and thus the wiring life of the wiring 205 and the wiring 206 is not improved. Therefore, the wiring 105 and the wiring 106 are factors that determine the life of the entire product, and there is a problem that the life of the product cannot be extended.

  In the semiconductor integrated circuit, when a flip-flop circuit is used as the block 202 in FIG. 8, the conventional technique is configured to supply the same clock signal to the clock signal input terminal of the flip-flop circuit. The life of the clock wiring of the clock signal supplied to the flip-flop circuit becomes a problem. Therefore, it is desired to extend the life of the clock wiring for the flip-flop circuit.

  A flip-flop circuit according to a first aspect of the present invention is a flip-flop circuit including a master latch unit and a slave latch unit, and the flip-flop circuit includes first and second clocks supplied to the flip-flop circuit. The first and second clock signals include a period in which both are inactive and a period in which one of them is active, and both the first and second clock signals are When inactive, the master latch unit captures data from a data input, and the slave latch unit holds data from the master latch unit and outputs it to a data output, whichever one of the first and second clock signals When one of them is active, the master latch unit holds data from the data input, and the slave latch unit Output to the data output fetches the data from the master latch.

  According to the flip-flop circuit of the present invention, the clock signal supplied to the flip-flop circuit is separated into the first clock signal and the second clock signal, and each frequency is supplied to the normal flip-flop. Since the flip-flop circuit is configured to operate with a clock signal that is reduced by a factor, a flip-flop circuit capable of extending the life of the clock wiring can be provided.

1 is a circuit diagram of a flip-flop circuit according to Embodiment 1 of the present invention. It is a circuit diagram which shows the detail of a transfer gate. It is a wave form diagram of the flip-flop circuit which concerns on Example 1 of this invention. It is a wave form diagram of the flip-flop circuit which concerns on Example 1 of this invention, and the conventional flip-flop circuit. It is a block diagram which shows the clock structure of the semiconductor device which concerns on Example 2 of this invention. It is a circuit diagram which shows an example of the conventional flip-flop circuit. FIG. 7 is a waveform diagram of the flip-flop circuit of FIG. 6. It is a block diagram which shows the conventional semiconductor device.

  Embodiments of the present invention will be described with reference to the drawings as necessary. In addition, drawing quoted in description of embodiment and the code | symbol of drawing are shown as an example of embodiment, and, thereby, the variation of embodiment by this invention is not restrict | limited.

  As shown in FIG. 1, the flip-flop circuit 1 according to the first embodiment of the present invention is a flip-flop circuit including a master latch unit 2 and a slave latch unit 3, and the flip-flop circuit 1 includes the flip-flop circuit 1. The first clock signal 50 and the second clock signal 54 are operated in synchronization with the first clock signal 50 and the second clock signal 54, and both of the first clock signal 50 and the second clock signal 54 are inactive. Includes a period during which both the first clock signal 50 and the second clock signal 54 are inactive, the master latch unit 2 captures data from the data input 60, and the slave latch unit 3 2 is held and output to the data output 64, and either the first clock signal 50 or the second clock signal 54 is output. When it is active, the master latch unit 2 holds the data from the data input 60, the slave latch unit 3 outputs the data output 64 fetches the data from the master latch unit 2.

  As shown in FIG. 1, the flip-flop circuit 1 according to the second embodiment of the present invention is a flip-flop circuit including a master latch unit 2 and a slave latch unit 3, and the flip-flop circuit 1 includes the flip-flop circuit 1. The first clock signal 50 and the second clock signal 54 are operated in synchronization with the first clock signal 50 and the second clock signal 54, and both of the first clock signal 50 and the second clock signal 54 are inactive. The master latch unit 2 includes a first data transfer unit inserted between the first brushing inverter circuit 4 and the data input 60 and the input node 66 of the first brushing inverter circuit. 10 and the second data transfer unit 12 inserted on the path returning from the output node 68 to the input node 66 of the first slashing inverter circuit The slave latch unit 3 includes a second brushing inverter circuit 5, a third data transfer unit 14 inserted between the output 62 of the master latch unit and the input node 72 of the second brushing inverter circuit, and And a fourth data transfer unit 16 inserted on a path returning from the output node 74 to the input node 72 of the second chopping inverter circuit, and the first clock signal 50 and the second clock signal 54. When both are inactive, the master latch unit 2 captures data from the data input 60 when the first data transfer unit 10 becomes conductive, and the slave latch unit 3 when the fourth data transfer unit 16 becomes conductive. Holds the data from the master latch unit 2 and outputs it to the data output 64. The first clock signal 50 and the second clock signal 54 When one of them is active, the second data transfer unit 12 becomes conductive, whereby the master latch unit 2 holds the data from the data input 60, and the fourth data transfer unit 16 becomes conductive, so that the slave latch unit 3 fetches data from the master latch unit 2 and outputs it to the data output 64.

  As shown in FIG. 5, the semiconductor integrated circuit according to the third embodiment of the present invention includes flip-flop circuits (312, 314, 316; 312, 314, 316 are provided by the flip-flop circuit 1 according to the first embodiment. A semiconductor integrated circuit including a clock generation circuit 300 that generates a first clock signal 321 and a second clock signal 323, and the first clock signal 321 and the second clock signal 323 are The first clock signal 321 and the second clock signal 323 have the same frequency, and either the first clock signal 321 or the second clock signal 323 is active during the period when both the first clock signal 321 and the second clock signal 323 are inactive. The period is repeated alternately.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

[Configuration of Example 1]
1 is a circuit diagram of a flip-flop circuit 1 according to a first embodiment of the present invention. The flip-flop circuit 1 operates in synchronization with a clock signal A (first clock signal) 50 and a clock signal B (second clock signal) 54 which are two clock inputs. The flip-flop circuit 1 includes a clock input terminal A that receives a clock signal A50 and a clock input terminal B that receives a clock signal B54. The flip-flop circuit 1 has an input terminal D of a data input 60 supplied to the flip-flop circuit 1 and an output terminal Q of a data output 64 output from the flip-flop circuit 1. Part 3 is provided. Master latch is performed in the master latch unit 2 and slave latch is performed in the slave latch unit 3, whereby the flip-flop circuit 1 operates as a master-slave type flip-flop circuit.

  The clock signal A50 supplied to the clock input terminal A is input to the inverter 42, and a signal 52 obtained by inverting the clock signal A is generated. Similarly, the clock signal B54 supplied to the clock input terminal B is input to the inverter 46, and a signal 56 obtained by inverting the clock signal B is generated. The clock signal A50, the clock signal B54, the signal 52 obtained by inverting the clock signal A, and the signal 56 obtained by inverting the clock signal B are supplied to the transfer gates (18, 20, 22, 24, 26, 28, 30, 32). Is done.

  Next, the configuration of the master latch unit 2 will be described. In the master latch unit 2, a signal input from the data input 60 is connected to the first slashing inverter circuit 4 via the first data transfer unit 10. The first data transfer unit 10 includes two transfer gates 18 and 20 connected in series. The transfer gates 18 and 20 are data transfer elements whose conduction / non-conduction is controlled by the clock signal A50 and the clock signal B54.

  Here, the details of the transfer gate will be described with reference to FIG. FIG. 2A is a circuit symbol indicating a transfer gate. In FIG. 2B, the transfer gate is configured by tying a PMOS transistor 88 and an NMOS transistor 90 together. The transfer gate is used as a switch for conducting / non-conducting between the bidirectional terminals 84 and 86. In the case of conduction, a signal propagates between the two bidirectional terminals 84 and 86. On the other hand, in the case of non-conduction, the two bidirectional terminals 84 and 86 are in a high impedance state. Only one of the PMOS transistor 88 and the NMOS transistor 90 functions as a switch, but there is a problem that the on-resistance between the drain and the source varies greatly depending on the signal level that passes through. Therefore, by tying the NMOS transistor and the PMOS transistor together That has solved the problem. The gate of the PMOS transistor 88 is a clock input terminal 80, and the gate of the NMOS transistor 90 is an inverted clock input terminal 82. Clock signals whose logics are inverted are supplied to the clock input terminal 80 and the inverted clock input terminal 82. The substrate terminal of the PMOS transistor 88 is connected to the power supply voltage VDD, and the substrate terminal of the NMOS transistor 90 is connected to the ground.

  When the signal at the clock input terminal 80 is “0” and the signal at the inverted clock input terminal 82 is “1”, both the PMOS transistor 88 and the NMOS transistor 90 are turned on, and the transfer gate becomes conductive. On the other hand, when the signal at the clock input terminal 80 is “1” and the signal at the inverted clock input terminal 82 is “0”, both the PMOS transistor 88 and the NMOS transistor 90 are turned off, and the transfer gate is turned off. .

  In the flip-flop circuit shown in FIG. 1, the case where a transfer gate is used as a data transfer element is illustrated, but the present invention is not limited to this, and the data transfer element controls conduction / non-conduction with a clock signal. Anything is possible as long as it is possible. The same applies not only to the transfer gates 18 and 20, but also to the other transfer gates (22, 24, 26, 28, 30, 32) in FIG.

  Next, returning to FIG. 1, the description of the configuration of the master latch unit 2 will be continued. The clock signal A50 is supplied to the clock input terminal of the transfer gate 18, and the inverted signal 52 of the clock signal A is supplied to the inverted clock input terminal of the transfer gate 18. The clock signal B54 is supplied to the clock input terminal of the transfer gate 20, and the signal 56 obtained by inverting the clock signal B is supplied to the inverted clock input terminal of the transfer gate 20.

  The first brush inverter circuit 4 has an input node 66 of the first brush inverter circuit and an output node 68 of the first brush inverter circuit, and an input terminal of the first brush inverter circuit is an input node of the first brush inverter circuit. 66 includes an inverter 34 whose output terminal is connected to the output node 68 of the first brushing inverter circuit. Further, an inverter 36 whose input terminal is connected to the output node 68 of the first brushing inverter circuit, and whose output terminal is connected to the input node 66 of the first brushing inverter circuit via the second data transfer unit 12. Is provided. That is, the inverter 36 and the second data transfer unit 12 are inserted in series on a path that returns from the output node 68 of the first brushing inverter circuit to the input node 66 of the first brushing inverter circuit. Further, in the first brushing inverter circuit 4, when the second data transfer unit 12 becomes conductive, the two inverters 34 and 36 are connected in a brushing manner and perform a latch operation.

  Here, the second data transfer unit 12 includes two transfer gates 22 and 24 connected in parallel. A signal 52 obtained by inverting the clock signal A is supplied to the clock input terminal of the transfer gate 22, and a clock signal A 50 is supplied to the inverted clock input terminal of the transfer gate 22. Further, the signal 56 obtained by inverting the clock signal B is supplied to the clock input terminal of the transfer gate 24, and the clock signal B 54 is supplied to the inverted clock input terminal of the transfer gate 24.

  Next, the configuration of the slave latch unit 3 will be described. The slave latch unit 3 receives the output 62 of the master latch unit. In the slave latch unit 3, the output 62 of the master latch unit is connected to the second flyback inverter circuit 5 through the third data transfer unit 14.

  Here, the third data transfer unit 14 includes two transfer gates 26 and 28 connected in parallel. A signal 52 obtained by inverting the clock signal A is supplied to the clock input terminal of the transfer gate 26, and a clock signal A50 is supplied to the inverted clock input terminal of the transfer gate 26, respectively. Further, a signal 56 obtained by inverting the clock signal B is supplied to the clock input terminal of the transfer gate 28, and a clock signal B 54 is supplied to the inverted clock input terminal of the transfer gate 28. As can be seen from FIG. 1, the second data transfer unit 12 and the third data transfer unit 14 have the same connection form of the two internal transfer gates, and the clock signal supplied to the two transfer gates. Is the same.

  The second brushing inverter circuit 5 includes an input node 72 of the second brushing inverter circuit and an output node 74 of the second brushing inverter circuit, and an input terminal of the second brushing inverter circuit is an input node of the second brushing inverter circuit. 72 includes an inverter 38 whose output terminal is connected to the output node 74 of the second pre-splash inverter circuit. The inverter 40 has an input terminal connected to the output node 74 of the second brushing inverter circuit, and an output terminal connected to the input node 72 of the second brushing inverter circuit via the fourth data transfer unit 16. Is provided. That is, the inverter 40 and the fourth data transfer unit 16 are inserted in series on a path returning from the output node 74 of the second brushing inverter circuit to the input node 72 of the second brushing inverter circuit. Further, in the second brushing inverter circuit 5, when the fourth data transfer unit 16 becomes conductive, the two inverters 38 and 40 are connected in a brushing manner and perform a latch operation.

  Here, the fourth data transfer unit 16 includes two transfer gates 30 and 32 connected in series. A clock signal A50 is supplied to the clock input terminal of the transfer gate 30, and a signal 52 obtained by inverting the clock signal A is supplied to the inverted clock input terminal of the transfer gate 30. The clock signal B54 is supplied to the clock input terminal of the transfer gate 32, and the signal 56 obtained by inverting the clock signal B is supplied to the inverted clock input terminal of the transfer gate 32. As can be seen from FIG. 1, the first data transfer unit 10 and the fourth data transfer unit 16 have the same connection form of two internal transfer gates, and clock signals supplied to the two transfer gates. Is the same.

  The data output 64 of the flip-flop circuit 1 outputs the output of the slave latch unit 3. Further, the flip-flop circuit 1 can also output an inverted signal of the data output 64 from the input node 72 of the second slashing inverter circuit as necessary.

[Operation of Embodiment 1]
Next, the operation of the flip-flop circuit 1 according to the first embodiment will be described in detail with reference to the drawings. First, the clock signal A50 and the clock signal B54 supplied to the flip-flop circuit 1 will be described. The second and third stages from the top of FIG. 4 are the waveforms of the clock signal A50 and the clock signal B54, respectively. These are signals obtained by alternately distributing the clock signal φ supplied to the conventional flip-flop shown in the uppermost stage of FIG. 4 into the clock signal A50 and the clock signal B54. That is, the clock signal A50 and the clock signal B54 have the same frequency that is half that of the clock signal φ supplied to the conventional flip-flop, and both the clock signal A50 and the clock signal B54 are inactive (“0”). And a period in which one of them becomes active (“1”) are alternately repeated.

  Next, the conduction / non-conduction relationship between the clock signal A50 and the clock signal B54 and the first to fourth data transfer units (10, 12, 14, 16) will be summarized below. When both the clock signal A50 and the clock signal B54 are inactive ("0"), both the first data transfer unit 10 and the fourth data transfer unit 16 conduct the first transfer. The data transfer unit 10 and the fourth data transfer unit 16 become conductive. In addition, in the first data transfer unit 10 and the fourth data transfer unit 16, when either one of the clock signal A50 and the clock signal B54 is active (“1”), one of the internal transfer gates is non-conductive. Therefore, the first data transfer unit 10 and the fourth data transfer unit 16 are in a non-conductive state.

  Next, in the second data transfer unit 12 and the third data transfer unit 14, when both the clock signal A50 and the clock signal B54 are inactive ("0"), both internal transfer gates become non-conductive. Therefore, the second data transfer unit 12 and the third data transfer unit 14 become non-conductive. Further, the second data transfer unit 12 and the third data transfer unit 14 are configured such that when either one of the clock signal A50 and the clock signal B54 becomes active, one of the internal transfer gates becomes conductive. The data transfer unit 12 and the third data transfer unit 14 become conductive.

  Next, the operation of the flip-flop circuit 1 will be described in detail with reference to the waveform diagram shown in FIG. FIG. 3 shows the waveform of each part at times t1 to t5. First, the uppermost part of FIG. 3 is an example of a signal supplied to the data input 60. The second and third stages in FIG. 3 are the waveforms of the clock signal A50 and the clock signal B54, respectively, and are the same as the waveforms of the clock signal A and the clock signal B at times t1 to t5 shown in FIG. .

  In the waveforms of the outputs of the first to fourth data transfer units (10, 12, 14, 16) shown in FIG. 3, the high impedance “Hi-Z” is indicated when the output is non-conductive. As described above, the first data transfer unit 10 and the fourth data transfer unit 16 become conductive at times t1 to t2 and t3 to t4 when both the clock signal A50 and the clock signal B54 become inactive “0”. The second data transfer unit 12 and the third data transfer unit 14 become non-conductive. In addition, at time t2 to t3 and t4 to t5 when either one of the clock signal A50 and the clock signal B54 becomes active, the first data transfer unit 10 and the fourth data transfer unit 16 become non-conductive, and the second The data transfer unit 12 and the third data transfer unit 14 become conductive.

  Next, the operation of the flip-flop circuit 1 at each time will be described. First, at time t1 to t2, the first data transfer unit 10 of the master latch unit 2 is turned on, so that the input node 66 of the first slashing inverter circuit has the “0” level of the data input 60 taken in. The state is reached (the output of the first data transfer unit 10 in FIG. 3, the level of the input node 66 of the first slashing inverter circuit is “Lo”). Since the level of the output 62 of the master latch passes through the inverter 34, it becomes “1” level (the level of the output 62 of the master latch unit in FIG. 3 is “Hi”). During this period, the master latch unit 2 is in a state of continuously taking in data from the data input 60. On the other hand, since the second data transfer unit 12 becomes non-conductive, feedback from the output node 68 of the first brushing inverter circuit to the input node 66 of the first brushing inverter circuit is not applied. Latch operation is not performed.

  In the slave latch unit 3, the third data transfer unit 14 is non-conductive, and the master latch unit 2 and the slave latch unit 3 are disconnected. On the other hand, the fourth data transfer unit 16 becomes conductive, and a feedback is applied from the output node 74 of the second brushing inverter circuit to the input node 72 of the second brushing inverter circuit, and the slave latch unit during this period 3 is in a state where the data before time t1 is held (the level of the input node 72 of the second pre-passing inverter circuit in FIG. 3 is “Hi” and the level of the data output Q is “Lo”).

  Next, at time t2 to t3, the first data transfer unit 10 of the master latch unit 2 is turned off and the second data transfer unit 12 is turned on (internally, the transfer gate 22 is turned on). Then, the transfer gate 24 becomes non-conductive. Since these transfer gates are connected in parallel, the second data transfer unit 12 becomes conductive. As a result, feedback is applied to the input node 66 of the inverter circuit, and the master latch unit in this period is in a state of holding the previously captured data. Specifically, since the data is continuously taken in at the times t1 to t2, the value of the data input 60 at the timing of the time t2 is held at the times t2 to t3 (the first in FIG. 3). 2) and the input level of the input node 66 of the first slashing inverter circuit is “Lo”). At this time, the level of the output 62 of the master latch unit becomes “1” by the inverter 34 (the level of the output 62 of the master latch unit in FIG. 3 is “Hi”).

  In the slave latch unit 3, the third data transfer unit 14 becomes conductive (internally, the transfer gate 26 becomes conductive and the transfer gate 28 becomes nonconductive. These transfer gates are connected in parallel. Therefore, the data “1” of the output 62 of the master latch unit during this period is the input node of the output of the third data transfer unit 14 and the input node of the second slashing inverter circuit. 72 (the output of the third data transfer unit 14 in FIG. 3, the level of the input node 72 of the second pre-shift inverter circuit is “Hi”). Since the level of the data output 62 passes through the inverter 38, the level becomes “0” (the level of the data output Q in FIG. 3 is “Lo”). During this period, the slave latch unit 3 is in a state of taking in data from the output 62 of the master latch unit. On the other hand, since the fourth data transfer unit 16 becomes non-conductive, the feedback from the output node 74 of the second brushing inverter circuit to the input node 72 of the second brushing inverter circuit is not applied. Latch operation is not performed.

  Next, since the conduction / non-conduction state of the first to fourth data transfer units (10, 12, 14, 16) at time t3 to t4 is the same as that at time t1 to t2, at time t3 to t4, The operation is similar to that at times t1 to t2. The master latch unit 2 is in a state of continuously taking in data from the data input 60. Specifically, the data input 60 during this period is “1”, and “1” is being acquired. On the other hand, the slave latch unit 3 is in a state of holding the value fetched from the master latch unit 2 at times t2 to t3. A description of the waveforms of the respective parts in FIG. 3 is omitted.

  Next, since the conduction / non-conduction state of the first to fourth data transfer units (10, 12, 14, 16) from time t4 to t5 is the same as that from time t2 to t3, at time t4 to t5, The operation is similar to that at times t2 to t3. The master latch unit 2 is disconnected from the data input 60, and feedback from the output node 68 of the first brushing inverter circuit to the input node 66 of the first brushing inverter circuit is applied. , It will be in a state to hold the previously captured data. Specifically, since the data is continuously taken in from time t3 to t4, the value of the data input 60 at the timing of time t4 is held from time t4 to t5. On the other hand, the slave latch unit 3 enters a state where the output 62 of the master latch unit during this period is captured, and the captured data is inverted by the inverter 38 and output to the data output 64. In addition, from time t4 to t5, the second data transfer unit 12 and the third data transfer unit 14 become conductive, but internally, the transfer gate 24 becomes conductive in the second data transfer unit 12, and the second data transfer unit 12 becomes conductive. 3, the transfer gate 28 becomes conductive.

  As described above, the flip-flop circuit 1 according to the first embodiment operates. Further, the data output 64 holds the input data 60 at the timing when both the clock signal A50 and the clock signal B54 are changed from the inactive state to the active state. That is, the data output 64 operates so as to hold the input data 60 at the timings t2 and t4 in FIG.

  FIG. 4 shows changes in the clock signal A50, the clock signal B54, and the output data 64 (output data Q) of the flip-flop circuit 1. The output data 64 of the flip-flop circuit 1 changes at the positions of the rising edges of the clock signal A50 and the clock signal B54 (positions indicated by arrows in the clock signal A50 and the clock signal B54 in FIG. 4). On the other hand, when the conventional flip-flop circuit is operated with the clock signal φ of the conventional flip-flop circuit shown at the top of FIG. 4, the output data 64 (output data Q) of the flip-flop circuit operates similarly. To do. That is, when the flip-flop circuit 1 according to the first embodiment is operated by the clock signal A50 and the clock signal B54, the same operation as when the conventional flip-flop circuit is operated by the clock signal φ of the conventional flip-flop can be performed. Is possible.

  The clock wiring supplied to the flip-flop circuit 1 according to the first embodiment supplies the clock signal A50 to the transfer gates 18, 22, 26, and 30 and supplies the clock signal B54 to the transfer gates 20, 24, 28, and 32. Thus, the clock wiring path is completely separated into two.

  The clock signal A50 and the clock signal B54 operate at half the frequency of the clock signal (φ in FIG. 4) of the conventional flip-flop, so the activation rate of the clock wiring supplied to the flip-flop circuit is halved. Thus, the flip-flop circuit capable of extending the life of the clock wiring can be provided.

  FIG. 5 is a block diagram illustrating a clock configuration of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment includes a clock generation circuit 300 that generates a clock signal A (first clock signal) 321 and a clock signal B (second clock signal) 323, and a plurality of flip-flop circuits (clock signal A321). 312, 314, 316), a second clock tree 308 that supplies the clock signal B 323 to a plurality of flip-flops, and a plurality of flip-flop circuits (312, 314, 316). Block 310. However, the plurality of flip-flop circuits (312, 314, 316) has the configuration of the flip-flop circuit 1 (FIG. 1) according to the first embodiment.

  The clock generation circuit 300 has a first clock generation circuit 302 and a second clock generation circuit 304 internally. The first clock generation circuit 302 is a circuit that generates a clock signal A321. As shown in FIG. 4, the clock signal A321 is a clock signal having a frequency half that of the clock signal φ supplied to the conventional flip-flop and a duty ratio of 25%. The second clock generation circuit 304 receives the clock signal A321 generated by the first clock generation circuit 302, shifts the phase by 180 degrees, and generates and outputs the clock signal B323. With the clock generation circuit 300 having such a configuration, the clock signal A321 and the clock signal B323 shown in FIG. 4 can be generated.

  In FIG. 5, the plurality of output signals of the first clock tree 306 are connected to the clock input terminals A of the plurality of flip-flops (312 314 316). On the other hand, the plurality of output signals of the second clock tree 308 are connected to the clock input terminals B of the plurality of flip-flops (312, 314, 316). In FIG. 5, the clock wiring through which the clock signal A321 propagates is the clock wiring A (320, 324, 328, 332), while the clock wiring through which the clock signal B323 propagates is the clock wiring B (322, 326, 330). 334). That is, from the output terminals of the clock generation circuit 300 (OUT of the first clock generation circuit 302, OUT of the second clock generation circuit 304), clock input terminals A and B of the plurality of flip-flops (312 314, and 316). The clock lines up to are separated into a clock line A (320, 324, 328, 332) through which the clock signal A321 propagates and a clock line B (322, 326, 330, 334) through which the clock signal B323 propagates.

  Also in the semiconductor device having a plurality of flip-flops shown in FIG. 5, the frequency of the clock wiring supplied to the flip-flops is half the frequency of the clock signal (φ in FIG. 4) supplied to the conventional flip-flops. Therefore, the activation rate of the clock wiring can be reduced by half, and the life of the clock wiring can be extended.

[Comparative example]
Next, a conventional flip-flop circuit 100 will be described as a comparative example. FIG. 6 is a circuit diagram of a conventional flip-flop circuit 100. The flip-flop circuit 100 operates in synchronization with the clock signal φ. The flip-flop circuit 100 has a clock input terminal for receiving the clock signal φ, an input terminal for the data input 104 (D in FIG. 6), and an output terminal for the data output 106 (Q in FIG. 6). A latch unit 103 is provided. The clock signal (φ in FIGS. 6 and 4) 138 supplied to the clock input terminal is input to the inverter 136, and a signal 140 obtained by inverting the clock signal is generated. These two clock signals 138 and the inverted signal 140 are supplied to transfer gates (112, 114, 116, 118).

  In the master latch unit 102, the signal input from the data input 104 is connected to the first slashing inverter circuit 108 via the transfer gate 112. A clock signal 138 is supplied to the clock input terminal of the transfer gate 112, and a signal 140 obtained by inverting the clock signal is supplied to the inverted clock input terminal of the transfer gate 112. The first brushed inverter circuit 108 includes an input node 128 of the first brushed inverter circuit and an output node 130 of the first brushed inverter circuit, and an input terminal is connected to the input node 128 of the first inverter circuit. An inverter 120 is connected, the output terminal of which is connected to the output node 130 of the first brushing inverter circuit. In addition, an inverter 122 having an input terminal connected to the output node 130 of the first inverter circuit and an output terminal connected to the input node 128 of the first brushing inverter circuit via the transfer gate 114 is provided. That is, the inverter 122 and the transfer gate 114 are inserted in series on a path that returns from the output node 130 of the first brushing inverter circuit to the input node 128 of the first brushing inverter circuit. Here, a signal 140 obtained by inverting the clock signal is supplied to the clock input terminal of the transfer gate 114, and a clock signal 138 is supplied to the inverted clock input terminal of the transfer gate 114.

  The output 105 of the master latch unit 102 is input to the slave latch unit 103. In the slave latch unit 103, the output 105 of the master latch unit is connected to the second slashing inverter circuit 110 via the transfer gate 116. Here, the inverted signal 140 is supplied to the clock input terminal of the transfer gate 116, and the clock signal 138 is supplied to the inverted clock input terminal of the transfer gate 116. The second brushing inverter circuit 110 includes an input node 132 of the second brushing inverter circuit and an output node 134 of the second brushing inverter circuit, and an input terminal of the second brushing inverter circuit is an input node of the second brushing inverter circuit. 132 includes an inverter 124 whose output terminal is connected to the output node 134 of the second pre-fire inverter circuit. In addition, an inverter 126 having an input terminal connected to the output node 134 of the second inverter circuit and an output terminal connected to the input node 132 of the second brushing inverter circuit via the transfer gate 118 is provided. That is, the inverter 126 and the transfer gate 118 are inserted in series on a path that returns from the output node 134 of the second brushing inverter circuit to the input node 132 of the first brushing inverter circuit. Here, a clock signal 138 is supplied to the clock input terminal of the transfer gate 118, and a signal 140 obtained by inverting the clock signal is supplied to the inverted clock input terminal of the transfer gate 118.

  Next, the operation of the conventional flip-flop circuit 100 shown in FIG. 6 will be described with reference to the drawings. FIG. 7 is a waveform diagram showing the operation of the flip-flop circuit 100. At time t1 to t2, the transfer gate 112 of the master latch unit 102 is turned on, so that the input node 128 of the first slashing inverter circuit is in a state in which the “0” level of the data input 104 is captured (FIG. 7). The output of the transfer gate 112 and the level of the input node 128 of the first pre-passing inverter circuit are “Lo”). The level of the output 105 of the master latch unit passes through the inverter 120 and becomes “1” level (the level of the output 105 of the master latch unit in FIG. 7 is “Hi”). During this period, the master latch unit 102 continuously takes in data from the data input 104. On the other hand, the transfer gate 114 becomes non-conductive and the latch operation is not performed. In the slave unit 103, the transfer gate 116 is non-conductive, and the master latch unit 102 and the slave latch unit 103 are disconnected. On the other hand, the transfer gate 118 becomes conductive, the second pre-passing inverter circuit 110 enters a state where feedback is applied, and a latch operation is performed, and the slave latch unit 103 during this period holds the data before time t1. (The level of the input node 132 of the second pre-passing inverter circuit in FIG. 7 is “Hi”, and the level of the data output Q is “Lo”).

  Next, at time t2 to t3, the transfer gate 112 of the master latch unit 102 is turned off and the transfer gate 114 is turned on. Feedback is applied by the first slashing inverter circuit 108, a latch operation is performed, and the master latch unit 102 in this period is in a state of holding previously captured data. Specifically, since the data is continuously taken in at the times t1 to t2, the value of the data input 104 at the timing of the time t2 is held at the times t2 to t3 (transfer in FIG. 7). The output of the gate 114 and the level of the input node 128 of the first pre-fire inverter circuit are “Lo”). At this time, the level of the output 105 of the master latch unit becomes “1” by the inverter 120 (the level of the output 105 of the master latch unit in FIG. 7 is “Hi”). In the slave latch unit 103, the transfer gate 116 becomes conductive, so that the data “1” of the output 105 of the master latch unit during this period is taken into the output of the transfer gate 116 and the input node 132 of the second pre-shift inverter circuit 110. (The output of the transfer gate 116 in FIG. 7 and the level of the input node 132 of the second pre-shift inverter circuit are “Hi”). Then, since the level of the data output 106 passes through the inverter 124, the level becomes “0” (the level of the data output Q in FIG. 7 is “Lo”).

  Next, the operation from time t3 to t4 is the same as the operation at time t1 to t2, and the operation from time t4 to t5 is the same as the operation from time t2 to t3.

  Comparing the waveform diagrams of FIG. 7 and FIG. 3, it can be seen that the levels of both data outputs Q have the same result. As described above, in the flip-flop circuit of the present invention, the clock wiring is completely separated into two, and the frequencies of the clock signal A (first clock signal) and the clock signal B (second clock signal) are conventionally known. The frequency of the clock signal supplied to the flip-flop (φ in FIG. 4) is halved, and the activation rate of the clock wiring is halved. In addition, the clock signal A and the clock signal B are completely separated, and there are no unseparable wiring portions like the conventional wirings 205 and 206 (FIG. 8) described in Patent Document 1. It is possible to extend the life of the clock wiring.

  The present invention can be applied to a semiconductor device having a built-in flip-flop circuit that can ensure a product life and perform high-speed operation.

  It should be noted that the embodiments and examples can be changed and adjusted within the scope of the entire disclosure (including claims) of the present invention and based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1,100,312,314,316: Flip-flop circuit 2,102: Master latch part 3,103: Slave latch part 4,108: 1st lighting inverter circuit 5,110: 2nd lighting inverter circuit 10: First data transfer unit 12: Second data transfer unit 14: Third data transfer unit 16: Fourth data transfer unit 18, 20, 22, 24, 26, 28, 30, 32, 112, 114, 116, 118: Transfer gate (data transfer element)
34, 36, 38, 40, 42, 46, 120, 122, 124, 126, 136: inverter 50, 321: clock signal A (first clock signal)
320, 324, 328, 332: Clock wiring A
52: A signal obtained by inverting the clock signal A (a signal obtained by inverting the first clock signal)
54, 323: Clock signal B (second clock signal)
322, 326, 330, 334: Clock wiring B
56: A signal obtained by inverting the clock signal B (a signal obtained by inverting the second clock signal)
60, 104: Data input 62, 105: Output 64 of the master latch unit, 106: Data output 66, 128: Input node 68 of the first pre-shift inverter circuit, 130: Output node 72 of the first pre-break inverter circuit, 132: Input node 74 of the second brushing inverter circuit, 134: Output node 80 of the second brushing inverter circuit: Clock input terminal 82: Inverted clock input terminal 84, 86: Bidirectional terminal 88: PMOS transistor 90: NMOS transistor 138: clock signal 140: inverted signal 200: switch 201a, 201b: clock tree 202: block 203: clock driver 204: built-in timer 205, 206: wiring 207: power supply line 300: clock generation circuit 302 : No. The clock generating circuit 304: second clock generation circuit 306: first clock tree 308: second clock tree 310: Block

Claims (8)

A flip-flop circuit including a master latch unit and a slave latch unit,
The flip-flop circuit operates in synchronization with first and second clock signals supplied to the flip-flop circuit,
The first and second clock signals include a period in which both are inactive and a period in which one is active,
When both the first and second clock signals are inactive, the master latch unit captures data from the data input, and the slave latch unit holds the data from the master latch unit and outputs it to the data output. ,
When either one of the first and second clock signals is active, the master latch unit holds data from the data input, and the slave latch unit takes in data from the master latch unit and outputs the data A flip-flop circuit that outputs to the output.   2. The data output according to claim 1, wherein the data output holds the input data at a timing at which one of the first and second clock signals changes from an inactive state to an active state. The flip-flop circuit described. The master latch unit includes a first brushing inverter circuit,
A first data transfer unit inserted between the data input and an input node of the first pre-splash inverter circuit;
A second data transfer unit inserted on a path that returns from the output node of the first chopping inverter circuit to the input node, and
The slave latch unit includes a second brushing inverter circuit;
A third data transfer unit inserted between the output of the master latch unit and the input node of the second pre-fire inverter circuit;
A fourth data transfer unit inserted on a path that returns from the output node of the second chopping inverter circuit to the input node, and
When both the first and second clock signals are inactive, the first data transfer unit becomes conductive, whereby the master latch unit captures data from the data input, and the fourth data transfer unit By conducting, the slave latch unit holds the data from the master latch unit and outputs to the data output,
When either one of the first and second clock signals is active, the second data transfer unit is turned on, whereby the master latch unit holds data from the data input, and the fourth data 3. The flip-flop circuit according to claim 1, wherein when the transfer unit is turned on, the slave latch unit captures data from the master latch unit and outputs the data to the data output. Each of the first and fourth data transfer units includes two data transfer elements connected in series,
The second and third data transfer units are each composed of two data transfer elements connected in parallel,
One data transfer element of the first and fourth data transfer units and one data transfer element of the second and third data transfer units are in a conductive / non-conductive state by the first clock signal. Are controlled to be reversed,
The other data transfer element of the first and fourth data transfer units and the other data transfer element of the second and third data transfer units are in a conductive / non-conductive state according to the second clock signal. 4. The flip-flop circuit according to claim 3, wherein the flip-flop circuit is controlled to be reversed. A semiconductor integrated circuit comprising: the flip-flop circuit according to claim 1; and a clock generation circuit that generates the first and second clock signals.
The first clock signal and the second clock signal have the same frequency;
A semiconductor integrated circuit characterized by alternately repeating a period in which both the first and second clock signals are inactive and a period in which one of the first and second clock signals is active. The clock generation circuit includes a first clock generation circuit and a second clock generation circuit,
The first clock generation circuit generates the first clock signal;
The second clock generation circuit receives the first clock signal and outputs the second clock signal obtained by shifting the phase of the first clock signal by approximately 180 degrees. 5. The semiconductor integrated circuit according to 5. A plurality of flip-flop circuits according to any one of claims 1 to 4, and the clock generation circuit,
A first clock tree for supplying a first clock signal generated by the clock generation circuit to the plurality of flip-flop circuits;
The semiconductor integrated circuit according to claim 5, further comprising: a second clock tree that supplies the second clock signal generated by the clock generation circuit to the plurality of flip-flop circuits. .   The plurality of clock wirings from the output terminal of the clock generation circuit to the clock input terminal of the flip-flop circuit are a clock wiring through which the first clock signal propagates and a clock wiring through which the second clock signal propagates. 8. The semiconductor device according to claim 5, wherein the semiconductor device is separated.

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