JP2012242593A - Plasma display device and driving method of plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress occurrence of a discharge failure without providing an initialization period and prevent deterioration of image quality.SOLUTION: A plasma display device comprises: a plasma display panel 10 including a plurality of display electrode pairs consisting of a scanning electrode and a sustaining electrode extended in a first direction, a plurality of data electrodes extended in a second direction, and a pixel having a discharge cell formed in a portion where a display electrode pair and a data electrode intersect; and a control part 100. A plurality of subfields include a writing period without an initialization period. Other subfields except specified subfields include a sustaining period after the writing period. The specified subfields have luminance weight lower than that of the other subfields by not including a sustaining period or including a sustaining period without generating a sustaining discharge. The control part controls a drive part in the specified subfields so as not to simultaneously light a first discharge cell and a second discharge cell, and/or so as not to simultaneously light the first discharge cell and the third discharge cell.

Description

  The present invention relates to an AC surface discharge type plasma display apparatus and a method for driving a plasma display panel.

  A plasma display panel (hereinafter referred to as a “panel”) includes a plurality of discharge cells having scan electrodes, sustain electrodes, and data electrodes, and each color of red, green, and blue is generated by ultraviolet rays generated by gas discharge in the discharge cells. These phosphors are excited to emit light for color display.

  As a method of driving the panel, a subfield method, that is, a single field is formed using a plurality of subfields having an initialization period, an address period, a sustain period, and an erase period, and gradation display is performed by combining subfields that emit light. The method of performing is common. An initialization operation is performed in the initialization period of each subfield, a write operation is performed in the write period, a sustain operation is performed in the sustain period, and an erase operation is performed in the erase period.

  The initializing operation is an operation for generating an initializing discharge in all the discharge cells and activating charges in the discharge cells so that the subsequent address operation is suitably performed. The address operation is an operation in which address discharge is selectively generated in the discharge cells in accordance with an image to be displayed to form wall charges. The sustain operation is an operation in which a sustain pulse is alternately applied to the display electrode pair to generate a sustain discharge, and the phosphor layer of the corresponding discharge cell emits light. The erasing operation is an operation in which an erasing discharge is selectively generated in a discharge cell that has generated an address discharge to erase the wall charge history, and wall charges necessary for the subsequent address discharge are formed on each electrode.

  In the sustain operation in the sustain period, the sustain cell is repeatedly generated by the number of sustain pulses by the number of sustain pulses corresponding to the luminance weight determined in advance for each subfield, thereby causing the discharge cells to emit light. Is going. Conventionally, there has been proposed a plasma display device in which low gradation display is improved by providing a subfield having a luminance weight lower than the minimum luminance weight due to the sustain discharge (see Patent Document 1). In this patent document 1, low gradation display is improved by reducing the light emission quantity of the discharge cells that selectively generate the address discharge by not applying the sustain pulse.

  On the other hand, it is required to improve the contrast by reducing light emission not related to gradation display as much as possible and lowering the luminance when displaying black, which is the lowest gradation in the subfield method. For this purpose, it is only necessary not to provide an initialization period for generating an initialization discharge in all the discharge cells. However, if the initialization period is not provided, the effect of activating the charge in the discharge cells is lost, and therefore, the address discharge is not suitably performed and the possibility of occurrence of a discharge failure increases.

  The effect of activating the charge in the discharge cell can also be obtained by light emission of address discharge or sustain discharge, but light emission of address discharge or sustain discharge does not occur in the discharge cells displaying black. Therefore, simply by not providing the initialization period, the discharge cells that display black longer have a higher possibility of occurrence of discharge failure. As described above, when the initialization period is not provided, it is required to suppress the occurrence of defective discharge.

JP 2005-107495 A

  In order to suppress the occurrence of defective discharge, for example, it is conceivable to include a subfield having a luminance weight lower than the minimum luminance weight due to the sustain discharge as described in Patent Document 1 above. By providing such a subfield with a low luminance weight, the light emission probability of the discharge cell can be increased. When the light emission probability of the discharge cell increases, it is possible to obtain an effect of activating charges in the discharge cell by the light emission, and as a result, it is possible to suppress the occurrence of discharge failure.

  However, according to experiments by the inventors, for example, as described in Patent Document 1 described above, when the amount of light emitted from the discharge cell that selectively generated the address discharge is reduced by not applying the sustain pulse, It became clear that when adjacent pixels are lit simultaneously, a conspicuous luminescent spot is generated and the image quality deteriorates.

  The present invention solves the above-described problems, and provides a plasma display device and a plasma display panel driving method that can suppress the occurrence of defective discharge without providing an initialization period and can prevent deterioration in image quality. For the purpose.

  A plasma display apparatus according to an aspect of the present invention is a plasma display apparatus that displays an image based on an input image signal, and each includes a plurality of display electrode pairs each including a scan electrode and a sustain electrode extending in a first direction; A plasma display panel, comprising: a plurality of data electrodes extending in a second direction intersecting the first direction; and a pixel having a discharge cell formed at a portion where the display electrode pair and the data electrode intersect. A driving unit that applies a driving voltage to at least one of the scan electrode, the sustain electrode, and the data electrode so that a luminance weight is different for each of a plurality of subfields included in a field period; and A plurality of subfields each including the scan electrode, the data electrode, and the control electrode. Including an initializing period for generating an initializing discharge for activating a charge in the discharge cell by applying a driving voltage to the holding electrode, including a predetermined addressing period, and Each of the subfields other than the specific subfield includes a predetermined sustain period after the address period, and the driving unit applies a scan pulse to the scan electrode and the data electrode in the address period. An address pulse is applied to the discharge cell to selectively generate an address discharge, and the driving unit alternately applies a sustain pulse corresponding to the luminance weight to the scan electrode and the sustain electrode in the sustain period. A sustain discharge is generated in the discharge cells selected in the address period, and the specific subfield does not include the sustain period, or By including a sustain period in which the sustain pulse is not applied by the driving unit and the sustain discharge does not occur, the luminance weight is lower than that of the other subfield including the sustain period, and the plasma display panel One pixel, a second pixel adjacent to the first pixel in the first direction, and a third pixel adjacent to the first pixel in the second direction, wherein the first pixel is a first discharge The second pixel includes a second discharge cell adjacent to the first discharge cell in the first direction, and the third pixel is adjacent to the first discharge cell in the second direction. The control unit includes three discharge cells so that the first discharge cell and the second discharge cell are not turned on simultaneously in the specific subfield and / or the first discharge cell and the third discharge cell. The drive unit is controlled so that the discharge cells are not lit simultaneously.

  According to this configuration, the plasma display panel includes a plurality of display electrode pairs each including a scan electrode and a sustain electrode extending in the first direction, a plurality of data electrodes extending in the second direction intersecting the first direction, and the display electrodes. And a pixel having a discharge cell formed at a portion where the pair and the data electrode cross each other. The driving unit applies a driving voltage to at least one of the scan electrode, the sustain electrode, and the data electrode so that the luminance weight is different for each of the plurality of subfields included in one field period. The control unit controls the drive unit. Each of the plurality of subfields does not include an initialization period in which a driving voltage is applied between the scan electrode, the data electrode, and the sustain electrode to generate an initialization discharge for activating charges in the discharge cell. , Including a predetermined writing period. Therefore, contrast can be improved.

  All of the subfields other than the specific subfield among the plurality of subfields include a predetermined sustain period after the writing period. In the address period, the driver applies a scan pulse to the scan electrodes and applies an address pulse to the data electrodes to selectively generate an address discharge in the discharge cells. The driving unit alternately applies a sustain pulse corresponding to the luminance weight to the scan electrode and the sustain electrode in the sustain period, and generates a sustain discharge in the discharge cell selected in the address period. The specific subfield has a lower luminance weight than other subfields including the sustain period by not including the sustain period or by including a sustain period in which the sustain pulse is not applied without the sustain pulse being applied by the driving unit. Therefore, the light emission probability of the discharge cell can be increased as compared with the case where only the subfield including the sustain period in which the sustain discharge occurs is provided. When the light emission probability of the discharge cells increases, the number of discharge cells that display black for a long time is reduced, so that the occurrence of discharge failure can be suppressed.

  The plasma display panel includes a first pixel, a second pixel adjacent to the first pixel in the first direction, and a third pixel adjacent to the first pixel in the second direction. The first pixel includes a first discharge cell. The second pixel includes a second discharge cell adjacent to the first discharge cell in the first direction. The third pixel includes a third discharge cell adjacent to the first discharge cell in the second direction. In the specific subfield, the controller may turn on the driving unit so that the first discharge cell and the second discharge cell are not turned on simultaneously and / or the first discharge cell and the third discharge cell are not turned on simultaneously. Control. Therefore, it is possible to prevent a conspicuous bright spot from being generated, and as a result, it is possible to prevent a deterioration in image quality.

  In the plasma display device, the pixels included in the plasma display panel are arranged in a matrix in the first direction and the second direction, and the control unit performs error diffusion processing on the video signal. After the error diffusion processing by the error diffusion processing unit and the error diffusion processing unit, the video signal of the correction target pixel selected from the pixels arranged in the matrix is corrected to zero in the specific subfield. A thinning processing unit that performs a thinning process for turning off the correction target pixel, and the thinning processing unit corrects pixels selected in a checkered pattern from the pixels arranged in the matrix as the thinning process Of the pixels arranged in a matrix, the first thinning-out process as a target pixel, and the pixels arranged in the first direction It is preferred to carry out the second thinning processing of the pixels included in the selected pixel row pixel column is selected in every other column in the second direction and the correction target pixel, one of the.

  According to this configuration, the pixels included in the plasma display panel are arranged in a matrix in the first direction and the second direction. The control unit includes an error diffusion processing unit and a thinning processing unit. The error diffusion processing unit performs error diffusion processing on the video signal. After the error diffusion processing by the error diffusion processing unit, the thinning processing unit corrects the video signal of the correction target pixel selected from the pixels arranged in a matrix in a specific subfield to zero and turns off the correction target pixel. Process. The thinning-out processing unit performs a first thinning process in which pixels selected in a checkered pattern from pixels arranged in a matrix as a correction target pixel as a thinning-out process and a pixel in a first direction among the pixels arranged in a matrix One of the second thinning-out processing is performed in which the pixels included in the selected pixel column in which the arranged pixel columns are selected every other column in the second direction are correction target pixels.

  When the first thinning process is performed in which pixels selected in a checkered pattern from pixels arranged in a matrix are corrected, the first discharge cell and the second discharge cell are not turned on simultaneously in the specific subfield. And the 1st discharge cell and the 3rd discharge cell do not light simultaneously. In addition, out of the pixels arranged in a matrix, the second thinning-out process is performed using the pixels included in the selected pixel column in which the pixel columns arranged in the first direction are selected every other column in the second direction as the correction target pixels. In the specific subfield, the first discharge cell and the third discharge cell are not turned on simultaneously. Therefore, it is possible to prevent a conspicuous bright spot from being generated, and as a result, it is possible to prevent a deterioration in image quality.

  In the plasma display device, the control unit further includes a gradation correction unit that increases and corrects the level of the video signal by a predetermined width and outputs the level to the error diffusion processing unit, and the error diffusion processing unit includes the level diffusion unit. It is preferable that the error diffusion process is performed on the video signal that has been increased and corrected by the tone correction unit.

  According to this configuration, the control unit further includes a gradation correction unit that increases and corrects the level of the video signal by a predetermined width and outputs it to the error diffusion processing unit. The error diffusion processing unit performs error diffusion processing on the video signal that has been increased and corrected by the gradation correction unit. Here, after the error diffusion processing, when the thinning processing unit performs thinning processing that corrects the video signal of the correction target pixel to zero and turns off the correction target pixel, the luminance of the video decreases. However, in this configuration, the level of the video signal is increased and corrected by a predetermined width by the gradation correction unit, and the error diffusion processing unit performs error diffusion processing on the video signal that has been increased and corrected by the gradation correction unit. Therefore, it is possible to suppress a decrease in the luminance of the video that occurs when the thinning processing unit performs the thinning processing after the error diffusion processing.

  In the above plasma display device, a pixel column that is arranged in the first direction and includes pixels including the first pixel and the second pixel is defined as a first pixel column, and the third pixel is arranged in the first direction. The error diffusion processing unit is adjacent to each other in the second direction after the error diffusion processing, and the pixels of the first pixel column and the second pixel column It is preferable that the error diffusion process is performed so that a pair of the pixels including the pixels are turned on or off at the same time.

  According to this configuration, a pixel column that is arranged in the first direction and includes pixels including the first pixel and the second pixel is defined as a first pixel column, and a pixel that is arranged in the first direction and includes pixels including the third pixel. Let the column be the second pixel column. After the error diffusion processing, the error diffusion processing unit is adjacent to each other in the second direction, and a pair of pixels including the pixels in the first pixel column and the pixels in the second pixel column are turned on or off at the same time. Perform error diffusion processing. Therefore, after the error diffusion process, the number of lit pixels in the first pixel column is equal to the number of lit pixels in the second pixel column. When the thinning processing unit performs the first thinning process after the error diffusion process, half of the lit pixels in the first pixel column and the lit pixels in the second pixel column are turned off, so that the first pixel column and the second pixel column The total number of lit pixels is halved compared to before the first thinning process. Further, when the thinning-out processing unit performs the second thinning-out process after the error diffusion processing, all the lighting pixels in one of the first pixel column and the second pixel column are turned off, so that the total of the first pixel column and the second pixel column As in the first thinning process, the number of lit pixels is halved compared to that before the second thinning process. As described above, regardless of whether the first thinning process or the second thinning process is performed, the number of lit pixels in the first pixel row and the second pixel row is halved compared to before the thinning process. Therefore, after performing the thinning-out process, the number of lit pixels remains so much that the image becomes too bright than the original brightness, or the number of lit pixels becomes too small and the image becomes too dark than the original brightness. There is no advantage.

  In the plasma display device, the thinning-out processing unit includes a first determination unit that determines whether or not the gradation of each pixel in the specific subfield is equal to or higher than a predetermined specific gradation, and the thinning-out processing unit It is preferable that neither the first thinning-out process nor the second thinning-out process is performed on the pixels for which the gradation is determined by the first determination unit to be equal to or higher than the specific gradation.

  According to this configuration, the thinning processing unit includes the first determination unit that determines whether the gradation of each pixel in the specific subfield is equal to or higher than a predetermined specific gradation. The thinning-out processing unit does not perform either the first thinning-out processing or the second thinning-out processing for the pixels determined by the first determination unit that the gradation is equal to or higher than the specific gradation. Pixels with gradations of a specific gradation or higher are inconspicuous in the change in luminance depending on whether or not thinning processing is performed in a specific subfield. In addition, a bright spot in a specific subfield is not conspicuous for a pixel whose gradation is equal to or higher than a specific gradation. Therefore, the image quality of a pixel having a gradation greater than or equal to a specific gradation does not deteriorate even if the thinning process is not performed.

  The plasma display device may further include a second determination unit that calculates an average gradation of the video signal and determines whether the calculated average gradation is equal to or greater than a preset threshold value. When the second determination unit determines that the average gradation is equal to or higher than the threshold value, the first decimation process is performed, and when the second determination unit determines that the average gradation is less than the threshold value, the second determination unit performs the second thinning process. It is preferable to perform a thinning process.

  According to this configuration, the image processing apparatus further includes the second determination unit that calculates the average gradation of the video signal and determines whether the calculated average gradation is equal to or greater than a preset threshold value. The thinning processing unit performs the first thinning process when the second determination unit determines that the average gradation is equal to or higher than the threshold, and performs the second thinning process when the second determination unit determines that the average gradation is less than the threshold. .

  Therefore, in the first thinning-out process, driving is performed so that the first discharge cell and the second discharge cell are not turned on simultaneously and the first discharge cell and the third discharge cell are not turned on simultaneously in the specific subfield. Control part. As a result, deterioration in image quality can be further suppressed. In this case, since the average gradation is equal to or higher than the threshold value, the light emission probability of the discharge cell is high, so that the first discharge cell and the second discharge cell do not light simultaneously, and the first discharge cell and the third discharge cell. Even if they are not lit simultaneously, the occurrence of defective discharge does not increase.

  On the other hand, in the second thinning-out process, the drive unit is controlled so that the first discharge cell and the third discharge cell are not turned on simultaneously in the specific subfield. In this case, it is possible that the first discharge cell and the second discharge cell are lit simultaneously. Therefore, since the number of discharge cells that display black is reduced, an effect of activating the charge in the discharge cells can be easily obtained.

  The plasma display device further includes a third determination unit that measures the duration of the state in which one or a plurality of pixels are not lit, and determines whether the measured duration exceeds a preset time. The decimation processing unit performs the second decimation process when the third determination unit determines that the duration exceeds the set time, and the third determination unit determines that the duration is equal to or less than the set time. When it is determined, the first thinning process is preferably performed.

  According to this configuration, the third determination unit further includes a third determination unit that measures a continuation time in a state where one or a plurality of pixels are not lit, and determines whether the measured continuation time exceeds a preset set time. The decimation processing unit performs the second decimation process when the third determination unit determines that the duration exceeds the set time, and performs the first decimation process when the third determination unit determines that the duration is equal to or less than the set time. Do. If the duration of the non-lighting state exceeds the set time, it is considered that a discharge failure is likely to occur. By performing the second thinning process, the first discharge cell and the third discharge cell are prevented from being turned on at the same time to prevent the bright spots from being generated, while the first discharge cell and the second discharge cell are turned on at the same time. Is possible. Therefore, compared to the first thinning-out process, the number of discharge cells that display black is reduced, so that an effect of activating the charge in the discharge cells can be easily obtained. On the other hand, if the duration of the non-lighting state is equal to or shorter than the set time, it is considered that a discharge failure is unlikely to occur. Therefore, by performing the first thinning process, the first discharge cell and the second discharge cell are not turned on at the same time, and the first discharge cell and the third discharge cell are not turned on at the same time. It can be suppressed more.

  In the plasma display device, the first pixel may include a fourth discharge cell adjacent to the first discharge cell in the first direction or the second direction, and the control unit may include the fourth discharge cell in the specific subfield. It is preferable to control the driving unit so that the first discharge cell and the fourth discharge cell are not lit simultaneously.

  According to this configuration, the first pixel includes the fourth discharge cell adjacent to the first discharge cell in the first direction or the second direction. The control unit controls the driving unit so that the first discharge cell and the fourth discharge cell are not turned on simultaneously in the specific subfield. By preventing the fourth discharge cell and the first discharge cell adjacent to the first discharge cell from being turned on simultaneously in the first direction or the second direction, it is possible to reliably prevent the occurrence of bright spots.

  In the plasma display device, each of the first pixels has N (N is an integer of 2 or more) discharge cells including the first discharge cells, each corresponding to a predetermined set color different from each other. Each of the third pixels corresponds to the set color and has N discharge cells including the third discharge cell, and the first discharge cell and the third discharge cell may correspond to the same color. preferable.

  According to this configuration, the first pixel has N (N is an integer of 2 or more) discharge cells including the first discharge cells, which correspond to different predetermined colors. Each third pixel corresponds to a set color and has N discharge cells including the third discharge cells. The first discharge cell and the third discharge cell correspond to the same color. Accordingly, it is possible to prevent generation of bright spots by the first discharge cells and the third discharge cells that are adjacent in the second direction and correspond to the same color.

  A driving method of a plasma display panel according to another aspect of the present invention includes a plurality of display electrode pairs each formed of a scan electrode and a sustain electrode extending in a first direction, and a plurality of display electrodes extending in a second direction intersecting the first direction. A plasma display panel driving method for driving a plasma display panel, comprising: a data electrode; and a pixel having a discharge cell formed at a portion where the display electrode pair and the data electrode intersect with each other. Includes a first pixel, a second pixel adjacent to the first pixel in the first direction, and a third pixel adjacent to the first pixel in the second direction, wherein the first pixel is The first pixel includes a first discharge cell, the second pixel includes a second discharge cell adjacent to the first discharge cell in the first direction, and the third pixel includes the second discharge cell. The scan electrodes, the sustain electrodes, and the data electrodes, each including a third discharge cell adjacent to the first discharge cell in a direction and having different luminance weights for each of a plurality of subfields included in one field period. A driving voltage is applied to at least one electrode by a driving unit, and each of the plurality of subfields applies a driving voltage between the scan electrode, the data electrode, and the sustain electrode, thereby generating a voltage in the discharge cell. An initializing period for generating an initializing discharge for activating the charge is not included, and a predetermined address period is included, and any of the subfields other than the specific subfield among the plurality of subfields is Is configured to include a predetermined sustain period after the address period, and the driving unit applies the scan electrode to the scan electrode in the address period. And applying an address pulse to the data electrode to selectively generate an address discharge in the discharge cell, and the driving unit applies the luminance weight to the scan electrode and the sustain electrode in the sustain period. The sustain pulses corresponding to the first and second sustain pulses are alternately applied to generate a sustain discharge in the discharge cells selected in the address period, and the specific subfield does not include the sustain period or the sustain pulse is generated by the driver. Including a sustain period in which the sustain discharge is not generated without being applied, so that the luminance weight is lower than that of the other subfield including the sustain period, and the first discharge is performed in the specific subfield. So that the cell and the second discharge cell are not lit at the same time, and / or the first discharge cell and the third discharge cell are The drive unit is controlled so that it does not light up at the same time.

  According to this configuration, the plasma display panel includes a plurality of display electrode pairs each including a scan electrode and a sustain electrode extending in the first direction, a plurality of data electrodes extending in the second direction intersecting the first direction, and the display electrodes. And a pixel having a discharge cell formed at a portion where the pair and the data electrode cross each other. The plasma display panel includes a first pixel, a second pixel adjacent to the first pixel in the first direction, and a third pixel adjacent to the first pixel in the second direction. The first pixel includes a first discharge cell. The second pixel includes a second discharge cell adjacent to the first discharge cell in the first direction. The third pixel includes a third discharge cell adjacent to the first discharge cell in the second direction.

  According to this configuration, the driving voltage is applied to at least one of the scan electrode, the sustain electrode, and the data electrode by the driving unit so that the luminance weight is different for each of the plurality of subfields included in one field period. To do. Each of the plurality of subfields does not include an initialization period in which a driving voltage is applied between the scan electrode, the data electrode, and the sustain electrode to generate an initialization discharge for activating charges in the discharge cell. And a predetermined writing period. Therefore, contrast can be improved.

  All the subfields other than the specific subfield among the plurality of subfields are configured to include a predetermined sustain period after the write period. In the address period, the drive unit applies a scan pulse to the scan electrode and an address pulse to the data electrode to selectively generate an address discharge in the discharge cells. In the sustain period, the drive unit alternately applies a sustain pulse corresponding to the luminance weight to the scan electrode and the sustain electrode, thereby generating a sustain discharge in the discharge cell selected in the address period. The specific subfield does not include a sustain period, or includes a sustain period in which a sustain discharge is not generated when a sustain pulse is not applied by the driver, so that the specific subfield has a lower luminance weight than other subfields including the sustain period. Configure. Therefore, the light emission probability of the discharge cell can be increased as compared with the case where only the subfield including the sustain period in which the sustain discharge occurs is provided. When the light emission probability of the discharge cells increases, the number of discharge cells that display black for a long time is reduced, so that the occurrence of discharge failure can be suppressed.

  In the specific subfield, the driving unit is controlled so that the first discharge cell and the second discharge cell are not lit simultaneously and / or the first discharge cell and the third discharge cell are not lit simultaneously. Therefore, it is possible to prevent a conspicuous bright spot from being generated, and as a result, it is possible to prevent a deterioration in image quality.

  According to the present invention, it is possible to suppress the occurrence of defective discharge without providing an initialization period, and to prevent deterioration in image quality.

It is a block diagram which shows the electric constitution of the plasma display apparatus in one Embodiment of this invention. It is a figure which shows the electrode arrangement | sequence and drive part of a panel which are used for the plasma display apparatus in one Embodiment of this invention. It is a disassembled perspective view of the panel used for the plasma display apparatus in one Embodiment of this invention. It is a schematic diagram explaining the drive of the panel in this embodiment. It is a schematic diagram explaining the light emission probability of a luminance weight. It is a block diagram which shows the structure of the signal processing part shown by FIG. It is a schematic diagram explaining the function of a 1st subfield gradation correction | amendment part. It is a block diagram which shows the structure of a vertically long error diffusion process part. It is a figure for demonstrating operation | movement of the vertically long error diffusion process part shown by FIG. It is a figure for demonstrating operation | movement of the vertically long error diffusion process part shown by FIG. It is a figure for demonstrating operation | movement of the vertically long error diffusion process part shown by FIG. It is a figure for demonstrating operation | movement of the vertically long error diffusion process part shown by FIG. It is a figure for demonstrating operation | movement of the vertically long error diffusion process part shown by FIG. It is a block diagram which shows the structure of a 1st subfield thinning part. It is a schematic diagram explaining a 1st thinning process. It is a schematic diagram explaining a 2nd thinning process. It is a figure which shows typically the lighting state of each pixel by this embodiment. It is a figure which shows typically the lighting state of each pixel by a comparative example. It is a figure which shows typically the lighting state of each pixel by a comparative example. It is a figure which shows typically the lighting state of each pixel by a comparative example. It is a figure which shows typically the lighting state of each pixel by a comparative example. It is a figure which shows typically the lighting state of each pixel by a comparative example. It is a schematic diagram which shows schematically another form of a thinning process. It is a schematic diagram which shows schematically another form of a thinning process.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an electrical configuration of a plasma display device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an electrode arrangement and a driving unit of the panel 10 used in the plasma display device according to the embodiment of the present invention. FIG. 3 is an exploded perspective view of the panel 10 used in the plasma display device according to the embodiment of the present invention.

  As shown in FIG. 3, a plurality of display electrode pairs 24 including scan electrodes 22 and sustain electrodes 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33. As a red phosphor, for example, (Y, Gd) BO3: Eu, as a green phosphor, Zn2SiO4: Mn, for example, and as a blue phosphor, BaMgAl10O17: Eu, for example, as a main component is used. Is used.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light, whereby an image is displayed on the panel 10. Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  As shown in FIG. 2, panel 10 includes scan electrode 22 including n scan electrodes SC <b> 1 to scan electrode SCn extending in the row direction (first direction) and n sustain electrodes SU <b> 1 to sustain electrode SUn. The sustain electrodes 23 are arranged, and data electrodes 32 including m data electrodes D1 to Dm extending in the column direction (second direction) are arranged. Then, a discharge cell is formed at a portion where the display electrode pair including the pair of scan electrodes SCi (i = 1 to n) and the sustain electrode SUi and the one data electrode Dj (j = 1 to m) intersect. The M × n discharge cells are formed in the discharge space. FIG. 2 shows a pixel Px including discharge cells DCr, DCg, and DCb that emit red, green, and blue light.

  As shown in FIG. 1, the plasma display apparatus according to the present embodiment includes a signal processing unit 100, a drive signal generation unit 110, a data write drive unit 120, a sustain drive unit 130, an erase drive unit 140, and a black time determination unit 150. The gradation determination unit 160 is provided. The signal processing unit 100 generates subfield data Rsf2, Gsf2, and Bsf2 from the input synchronization signal Ssync and the image signals Ri, Gi, and Bi, and outputs them to the drive signal generation unit 110 together with the synchronization signal Ssync. The signal processing unit 100 will be described in detail later.

  The drive signal generation unit 110 generates write data and a synchronization signal for operating the drive units 120 to 140 from the synchronization signal Ssync and the subfield data Rsf2, Gsf2, and Bsf2 input from the signal processing unit 100. The data write drive unit 120 applies a scan pulse to the scan electrode 22 and applies a write pulse to the data electrode 32 based on the write data and the synchronization signal from the drive signal generation unit 110 in the write period to emit light. An address operation is performed in which address discharge is selectively generated in the power discharge cells DC to form wall charges. Based on the synchronization signal from the drive signal generator 110, the sustain driver 130 displays the number of sustain pulses corresponding to the luminance weight predetermined for each subfield in the sustain period, including the scan electrodes 22 and the sustain electrodes 23. A sustain operation is performed in which a discharge is generated by applying a sustain discharge in the discharge cells DC that have generated the address discharge alternately by being applied to the electrode pair 24 alternately. The erase driver 140 applies a voltage to the display electrode pair 24 including the scan electrode 22 and the sustain electrode 23 in the erase period based on the synchronization signal from the drive signal generator 110, and discharges the address discharge in the immediately preceding address period. An erase discharge is selectively generated only in the generated discharge cells DC, the history of wall charges formed by the address discharge or the subsequent sustain discharge is erased, and the wall charges necessary for the subsequent address discharge are formed on each electrode. Perform an erase operation. The black time determination unit 150 counts the time during which the turn-off continues for one pixel or a plurality of pixels, and determines whether the turn-off duration exceeds a preset time. The gradation determination unit 160 calculates an average gradation of the input video signal and determines whether the calculated average gradation is equal to or greater than a preset threshold value. In the present embodiment, the data write driving unit 120, the sustain driving unit 130, and the erasing driving unit 140 correspond to an example of a driving unit, and the black time determination unit 150 corresponds to an example of a third determination unit. The determination unit 160 corresponds to an example of a second determination unit.

  FIG. 4 is a schematic diagram illustrating driving of the panel 10 in the present embodiment. The plasma display device displays an image on the panel 10 by subfield method, that is, dividing one field into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield.

  As shown in FIG. 4, the configuration of the subfields generated by the drive signal generation unit 110 is, for example, one field into eight subfields of a first subfield SF1,..., An eighth subfield SF8. Each subfield has a luminance weight of p, 1, 2, 4, 8, 16, 32, 64, for example. However, p <1. As shown in FIG. 4, no initialization period is provided in any subfield. Further, the sustain period is not provided in the first first subfield SF1, and the sustain period is provided in the second to eighth subfields SF2 to SF8 thereafter. The present invention is not limited to the subfield configuration such as the number of subfields and the luminance weight.

  FIG. 5 is a schematic diagram for explaining the light emission probability of the luminance weight p. The luminance weight p is described with reference to FIG.

  The level L1 in FIG. 5 corresponds to the brightness of the luminance weight 1 that the second subfield SF2 has in the driving shown in FIG. That is, when the level of the input signal is equal to or higher than the level L1, the light emission probability of the second subfield SF2 having the luminance weight 1 is 100%. When the level of the input signal is lower than the level L1, the light emission probability according to the level. Also lower.

  On the other hand, the level L0 in FIG. 5 corresponds to the brightness of the minimum luminance weight p of the first subfield SF1 in the driving shown in FIG. That is, when the level of the input signal is equal to or higher than the level L0, the light emission probability of the first subfield SF1 having the luminance weight p is 100%, and when the level of the input signal is lower than the level L0, the light emission probability according to the level. Also lower. From FIG. 5, it can be seen that the first subfield SF1 having the luminance weight p (p <1) has a higher light emission probability than the second subfield SF2 having the luminance weight 1.

  When the initialization period is not provided in the subfield, as described above, there is a high possibility that a discharge failure will occur in the address discharge. However, in the drive shown in FIG. 4, the light emission probability of each discharge cell is increased by providing the first subfield SF1 having the luminance weight p (p <1). When a discharge cell emits light, the charge of the discharge cell is activated by the light emission, so that the light emission probability of each discharge cell increases, thereby preventing the occurrence of discharge failure without providing an initialization period. It becomes possible.

  In the first subfield SF1, as described above, no sustain period is provided. In the first subfield SF1, light emission with luminance weight p is realized by address discharge in the address period, not by sustain discharge by the sustain pulse. In the first subfield SF1 having the luminance weight p, since the luminance weight p is small, there is almost no contribution to the video as luminance. However, according to the observations by the inventors, as described above, it is clear that when the light emission of the luminance weight p is simultaneously performed in the adjacent pixels in the first subfield SF1, a conspicuous bright spot is generated and the image quality is deteriorated. It became.

  Therefore, in this embodiment, by providing the first subfield SF1 having the luminance weight p (p <1), the signal processing unit 100 simultaneously prevents adjacent pixels in the first subfield SF1 from being generated. Generation of bright spots is suppressed by avoiding lighting. In the present embodiment, the first subfield SF1 corresponds to an example of a specific subfield.

  FIG. 6 is a block diagram showing a configuration of the signal processing unit 100 shown in FIG. As shown in FIG. 6, the signal processing unit 100 includes a first subfield (SF) tone correction unit 210, a vertical error diffusion processing unit 220, a subfield conversion unit 240, and a first subfield (SF) thinning unit 250. Is provided. The first subfield gradation correction unit 210 corrects the input image signals Ri, Gi, Bi to generate correction signals Rc, Gc, Bc, and synchronizes the generated correction signals Rc, Gc, Bc. It is output to the vertically long error diffusion processing unit 220 together with the signal Ssync. The vertical error diffusion processing unit 220 performs vertical error diffusion processing based on the input correction signals Rc, Gc, and Bc so that the light is turned on or off continuously in the vertical direction, and the processed diffusion signals Rdf, Gdf, and Bdf are processed. Is output to the subfield conversion unit 240. The subfield conversion unit 240 performs a known conversion process for converting the input spread signals Rdf, Gdf, and Bdf into subfield data, and converts the subfield data Rsf1, Gsf1, and Bsf1 after the conversion process into a first subfield thinning unit. Output to 250. The first subfield thinning unit 250 performs a 50% thinning process on the subfield data Rsf1, Gsf1, and Bsf1 of the first subfield SF1, and generates a drive signal for the subfield data Rsf2, Gsf2, and Bsf2 after the thinning process. Output to the unit 110. In the present embodiment, the first subfield gradation correction unit 210 corresponds to an example of a gradation correction unit, the vertical error diffusion processing unit 220 corresponds to an example of an error diffusion processing unit, and the first subfield thinning unit Reference numeral 250 corresponds to an example of a thinning processing unit. Hereinafter, the first subfield tone correction unit 210, the vertical error diffusion processing unit 220, and the first subfield thinning unit 250 will be described in detail with reference to the drawings.

  FIG. 7 is a schematic diagram for explaining the function of the first subfield gradation correction unit 210. In FIG. 7, level L3 is an input signal level at which the first subfield SF1 (luminance weight p) is turned on by 50%, and level L4 is an input at which the first subfield SF1 (luminance weight p) is turned on by 100%. This is the signal level. In addition, a luminance curve P1 indicated by a broken line in FIG. 7 indicates a state where the input signal is not corrected.

The first subfield tone correction unit 210 corrects the luminance curve P1 indicating no correction so that the input signal level increases as indicated by the luminance curve P2. Specifically, the first subfield gradation correction unit 210 corrects the signal level at which the first subfield SF1 is turned on by 50% in the uncorrected state by raising the signal level by 50% so that the first subfield SF1 is turned on by 100%. I do. In the signal level where the first subfield SF1 is lit from 0% to 50%, the first subfield gradation correction unit 210
Output signal level = input signal level x 2
To correct. In addition, when the level of the input signal is such that the first subfield SF1 is lighted by 50% or more, the first subfield gradation correction unit 210 has the amount that the first subfield SF1 is lighted by 50% at the original input signal level. Just make a correction to raise.

  When the first subfield thinning unit 250 performs the 50% thinning process on the first subfield SF1 by the increase correction of the first subfield gradation correction unit 210, the original “no correction” luminance is obtained. It corresponds to the curve P1.

  As a comparative example, the luminance curve P3 shown in FIG. 7 shows the luminance when 50% thinning processing is performed by the first subfield thinning unit 250 without performing correction by the first subfield gradation correcting unit 210. The corresponding output signal level is shown.

  FIG. 8 is a block diagram showing the configuration of the vertically long error diffusion processing unit 220. The processing by the vertical error diffusion processing unit 220 is performed for each of the R, G, and B signals. For convenience of explanation, only the configuration for the R signal is shown in FIG.

  The input correction signal Rc is divided into an integer part and a decimal part. The decimal part is sent to the adder 221 and the integer part is sent to the adder 225. The adder 221 adds the spread error input from the T delay buffer 223 and the line delay buffer 224 and the decimal part of the correction signal Rc. In the addition result of the adder 221, when it is raised to an integer, it is distributed to the integer part and the decimal part that are raised, the integer part is sent to the adder 225, and the decimal part is sent to the decimal part distribution unit 222. The fractional distribution unit 222 distributes the decimals to the T delay buffer 223 and the line delay buffer 224 at a ratio set in advance as the error diffusion direction. The T delay buffer 223 is composed of, for example, a flip-flop, and delays input data by one pixel and outputs it to the adder 221. The line delay buffer 224 is composed of, for example, an SRAM, and delays input data by one line and outputs it to the adder 221. That is, the error is propagated to the pixel on the right by the T delay buffer 223, and the error is propagated to the pixel immediately below by the line delay buffer 224.

  The adder 225 outputs the integer part that is the result of the error diffusion processing to the line delay buffer 226 and the exclusive OR processing unit 227. The line delay buffer 226 is composed of, for example, an SRAM, and delays input data by one line and outputs it to the exclusive OR processing unit 227. The exclusive OR processing unit 227 performs first subtraction on input data for two lines, that is, current pixel-of-interest data and pixel data on one line of the pixel of interest (one-line past data). The difference of the first bit data corresponding to the field SF1 is distributed as an error. The exclusive OR processing unit 227 outputs the distributed error to the line delay buffer 228 and outputs the remainder of the distributed error to the line delay buffer 229. The line delay buffer 228 is composed of, for example, an SRAM, and delays input data by one line and outputs it to the adder 221. The line delay buffer 229 is composed of, for example, an SRAM, and delays input data by one line and outputs it to the output line selector 230. The output line selector 230 sequentially sends the input data to the subfield conversion unit 240 as diffusion signals Rdf, Gdf, and Bdf as error diffusion processing results.

  9 to 13 are diagrams for explaining the operation of the vertical error diffusion processing unit 220 shown in FIG. In FIG. 9 to FIG. 13, for the sake of simplicity of explanation, all input data is set to 0.5, and errors are propagated 100% downward. That is, the decimal number distribution unit 222 outputs all the input decimal numbers to the line delay buffer 224.

  First, an outline of error diffusion processing by the vertically long error diffusion processing unit 220 will be described. In this error diffusion process, a process for making the first bit (corresponding to the first subfield SF1) of the integer part common in units of two lines is performed following the normal error diffusion process. That is, normal error diffusion processing is performed by the adders 221 and 225, the decimal number distribution unit 222, the T delay buffer 223, and the line delay buffer 224. The result of this normal error diffusion processing is delayed by one line by the line delay buffer 226, and the result of error diffusion processing for two lines is compared by the exclusive OR processing unit 227. If both the first bits are different, an error is sent to the lower line. Then, the line delay buffer 229 outputs the result of error diffusion processing line by line.

  Next, the operation when data of the first line LN1 is input will be described with reference to FIG. When the input data = 0.5 of the first line LN1 is input, it is distributed to the integer part = 0 and the decimal part = 0.5. The decimal part = 0.5 is sent to the adder 221, and 0 is added by the adder 221, and an error addition result = 0.5 is obtained. As a result, the carry of the integer part = 0 is distributed to the decimal part = 0.5, and the decimal part = 0.5 is sent to the decimal part 222. As described above, since the decimal number distribution unit 222 distributes 100% to the line delay buffer 224, T delay error = 0 and line delay error = 0.5. On the other hand, since the carry of the integer part that is the addition result of the adder 221 is 0, the output as the error diffusion processing result by the addition result of the adder 225 is 0.

  Next, the operation when the data of the second line LN2 is input will be described using FIG. When the input data = 0.5 of the second line LN2 is input, it is distributed to the integer part = 0 and the decimal part = 0.5. The decimal part = 0.5 is sent to the adder 221. Here, the line delay error = 0.5 (see FIG. 9) of the upper line, that is, the first line LN1, is input to the adder 221 from the line delay buffer 224. Further, T delay error = 0 (see FIG. 9) from the left adjacent pixel is input to the adder 221 from the T delay buffer 223. Therefore, the error addition result = 1.0 by the adder 221 is obtained. As a result, the carry of the integer part = 1 is assigned to the decimal part = 0, and the decimal part = 0 is sent to the decimal part assignment part 222. As a result, the outputs of the fractional sorting unit 222 are T delay error = 0 and line delay error = 0.

  On the other hand, since the carry of the integer part by the addition result of the adder 221 is 1, the output as the error diffusion processing result by the addition result of the adder 225 becomes 1, which is exclusive as the output of the second line LN1 = 1. To the logical OR processing unit 227. At the same time, the output of the first line LN 1 delayed by one line = 0 (see FIG. 9) is sent from the line delay buffer 226 to the exclusive OR processing unit 227. Since the difference between the output of the first line LN1 and the output of the second line LN2 is 1, the exclusive OR processing unit 227 sends the difference of the first subfield SF1 = 1 to the line delay buffer 228. On the other hand, from the exclusive OR processing unit 227, the output = 0 of the first line LN1 is sent to the output line selector 230, and the output = 0 of the second line LN2 is sent to the line delay buffer 229. As a result, the output = 0 of the first line LN1 is output from the output line selector 230.

  Next, the operation when the data of the third line LN3 is input will be described using FIG. When the input data = 0.5 of the third line LN3 is input, it is distributed to the integer part = 0 and the decimal part = 0.5. The decimal part = 0.5 is sent to the adder 221. Here, the line delay error = 0 (see FIG. 10) of the upper line, that is, the second line LN2, is input to the adder 221 from the line delay buffer 224. Further, T delay error = 0 (see FIG. 10) from the left adjacent pixel is input from the T delay buffer 223 to the adder 221. Further, the difference of the first subfield SF1 = 1 (see FIG. 10) is input from the line delay buffer 228 to the adder 221. Therefore, the error addition result = 1.5 by the adder 221 is obtained. As a result, the carry of the integer part = 1 is assigned to the decimal part = 0.5, and the decimal part = 0.5 is sent to the decimal part distribution part 222. As a result, the outputs of the fractional sorting unit 222 are T delay error = 0 and line delay error = 0.5.

  On the other hand, since the carry of the integer part by the addition result of the adder 221 is 1, the output as the error diffusion processing result by the addition result of the adder 225 becomes 1 and is sent to the line delay buffer 226. On the other hand, the output = 0 (see FIG. 10) of the second line LN 2 delayed by one line is sent from the line delay buffer 229 to the output line selector 230. As a result, the output of the second line LN2 = 0 is output from the output line selector 230.

  Next, the operation when the data of the fourth line LN4 is input will be described using FIG. When the input data = 0.5 of the fourth line LN4 is input, it is distributed to the integer part = 0 and the decimal part = 0.5. The decimal part = 0.5 is sent to the adder 221. Here, to the adder 221, the line delay error of the upper line, that is, the third line LN3 = 0.5 (see FIG. 11) is input from the line delay buffer 224. Further, T delay error = 0 (see FIG. 11) from the left adjacent pixel is input from the T delay buffer 223 to the adder 221. Therefore, the error addition result = 1.0 by the adder 221 is obtained. As a result, the carry of the integer part = 1 is assigned to the decimal part = 0, and the decimal part = 0 is sent to the decimal part assignment part 222. As a result, the outputs of the fractional sorting unit 222 are T delay error = 0 and line delay error = 0.

  On the other hand, since the carry of the integer part by the addition result of the adder 221 is 1, the output as the error diffusion processing result by the addition result of the adder 225 becomes 1, which is exclusive as the output of the fourth line LN4 = 1. To the logical OR processing unit 227. At the same time, the output of the third line LN 3 delayed by one line = 1 (see FIG. 11) is sent from the line delay buffer 226 to the exclusive OR processing unit 227. Since the difference between the output of the third line LN1 and the output of the second line LN2 is zero, the difference between the first subfield SF1 = 0 is sent from the exclusive OR processing unit 227 to the line delay buffer 228. On the other hand, from the exclusive OR processing unit 227, the output of the third line LN3 = 1 is sent to the output line selector 230, and the output of the fourth line LN4 = 1 is sent to the line delay buffer 229. As a result, the output of the third line LN3 = 1 is output from the output line selector 230.

  Next, the operation when the data of the fifth line LN5 is input will be described using FIG. When the input data = 0.5 of the fifth line LN5 is input, it is distributed to the integer part = 0 and the decimal part = 0.5. The decimal part = 0.5 is sent to the adder 221. Here, since the errors inputted to the adder 221 from the line delay buffer 224, the T delay buffer 223, and the line delay buffer 228 are all error = 0, the error addition result by the adder 221 = 0.5. Is obtained. As a result, the carry of the integer part = 0 is distributed to the decimal part = 0.5, and the decimal part = 0.5 is sent to the decimal part 222. As a result, the outputs of the fractional sorting unit 222 are T delay error = 0 and line delay error = 0.5.

  On the other hand, since the carry of the integer part by the addition result of the adder 221 is 0, the output as the error diffusion processing result by the addition result of the adder 225 becomes 0 and is sent to the line delay buffer 226. On the other hand, the output of the fourth line LN4 delayed by one line = 1 (see FIG. 12) is sent from the line delay buffer 229 to the output line selector 230. As a result, the output of the fourth line LN4 = 1 is output from the output line selector 230.

  With the above processing, in normal error diffusion processing, the decimal gradation 0.5 is output as halftones of integer gradations 0, 1, 0, 1, 0, 1, 0, 1,. Are converted into vertically long particles and output as 0, 0, 1, 1, 0, 0, 1, 1,. That is, two pixels in the column direction (second direction) are turned on or off simultaneously.

  FIG. 14 is a block diagram showing a configuration of the first subfield thinning unit 250. FIG. 15 is a schematic diagram for explaining checkered thinning processing. 15A shows an example of an input image, FIG. 15B shows an error diffusion processing result by the vertical error diffusion processing unit 220, FIG. 15C shows a processing result by checkered thinning processing, FIG. 15D shows correction target pixels selected in a checkered pattern. FIG. 16 is a schematic diagram for explaining interlace thinning processing. FIG. 16A shows an example of an input image, FIG. 16B shows an error diffusion processing result by the vertically long error diffusion processing unit 220, FIG. 16C shows a processing result by interlaced thinning processing, FIG. 16D shows correction target pixels selected in an interlaced manner. In FIG. 15 and FIG. 16, for example, the input image signal is the R signal and the lighting state of the R pixel is shown, but the same applies to the G and B pixels. The thinning process by the first subfield thinning unit 250 will be described with reference to FIGS. 14 to 16.

  The first subfield thinning unit 250 includes a coordinate counter 251, a mask signal generation unit 252, a signal conversion unit 253, a mask determination unit 254, and a first subfield (SF) mask unit 255. The coordinate counter 251 counts pixel coordinates based on the synchronization signal Ssync. The signal conversion unit 253 performs conversion processing for returning the subfield data Rsf1, Gsf1, and Bsf1 to the original spread signals Rdf, Gdf, and Bdf, and converts the spread signals Rdf, Gdf, and Bdf that are processing results into the mask signal generation unit 252 and the mask determination. Output to the unit 254.

  The mask signal generation unit 252 generates a mask signal for correcting the signal level of the correction target pixel to zero based on the count value from the coordinate counter 251, and outputs the mask signal to the mask determination unit 254. As shown in FIG. 15 (d), the mask signal generation unit 252 generates a first mask signal that uses a pixel selected in a checkered pattern from pixels arranged in a matrix as a correction target pixel. Further, as shown in FIG. 16D, the mask signal generator 252 is arranged in a pixel column selected in an interlaced manner among pixels arranged in a matrix, that is, in a row direction (first direction). A second mask signal is generated with the selected pixel columns Pc11 and Pc12 selected every other column in the column direction (second direction) as the correction target pixels.

  The mask determination unit 254 determines whether or not to perform the thinning process based on the level of the spread signals Rdf, Gdf, and Bdf from the signal conversion unit 253, and when determining that the thinning process is performed, the mask signal generation unit The mask signal sent from 252 is sent to the first subfield mask unit 255. For example, the mask determination unit 254 determines not to perform the thinning process when the levels of the diffusion signals Rdf, Gdf, and Bdf are equal to or higher than a specific gradation. The specific gradation is, for example, a gradation that can ignore a change in luminance caused by thinning out the first subfield SF1. For example, the specific gradation refers to a gradation in which not only the first subfield SF1, but also the second subfield SF2 with one luminance weight and the third subfield SF3 with two luminance weights are all lit. When the thinning process is not performed, the first subfield gradation correction unit 210 increases the luminance by 50%, and the vertical error diffusion processing unit 220 has a portion where two adjacent pixels are lit simultaneously. However, since the bright spot is inconspicuous at the gradation above the gradation at which all of the first to third subfields SF1, SF2, and SF3 are lit, the image quality does not deteriorate even if the thinning process is not performed.

  Further, for example, when the black time determination unit 150 determines that the turn-off duration exceeds a preset time, the mask determination unit 254 sets the correction target pixel as a pixel selected in an interlaced manner. It is determined that the thinning process is performed. This increases the probability of occurrence of defective discharge due to the long turn-off duration, but it is possible to suppress the occurrence of defective discharge for pixels adjacent in the row direction (first direction) as compared with checkered thinning processing. . Further, for example, when the black time determination unit 150 determines that the turn-off duration is equal to or less than a preset set time, the mask determination unit 254 sets the correction target pixel as a pixel selected in a checkered pattern. It is determined that processing is to be performed. As a result, the pixels adjacent in the row direction (first direction) and the pixels adjacent in the column direction (second direction) do not light up at the same time, so that the image quality can be improved compared to the second thinning process. .

  For example, when the gradation determination unit 160 determines that the average gradation of the video signal is equal to or higher than a preset threshold, the mask determination unit 254 sets the correction target pixel as a checkered pixel. It is determined that one thinning-out processing is performed. Since the average gradation of the video signal is equal to or greater than the threshold value, the lighting probability of each pixel is high, so that the image quality can be improved without increasing the occurrence of defective discharge by performing checkered thinning processing. . For example, when the gradation determination unit 160 determines that the average gradation of the video signal is less than a preset threshold, the mask determination unit 254 sets the correction target pixel as a pixel selected in an interlaced manner. It is determined that 2-thinning processing is performed. Since the average gradation of the video signal is less than the threshold value, the lighting probability of each pixel is low. However, the occurrence of discharge failure can be suppressed by performing interlaced thinning processing.

  Further, when the mask determination unit 254 determines to perform the first thinning process, the mask determination unit 254 outputs a first mask signal that sets the correction target pixel as a checkered pixel to the first subfield mask unit 255, and When it is determined that the two-thinning process is to be performed, a second mask signal having the pixel row selected in an interlaced manner as a correction target pixel is output to the first subfield mask unit 255.

  The first subfield mask unit 255 performs a thinning process on the data of the first subfield SF1 among the input subfield data Rsf1, Gsf1, and Bsf1 using the mask signal sent from the mask determination unit 254. Subfield data Rsf2, Gsf2, and Bsf2 are generated and output to the drive signal generator 110 (FIG. 1).

  For example, when the error diffusion processing by the vertically long error diffusion processing unit 220 is performed on the input image shown in FIG. 15A, the processing result shown in FIG. 15B is obtained. In FIG. 15B, the red sub-pixel Pr1, the red sub-pixel Pr2 adjacent to the red sub-pixel Pr1 in the row direction (first direction), and the red sub-pixel Pr1 are adjacent to the column direction (second direction). A red sub-pixel Pr3 and pixel columns Pc1 and Pc2 arranged in the row direction are shown. As shown in FIG. 15B, a pair of pixels that are adjacent to each other in the column direction and are composed of the pixels in the pixel column Pc1 and the pixels in the pixel column Pc2 are turned on or off at the same time. For example, the red subpixel Pr1 and the red subpixel Pr3 are turned on simultaneously. When the video signal of each pixel in the first subfield SF1 is masked by the checkered mask signal shown in FIG. 15D in the state shown in FIG. 15B, each pixel is shown in FIG. ) As shown in FIG. The red sub-pixel corresponds to the discharge cell DCr (FIG. 2) that emits red light.

  For example, when the error diffusion processing by the vertically long error diffusion processing unit 220 is performed on the input image shown in FIG. 16A, the processing result shown in FIG. 16B is obtained as in FIG. 15B. can get. In the state shown in FIG. 16B, when the video signal of each pixel in the first subfield SF1 is masked by the interlaced mask signal shown in FIG. 16D, each pixel is shown in FIG. ). In the present embodiment, the mask determination unit 254 corresponds to an example of a first determination unit. A pixel including the red subpixel Pr1 corresponds to an example of the first pixel, a pixel including the red subpixel Pr2 corresponds to an example of the second pixel, and a pixel including the red subpixel Pr3 is an example of the third pixel. Correspondingly, the pixel column Pc1 corresponds to the first pixel column, and the pixel column Pc2 corresponds to the second pixel column.

  FIG. 17 is a diagram schematically illustrating a lighting state of each pixel according to the present embodiment. 18 to 22 are diagrams schematically illustrating lighting states of the pixels according to the comparative example. 17 to 22 show, for example, the lighting state of the R pixel. The effects of the present embodiment will be described with reference to FIGS.

  In FIG. 19, the subfield is not provided with an initialization period, does not include the subfield with the luminance weight p (that is, the first subfield SF1 of the present embodiment), and has a luminance field of 1 or more (for example, the present embodiment). In the case where only the second to eighth subfields SF2 to SF8) are included, the case where the normal error diffusion processing is performed is schematically shown. FIG. 19A shows an input image. FIG. 19B shows a state where error diffusion processing has been performed on the input image shown in FIG. In the lower part of FIG. 19B, the signal level of each pixel is schematically shown by shades of hatching. FIG. 19C shows a lighting state on the screen. In the lower part of FIG. 19C, the lighting state of each pixel is schematically shown by shades of hatching. As can be seen by comparing FIG. 19B and FIG. 19C, since no initialization period is provided, a discharge failure occurs and each pixel is difficult to light.

  FIG. 20 schematically shows a case where normal error diffusion processing is performed in the case where the initialization period is not provided in the subfield and the subfield of the luminance weight p is included (that is, the first subfield SF1 of the present embodiment). Is shown. FIG. 20A shows an input image. FIG. 20B shows a state where error diffusion processing has been performed on the input image shown in FIG. In the lower part of FIG. 20B, the signal level of each pixel is schematically shown by shades of hatching. FIG. 20C shows a lighting state on the screen. In the lower part of FIG. 20C, the lighting state of each pixel is schematically shown by shaded shades. In FIG. 20C, although the discharge failure has occurred, the lighting probability of each pixel is increased by the subfield of the luminance weight p, and therefore, it is reduced compared to FIG. 19C. On the other hand, since a bright spot is generated at a location that is continuously lit with adjacent pixels, the gradation is degraded in the subfield of the luminance weight p.

  FIGS. 21 and 22 show an example in which the luminance is maintained by thinning out the number of lines in a specific subfield and extending the sustain period by the thinned out amount. FIG. 21A shows an example of the lighting state of each pixel after performing the error diffusion process. In the state shown in FIG. 21A, when the odd lines are turned off as the half-line thinning process, the state shown in FIG. In FIG. 21B, the brightness is much darker than half of the state of FIG. 21A due to the half-line thinning process. After this thinning process, if the sustain period of the subfields that were not thinned is doubled, the state shown in FIG. Since the screen is too dark at the time of the thinning process in FIG. 21B, the entire screen remains dark in FIG. 21C even if the sustain period of the lit pixels is doubled. It has become.

  On the other hand, when the even-numbered lines are turned off as the half-line thinning process with respect to the state shown in FIG. 21A, the state shown in FIG. In FIG. 21 (d), even if the half-thinning process is performed, the brightness is more than 1/2 compared to the state of FIG. 21 (a), and it is not darkened to 1/2. After the thinning process, if the sustain period of the subfield that has not been thinned is doubled, the state shown in FIG. Since the screen is bright at the time of the thinning process in FIG. 21D, in FIG. 21E, if the sustain period of the lit pixels is doubled, the entire screen becomes too bright.

  FIG. 22A shows another example of the lighting state of each pixel after performing error diffusion processing. In the state of FIG. 22A, when the odd lines are turned off as the half-line thinning process, the entire screen is turned off and very dark as shown in FIG. For this reason, even if the sustain period of the subfields that are not thinned out is doubled, the entire screen remains dark as shown in FIG. On the other hand, in the state shown in FIG. 22A, when the even-numbered line is turned off as the half-line thinning process, as shown in FIG. 22D, it is not different from FIG. After this thinning process, if the sustain period of the subfields that were not thinned is doubled, the entire screen becomes too bright as shown in FIG. Thus, in the examples of FIGS. 21 and 22, the gradation is degraded.

  FIG. 18 schematically shows a case where normal error diffusion processing is performed in the subfield configuration of the present embodiment. FIG. 18A shows an input image signal, and shows an image signal in which the signal level of each pixel is p / 4 (that is, 1/4 of the luminance weight p of the first subfield SF1). When a normal error diffusion process is performed when the image signal shown in FIG. 18A is input, the ratio of the pixels in the first subfield SF1 is 1/4 as shown in FIG. 18B. (4 in FIG. 18B) lights up.

  The present embodiment will be described with reference to FIG. FIG. 17A shows an input image signal. Similarly to FIG. 18A, the signal level of each pixel is p / 4 (that is, 1/4 of the luminance weight p of the first subfield SF1). An image signal is shown. When the image signal shown in FIG. 17A is input, first, as described with reference to FIGS. 6 and 7, the first subfield tone correction unit 210 has a signal level of p / 2. The image signal is corrected so as to increase. In FIG. 17 (b), the increase in signal level with respect to FIG. 17 (a) is schematically shown by the density of hatching.

  Next, as described with reference to FIG. 6 and FIGS. 8 to 13, the vertical error diffusion processing unit 220 is configured such that the pixels in the first subfield SF1 are arranged in the column direction. A vertically long error diffusion process is performed so that the light is turned on or off continuously every two lines. As a result, as shown in FIG. 17C, two pixels are continuously turned on or off in the column direction in the first subfield SF1. Further, by this error diffusion processing, the pixels in the first subfield SF1 are lit at a ratio of 1/2 (eight in FIG. 17B).

  Next, as described with reference to FIGS. 6 and 14 to 16, the first subfield thinning unit 250 performs a thinning process that turns off each pixel of the first subfield SF <b> 1 in a checkered pattern or an interlaced pattern. . In FIG. 17D, interlaced thinning processing is performed. As a result of this thinning process, as shown in FIG. 17D, the pixels in the first subfield SF1 are lit at a ratio of 1/4 (four in FIG. 17D). As a result, the same result as in FIG. 18D is obtained in FIG.

  As described above, in the present embodiment, on the assumption that the data of the first subfield SF1 is decimated to 1/2 in the subsequent stage, the first subfield gradation correction unit 210 performs the subfield to be decimated. In other words, a signal level corresponding to 1/2 of the luminance of the first subfield SF1 is added in advance. In addition, when performing error diffusion processing, the vertical error diffusion processing unit 220 has pixels arranged in the column direction in the row direction so that the luminance is always ½ when thinning is performed in the subsequent stage. Halftoning is performed so that the light is turned on or off continuously every two lines. Further, the first subfield thinning unit 250 performs a thinning process in an interlaced or checkered pattern. Since one pixel out of two pixels is always thinned out by the interlaced or checkered thinning process, it is possible to ensure that the luminance is always halved (that is, returns to the level of the input signal). In addition, the generation of bright spots can be prevented by the interlaced or checkered thinning process. As a result, deterioration in image quality can be suppressed.

  In the present embodiment, since the first subfield SF1 having the luminance weight p (p <1) is provided, the lighting probability of each pixel can be increased. As a result, the occurrence of defective discharge can be suppressed without providing an initialization period.

  In the above-described embodiment, as described with reference to FIGS. 1 and 6, the signal processing unit 100 performs signal processing for each of the R, G, and B signals. This prevents adjacent pixels from being lit simultaneously in the first subfield SF1. In other words, in the above-described embodiment, by performing the first thinning process in which the correction target pixel is a pixel selected in a checkered pattern, the discharge cells of the same color adjacent in the row direction and the same color adjacent in the column direction This prevents the discharge cells from being turned on simultaneously. Further, in the above embodiment, the second thinning process is performed in which the correction target pixel is a pixel selected in an interlaced manner, thereby preventing discharge cells of the same color adjacent in the column direction from being lit simultaneously. However, the thinning process of the present invention is not limited to this.

  23 and 24 are schematic diagrams schematically showing another form of the thinning process. 23 and 24 show pixels arranged in a matrix and discharge cells included in the pixels. 23 and 24, the discharge cells to be masked are shown in black, and the discharge cells not masked are shown in white.

  In the example shown in FIG. 23, every discharge signal of the same color adjacent in the row direction (first direction) is masked every other R, G, and B signals to prevent simultaneous lighting. For example, the red discharge cell DCr1 of the pixel Px1 is masked, and the red discharge cell DCr2 of the pixel Px2 adjacent in the row direction is not masked. For example, the green discharge cell DCg1 of the pixel Px1 is not masked, and the green discharge cell DCg2 of the pixel Px2 adjacent in the row direction is masked. For example, the blue discharge cell DCb1 of the pixel Px1 is not masked, and the blue discharge cell DCb2 of the pixel Px2 adjacent in the row direction is masked.

  In the example shown in FIG. 24A, discharge cells adjacent in the row direction (first direction) and discharge cells adjacent in the column direction (second direction) are prevented from being lit simultaneously. That is, adjacent discharge cells are prevented from being lit simultaneously in the same pixel as well as between adjacent pixels. For example, the red discharge cell DCr1 of the pixel Px1 is masked, the green discharge cell DCg1 adjacent in the row direction is not masked, the blue discharge cell DCb1 adjacent in the row direction is further masked, and the pixel Px2 adjacent in the row direction is further masked. The red discharge cell DCr2 is not masked. In the pixel Px3 adjacent to the pixel Px1 in the column direction, the red discharge cell DCr3 is not masked, the green discharge cell DCg3 is masked, and the blue discharge cell DCb3 is not masked. In the form shown in FIG. 24A, the pixel Px1 corresponds to an example of the first pixel, the pixel Px2 adjacent to the pixel Px1 in the row direction corresponds to an example of the second pixel, and is adjacent to the pixel Px1 in the column direction. The pixel Px3 to correspond corresponds to an example of a third pixel. The blue discharge cell DCb1 of the pixel Px1 corresponds to an example of the first discharge cell, the red discharge cell DCr2 adjacent to the blue discharge cell DCb1 in the row direction corresponds to an example of the second discharge cell, and the blue discharge cell DCb1 The blue discharge cell DCb3 adjacent in the column direction corresponds to an example of a third discharge cell. The green discharge cell DCg1 of the pixel Px1 adjacent to the blue discharge cell DCb1 of the pixel Px1 corresponds to an example of a fourth discharge cell.

  In the example shown in FIG. 24B, discharge cells adjacent in the row direction (first direction) are prevented from being lit simultaneously. In the example shown in FIG. 24C, discharge cells adjacent in the column direction (second direction) are prevented from being lit simultaneously.

  Moreover, in the said embodiment, although the black time determination part 150 is provided, the black time determination part 150 is not an essential structure. Alternatively, the black time determination unit 150 may not be provided. Similarly, although the gradation determination unit 160 is provided in the above embodiment, the gradation determination unit 160 is not an essential configuration. Alternatively, the gradation determination unit 160 may not be provided. Moreover, in the said embodiment, although the mask determination part 254 is provided and it is determined whether mask processing is performed, it replaces with 1st thinning-out process or 2nd thinning-out process without providing the mask determination part 254 instead. Either of the above may always be performed.

  The present invention is useful as a plasma display device and a method for driving a plasma display panel because it can suppress the occurrence of defective discharge without providing an initialization period and can prevent deterioration of image quality.

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 110 Drive signal production | generation part 120 Data write drive part 130 Maintenance drive part 140 Erase drive part 150 Black time determination part 160 Gradation determination part 210 1st subfield floor Tone correction unit 220 Vertical error diffusion processing unit 250 First subfield thinning unit DC discharge cell

Claims (10)

A plasma display device for displaying an image based on an input image signal,
A plurality of display electrode pairs each consisting of a scan electrode and a sustain electrode extending in the first direction, a plurality of data electrodes extending in a second direction intersecting the first direction, and the display electrode pair and the data electrode intersecting each other. A plasma display panel comprising: a pixel having a discharge cell formed in a portion;
A driving unit that applies a driving voltage to at least one of the scan electrode, the sustain electrode, and the data electrode so that the luminance weights are different for each of a plurality of subfields included in one field period;
A control unit for controlling the driving unit;
With
In each of the plurality of subfields, an initializing discharge is generated to activate a charge in the discharge cell by applying a driving voltage between the scan electrode, the data electrode, and the sustain electrode. Not including the conversion period, including the predetermined writing period,
Each of the subfields other than the specific subfield among the plurality of subfields includes a predetermined sustain period after the writing period,
In the address period, the driving unit applies a scan pulse to the scan electrode and an address pulse to the data electrode to selectively generate an address discharge in the discharge cells,
The driving unit alternately applies a sustain pulse corresponding to the luminance weight to the scan electrode and the sustain electrode in the sustain period, and generates a sustain discharge in a discharge cell selected in the address period,
The specific subfield includes the sustain period by not including the sustain period or including a sustain period in which the sustain pulse is not applied without the sustain pulse being applied by the driving unit. Having a lower luminance weight,
The plasma display panel includes a first pixel, a second pixel adjacent to the first pixel in the first direction, and a third pixel adjacent to the first pixel in the second direction,
The first pixel includes a first discharge cell,
The second pixel includes a second discharge cell adjacent to the first discharge cell in the first direction;
The third pixel includes a third discharge cell adjacent to the first discharge cell in the second direction;
In the specific subfield, the control unit may prevent the first discharge cell and the second discharge cell from lighting simultaneously and / or the first discharge cell and the third discharge cell from lighting simultaneously. As described above, the plasma display apparatus controls the driving unit. The pixels included in the plasma display panel are arranged in a matrix in the first direction and the second direction,
The controller is
An error diffusion processing unit that performs error diffusion processing on the video signal;
After the error diffusion processing by the error diffusion processing unit, in the specific subfield, the video signal of the correction target pixel selected from the pixels arranged in a matrix is corrected to zero and the correction target pixel is turned off. A decimation processing unit for performing decimation processing,
Including
The thinning-out processing unit includes, as the thinning-out processing, a first thinning-out processing in which pixels selected in a checkered pattern from the pixels arranged in the matrix are the correction target pixels, and the pixels arranged in the matrix Any one of the second thinning-out processing, in which pixels included in the selected pixel column selected every other column in the second direction are arranged in the first direction as the correction target pixel. The plasma display device according to claim 1, wherein the plasma display device is performed. The control unit further includes a gradation correction unit that increases the level of the video signal by a predetermined width and outputs the level to the error diffusion processing unit,
The plasma display apparatus according to claim 2, wherein the error diffusion processing unit performs the error diffusion processing on the video signal that has been increased and corrected by the gradation correction unit. A pixel column that is arranged in the first direction and includes pixels including the first pixel and the second pixel is defined as a first pixel column,
A pixel column composed of pixels arranged in the first direction and including the third pixel is defined as a second pixel column,
After the error diffusion processing, the error diffusion processing unit is configured such that a pair of the pixels that are adjacent to each other in the second direction and include the pixels of the first pixel column and the pixels of the second pixel column are simultaneously turned on or The plasma display device according to claim 2, wherein the error diffusion process is performed so that the light is extinguished. The thinning processing unit includes a first determination unit that determines whether the gradation of each pixel in the specific subfield is equal to or higher than a predetermined specific gradation,
The thinning-out processing unit does not perform either the first thinning-out processing or the second thinning-out processing for the pixels for which the gradation is determined to be equal to or higher than the specific gradation by the first determination unit. The plasma display device according to any one of claims 2 to 4. A second determination unit that calculates an average gradation of the video signal and determines whether the calculated average gradation is equal to or greater than a preset threshold;
The thinning-out processing unit performs the first thinning-out processing when the second determination unit determines that the average gradation is equal to or higher than the threshold, and the second determination unit determines that the average gradation is less than the threshold. The plasma display apparatus according to claim 2, wherein the second thinning process is performed. A third determination unit for measuring a duration of the state in which one or a plurality of pixels are not lit, and determining whether the measured duration exceeds a preset time;
The decimation processing unit performs the second decimation process when the third determination unit determines that the duration exceeds the set time, and determines that the duration is equal to or less than the set time by the third determination unit. 5. The plasma display device according to claim 2, wherein the first thinning process is performed. The first pixel includes a fourth discharge cell adjacent to the first discharge cell in the first direction or the second direction,
8. The control unit according to claim 1, wherein the control unit controls the driving unit so that the first discharge cell and the fourth discharge cell are not turned on simultaneously in the specific subfield. The plasma display device according to item. Each of the first pixels has N (N is an integer greater than or equal to 2) discharge cells including the first discharge cells, which correspond to different predetermined colors.
The third pixel has N discharge cells each corresponding to the set color and including the third discharge cell,
The plasma display apparatus according to any one of claims 1 to 8, wherein the first discharge cell and the third discharge cell correspond to the same color. A plurality of display electrode pairs each consisting of a scan electrode and a sustain electrode extending in the first direction, a plurality of data electrodes extending in a second direction intersecting the first direction, and the display electrode pair and the data electrode intersecting each other. A plasma display panel driving method for driving a plasma display panel including a pixel having a discharge cell formed in a part thereof,
The plasma display panel includes a first pixel, a second pixel adjacent to the first pixel in the first direction, and a third pixel adjacent to the first pixel in the second direction. One pixel includes a first discharge cell, the second pixel includes a second discharge cell adjacent to the first discharge cell in the first direction, and the third pixel includes the second discharge cell in the second direction. Including a third discharge cell adjacent to one discharge cell;
A driving voltage is applied to at least one of the scan electrode, the sustain electrode, and the data electrode by a driving unit so that a luminance weight is different for each of a plurality of subfields included in one field period,
In each of the plurality of subfields, an initializing discharge is generated to activate a charge in the discharge cell by applying a driving voltage between the scan electrode, the data electrode, and the sustain electrode. Configured to include a predetermined writing period, not including
Each of the subfields other than the specific subfield among the plurality of subfields is configured to include a predetermined sustain period after the write period,
In the address period, the drive unit applies a scan pulse to the scan electrode and an address pulse to the data electrode to selectively generate an address discharge in the discharge cells,
In the sustain period, the driving unit alternately applies a sustain pulse corresponding to the luminance weight to the scan electrode and the sustain electrode to generate a sustain discharge in the discharge cells selected in the address period,
The specific subfield includes the sustain period by not including the sustain period or including a sustain period in which the sustain pulse is not applied without the sustain pulse being applied by the driving unit. Configured to have a lower luminance weight,
In the specific subfield, the driving is performed so that the first discharge cell and the second discharge cell are not lit simultaneously and / or so that the first discharge cell and the third discharge cell are not lit simultaneously. A method for driving a plasma display panel, characterized by controlling a unit.