JP2012235066A - Inspection method, processing method of wiring board, wiring board and board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily understand the state of a plated layer.SOLUTION: Terminals 26a, 26b, 31a, 31b are formed on a wiring board 21 which is used in a semiconductor device and on which a semiconductor chip is mounted so that probe terminals 51, 52 for measuring a high frequency property can contact with wiring 23a connected to the pad of the semiconductor chip by a bonding wire. Each of terminals 26a, 26b, 31a, 31b is connected to ground wiring 28 formed in the board 21. Plating having a nickel layer and a gold layer is formed on the wiring 23a. A high frequency signal reaches to the wiring 23a and the high frequency property according to the state of the surface of the plating is obtained by making terminals 26a, 26b and the wiring 23a contact with the probe terminal 51, and terminals 31a, 31b and the wiring 23a contact with the probe terminal 52, separately.

Description

  The present invention relates to an inspection method, a method for processing a wiring board, a wiring board, and a board.

  2. Description of the Related Art Conventionally, a package substrate on which a semiconductor chip is mounted has wiring for connecting pads connected to the pads of the semiconductor chip by bonding wires and connection terminals (for example, bumps) provided for mounting the package. (For example, refer patent document 1). The pads and wirings formed on the substrate are made of, for example, copper. A nickel layer and a gold layer are formed on the surface of the pad and wiring to prevent wire bonding and corrosion. The nickel layer and the gold layer are formed by, for example, an electrolytic plating method.

  The manufacturing process of the package substrate includes the measurement of the thickness of the nickel layer and the gold layer and the measurement of wire bonding characteristics. For film thickness measurement, for example, X-rays are used. In wire bonding characteristic measurement, the tensile strength of bonding is measured. A substrate having a low bonding tensile strength is confirmed by a scanning electron microscope (SEM), and the crystal state of plating is confirmed, and the observation result is fed back to the substrate manufacturing process.

JP 2010-135555 A

  By the way, the surface state of the plating formed on the wiring affects the wire bonding property. However, in the above-described film thickness measurement, inspection light (X-rays) is irradiated to a relatively wide area on the substrate. For this reason, it becomes difficult to grasp the surface state of the plating that includes a partial defect in the irradiation region, for example, a portion that is not covered with the gold layer, that is, a portion where the nickel layer is exposed. In addition, a predetermined pretreatment (metal treatment) is required for observation by SEM that can confirm the surface state in detail. This pretreatment is difficult to process non-destructively on the substrate.

  According to one aspect of the present invention, there is provided an inspection method for inspecting a wiring board having a wiring formed on one main surface, the step of measuring a film thickness of a plating formed on the wiring and including at least a nickel layer and a gold layer. A signal pin of the measurement probe in contact with the wiring, and a ground pin of the measurement probe in contact with a pad connected to a metal layer disposed opposite to the wiring to measure the high-frequency characteristics of the wiring And including.

  According to one aspect of the present invention, the state of the plating layer can be easily grasped.

It is a schematic block diagram of a semiconductor device. (A) is a partial top view of a wiring board, (b) is a fragmentary sectional view of a wiring board. It is a schematic block diagram of a board | substrate. It is a flowchart which shows a part of manufacturing process of a wiring board. It is explanatory drawing of a high frequency characteristic measurement. It is a characteristic view which shows the frequency and transmission loss of a signal. It is a schematic block diagram of another board | substrate.

Hereinafter, the present embodiment will be described with reference to FIGS.
Note that the attached drawings are for explaining the outline of the configuration, and do not represent actual sizes and ratios.

  As shown in FIG. 1, the semiconductor device 10 (semiconductor package) includes a wiring board 21 and a semiconductor chip 11 mounted on one main surface (upper surface) of the wiring board 21. The semiconductor chip 11 has a plurality of pads 12 connected to a built-in circuit formed on the upper surface.

  The wiring board 21 has pads 22 formed on the upper surface according to the positions of the pads 12 of the semiconductor chip 11. The pads 12 of the semiconductor chip 11 and the pads 22 of the wiring substrate 21 are connected to each other by bonding wires 13. Each pad 22 is connected to a wiring 23 formed on the upper surface of the substrate. The material of the pad 22 and the wiring 23 is, for example, copper. The material of the bonding wire 13 is, for example, gold. The wiring board 21 has bumps 24 for mounting the semiconductor device 10 on the lower surface. The material of the bump 24 is, for example, gold tin solder.

  As shown in FIG. 2A, a plurality of wirings 23 are formed on the upper surface of the wiring board 21. One of the plurality of wirings 23 is shown as a wiring 23 a in order to distinguish from the other wirings 23. On the upper surface of the substrate on the central end side where the pads 22 of the wirings 23 are formed, terminals 26 are formed between the wirings 23 so as to be separated from the wirings 23. The terminal 26 is made of, for example, copper. In the wiring substrate 21 on the outer end side of the wiring 23, a via 27 is formed in a through hole that penetrates the substrate from the upper surface to the lower surface. The via 27 is formed by, for example, copper plating. The pad 22 and the via 27 are connected via the wiring 23. The wiring 23 and the bump 24 shown in FIG. 1 are connected through a via 27. Accordingly, the bump 24 is connected to the pad 12 of the semiconductor chip 11 via the via 27, the wiring 23 and the bonding wire 13.

  As shown in FIG. 2B, the wiring board 21 is a multilayer board, and a plurality (two in FIG. 2B) of insulating members 25 are formed. The material of the insulating member 25 is, for example, an insulating resin (such as an epoxy resin). A ground wiring 28 is formed between the first and second insulating members 25 of the wiring board 21. The ground wiring 28 and the wiring 23 a (wiring 23) are disposed to face each other with the insulating member 25 interposed therebetween. The ground wiring 28 is a metal layer formed from copper, for example. The ground wiring 28 is formed with, for example, a circular clear (conductor non-formed portion) (not shown) with respect to the via 27 so as not to be connected to the via 27 shown in FIG.

  As shown in the enlarged view of FIG. 2B, a nickel layer 29 is formed on the upper surface of the pad 22 and the wiring 23 (including the wiring 23a), and a gold layer 30 is formed on the upper surface of the nickel layer 29. Yes. The nickel layer 29 and the gold layer 30 are plating formed by, for example, an electrolytic plating method. The thickness of the nickel layer 29 is, for example, 2 μm, and the thickness of the gold layer 30 is, for example, 0.02 μm.

  As shown in FIG. 2A, terminals 31a and 31b are formed on the upper surface of the substrate on the outer end side (via 27 side) of the wiring 23a with the wiring 23a interposed therebetween. The terminals 31a and 31b are formed apart from the wiring 23a. The material of the terminals 31a and 31b is, for example, copper. Each terminal 31a, 31b is formed in a rectangular shape having a side of about 100 μm.

  The ground wiring 28 is formed in a range including the wiring 23 indicated by a one-dot chain line in FIG. 2A except for the clear portion including the via 27. The terminal 26 is connected to the ground wiring 28 via the via 32. The terminals 31a and 31b are connected to the ground wiring 28 via vias 33a and 33b. The ground pad 12 of the semiconductor chip 11 is connected to the ground wiring 28 via a bonding wire 13 or the like. The wiring 23a (wiring 23), the ground wiring 28, and the insulating member 25 formed as described above form a microstrip line structure. The surface state of the nickel layer 29 and the gold layer 30 (see FIG. 2B) is inspected by measuring the high frequency characteristics of the wiring 23a as an inspection wiring.

  The wiring board 21 is made from, for example, a board (work) 35 shown in FIG. In the manufacturing process of the wiring substrate 21, the substrate (work) 35 transported to the plating apparatus includes a plurality of substrate regions 21 a for forming the wiring substrate 21 and a frame 36. The substrate 35 is formed in a rectangular plate shape, and a plurality of substrate regions 21a are arranged in a matrix. A frame 36 having a predetermined width is formed around the plurality of substrate regions 21a. The frame 36 includes an outer peripheral frame portion 36a formed on the outer peripheral portion of the substrate 35, and the frame 36 in the center of the substrate 35 (between the third and fourth of the substrate regions 21a arranged in the vertical direction in FIG. 3). And a central frame portion 36b formed to have a width wider than that portion.

Next, the manufacturing process of the wiring board 21 will be described.
First, in the manufacturing process of the substrate 35, for example, a substrate region 21a is set on a work of an insulating member made of an insulating resin (epoxy resin or the like), and the ground wiring 28, the insulating member 25, or the like is provided in each substrate region 21a. Form in multiple layers. Next, wirings 23 and the like are formed on one main surface (upper surface) of each substrate region 21a by electroless copper plating and electrolytic copper plating to form a substrate 35.

  Next, as shown in FIG. 4, the substrate 35 is subjected to a plating process (step 41). In the plating process, the step of forming the nickel layer 29 and the step of forming the gold layer 30 are continuously performed in the same apparatus.

  Next, the film thickness of the plating is measured (step 42). In the film thickness measurement, the plated wiring 23 is irradiated with X-rays, and the film thicknesses of the nickel layer 29 and the gold layer 30 are measured based on the intensity of the generated fluorescent X-rays. In the film thickness measurement, for example, a reference measurement position is set for each product of each semiconductor device 10, and measurement is performed for each substrate 35. Then, the film thickness is confirmed by comparing the measurement result with a predetermined threshold value.

  Next, the high-frequency characteristics of the wiring 23a shown in FIG. 2A are measured (step 43), and it is determined whether to perform the plating process based on the measurement result (step 44). The high frequency characteristics (for example, transmission loss) correspond to the surface state of the plating formed on the wiring. Therefore, based on the high frequency characteristics of the wiring 23a, the substrate 35 from which the nickel layer 29 is exposed is extracted, and the substrate 35 is subjected to a plating process (step 45). As a result, defects (for example, insufficient coverage with the gold layer) on the plating surface can be reduced, and the wiring substrate 21 having a low bonding tensile strength can be reduced. And the frequency | count of the test | inspection using the scanning electron microscope (SEM: Scanning Electron Microscope) in which it is difficult to test | inspect the wiring board 21 nondestructively can be reduced.

  The high-frequency characteristic measurement method will be described in detail. As shown in FIG. 5, the measurement is performed by bringing two high-frequency measurement probe terminals 51 and 52 into contact with the wiring substrate 21 (wiring 23a) on the substrate 35. The probe terminal 51 is a GSG type probe terminal, and has one signal pin 51a and ground pins 51b and 51c provided on both sides of the signal pin 51a. Since the probe terminal 52 has the same configuration as the probe terminal 51, the description thereof is omitted.

  In the probe terminal 51, the ground pins 51b and 51c are in contact with the terminals 26a and 26b sandwiching the wiring 23a, and the signal pin 51a is in contact with the wiring 23a (pad 22) between the terminals 26a and 26b. In the probe terminal 52, the ground pins 52b and 52c are in contact with the terminals 31a and 31b, respectively, and the signal pin 52a is in contact with the wiring 23a between the terminals 31a and 31b. Then, a high frequency signal is input from one of the signal pins 51a and 52a of the probe terminals 51 and 52 to the wiring 23a, and the signal transmitted from the other is measured.

  FIG. 6 shows the result of the simulation of the high frequency characteristics for the wiring with the wiring 23a simplified. In FIG. 6, a curve H1 indicates a case where the exposure rate of the nickel layer is 0%, a curve H2 indicates a case where the exposure rate is 20%, a curve H3 indicates a case where the exposure rate is 50%, and a curve H4 indicates 100%. Represents the case. The horizontal axis represents the frequency of the high-frequency signal input to the wiring, and S21 on the vertical axis represents one of the S parameters representing the characteristics of the high-frequency circuit and represents the transmission loss of the wiring due to the transmission of the high-frequency signal.

  As shown in FIG. 6, the exposure loss curves H1 to H4 have different transmission losses as the frequency of the signal transmitted through the wiring 23a increases. For example, when the frequency of a signal to be transmitted is set to 60 GHz, a difference of about 1 dB occurs in the transmission loss in the curve H2 having an exposure rate of 20% compared to the curve H1 having an exposure rate of 0%. A certain correlation was confirmed between the simulation result and the actual measurement value of the wiring board 21. That is, when the crystal growth of the gold layer 30 is not sufficient, the exposure of the nickel layer 29 and the skin effect of the current in the high-frequency signal have a synergistic effect, resulting in a reduction in transmission loss. Therefore, by measuring the high frequency characteristics of the wiring 23a in a relatively high frequency band, the wiring substrate 21 having a high exposure rate of the nickel layer 29 can be extracted from the transmission loss.

  As shown in FIG. 4, after the high-frequency characteristic measurement (step 43), it is determined whether or not to perform gold plating according to the measured transmission loss (step 44). In this determination, for example, a high frequency characteristic is measured for the wiring 23a having the same configuration (line length, shape, etc.) as the wiring 23a and having no problem in wire bonding, and a threshold value is determined in advance from the result. In addition, in the case where it is difficult to inspect all the wiring boards 21 in the high frequency inspection, even if a part of a plurality of substrates 35 included in the same lot is extracted and inspected. Good. In FIG. 5, the conductor portions other than the portion between the probe terminal 51 and the probe terminal 52, that is, the wiring 23a on the via 27 side from the portion where the signal pin 52a is in contact, the via 27, and the like are in a stub state. Even in the wiring 23a including such a stub state circuit, the high frequency characteristics can be determined by comparing the transmission loss including the conductor portion in the stub state.

  If it is determined in step 44 that the plating process is necessary, the plating process is performed (step 45). A plating process (step 45) performs gold plating. Next, the film thickness is measured (step 42).

  If it is determined in step 44 that the plating process is unnecessary, the wire bonding property is measured (step 46). In the wire bonding characteristic measurement, for example, a bonding wire is connected to a test wiring formed on the substrate 35, and the tensile strength of the bonding is measured. In step 47, the substrate 35 in which the tensile strength of the bonding satisfies the reference value ends the plating process. Further, the substrate 35 having a low bonding tensile strength is confirmed by SEM in the crystal state of plating (step 48), and the observation result is fed back to the manufacturing process of the substrate 35.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The wiring board 21 used in the semiconductor device 10 can be brought into contact with the probe terminals 51 and 52 for measuring high-frequency characteristics with respect to the wiring 23a connected to the pads 12 of the semiconductor chip 11 and the bonding wires 13. Terminals 26a, 26b, 31a, 31b are formed. In the inspection process of the wiring board 21, the probe terminal 51 is brought into contact with the terminals 26a, 26b and the wiring 23a, the probe terminal 52 is brought into contact with the terminals 31a, 31b and the wiring 23a, and a high frequency signal is transmitted to the wiring 23a to measure transmission loss. (Step 43). It is determined whether to perform the plating process based on the measured transmission loss (step 44). Therefore, by extracting the wiring board 21 with a high exposure rate of the nickel layer 29 from the high frequency characteristics of the wiring 23a and plating the substrate (work) 35 including the wiring board 21, the surface condition of the plating is good. The wiring board 21 can be obtained. In other words, it is possible to reduce the number of wiring boards 21 having a low bonding tensile strength.

  (2) The high-frequency inspection (step 43) can be measured by bringing the probe terminals 51 and 52 into contact with the wiring 23a and the terminals 26a, 26b, 31a and 31b, so that the wiring board 21 can be inspected nondestructively.

(3) Since the terminals 31a and 31b are provided for each wiring board 21, the high frequency characteristics of each wiring board 21 can be measured even after being separated into individual pieces.
In addition, you may implement the said embodiment in the following aspects.

  In the above embodiment, the measurement of the high frequency characteristics is performed on the wiring substrate 21 formed in plural on the substrate 35, but is not limited thereto. For example, as shown in FIG. 7, in the substrate 60, a region 61a is set in the central portion of each side of the outer peripheral frame portion 36a, and a region 61b is set in the central portion of the central frame portion 36b (the central portion of the substrate 60). 7 is a portion indicated by a broken line). In each of the regions 61a and 61b, as shown in the enlarged view of FIG. 7, a linear wiring 62 is formed on the upper surface of the substrate. Terminals 63a and 63b are formed on one end side in the longitudinal direction of the wiring 62, and terminals 64a and 64b are formed on the upper surface of the substrate so as to be separated from the wiring 62 on the other end side. Further, the substrate 60 has a ground wiring 65 formed through an insulating member in a range including the wiring 62 and the terminals 63a, 63b, 64a and 64b in the respective regions 61a and 61b. Each terminal 63a, 63b, 64a, 64b is connected to a ground wiring 65. The substrate 60 configured as described above can inspect the surface condition of the plating of the wiring substrate 21 by measuring the high frequency characteristics of the wiring 62 in each of the regions 61a and 61b.

  Accordingly, since the high frequency characteristics are measured using the substrate 60 as an inspection target, handling (conveyance), fixing of the substrate for inspection, and the like are facilitated as compared with the case where the measurement is performed on the individual wiring substrate 21. . Further, since the inspection wiring 62 and the like are formed on the frame 36, when the frame 36 is cut to individualize the wiring board 21, the wiring 62 and the like can be discarded. The wiring 62 and the terminals 63a, 63b, 64a, and 64b provided on the frame 36 may be provided separately from the wiring 23 in the board region 21a (wiring board 21). Further, wiring and terminals capable of measuring high frequency characteristics may be provided in both the substrate region 21a and the frame 36.

-In the said embodiment, you may test | inspect from the high frequency characteristic measurement (step 43), abbreviate | omitting a film thickness measurement (step 42), and the test process after performing a plating process (step 45).
In the above embodiment, the wiring substrate 21 is embodied as a wiring substrate for mounting the semiconductor chip 11, but may be embodied in another wiring substrate having a wiring on which plating is formed on one main surface.

In the above embodiment, the ground wiring 28 may be formed on the lower surface (bump 24 side) of the wiring substrate 21 without being limited to between the insulating members 25.
In the above embodiment, the metal layer disposed opposite to the wiring 23a (wiring 23) is not limited to the ground wiring 28. For example, the wiring that supplies a high potential to the semiconductor chip 11 and the terminals 26a, 26b, and 31a. , 31b may be used.

In the above embodiment, the probe terminals 51 and 52 may be, for example, GS type probe terminals including a pair of signal pins and ground pins.
-In the said embodiment, the metal used for metal plating is not limited to the combination of nickel and gold, For example, you may use nickel, palladium, and gold | metal | money.

In the above embodiment, the plating process may be performed using an electroless plating method.
-In the said embodiment, the material of the insulating member 25 is not limited to insulating resin (epoxy resin etc.), For example, you may use a ceramic and silicon | silicone.

  -In the said embodiment, the material of the pad 22, the wiring 23, the ground wiring 28, and the terminals 26, 31a, and 31b is not limited to copper, For example, you may use tungsten.

11 Semiconductor chip (chip)
12 pads (ground pads)
13 Bonding wire 21 Wiring substrate 21a Substrate region 23, 23a, 62 Wiring 25 Insulating member 26a, 26b, 31a, 31b Terminal (pad)
28,65 Ground wiring (metal layer)
29 Nickel layer 30 Gold layer 35, 60 Substrate 36 Frame 51, 52 Probe terminal (probe for measurement)
51a, 52a Signal pins 51b, 51c, 52b, 52c Ground pins 63a, 63b, 64a, 64b Terminals (pads)

Claims (6)

An inspection method for inspecting a wiring board having wiring formed on one main surface,
Measuring the film thickness of the plating formed on the wiring and including at least a nickel layer and a gold layer;
A step of contacting a signal pin of a measurement probe with the wiring, contacting a ground pin of the measurement probe with a pad connected to a metal layer disposed opposite to the wiring, and measuring high-frequency characteristics of the wiring;
The inspection method characterized by including. A method of processing a wiring board on which a chip is mounted,
On one main surface of the wiring board, a wiring on which plating including at least a nickel layer and a gold layer connected to the chip via a bonding wire is formed, and a signal pin of a measurement probe is brought into contact with the wiring Sometimes a pad with which the ground pin of the measuring probe can come into contact is formed, and the pad is connected to a metal layer disposed opposite to the wiring,
Supplying a signal to the wiring by the measurement probe to measure high-frequency characteristics of the wiring;
Forming a plating on the wiring according to the measurement result of the high-frequency characteristics;
A step of inspecting the wire bonding property of the wiring board for measuring the high-frequency characteristics;
A method for treating a wiring board, comprising: Including the step of measuring the thickness of the plating formed on the wiring,
The method for processing a wiring board according to claim 2, wherein a step of measuring the high-frequency characteristics is performed on the wiring board whose thickness has been measured. A wiring formed with plating including at least a nickel layer and a gold layer formed on a surface on which the chip is mounted and connected to the chip via a bonding wire;
A pad connected to a metal layer disposed so as to be in contact with the wiring, the ground pin of the measuring probe being formed in contact with the signal pin of the measuring probe in contact with the wiring;
A wiring board comprising: A plurality of substrate regions for forming a wiring substrate on which the chip is mounted;
In the frame portion around the substrate region, the wiring in which the signal pin of the measurement probe is formed so as to be in contact and the plating including at least the nickel layer and the gold layer is formed,
A pad connected to a metal layer formed on the frame portion so that a ground pin of the measurement probe can be contacted, and disposed opposite to the wiring;
A substrate characterized by comprising: A wiring formed with a plating including at least a nickel layer and a gold layer connected to the chip region via the chip and a bonding wire;
A pad connected to a metal layer disposed so as to be in contact with the wiring, the ground pin of the measuring probe being formed in contact with the signal pin of the measuring probe in contact with the wiring;
The substrate according to claim 5, comprising:

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