JP2012233224A - Plating apparatus and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plating apparatus that can normally grow a film on the peripheral part of a wafer.SOLUTION: The plating apparatus includes: a first electrode 6 mounted in a plating tank 2; an annular first and a second openings 7a, 7b adjacent in the order of small diameter from the plating tank 2 toward the outside via an annular flange 7c on a side wall 5c of the plating tank 2; a seal packing 8 mounted on the flange 7c in the second opening 7b; an annular second electrode 9 mounted on the seal packing 8 away from the inner wall of the second opening 7b; a wafer stage 11 larger than the second opening 7b having a wafer holding area 11x with a peripheral edge in a position facing the second electrode 9; a pressurizing hole 11i formed on a region around the wafer holding area 11x of the wafer stage 11, one end of which is directed to the seal packing 8; and a drive part 13 which moves the wafer stage 11 and abuts it on the side wall 5c of the plating tank 2 for closing the second opening 7b.

Description

  The present invention relates to a plating apparatus and a method for manufacturing a semiconductor device.

  Along with the high integration and miniaturization of semiconductor devices, there are an increasing number of products that connect semiconductor devices via bumps. As a method for forming the bump, an electrolytic plating method is mainly employed. The electrolytic plating method is advantageous in that the manufacturing equipment is cheaper and the film forming speed is faster than the sputtering method and the vapor phase growth method.

  As an electroplating apparatus, for example, an apparatus having a wafer carrier that holds a wafer and a suction unit that attracts the back surface of the wafer to the wafer carrier is known. According to this apparatus, a film is grown on the surface of the wafer by supplying an electrolytic solution to the surface of the wafer while rotating the wafer carrier.

  Since the electrolyte easily flows around the wafer carrier around the wafer carrier, a structure is known in which gas is blown into the electrolyte from the wafer carrier through the periphery of the wafer in order to prevent the electrolyte from flowing around.

JP 2005-528794 A

  However, according to the structure in which gas is blown into the electrolytic solution from the periphery of the wafer, the electrolytic solution is not sufficiently supplied to the outer peripheral region of the wafer, and there is a problem that the film is difficult to grow in the outer peripheral region of the wafer. A plating apparatus having a structure that does not rotate the wafer is also known, but there is a problem that a film is difficult to be normally formed at the peripheral edge of the wafer.

  An object of the present invention is to provide a plating apparatus capable of normally growing a film at the peripheral edge of a wafer, a plating apparatus for growing a film by the plating apparatus, and a method for manufacturing a semiconductor device including a plating step. .

According to one aspect of the present invention, a plating tank, a first electrode attached to the inside of the plating tank, and a side wall of the plating tank, from the inside to the outside of the plating tank via an annular flange. An annular first opening and an annular second opening that are adjacent to each other in order of decreasing diameter, a seal packing that is mounted on the flange within the second opening, and on the seal packing, An annular second electrode attached away from the inner wall of the second opening, and a wafer holding region having a peripheral edge at a position facing the second electrode, and larger than the second opening A wafer stage to be formed, a pressurizing hole formed in an area around the wafer holding area in the wafer stage, one end of which is directed to the seal packing, and the wafer stage. There is provided a plating apparatus comprising: a drive unit that presses against a side wall of a tank and closes the second opening; and a voltage source that generates a potential difference between the first electrode and the second electrode. The
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

The pressure of the space surrounded by the second opening, the seal packing, the wafer and the wafer stage can be adjusted while the wafer attached to the wafer holding area of the wafer stage is fitted in the second opening of the plating tank. it can. As a result, even if the force for pressing the wafer against the flange inside the second opening is weaker than before, the plating solution in the plating tank can be prevented from leaking into the space, and the gas in the space can be prevented. Can be prevented from entering the plating solution.
Therefore, since the thickness of the side wall around the first opening can be made thinner than before, the thickness of the side wall protruding from the wafer into the plating tank is suppressed, the step between the side wall and the wafer is reduced, and plating by the step is performed. Liquid retention can be prevented. As a result, variation in the thickness of the metal formed on the peripheral edge of the wafer by plating can be suppressed.

FIG. 1A is a side sectional view showing an example of a plating apparatus according to this embodiment, and FIG. 1B is a partially enlarged sectional view of the plating apparatus illustrated in FIG. FIG. 2 is a front view showing an example of an opening of a plating tank applied to the plating apparatus according to the embodiment. FIG. 3 is a plan view illustrating an example of a first surface of a wafer stage applied to the plating apparatus according to the embodiment. FIG. 4A is a side sectional view showing an example of a plating state in the plating apparatus according to this embodiment, and FIG. 1B is a partially enlarged sectional view of the plating apparatus illustrated in FIG. FIG. 5 is a plan view showing an example of a wafer on which a film is formed by the plating apparatus according to the present embodiment. FIG. 6 is a cross-sectional view showing a part of a plating apparatus according to a comparative example. FIG. 7 is a partially enlarged view of another example of the plating apparatus according to the embodiment. 8A to 8C are cross-sectional views illustrating a part of the first example of the manufacturing process of the semiconductor device according to the embodiment. 8D to 8F are cross-sectional views illustrating a part of the first example of the manufacturing process of the semiconductor device according to the embodiment. 9A to 9C are cross-sectional views illustrating a part of a second example of the manufacturing process of the semiconductor device according to the embodiment. 9D to 9F are cross-sectional views illustrating a part of the second example of the manufacturing process of the semiconductor device according to the embodiment. FIG. 10 is a plan view illustrating another example of the first surface of the wafer stage used in the plating apparatus according to the embodiment.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings. In the figure, similar components are given the same reference numerals.
FIG. 1A is a side sectional view showing an example of a plating apparatus according to the present embodiment, and FIG. 1B is an enlarged sectional view of a portion surrounded by a broken line in FIG. FIG. 2 is a front view showing an example of an opening formed in the plating apparatus shown in FIG. Further, FIG. 3 is a plan view showing an example of a wafer stage mounted on the plating apparatus shown in FIG.

  A plating apparatus 1 shown in FIG. 1 includes a plating tank 2 formed from a metal such as titanium, and a disk-shaped wafer stage 11 formed from an insulating material such as vinyl chloride.

In the plating tank 2, the first divided into two by a partition 3 formed lower than the outer peripheral wall.
The tank 4 and the second tank 5 are provided. The first liquid passage port 4 a formed on the bottom surface of the first tank 4 is connected to the plating solution storage tank 21 through the first liquid pipe 20. The second liquid passage port 5 a formed on the bottom surface of the second tank 5 is connected to the plating solution storage tank 21 through the second liquid tank 22 and the pump 23.

  In the second tank 5, an anode electrode 6 is attached to the wall of the partition 3. The side wall of the second tank 5 facing the anode electrode 6 functions as a cathode holder 5c that supports a cathode electrode 9 described later. A circular opening 7 having an inner diameter smaller than the diameter of the wafer stage 11 is formed in the cathode holder 5c. As illustrated in FIG. 2, the opening 7 includes a first opening 7 a and a second opening 7 b having the same central axis.

  The first opening 7a is formed closer to the inside of the second tank 5 than the second opening 7b, and has a smaller diameter than the second opening 7b. As a result, an annular inner flange is formed around the first opening 7a, that is, at the boundary between the first opening 7a and the second opening 7b, as shown in FIGS. 7c is formed.

  The inner diameter of the first opening 7a is formed to be smaller than the diameter of the wafer 30 fitted in the second opening 7b. Further, the inner diameter of the second opening 7 b is formed smaller than the diameter of the wafer stage 11, while being formed larger than the diameter of the wafer 30.

  Further, the inner surface of the first opening 7a has a thickness of about 1 mm, for example. Further, the inner surface of the second opening 7b is formed to be the same as or slightly thinner than the total thickness of the wafer 30, a seal packing 8 and a cathode electrode 9, which will be described later. It has a thickness of 4 mm. Here, the thickness of the first and second openings 7a and 7b is the thickness in the direction along the central axis of the first and second openings 7a and 7b.

  In the second opening 7b, as shown in FIG. 1B, an annular seal packing 8 that is overlaid on the inner flange 7c is fitted. The seal packing 8 is formed from an insulating material such as a resin such as silicone to a thickness of about 1 mm, for example.

  Further, an annular cathode electrode 9 is attached in the second opening 7b so as to overlap and be fixed on the seal packing 8. The outer diameter of the cathode electrode 9 has a size that does not contact the inner wall of the second opening 7 b, and the inner diameter of the cathode electrode 9 is slightly smaller than the diameter of the wafer 30, It has a size that allows contact. The cathode electrode 9 has, for example, a two-layer structure of titanium and platinum.

  As shown in FIGS. 1A and 3, the wafer stage 11 is formed in a disc shape having a larger diameter than the second opening 7b of the cathode holder 5c. The first surface of the wafer stage 11 is a surface that closes the second opening 7b of the cathode holder 5c, and the second surface is connected to a plunger 13 that is driven to move forward and backward with respect to the plating tank 2. It is the surface to be done.

  As illustrated in FIG. 3, an annular inner sealing groove 11 a and an annular outer sealing groove 11 b having the same central axis and different diameters are formed on the first surface of the wafer stage 11. Yes. The diameter of the outer periphery of the inner sealing groove 11 a is smaller than the diameter of the wafer 30, and is formed so as to overlap the peripheral edge of the wafer 30. The outer sealing groove 11b has a diameter that abuts on the outer wall of the cathode holder 5c in the region surrounding the second opening 7b shown in FIG.

On the first surface of the wafer stage 11, the annular region between the inner seal groove 11a and the outer seal groove 11b is divided into a plurality of portions along the circumferential direction, and the pressure regions 11d, 11e, 11f
Used as. The pressurizing regions 11d, 11e, and 11f are peripheral portions of the wafer holding region 11x that holds the wafer 30. A partition seal groove 11c is formed at each of the boundaries between the pressurizing regions 11d, 11e, and 11f. The partition seal groove 11c is connected to the inner seal groove 11a and the outer seal groove 11b. FIG. 3 shows an example in which the annular seal region is divided into three pressurizing regions 11d to 11f.

  The first pressure region 11d is disposed at a position corresponding to the upper portion of the second opening 7b. Further, the partition seal groove 11c that partitions the second and third pressurizing regions 11e and 11f is located below the second opening 7b.

  An annular seal 12 having a thickness protruding from the grooves 11a, 11b, and 11c is fitted into the inner seal groove 11a, the outer seal groove 11b, and the partition seal groove 11c. The annular seal 12 is formed of an insulating elastic material such as silicone, and is depressed by being pressed against the wafer stage 11 from the back surface of the wafer 30 to be deformed into a shape that does not substantially protrude from the first surface of the wafer stage 11. It is formed by conditions. As shown in FIG. 3, a protrusion 12 a is formed in a portion of the annular seal 12 positioned in the partition seal groove 11. The protrusion 12a is used to partition an annular space formed around the wafer 30 in a sealed state in a state where the opening 7 of the wafer stage 11 is closed by the cathode holder 5c.

  In the wafer stage 11, each of the first to third pressure regions 11d to 11f surrounded by the inner and outer sealing grooves 11a and 11b and the partition sealing groove 11c passes through the wafer stage 11 in the thickness direction. First to third pressurizing holes 11g to 11i are formed. The pressurizing holes 11g to 11i are formed around the wafer holding region 11x, and face the seal packing 8 around the wafer 30 in a state where the second opening 7b is closed by the wafer stage 11 as illustrated in FIG. It is formed in the position to do.

  Each of the first to third pressurizing holes 11g to 11i is connected to the first to third gas pipes 25a to 25c from the second surface side of the wafer stage 11 as illustrated in FIG. Furthermore, the same pressurization pump 26 is connected through the first to third gas pipes 25a to 25c. Pressure adjusting valves 27a to 27c are connected in the middle of the first to third gas pipes 25a to 25c, respectively.

  In the intake area 11j surrounded by the inner seal groove 11a on the first surface of the wafer stage 11, annular inner and outer intake grooves 11k and 11m having the same central axis and different diameters are formed. . Further, air intake holes 11n penetrating the wafer stage 11 in the thickness direction are formed at a plurality of locations of the inner air intake groove 11k and the outer air intake groove 11m, respectively. As illustrated in FIG. 1A, branch pipes of the intake pipes 28 are respectively connected to the second surface side of the wafer stage 11 in the plurality of intake holes 11n. The intake pipe 28 is connected to an intake pump 29.

  Next, a method of using the plating apparatus 1 as described above to use a silicon wafer 31 as the wafer 30 and forming a metal layer on the silicon wafer 31 by electrolytic plating will be described.

First, as illustrated in FIG. 1A, the silicon wafer 31 is placed on the first surface of the wafer stage 11, and the position of the silicon wafer 31 is adjusted so that the edge of the silicon wafer 31 is annular as shown in FIG. 3. The seal regions 11d, 11e, and 11f are overlapped with each other. Thereby, since the annular seal 12 on the inner seal groove 11a contacts the back surface of the silicon wafer 31 along the outer periphery thereof, a sealed space is formed between the annular seal 12, the silicon wafer 31 and the wafer stage 11. It is formed.

  Here, a metal layer 32 is formed on one surface of the silicon wafer 31, and a resist pattern 33 is formed on the metal layer 32. As illustrated in the enlarged view of FIG. 4B, the resist pattern 33 has a pattern opening 33 a and an edge opening 33 b for exposing the metal layer 32 at the outer peripheral edge of the silicon wafer 31. Yes.

  Subsequently, the suction hole 29 n of the wafer stage 11 is sucked by the suction pump 29 through the suction pipe 28. As a result, the space enclosed by the inner portion of the annular seal 12, the wafer stage 11, and the silicon wafer 31 is depressurized, and the silicon wafer 31 is attracted to the wafer stage 11 as shown in FIG.

  Further, the wafer stage 11 adsorbing the silicon wafer 31 is moved by the plunger 13, and the silicon wafer 31 is fitted into the second opening 7b of the cathode holder 5c as shown in FIG. 4A. In this case, the silicon wafer 31 is disposed so as not to contact the inner surface of the second opening 7b. Further, the annular seal 12 is pressed against the outer surface of the cathode holder 5c while surrounding the second opening 7b by the outer portion of the annular seal 12 on the wafer stage 11, and the second opening as shown in FIG. 4B. 7 b is closed by the seal 12 and the wafer stage 11.

  As a result, the metal layer 32 exposed from the edge opening 33b of the resist pattern 33 on the silicon wafer 31 is pressed by the annular cathode electrode 9 in the second opening 7b in the area shown by the shaded pattern in FIG. While being electrically connected. Further, as illustrated in FIG. 4B, the peripheral edge portion of the resist pattern 33 inside the cathode electrode 9 is pressed by the seal packing 8. Further, the space between the inner peripheral wall of the second opening 7 b and the silicon wafer 31 is hermetically separated from the plating tank 2 by the cathode electrode 9 and the seal packing 8 behind it.

  The space is sealed by the first surface of the front wafer stage 11 and the annular seal 12 thereon, and is partitioned into three regions by the protrusions 12a of the annular seal 12 shown in FIG.

  Next, when the plating solution 18 is pumped up from the plating solution storage tank 21 using the pump 23 and is continuously supplied to the second tank 5 of the plating tank 3, the plating solution 18 in the second tank 5 increases in volume. And flows into the first tank 4 over the partition plate 3. Further, the plating solution 18 is returned to the plating solution storage tank 21 through the first liquid pipe 20 from the outlet 4 a at the bottom of the first tank 4. Thus, the plating solution 18 is circulated in the plating tank 2. Furthermore, a voltage is applied to the anode electrode 6 and the cathode electrode 9 from the DC voltage power supply 19 with a polarity in which the anode electrode 6 is positive and the cathode electrode 9 is negative.

  In such a state, a gas having a constant pressure higher than atmospheric pressure, for example, air or nitrogen, is added to the pressurizing holes 11g to 11i through the first to third gas pipes 25a to 25c from the pressurizing pump 26. In this case, the pressure fed through the first to third gas pipes 25a to 25c is adjusted to a pressure that does not leak into the plating tank 2 by adjusting the pressure of the pressure adjusting valves 27a to 27c. That is, the atmospheric pressure applied to the first to third pressurizing regions 11 d to 11 f shown in FIG. 3 is adjusted to a pressure equal to or slightly smaller than the water pressure applied to the space around the silicon wafer 31.

The pressure applied to each of the pressurizing holes 11g to 11i in the first to third pressurizing regions 11d to 11f of the wafer stage 11 need not be the same, and the depth of the plating solution 18 in the plating tank 3; That is, it is changed according to the water pressure of the plating solution 18. That is, since the water pressure is lower in the shallow region of the plating bath 2 than in the deep region of the plating solution 18, the pressure applied to the first pressurizing region 111d located at the top is the second and third below. The pressure is set to be smaller than the pressure applied to the pressurizing regions 11e and 11f. Each of the spaces corresponding to the first to third pressurizing regions 11 d to 11 f around the silicon wafer 31 is partitioned in an airtight state by the protrusions 12 a of the annular packing 12.

  As described above, by adjusting the pressure in the space around the silicon wafer 31, the plating solution 18 is prevented from leaking into the space. That is, when the pressure in the space is adjusted as described above as compared to the structure in which the pressure in the space around the silicon wafer 31 is not adjusted without providing the pressurizing holes 11g to 11i as illustrated in FIG. 18 will not leak into the space.

  From the above, according to the present embodiment, the plating solution 18 can be prevented from leaking into the space around the silicon wafer 31, so that the contact area between the seal packing 8, the cathode electrode 9 and the silicon wafer 31 can be made narrower than before. Can do. Thereby, the area of the element formation region of the silicon wafer 31 as shown in FIG. 3 can be increased, and the number of semiconductor devices 35 formed in a plurality of sections in the region can be increased as compared with the conventional case.

  Further, by adjusting the pressure of the space around the silicon wafer 31, not only can the gas in the space be prevented from leaking into the plating solution 18, but also the plating solution 18 can be prevented from leaking into the space. As a result, the difference in stress applied to the internal flange 7c around the first opening 7a from the inside and the outside can be reduced, so that the thickness of the first opening 7a is reduced and the pressing force of the silicon wafer 31 is reduced. It may be possible to lower the strength against. As a result, the step formed by the outer periphery of the silicon wafer 31 and the thickness of the first opening 7a can be reduced, and the stay of the plating solution 18 due to the step can be prevented.

  On the other hand, as shown in FIG. 6, when the pressure in the space around the silicon wafer 31 is not adjusted, the pressing force from the silicon wafer 31 to the internal flange 7c is increased so that the plating solution leaks into the space. There is a need to prevent. That is, it is necessary to increase the pressure resistance of the cathode holder 5c by increasing the thickness of the first opening 7a. According to this, since the step of the cathode holder 5c with respect to the upper surface of the silicon wafer 31 becomes higher, the plating solution stays at the step as shown by the one-dot chain line in FIG. The resulting metal is thinner than the inner region.

  Incidentally, in order to further reduce the distance from the surface of the silicon wafer 31 to the inner surface of the cathode holder 5c, the attachment position of the cathode electrode 9 on the seal packing 8 is adjusted as shown in FIG. You may make it contact with a periphery. In this case, it is necessary to ensure the connection between the cathode electrode 9 and the metal layer 32 by expanding the metal layer 32 to a region reaching the outer peripheral edge of the silicon wafer 31.

  In the state as described above, a voltage is applied from the DC voltage power supply 19 so that the potential of the cathode electrode 9 becomes negative with respect to the potential of the anode electrode 6. As a result, the metal contained in the plating solution 18 is deposited on the metal layer 32 through the openings 33a of the resist pattern 33, and a plated metal layer 34 as shown in FIG. 4B is formed.

A method of plating a metal film on a semiconductor wafer using the plating apparatus 1 according to this embodiment will be described below.
8A to 8F are cross-sectional views showing a process of forming a copper wiring on the silicon (semiconductor) wafer 31. 8A to 8F, the metal pad, insulating film, and metal film formed on the silicon wafer 31 are shown in cross section.

  As shown in FIG. 5, the silicon wafer 31 is divided into a plurality of sections, and a semiconductor device 35 is formed in these partitioned areas. As the semiconductor device 35, a semiconductor integrated circuit such as a MOS transistor or a wiring is formed.

  As shown in FIG. 8A, an aluminum metal pad 41 is formed on a layer of the silicon wafer 31 on which wirings and the like are formed. The metal pad 41 is electrically connected to a semiconductor integrated circuit (not shown) formed in the silicon wafer 31. Further, a cover film 42 having an opening 42 a on the metal pad 41 is formed on the silicon wafer 31. As the cover film 42, a silicon nitride film is formed by, for example, a CVD method.

  An insulating protective film 43 made of polyimide, for example, is formed on the cover film 42. The polyimide contains, for example, a photosensitive agent, and is applied onto the silicon wafer 31 to form openings 43a formed by exposure and development. The opening 43 a of the protective film 43 is formed on the metal pad 41 so as to cover the edge of the opening 42 a of the cover film 42.

  As illustrated in FIG. 8B, a titanium layer 44 and a copper seed layer 45 are sequentially formed on the silicon wafer 31 on which the metal pad 41, the cover film 42, and the protective film 43 are formed by sputtering. In this case, the titanium layer 44 and the copper seed layer 45 are formed on the entire surface of the silicon wafer 41 covering the metal pad 41 and the protective film 43.

  Next, as illustrated in FIG. 8C, a photoresist is applied onto the copper seed layer 45, and this is exposed and developed to form a resist pattern 46 corresponding to the resist pattern 33 shown in FIG. . The resist pattern 46 has a wiring opening 46a in a wiring formation region including the metal pad 41, and further exposes the copper seed layer 45 at the outer peripheral edge of the silicon wafer 31 as shown in FIG. It has an annular border. Thereafter, the copper seed layer 45 is cleaned through the wiring opening 46a.

  Next, the silicon wafer 31 is attached on the first surface of the wafer stage 11 by the same method as described above. Thereafter, the wafer stage 11 is moved by the same method as described above, and the peripheral edge of the resist pattern 46 on the silicon wafer 31 is pressed against the seal packing 8 on the inner flange 7c of the cathode holder 5c. At the same time, the copper seed layer 45 exposed from the border of the resist pattern 46 is brought into contact with and electrically connected to the annular cathode electrode 9.

  Thereafter, the plating solution 18 is supplied into the plating tank 2 by the same method as described above. As the plating solution 18, for example, a solution containing copper sulfate is used. Subsequently, a voltage is applied from the DC voltage source 19 to the anode electrode 6 and the cathode electrode 9, and the copper layer 47 is plated on the copper seed layer 45 exposed from the wiring opening 46a of the resist pattern 46 as shown in FIG. 8D. To do. In this case, as described above, the gas pressure is applied to the space formed around the silicon wafer 31 through the pressurizing holes 11g to 11i of the wafer stage 11 under the above conditions. This prevents gas from leaking into the plating tank 2 from the space, and further prevents the plating solution 18 from leaking into the space around the silicon wafer 31.

  Next, the plating solution 18 in the plating tank 2 is returned to the plating solution storage tank 21 to empty the plating tank 2. Further, the silicon wafer 31 is sucked to the wafer stage 11 through the intake hole 11n of the wafer stage 31. Thereafter, the wafer stage 11 is retracted from the plating tank 2 by driving the plunger 13. Then, the suction of the silicon wafer 31 is released and the silicon wafer 31 is taken out from the wafer stage 11.

  Next, as illustrated in FIG. 8E, after cleaning the silicon wafer 31, the resist pattern 46 is removed using a solvent. Further, as illustrated in FIG. 8F, the protective film 43 is exposed by wet etching the copper seed layer 45 and the titanium layer 44. For example, a solution containing a ferric chloride solution is used as the etchant for the copper seed layer 45, and a solution containing a reducing acid such as hydrofluoric acid is used as the etchant for the titanium layer 44.

  When the copper seed layer 45 is etched, the copper layer 47 formed in the wiring region is slightly thinned, but the total thickness of the remaining copper seed layer 45 and the copper layer 47 is the initial thickness of the plated copper layer 47. The thickness is almost equal. The remaining copper layer 47 and the copper seed layer 45 thereunder are used as copper wiring.

Next, an example of a process of forming a solder (solder) bump using the plating apparatus 1 will be described below.
9A to 9F are cross-sectional views illustrating a process of forming solder bumps on a semiconductor wafer.
As a wafer 30 on which solder bumps are formed, a silicon wafer 31 is used in the same manner as described above. As shown in FIG. 5, the silicon wafer 31 is divided into a plurality of sections, and a semiconductor device 35 is formed in these partitioned areas. As the semiconductor device 35, a semiconductor integrated circuit (not shown) such as a MOS transistor and wiring is formed in and on the silicon wafer 31.

  On the uppermost surface of the silicon wafer 31, as shown in FIG. 9A, an aluminum metal pad 51 connected to the semiconductor integrated circuit is formed. Further, a cover film 52 having an opening 52 a is formed on the metal pad 51 on the silicon wafer 31. As the cover film 52, for example, a silicon nitride film is formed by a CVD method.

  An insulating protective film 53 made of polyimide, for example, is formed on the cover film 52. The polyimide contains, for example, a photosensitive agent, and after being coated on the silicon wafer, the opening 53a is formed by exposure and development. The opening 53 a of the protective film 53 is formed on the metal pad 51 so as to cover the edge of the opening 52 a of the cover film 52.

  A titanium layer 54 and a copper seed layer 55 are sequentially formed on the silicon wafer 31 on which the metal pad 51, the cover film 52, and the protective film 53 are formed by a sputtering method. In this case, the titanium layer 54 and the copper seed layer 55 cover the protective film 53 and the metal pad 51, and are formed on the entire surface reaching the periphery of the silicon wafer 31 as shown in FIG. 4B.

  Next, as illustrated in FIG. 8B, a photoresist is applied on the copper seed layer 55, and this is exposed and developed to form a resist pattern 56. The resist pattern 56 has a bump forming opening 56 a on the metal pad 51, and further, as shown in FIG. 4B, an annular shape exposing the copper seed layer 55 at the outer peripheral edge of the silicon wafer 31. Has a border. The rim has a shape in which the copper seed layer 55 is brought into contact with the cathode electrode 9 at the peripheral portion of the silicon wafer 31.

  After cleaning the opening 56 a of the resist pattern 56 and the copper seed layer 55 exposed from the edging, the silicon wafer 31 is attached on the first surface of the wafer stage 11. The silicon wafer 31 is attached to the wafer stage 11 by the same method as described above. Thereafter, the wafer stage 11 is moved by the same method as described above, and the outer peripheral edge portion of the resist pattern 56 of the silicon wafer 31 is pressed against the seal packing 8 on the inner flange 7c of the cathode holder 5c. At the same time, the copper seed layer 55 on the outer periphery of the silicon wafer 31 is connected to the annular cathode electrode 9.

Next, steps required until a structure shown in FIG. 9C is formed will be described.
First, the plating solution 18 is supplied into the plating tank 2 by the same method as described above, and a voltage is applied between the anode electrode 6 and the cathode electrode 9 from the DC voltage source 19 to open the opening 56 a of the resist pattern 56. A nickel layer 57 is plated on the exposed copper seed layer 55. As the plating solution 18 for forming the nickel layer 57, for example, a solution containing either nickel sulfate or nickel sulfamate is used.

  Next, the SnAg solder layer 58 is plated on the nickel layer 57 by changing the plating solution 18 in the plating tank 3. As the plating solution 18 for forming the SnAg solder layer 58, for example, a solution containing silver methanesulfonate and tin methanesulfonate is used. The plating of the nickel layer 57 and the plating of the SnAg solder layer 58 may use separate plating apparatuses having the same structure as described above.

  At the time of plating, as described above, in the space formed around the silicon wafer 31 in the second opening 7b, the same conditions as described above are passed through the pressure holes 11g to 11i of the wafer stage 11. Gas pressure is applied. This prevents gas from leaking into the plating solution 18 from the space, and further prevents the plating solution 18 from leaking into the space around the silicon wafer 31.

  After the SnAg solder layer 58 is formed, the output of the DC voltage source 19 is turned off, and the plating solution 18 in the plating tank 2 is returned to the plating solution storage tank 21 to empty the inside. Thereafter, the silicon wafer 31 is sucked into the wafer stage 11 through the intake hole 11n of the wafer stage 11, and the wafer stage 11 is further retracted from the plating tank 2. Thereafter, the silicon wafer 31 is removed from the wafer stage 11 by releasing the suction of the silicon wafer 31.

  Next, as illustrated in FIG. 9D, after the silicon wafer 11 is cleaned, the resist pattern 56 is removed using a solvent. Further, as illustrated in FIG. 9E, the SnAg solder layer 58 is used as a mask, and the copper seed layer 55 and the titanium layer 54 are sequentially wet etched to expose the protective film.

  Next, the SnAg solder layer 58 left above the metal pad 51 is heated in an inert gas atmosphere at a temperature of, for example, about 230 ° C. and reflowed to make the exposed surface substantially spherical. The substantially spherical SaAg solder layer 58 is used as a bump.

  As described above, when the wiring 47 and the solder layer 58 are formed using the plating apparatus 1 in the step of forming the semiconductor device on the silicon wafer 31, the silicon wafer 31 and the seal packing 8 are formed as shown in FIG. The contact area of the cathode electrode 9 can be reduced. Thereby, the area | region which forms the semiconductor device 35 in the silicon wafer 31 spreads, and the number which forms the semiconductor device 35 can be increased.

  Moreover, the pressure in the space around the silicon wafer 31 in the second opening 7b is adjusted. Thereby, even if the pressure applied to the inner flange 7c of the cathode holder 5c is weaker than before, leakage of gas in the space to the plating solution 18 and leakage of the plating solution 18 to the space can be prevented.

  Furthermore, the cathode holder 5c around the first opening 7a where the pressing force is suppressed can be made thinner, and the stay of the plating solution 18 near the periphery of the silicon wafer 31 is eliminated. As a result, the uniformity of the film thickness distribution of the plated metal on the silicon wafer 31 is improved.

  By the way, as illustrated in FIG. 10, on one surface of the wafer stage 11, the region between the inner packing groove 11a and the outer packing groove 11b is divided into four or more regions 11o to 11t by the partition seal groove 11c. May be. In this case, a pressurizing hole 11u is formed in each of the partitioned regions 11o to 11t.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and Interpretation is not limited to conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Appendix 1) In the order of decreasing diameter from the inner side to the outer side of the plating tank through an annular flange on the plating tank, the first electrode attached to the inside of the plating tank, and the side wall of the plating tank An adjacent annular first opening and an annular second opening; a seal packing mounted on the flange in the second opening; and the second opening on the seal packing An annular second electrode attached away from the inner wall of the wafer, a wafer stage having a wafer holding region having a peripheral edge at a position facing the second electrode, and formed larger than the second opening; A pressurizing hole formed in an area around the wafer holding area of the wafer stage and having one end directed to the seal packing; and a side wall of the plating tank by moving the wafer stage A drive unit for closing the second opening by pressing, plating apparatus having a voltage source generating a potential difference between the first electrode and the second electrode. (Additional remark 2) The plating apparatus of Additional remark 1 characterized by having a suction hole for wafer adsorption in the wafer holding field.
(Supplementary note 3) The plating apparatus according to supplementary note 2, wherein the intake hole is connected to an intake pump through a gas pipe.
(Appendix 4) An annular inner packing groove and an annular outer packing groove formed on the inner side and the outer side of the wafer holding area of the wafer stage, respectively, and sandwiching the outer peripheral edge of the wafer holding area and the pressure hole. The plating apparatus according to any one of supplementary notes 1 to 3, further comprising: an inner packing groove and a packing that is fitted into the outer packing groove.
(Supplementary Note 5) A plurality of partition seal grooves that divide the annular region into a plurality along the outer periphery of the inner packing groove are formed in the annular region surrounded by the inner packing groove and the outer packing groove. In any one of the supplementary notes 1 to 5, the pressurizing hole is formed in each of the annular regions defined by the plurality of partition sealing grooves. Plating equipment.
(Appendix 6) The plating apparatus according to any one of appendices 1 to 5, wherein the pressurization hole is connected to a pressurization pump through a gas pipe and a pressurization regulator.
(Appendix 7) A step of forming a first metal layer on one whole surface of a semiconductor wafer, an annular rim opening that exposes the first metal layer at an outer peripheral edge of the semiconductor wafer, and the rim opening Forming a resist pattern on the first metal layer with a pattern opening exposing a part of the first metal layer on the inner side, attaching the semiconductor wafer on a wafer stage, plating An annular ring attached to a flange formed along the inner periphery of the plating opening by closing the plating opening formed in the bath with the wafer stage and fitting the semiconductor wafer into the plating opening. The seal packing is brought into contact with the outer peripheral edge of the resist pattern, and further, the seal is formed on the first metal layer through the edge opening of the resist pattern. A step of connecting a first electrode on the annular Kkin, and supplying the plating solution to the plating tank, the seal packing within the plating aperture, the first
A step of applying a pressure higher than atmospheric pressure to a space surrounded by the electrode, the semiconductor wafer and the wafer stage, and maintaining a space between the second electrode and the first electrode disposed in the plating solution in the plating tank; Forming a second metal film based on the metal contained in the plating solution on the first metal layer in the pattern opening by generating a potential difference in the semiconductor device. Production method.
(Appendix 8) After forming the second metal layer, discharging the plating solution from the plating tank, removing the semiconductor wafer from the wafer stage, and masking the second metal layer on the semiconductor wafer The method for manufacturing a semiconductor device according to appendix 7, further comprising: etching the first metal layer.
(Additional remark 9) The said atmospheric | air pressure is a magnitude | size which suppresses the leakage to the said plating solution of the said plating solution, and also suppresses the leakage to the said plating solution of the gas in the said space, The additional statement 7 characterized by the above-mentioned. Semiconductor device manufacturing method.

DESCRIPTION OF SYMBOLS 1 Plating apparatus 2 Plating tank 3 Partition 4 1st tank 5 2nd tank 6 Anode electrode 7 Opening part 7a 1st opening part 7b 2nd opening part 7c Inner flange 8 Seal packing 9 Cathode electrode 11 Wafer stage 11a Inner side Packing groove 11b Outer packing groove 11c Partition seal grooves 11d, 11e, 11f Pressurization regions 11g, 11h, 11i Pressurization hole 11n Intake hole 12 Annular seal 13 Plungers 25a-25c Gas pipe 26 Pressurization pump 27 Pressure adjustment Valve 28 Intake pipe 29 Pump 30 Wafer 31 Silicon wafer 32 Metal layer 33 Resist pattern 33a Pattern opening 33b Edge opening 34 Plating metal layer

Claims (5)

A plating tank;
A first electrode attached to the inside of the plating tank;
In the side wall of the plating tank, an annular first opening and an annular second opening that are adjacent to each other in order of decreasing diameter from the inside to the outside of the plating tank via an annular flange,
A seal packing mounted on the flange in the second opening;
An annular second electrode mounted on the seal packing away from the inner wall of the second opening;
A wafer stage having a wafer holding region having a peripheral edge at a position facing the second electrode, the wafer stage being formed larger than the second opening;
A pressurizing hole formed in a region around the wafer holding region of the wafer stage and having one end directed to the seal packing;
A driving unit that presses the wafer stage against a side wall of the plating tank and closes the second opening;
A voltage source that creates a potential difference between the first electrode and the second electrode;
A plating apparatus.   The plating apparatus according to claim 1, wherein the wafer holding region has a suction hole for wafer suction. An annular inner packing groove and an annular outer packing groove that are formed on the inner and outer sides of the wafer holding area of the wafer stage, respectively, and an outer peripheral edge of the wafer holding area and the pressure hole,
A packing fitted into the inner packing groove and the outer packing groove;
The plating apparatus according to claim 1 or 2, characterized by comprising: In the annular region surrounded by the inner packing groove and the outer packing groove, a plurality of partition sealing grooves that divide the annular region into a plurality along the outer periphery are formed,
4. The pressurizing hole is formed in each of the regions defined by the plurality of partition sealing grooves in the annular region. 5. The plating apparatus as described. Forming a first metal layer on the entire surface of the semiconductor wafer;
A resist pattern having an annular rim opening that exposes the first metal layer at an outer peripheral edge of the semiconductor wafer, and a pattern opening that exposes a portion of the first metal layer inside the rim opening. Forming on the first metal layer;
Attaching the semiconductor wafer onto a wafer stage;
The plating opening formed in the plating tank is closed by the wafer stage and fitted on the flange formed along the inner periphery of the plating opening by fitting the semiconductor wafer into the plating opening. Contacting an annular seal packing with an outer peripheral edge of the resist pattern, and further connecting an annular first electrode on the seal packing on the first metal layer through the edge opening of the resist pattern;
Supplying a plating solution into the plating tank;
Maintaining a pressure larger than atmospheric pressure in the space surrounded by the seal packing, the first electrode, the semiconductor wafer and the wafer stage in the plating opening; and
A potential difference is generated between the second electrode disposed in the plating solution in the plating tank and the first electrode, whereby the second metal film based on the metal contained in the plating solution is formed in the pattern opening. Forming on the first metal layer;
A method for manufacturing a semiconductor device, comprising:

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